Commit Graph
105516 Commits
Author SHA1 Message Date
Marek VasutandTom Rini d6a87d042e misc: i2c: eeprom-emul: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini 0bda59b1fa misc: cros_ec: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini e253640e3f mailbox: stm32-ipcc: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini 0a1347f0a1 mailbox: sandbox: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini 85f4b08691 mailbox: renesas: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini b2961202a7 mailbox: k3-sec-proxy: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini 44f6ca49e9 mailbox: imx: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini 499cb93dec mailbox: apple: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Mark Kettenis <kettenis@openbsd.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini 31df5fc7d4 clk: sunxi: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini 368255a9a0 clk: sunxi: Drop the extern
The struct clk_ops sunxi_clk_ops is private to the clock driver
and there are no external users, no need to expose it this way.
Drop the extern.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini f23324e49e clk: ast2600: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini a8f49cc193 clk: ast2500: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini 64abe3cfcc block: rockchip: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini 2908a3f35b ata: sata_mv: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
2026-05-18 16:56:07 -06:00
Marek VasutandTom Rini 06bf459570 ata: fsl_sata: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2026-05-18 14:26:36 -06:00
Tom Rini 11e1be868c Merge tag 'qcom-next-18May2026' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon into next
- SM6125 gains initial support
- The qcom clock drivers get better support for configuring UFS clocks
- ufetch gets some aesthetic improvements
- A minor bug in the qcm2290 clock driver is fixed
- A few qcom drivers get static/constified
- The GENI serial driver has the RX watermark register properly set
2026-05-18 10:48:20 -06:00
Biswapriyo NathandCasey Connolly 0d131b3b06 board/qualcomm: qcom-phone: Add poweroff command
This command helps to shutdown the device directly from serial command
line. Or, the phone has to be booted into recovery mode to power off.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-3-0a35d083d2da@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:06:53 +02:00
Biswapriyo NathandCasey Connolly bf6de81367 clk/qcom: qcm2290: Fix vote_bit of gpll6 clock
This changes the vote_bit same as enable_mask in Linux clock driver.

Fixes: 3ddc67573f ("clk/qcom: qcm2290: Add SDCC1 apps clock frequency table")
Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-2-0a35d083d2da@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:06:02 +02:00
Biswapriyo NathandCasey Connolly d54d2ec651 phy: qcom: Add SM6115 and SM6125 to QMP UFS PHY driver
The UFS on SM6125 can reuse SM6115 configuration, just like Linux.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-1-0a35d083d2da@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:06:02 +02:00
Marek VasutandCasey Connolly 5a995c2fe0 pci: pcie_dw_qcom: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260508122144.512818-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:47 +02:00
Marek VasutandCasey Connolly bc28119288 gpio: qcom: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260507220549.209113-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:21 +02:00
Marek VasutandCasey Connolly 246b0f185a gpio: qcom_pmic: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260507220549.209113-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:21 +02:00
Biswapriyo NathandCasey Connolly 60bc1eb8c2 drivers: pinctrl: Add Qualcomm SM6125 TLMM driver
Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on SM6125 SoC, with support for special pins.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
soc98: input: 1 [x] mmc@4784000.cd-gpios
soc98: input: 0 [x] mmc@4784000.cd-gpios
Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-3-9cf4c556557a@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Biswapriyo NathandCasey Connolly b6470f662a qcom_defconfig: Enable SM6125 clock driver
Enable the driver so that SM6125 devices can boot with qcom_defconfig.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
soc98: input: 1 [x] mmc@4784000.cd-gpios
soc98: input: 0 [x] mmc@4784000.cd-gpios
Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-2-9cf4c556557a@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Biswapriyo NathandCasey Connolly 140f248556 clk/qcom: Add SM6125 clock driver
Add clock driver for the GCC block found in the SM6125 SoC.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
soc98: input: 1 [x] mmc@4784000.cd-gpios
soc98: input: 0 [x] mmc@4784000.cd-gpios
Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-1-9cf4c556557a@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Quentin SchulzandCasey Connolly 218cbc4b12 cmd: ufetch: only show comma separator if there was a previous feature
Currently, if NET is disabled, the next feature to be printed will start
with a comma and a space which is not pretty. Add the comma and
whitespace only when a previous feature has already been shown.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260505-ufetch-net-v3-2-eee5eb9ca5ce@cherry.de
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Quentin SchulzandCasey Connolly 53e6ccc0c1 cmd: ufetch: show net feature when NET_LWIP is selected
We've had a new lwIP networking stack for a couple of years already, so
let's show there is a "net" feature if it's selected. Since NET_LEGACY
|| NET_LWIP is the same as NET, let's check on NET.

Reported-by: Simon Glass <sjg@chromium.org>
Closes: https://lore.kernel.org/u-boot/CAFLszTgZC1FGy8965pHiG-u=FhrguftRv41ghQ_Qb_RRXx6tyg@mail.gmail.com/
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://patch.msgid.link/20260505-ufetch-net-v3-1-eee5eb9ca5ce@cherry.de
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Timple Raj MandCasey Connolly 8fce24a418 serial: msm-geni: configure RX watermark register
The SE_GENI_RX_WATERMARK_REG was not being programmed in the RX
setup paths. Set it to DEF_RX_WM (2) in qcom_geni_serial_start_rx(),
msm_geni_serial_setup_rx() and _debug_uart_init() to align with the
Linux kernel driver behaviour.

Without this, the RX FIFO watermark interrupt threshold is left at
its hardware reset value, which may differ from the expected value
and can cause RX data loss or missed watermark interrupts.

Link: https://lore.kernel.org/all/20200227132223.864425794@linuxfoundation.org/
Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
Signed-off-by: Gurumoorthy Santhakumar <gurumoorthy.santhakumar@oss.qualcomm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Csey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260421044555.368486-1-gurumoorthy.santhakumar@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Aswin MuruganandCasey Connolly c9eb2d64e2 dts: lemans-evk-u-boot: add override dtsi
Add initial support for the lemans EVK platform based on lemans SoC.
Define memory layout statically.

Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260424104237.968195-1-sumit.garg@kernel.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Balaji SelvanathanandCasey Connolly 6d2bcb6398 ufs: qcom: Remove redundant POST_CHANGE clock setup call
The ufs_qcom_init() function was calling ufs_qcom_setup_clocks() with
POST_CHANGE twice. The first call after setting PA_TXHSADAPTTYPE
correctly enables the device reference clock. The second call after
ufs_qcom_advertise_quirks() is redundant as the clock is already
enabled.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-7-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Balaji SelvanathanandCasey Connolly 83edbe9426 drivers: ufs: qcom: Initialize and enable clocks before hardware access
Move UFS clock initialization and enabling before hardware setup
to ensure clocks are running when accessing UFS registers.

Previously, U-Boot depended on earlier bootloader stages to
initialize UFS clocks. When these bootloaders failed to do so,
UFS registers became inaccessible, causing initialization to fail.
This change makes U-Boot initialize and enable UFS clocks early
in the init sequence, removing the dependency on previous
bootloaders.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-6-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:14 +02:00
Balaji SelvanathanandCasey Connolly 7e670b7d6e clk: qcom: sc7280: Add UFS clock support
Add UFS clock support for sc7280 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:13 +02:00
Balaji SelvanathanandCasey Connolly 213edfd645 clk: qcom: qcs615: Add UFS clock support
Add UFS clock support for qcs615 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:13 +02:00
Balaji SelvanathanandCasey Connolly 4b1580e060 clk: qcom: sa8775p: Add UFS clock support
Add UFS clock support for SA8775P including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:13 +02:00
Balaji SelvanathanandCasey Connolly be1dc88b4a clk: qcom: clk-stub: Add compatibles for QCS615/SA8775P
Add RPMH clock compatible strings for QCS615 and SA8775P
SoCs to enable clock framework support on these platforms.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-2-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:13 +02:00
Balaji SelvanathanandCasey Connolly 40b43c94d2 clk: stub: Sort compatible strings alphabetically
Reorder compatible strings in stub_clk_ids to maintain alphabetical
order for easier maintenance.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-1-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-05-18 11:04:13 +02:00
Tom Rini dc4dd58926 Merge tag 'u-boot-imx-next-20260515' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/30134

- Several conversions to OF_UPSTREAM.
- Added i.MX9 Quickboot support.
- Added support for i.MX952 in the fsl_enetc driver.
- Update i.MX91 part number detection.
2026-05-15 17:32:13 -06:00
Ye LiandFabio Estevam 9e46861a01 net: fsl_enetc: Add support for i.MX952
Extend ENETC driver to support i.MX952 platform where 2 ENETC
controllers are located on different PCIe buses.

Key changes:
- Add enetc_dev_id_imx() to derive device ID from device tree "reg"
  property for i.MX952, mapping bus_devfn values 0x0 and 0x100 to device
  IDs 0 and 1 respectively
- Implement imx952_netcmix_init() to configure MII protocol and PCS
  settings based on PHY mode parsed from device tree
- Add i.MX952 to FSL_ENETC_NETC_BLK_CTRL Kconfig dependencies

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:40 -03:00
Clark WangandFabio Estevam 11af22cd1e net: fsl_enetc: fix the duplex setting on the iMX platform
The iMX and LS platforms use different bits in the same register to
set duplex, but their logics are opposite.
The current settings will result in unexpected configurations in
RGMII mode.

Fixes: e6df2f5e22 ("net: fsl_enetc: Update enetc driver to support i.MX95")
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
2026-05-15 17:31:40 -03:00
Ye LiandFabio Estevam a8684df5ed arm: imx9: Update i.MX91 part number detection
Change to not use NXP_RECOG fuse, but detect part number according
to feature disable fuses and SPEED fuse.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:40 -03:00
Ye LiandFabio Estevam 3ebee64e81 imx: priblob: Fix build break
Add config.h to fix CAAM_BASE_ADDR undeclared build error when
CONFIG_CMD_PRIBLOB enabled.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Francois BerderandFabio Estevam 1b0c1407d8 power: regulator: pfuze100: Fix unchecked pmic_reg_read, return value
pmic_reg_read returns a negative value if an error occurs. This
commit adds a missing check after calling pmic_reg_read.

Signed-off-by: Francois Berder <fberder@outlook.fr>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-05-15 17:31:39 -03:00
Peng FanandFabio Estevam cbd2dc2bdd arm: mx6: module_fuse: update node path for Linux 6.13
Update node path for 5.10 Kernel.
 - aips-bus renamed to bus
 - gpmi-nand renamed to nand-controller

cherry picked from https://github.com/nxp-imx/uboot-imx,
tag lf-6.12.3-1.0.0,
commit feb8178e97d4 ("LF-2637 mx6: fuse: update node path")

add changes node path for Linux 6.13

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
2026-05-15 17:31:39 -03:00
Marek VasutandFabio Estevam 5efdfae304 arm: mx6: cm-fx6: Staticize and constify driver ops
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-05-15 17:31:39 -03:00
Antoine GoubyandFabio Estevam 454e72874f board: toradex: verdin-imx95: remove gpio1 reg
The RGPIO2P driver contains legacy handling for compatible combinations
that expose two reg ranges (dual base) for i.MX8ULP and i.MX93.

The i.MX95 GPIO controller exposes a single register range, so the
dual-base handling is unnecessary.

Additionally, the second address of the gpio1 reg property was wrong.
When used, it needs to be offsetted by 0x40 to start at the Port Data
Output register.

Fixes: 60d8255d8d ("board: toradex: add Toradex Verdin iMX95")
Signed-off-by: Antoine Gouby <antoine.gouby@toradex.com>
2026-05-15 17:31:39 -03:00
Antoine GoubyandFabio Estevam 85319b2e67 board: toradex: smarc-imx95: remove gpio1 reg
The RGPIO2P driver contains legacy handling for compatible combinations
that expose two reg ranges (dual base) for i.MX8ULP and i.MX93.

The i.MX95 GPIO controller exposes a single register range, so the
dual-base handling is unnecessary.

Signed-off-by: Antoine Gouby <antoine.gouby@toradex.com>
2026-05-15 17:31:39 -03:00
Simona ToacaandFabio Estevam dffae7d2a6 doc: board: nxp: Add Quickboot documentation
Add instructions on how to use U-Boot to save
DDR training data to NVM and explain the saving
process.

Signed-off-by: Simona Toaca <simona.toaca@nxp.com>
2026-05-15 17:31:39 -03:00
Simona ToacaandFabio Estevam b37fa572ad board: nxp: imx9{4, 5, 52}_evk: Add qb save option in SPL
Call qb save automatically in the board-specific
spl_board_init(), if SPL_IMX_QB option is enabled.
This makes sure qb_save is called before any image
loading is done by the SPL. This option is also
suitable for the case where U-Boot proper is
missing (Falcon mode).

qb save refers to saving DDR training data to NVM,
so that OEI runs Quickboot flow on next reboot,
skipping full training and achieveing a lower boot
time.

Signed-off-by: Simona Toaca <simona.toaca@nxp.com>
2026-05-15 17:31:39 -03:00
Simona ToacaandFabio Estevam 36755f64b3 arm: mach-imx: Add command to expose QB functionality
This command exposes 3 methods:
- check -> checks if the data in volatile memory is valid
	   (integrity check)
- save  -> saves the data to non-volatile memory and
	   erases the data in volatile memory
- erase	-> erases the data in non-volatile memory

cmd_qb can be used either directly in the U-Boot console
or in an uuu script to save the QB data during flashing.
It supports specifying a different boot medium than the
current boot device for saving the data.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Simona Toaca <simona.toaca@nxp.com>
2026-05-15 17:31:39 -03:00
Simona ToacaandFabio Estevam c9a8f673e0 imx9: Add support for saving DDR training data to NVM
DDR training data can be saved to NVM and be available
to OEI at boot time, which will trigger QuickBoot flow.

U-Boot only checks for data integrity (CRC32), while
OEI is in charge of authentication when it tries to
load the data from NVM.

On iMX95 A0/A1, 'authentication' is done via another
CRC32. On the other SoCs, authentication is done by
using ELE to check the MAC stored in the ddrphy_qb_state
structure.

Supported platforms: iMX94, iMX95, iMX952 (using OEI)
Supported storage types: eMMC, SD, SPI flash.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Simona Toaca <simona.toaca@nxp.com>
2026-05-15 17:31:39 -03:00