vhaudiquet/u-boot-krane
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: qcom: sc7280: Add UFS clock support

Browse Source 
Add UFS clock support for sc7280 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
This commit is contained in:
Balaji Selvanathan
2026-05-18 11:04:13 +02:00
committed by Casey Connolly
parent 213edfd645
commit 7e670b7d6e
1 changed files with 52 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/clk/qcom/clock-sc7280.c
+52
View File
@@ -23,6 +23,10 @@
#define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058
#define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c
#define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054
#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77024
#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x7706c
#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x770a0
#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77084
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
@@ -54,6 +58,33 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),
F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),
F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),
F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),
{ }
};
static ulong sc7280_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -103,6 +134,26 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)
case GCC_PCIE1_PHY_RCHNG_CLK:
clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);
return 100000000;
case GCC_UFS_PHY_AXI_CLK:
freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
freq->pre_div, freq->m, freq->n, freq->src, 8);
return freq->freq;
case GCC_UFS_PHY_ICE_CORE_CLK:
freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
freq->pre_div, freq->m, freq->n, freq->src, 8);
return freq->freq;
case GCC_UFS_PHY_PHY_AUX_CLK:
freq = qcom_find_freq(ftbl_gcc_ufs_phy_phy_aux_clk_src, rate);
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR,
freq->pre_div, freq->m, freq->n, freq->src, 8);
return freq->freq;
case GCC_UFS_PHY_UNIPRO_CORE_CLK:
freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
freq->pre_div, freq->m, freq->n, freq->src, 8);
return freq->freq;
default:
return rate;
}
@@ -148,6 +199,7 @@ static const struct gate_clk sc7280_clks[] = {
GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)),
GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)),
GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0)),
GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)),
GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)),
GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)),