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clk: qcom: qcs615: Add UFS clock support

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Add UFS clock support for qcs615 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
This commit is contained in:
Balaji Selvanathan
2026-05-18 11:04:13 +02:00
committed by Casey Connolly
parent 4b1580e060
commit 213edfd645
1 changed files with 62 additions and 1 deletions
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drivers/clk/qcom/clock-qcs615.c
+62 -1
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@@ -19,6 +19,11 @@
#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c
#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf060
#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77020
#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x77048
#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77060
#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x7707c
#define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
#define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
#define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)
@@ -33,9 +38,37 @@
#define GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT BIT(26)
#define GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT BIT(27)
/* UFS PHY AXI clock frequency table */
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
{ }
};
/* UFS PHY ICE CORE clock frequency table */
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
{ }
};
/* UFS PHY UNIPRO CORE clock frequency table */
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
F(75000000, CFG_CLK_SRC_GPLL0, 8, 0, 0),
F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
{ }
};
static ulong qcs615_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
const struct freq_tbl *freq;
if (clk->id < priv->data->num_clks)
debug("%s: %s, requested rate=%ld\n", __func__,
@@ -52,6 +85,24 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)
5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
return rate;
case GCC_UFS_PHY_AXI_CLK:
freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
freq->pre_div, freq->m, freq->n, freq->src, 8);
return freq->freq;
case GCC_UFS_PHY_UNIPRO_CORE_CLK:
freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
freq->pre_div, freq->m, freq->n, freq->src, 8);
return freq->freq;
case GCC_UFS_PHY_ICE_CORE_CLK:
freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
freq->pre_div, freq->m, freq->n, freq->src, 8);
return freq->freq;
case GCC_UFS_PHY_PHY_AUX_CLK:
clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
return 19200000;
default:
return 0;
}
@@ -81,7 +132,17 @@ static const struct gate_clk qcs615_clks[] = {
GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT),
GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT),
GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)),
GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0))
GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)),
/* UFS clocks */
GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0)),
GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0)),
GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0)),
GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0)),
GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0)),
GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0)),
GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0)),
GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)),
};
static int qcs615_enable(struct clk *clk)