Merge tag 'qcom-next-18May2026' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon into next
- SM6125 gains initial support - The qcom clock drivers get better support for configuring UFS clocks - ufetch gets some aesthetic improvements - A minor bug in the qcm2290 clock driver is fixed - A few qcom drivers get static/constified - The GENI serial driver has the RX watermark register properly set
This commit is contained in:
Tom Rini
@@ -0,0 +1,19 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/ {
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/* Will be removed when bootloader updates later */
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x3ee00000>,
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<0x0 0xc0000000 0x0 0x0fd00000>,
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<0xD 0x00000000 0x2 0x54100000>,
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<0xA 0x80000000 0x1 0x80000000>,
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<0x9 0x00000000 0x1 0x80000000>,
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<0x1 0x00000000 0x3 0x00000000>,
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<0x0 0xd0000000 0x0 0x01900000>,
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<0x0 0xd3500000 0x0 0x2cb00000>;
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};
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};
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@@ -40,6 +40,7 @@ bootmenu_6=Dump clocks=clk dump; pause
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bootmenu_7=Dump environment=printenv; pause
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bootmenu_8=Board info=bdinfo; pause
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bootmenu_9=Dump bootargs=fdt print /chosen bootargs; pause
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bootmenu_10=Power off=poweroff
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# Allow holding the volume down button while U-Boot loads to enter
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# the boot menu
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+20
-9
@@ -157,26 +157,37 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc,
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printf(" (%d baud)", gd->baudrate);
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putc('\n');
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break;
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case FEATURES:
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case FEATURES: {
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const char *sep = "";
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printf("Features:" RESET " ");
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if (IS_ENABLED(CONFIG_NET_LEGACY))
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printf("Net");
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if (IS_ENABLED(CONFIG_EFI_LOADER))
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printf(", EFI");
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if (IS_ENABLED(CONFIG_CMD_CAT))
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printf(", cat :3");
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if (IS_ENABLED(CONFIG_NET)) {
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printf("%sNet", sep);
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sep = ", ";
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}
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if (IS_ENABLED(CONFIG_EFI_LOADER)) {
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printf("%sEFI", sep);
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sep = ", ";
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}
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if (IS_ENABLED(CONFIG_CMD_CAT)) {
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printf("%scat :3", sep);
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sep = ", ";
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}
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#ifdef CONFIG_ARM64
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switch (current_el()) {
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case 2:
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printf(", VMs");
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printf("%sVMs", sep);
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sep = ", ";
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break;
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case 3:
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printf(", full control!");
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printf("%sfull control!", sep);
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sep = ", ";
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break;
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}
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#endif
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printf("\n");
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break;
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}
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case RELOCATION:
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if (gd->flags & GD_FLG_SKIP_RELOC)
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printf("Relocated:" RESET " no\n");
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@@ -38,6 +38,7 @@ CONFIG_CMD_DFU=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_POWEROFF=y
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CONFIG_CMD_UFS=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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@@ -65,6 +66,7 @@ CONFIG_CLK_QCOM_QCS8300=y
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CONFIG_CLK_QCOM_SA8775P=y
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CONFIG_CLK_QCOM_SDM845=y
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CONFIG_CLK_QCOM_SM6115=y
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CONFIG_CLK_QCOM_SM6125=y
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CONFIG_CLK_QCOM_SM6350=y
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CONFIG_CLK_QCOM_SM7150=y
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CONFIG_CLK_QCOM_SM8150=y
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@@ -49,11 +49,13 @@ static struct clk_ops stub_clk_ops = {
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};
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static const struct udevice_id stub_clk_ids[] = {
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{ .compatible = "qcom,qcs615-rpmh-clk" },
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{ .compatible = "qcom,rpmcc" },
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{ .compatible = "qcom,sdm670-rpmh-clk" },
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{ .compatible = "qcom,sdm845-rpmh-clk" },
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{ .compatible = "qcom,sa8775p-rpmh-clk" },
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{ .compatible = "qcom,sc7180-rpmh-clk" },
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{ .compatible = "qcom,sc7280-rpmh-clk" },
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{ .compatible = "qcom,sdm670-rpmh-clk" },
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{ .compatible = "qcom,sdm845-rpmh-clk" },
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{ .compatible = "qcom,sm6350-rpmh-clk" },
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{ .compatible = "qcom,sm8150-rpmh-clk" },
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{ .compatible = "qcom,sm8250-rpmh-clk" },
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@@ -111,6 +111,14 @@ config CLK_QCOM_SM6115
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on the Snapdragon SM6115 SoC. This driver supports the clocks
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and resets exposed by the GCC hardware block.
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config CLK_QCOM_SM6125
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bool "Qualcomm SM6125 GCC"
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select CLK_QCOM
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help
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Say Y here to enable support for the Global Clock Controller
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on the Snapdragon SM6125 SoC. This driver supports the clocks
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and resets exposed by the GCC hardware block.
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config CLK_QCOM_SM6350
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bool "Qualcomm SM6350 GCC"
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select CLK_QCOM
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@@ -17,6 +17,7 @@ obj-$(CONFIG_CLK_QCOM_QCS615) += clock-qcs615.o
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obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
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obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
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obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
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obj-$(CONFIG_CLK_QCOM_SM6125) += clock-sm6125.o
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obj-$(CONFIG_CLK_QCOM_SM6350) += clock-sm6350.o
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obj-$(CONFIG_CLK_QCOM_SM7150) += clock-sm7150.o
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obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
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@@ -73,7 +73,7 @@ static const struct pll_vote_clk gpll6_clk = {
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.status = 0x6000,
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.status_bit = BIT(31),
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.ena_vote = 0x79000,
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.vote_bit = BIT(7),
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.vote_bit = BIT(6),
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};
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static const struct gate_clk qcm2290_clks[] = {
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@@ -19,6 +19,11 @@
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#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c
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#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf060
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#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77020
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#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x77048
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#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77060
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#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x7707c
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#define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
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#define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
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#define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)
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@@ -33,9 +38,37 @@
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#define GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT BIT(26)
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#define GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT BIT(27)
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/* UFS PHY AXI clock frequency table */
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static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
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F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
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F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
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F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
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F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
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F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
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{ }
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};
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/* UFS PHY ICE CORE clock frequency table */
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static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
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F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
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F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
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F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
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F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
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{ }
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};
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/* UFS PHY UNIPRO CORE clock frequency table */
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static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
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F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0),
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F(75000000, CFG_CLK_SRC_GPLL0, 8, 0, 0),
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F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
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{ }
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};
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static ulong qcs615_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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const struct freq_tbl *freq;
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if (clk->id < priv->data->num_clks)
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debug("%s: %s, requested rate=%ld\n", __func__,
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@@ -52,6 +85,24 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)
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5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
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clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
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return rate;
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case GCC_UFS_PHY_AXI_CLK:
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freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
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clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
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freq->pre_div, freq->m, freq->n, freq->src, 8);
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return freq->freq;
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case GCC_UFS_PHY_UNIPRO_CORE_CLK:
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freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
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clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
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freq->pre_div, freq->m, freq->n, freq->src, 8);
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return freq->freq;
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case GCC_UFS_PHY_ICE_CORE_CLK:
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freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
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clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
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freq->pre_div, freq->m, freq->n, freq->src, 8);
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return freq->freq;
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case GCC_UFS_PHY_PHY_AUX_CLK:
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clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
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return 19200000;
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default:
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return 0;
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}
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@@ -81,7 +132,17 @@ static const struct gate_clk qcs615_clks[] = {
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GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT),
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GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT),
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GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)),
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GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0))
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GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)),
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/* UFS clocks */
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GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
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GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0)),
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GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0)),
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GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0)),
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GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0)),
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GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0)),
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GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0)),
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GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0)),
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GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)),
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};
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static int qcs615_enable(struct clk *clk)
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@@ -19,6 +19,11 @@
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#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0x1b028
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#define USB3_PRIM_PHY_AUX_CMD_RCGR 0x1b06c
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#define UFS_PHY_AXI_CLK_CMD_RCGR 0x8302c
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#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x83074
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#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x830a8
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#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x8308c
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#define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
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#define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
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#define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)
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@@ -44,9 +49,35 @@
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#define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25)
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/* UFS AXI clock frequency table */
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static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
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F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
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F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
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F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
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F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
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{ }
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};
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|
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/* UFS ICE CORE clock frequency table */
|
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static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
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F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
|
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F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
|
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F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
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{ }
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};
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/* UFS UNIPRO CORE clock frequency table */
|
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static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
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F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
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F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
|
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F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
|
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{ }
|
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};
|
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|
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static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
|
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{
|
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
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const struct freq_tbl *freq;
|
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|
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if (clk->id < priv->data->num_clks)
|
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debug("%s: %s, requested rate=%ld\n", __func__,
|
||||
@@ -63,6 +94,24 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
|
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5, 0, 0, CFG_CLK_SRC_GPLL0, 8);
|
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clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
|
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return rate;
|
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case GCC_UFS_PHY_AXI_CLK:
|
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freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
|
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clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
|
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freq->pre_div, freq->m, freq->n, freq->src, 8);
|
||||
return freq->freq;
|
||||
case GCC_UFS_PHY_UNIPRO_CORE_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 8);
|
||||
return freq->freq;
|
||||
case GCC_UFS_PHY_ICE_CORE_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 8);
|
||||
return freq->freq;
|
||||
case GCC_UFS_PHY_PHY_AUX_CLK:
|
||||
clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
|
||||
return 19200000;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
@@ -106,6 +155,20 @@ static const struct gate_clk sa8775p_clks[] = {
|
||||
|
||||
/* QUP Wrapper 3 clocks */
|
||||
GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT),
|
||||
|
||||
/* UFS PHY clocks */
|
||||
GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1),
|
||||
GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1),
|
||||
GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1),
|
||||
GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1),
|
||||
GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, 1),
|
||||
GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, 1),
|
||||
GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, 1),
|
||||
GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, 1),
|
||||
GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, 1),
|
||||
|
||||
/* EDP reference clock (used by UFS PHY) */
|
||||
GATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, 1),
|
||||
};
|
||||
|
||||
static int sa8775p_enable(struct clk *clk)
|
||||
|
||||
@@ -23,6 +23,10 @@
|
||||
#define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058
|
||||
#define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c
|
||||
#define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054
|
||||
#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77024
|
||||
#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x7706c
|
||||
#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x770a0
|
||||
#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77084
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
|
||||
F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
|
||||
@@ -54,6 +58,33 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
|
||||
F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
|
||||
F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
|
||||
F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),
|
||||
F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
|
||||
F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
|
||||
F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),
|
||||
F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
|
||||
F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
|
||||
F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
|
||||
F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0),
|
||||
F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static ulong sc7280_set_rate(struct clk *clk, ulong rate)
|
||||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
@@ -103,6 +134,26 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)
|
||||
case GCC_PCIE1_PHY_RCHNG_CLK:
|
||||
clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);
|
||||
return 100000000;
|
||||
case GCC_UFS_PHY_AXI_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 8);
|
||||
return freq->freq;
|
||||
case GCC_UFS_PHY_ICE_CORE_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 8);
|
||||
return freq->freq;
|
||||
case GCC_UFS_PHY_PHY_AUX_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_ufs_phy_phy_aux_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 8);
|
||||
return freq->freq;
|
||||
case GCC_UFS_PHY_UNIPRO_CORE_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
|
||||
freq->pre_div, freq->m, freq->n, freq->src, 8);
|
||||
return freq->freq;
|
||||
default:
|
||||
return rate;
|
||||
}
|
||||
@@ -148,6 +199,7 @@ static const struct gate_clk sc7280_clks[] = {
|
||||
GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
|
||||
GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)),
|
||||
|
||||
@@ -0,0 +1,260 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Clock drivers for Qualcomm sm6125
|
||||
*
|
||||
* (C) Copyright 2026 Biswapriyo Nath <nathbappai@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/bug.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
|
||||
|
||||
#include "clock-qcom.h"
|
||||
|
||||
#define GCC_BASE 0x01400000
|
||||
|
||||
#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608
|
||||
#define SDCC1_APPS_CLK_CMD_RCGR 0x38028
|
||||
#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c
|
||||
|
||||
#define GCC_GPLL0_MODE 0x0
|
||||
#define GCC_GPLL3_MODE 0x3000
|
||||
#define GCC_GPLL4_MODE 0x4000
|
||||
#define GCC_GPLL5_MODE 0x5000
|
||||
#define GCC_GPLL6_MODE 0x6000
|
||||
#define GCC_GPLL7_MODE 0x7000
|
||||
#define GCC_GPLL8_MODE 0x8000
|
||||
#define GCC_GPLL9_MODE 0x9000
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
|
||||
F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625),
|
||||
F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625),
|
||||
F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
|
||||
F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625),
|
||||
F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75),
|
||||
F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25),
|
||||
F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75),
|
||||
F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0),
|
||||
F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15),
|
||||
F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25),
|
||||
F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
|
||||
F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375),
|
||||
F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75),
|
||||
F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625),
|
||||
F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0),
|
||||
F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0),
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
|
||||
F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
|
||||
F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
|
||||
F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0),
|
||||
F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0),
|
||||
F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0),
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct pll_vote_clk gpll0_clk = {
|
||||
.status = 0,
|
||||
.status_bit = BIT(31),
|
||||
.ena_vote = 0x79000,
|
||||
.vote_bit = BIT(0),
|
||||
};
|
||||
|
||||
static const struct gate_clk sm6125_clks[] = {
|
||||
GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, BIT(0)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, BIT(9)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, BIT(8)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, BIT(10)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, BIT(11)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, BIT(12)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, BIT(13)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, BIT(14)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, BIT(15)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, BIT(6)),
|
||||
GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, BIT(7)),
|
||||
GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, BIT(0)),
|
||||
GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, BIT(0)),
|
||||
GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, BIT(0)),
|
||||
GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, BIT(0)),
|
||||
GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, BIT(0)),
|
||||
GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, BIT(0)),
|
||||
GATE_CLK(GCC_SYS_NOC_UFS_PHY_AXI_CLK, 0x45098, BIT(0)),
|
||||
GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x45014, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x45010, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x45044, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x45078, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x4501c, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x45018, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x45040, BIT(0)),
|
||||
GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, BIT(0)),
|
||||
GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, BIT(0)),
|
||||
GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, BIT(0)),
|
||||
GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x80278, BIT(0)),
|
||||
GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, BIT(0)),
|
||||
GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, BIT(0)),
|
||||
GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, BIT(0)),
|
||||
GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)),
|
||||
};
|
||||
|
||||
static ulong sm6125_set_rate(struct clk *clk, ulong rate)
|
||||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
const struct freq_tbl *freq;
|
||||
|
||||
debug("%s: clk %s rate %lu\n", __func__, sm6125_clks[clk->id].name,
|
||||
rate);
|
||||
|
||||
switch (clk->id) {
|
||||
case GCC_QUPV3_WRAP0_S4_CLK:
|
||||
freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR,
|
||||
freq->pre_div, freq->m, freq->n, freq->src,
|
||||
16);
|
||||
return 0;
|
||||
case GCC_SDCC2_APPS_CLK:
|
||||
clk_enable_gpll0(priv->base, &gpll0_clk);
|
||||
freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
|
||||
WARN(freq->src != CFG_CLK_SRC_GPLL0,
|
||||
"SDCC2_APPS_CLK_SRC not set to GPLL0, requested rate %lu\n",
|
||||
rate);
|
||||
clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR,
|
||||
freq->pre_div, freq->m, freq->n, freq->src,
|
||||
8);
|
||||
return freq->freq;
|
||||
case GCC_SDCC1_APPS_CLK:
|
||||
/* The firmware turns this on for us and always sets it to this rate */
|
||||
return 384000000;
|
||||
default:
|
||||
return rate;
|
||||
}
|
||||
}
|
||||
|
||||
static int sm6125_enable(struct clk *clk)
|
||||
{
|
||||
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
||||
|
||||
if (priv->data->num_clks < clk->id) {
|
||||
debug("%s: unknown clk id %lu\n", __func__, clk->id);
|
||||
return 0;
|
||||
}
|
||||
|
||||
debug("%s: clk %s\n", __func__, sm6125_clks[clk->id].name);
|
||||
|
||||
switch (clk->id) {
|
||||
case GCC_USB30_PRIM_MASTER_CLK:
|
||||
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
|
||||
qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK);
|
||||
break;
|
||||
}
|
||||
|
||||
return qcom_gate_clk_en(priv, clk->id);
|
||||
}
|
||||
|
||||
static const struct qcom_reset_map sm6125_gcc_resets[] = {
|
||||
[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
|
||||
[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
|
||||
[GCC_UFS_PHY_BCR] = { 0x45000 },
|
||||
[GCC_USB30_PRIM_BCR] = { 0x1a000 },
|
||||
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
|
||||
[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
|
||||
[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
|
||||
[GCC_CAMSS_MICRO_BCR] = { 0x560ac },
|
||||
};
|
||||
|
||||
static const struct qcom_power_map sm6125_gdscs[] = {
|
||||
[USB30_PRIM_GDSC] = { 0x1a004 },
|
||||
[UFS_PHY_GDSC] = { 0x45004 },
|
||||
[CAMSS_VFE0_GDSC] = { 0x54004 },
|
||||
[CAMSS_VFE1_GDSC] = { 0x5403c },
|
||||
[CAMSS_TOP_GDSC] = { 0x5607c },
|
||||
[CAM_CPP_GDSC] = { 0x560bc },
|
||||
[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = { 0x7d060 },
|
||||
[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = { 0x80074 },
|
||||
[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = { 0x80084 },
|
||||
[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = { 0x80094 },
|
||||
};
|
||||
|
||||
static const phys_addr_t sm6125_gpll_addrs[] = {
|
||||
GCC_BASE + GCC_GPLL0_MODE, GCC_BASE + GCC_GPLL3_MODE,
|
||||
GCC_BASE + GCC_GPLL4_MODE, GCC_BASE + GCC_GPLL5_MODE,
|
||||
GCC_BASE + GCC_GPLL6_MODE, GCC_BASE + GCC_GPLL7_MODE,
|
||||
GCC_BASE + GCC_GPLL8_MODE, GCC_BASE + GCC_GPLL9_MODE,
|
||||
};
|
||||
|
||||
static const phys_addr_t sm6125_rcg_addrs[] = {
|
||||
0x0141a01c, // GCC_USB30_PRIM_MASTER_CMD_RCGR
|
||||
0x0141a034, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR
|
||||
0x0141a060, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR
|
||||
0x01438028, // GCC_SDCC1_APPS_CMD_RCGR
|
||||
0x0141e00c, // GCC_SDCC2_APPS_CMD_RCGR
|
||||
0x0141f148, // GCC_QUPV3_WRAP0_S0_CMD_RCGR
|
||||
0x0141f278, // GCC_QUPV3_WRAP0_S1_CMD_RCGR
|
||||
0x0141f3a8, // GCC_QUPV3_WRAP0_S2_CMD_RCGR
|
||||
0x0141f4d8, // GCC_QUPV3_WRAP0_S3_CMD_RCGR
|
||||
0x0141f608, // GCC_QUPV3_WRAP0_S4_CMD_RCGR
|
||||
0x0141f738, // GCC_QUPV3_WRAP0_S5_CMD_RCGR
|
||||
0x01445020, // GCC_UFS_PHY_AXI_CMD_RCGR
|
||||
0x01445048, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR
|
||||
0x01445060, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR
|
||||
0x0144507c, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR
|
||||
};
|
||||
|
||||
static const char *const sm6125_rcg_names[] = {
|
||||
"GCC_USB30_PRIM_MASTER_CMD_RCGR",
|
||||
"GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR",
|
||||
"GCC_USB3_PRIM_PHY_AUX_CMD_RCGR",
|
||||
"GCC_SDCC1_APPS_CMD_RCGR",
|
||||
"GCC_SDCC2_APPS_CMD_RCGR",
|
||||
"GCC_QUPV3_WRAP0_S0_CMD_RCGR",
|
||||
"GCC_QUPV3_WRAP0_S1_CMD_RCGR",
|
||||
"GCC_QUPV3_WRAP0_S2_CMD_RCGR",
|
||||
"GCC_QUPV3_WRAP0_S3_CMD_RCGR",
|
||||
"GCC_QUPV3_WRAP0_S4_CMD_RCGR",
|
||||
"GCC_QUPV3_WRAP0_S5_CMD_RCGR",
|
||||
"GCC_UFS_PHY_AXI_CMD_RCGR",
|
||||
"GCC_UFS_PHY_ICE_CORE_CMD_RCGR",
|
||||
"GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR",
|
||||
"GCC_UFS_PHY_PHY_AUX_CMD_RCGR",
|
||||
};
|
||||
|
||||
static struct msm_clk_data sm6125_gcc_data = {
|
||||
.resets = sm6125_gcc_resets,
|
||||
.num_resets = ARRAY_SIZE(sm6125_gcc_resets),
|
||||
.clks = sm6125_clks,
|
||||
.num_clks = ARRAY_SIZE(sm6125_clks),
|
||||
.power_domains = sm6125_gdscs,
|
||||
.num_power_domains = ARRAY_SIZE(sm6125_gdscs),
|
||||
|
||||
.enable = sm6125_enable,
|
||||
.set_rate = sm6125_set_rate,
|
||||
|
||||
.dbg_pll_addrs = sm6125_gpll_addrs,
|
||||
.num_plls = ARRAY_SIZE(sm6125_gpll_addrs),
|
||||
.dbg_rcg_addrs = sm6125_rcg_addrs,
|
||||
.num_rcgs = ARRAY_SIZE(sm6125_rcg_addrs),
|
||||
.dbg_rcg_names = sm6125_rcg_names,
|
||||
};
|
||||
|
||||
static const struct udevice_id gcc_sm6125_of_match[] = {
|
||||
{
|
||||
.compatible = "qcom,gcc-sm6125",
|
||||
.data = (ulong)&sm6125_gcc_data,
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(gcc_sm6125) = {
|
||||
.name = "gcc_sm6125",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = gcc_sm6125_of_match,
|
||||
.bind = qcom_cc_bind,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
@@ -410,7 +410,7 @@ static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigne
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct pinctrl_ops qcom_pmic_pinctrl_ops = {
|
||||
static const struct pinctrl_ops qcom_pmic_pinctrl_ops = {
|
||||
.get_pins_count = qcom_pmic_pinctrl_get_pins_count,
|
||||
.get_pin_name = qcom_pmic_pinctrl_get_pin_name,
|
||||
.set_state = pinctrl_generic_set_state,
|
||||
|
||||
@@ -1020,7 +1020,7 @@ static int qcom_spmi_pmic_pinctrl_pinmux_set_mux(struct udevice *dev, unsigned i
|
||||
return spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_EN_CTL, val);
|
||||
}
|
||||
|
||||
struct pinctrl_ops qcom_spmi_pmic_pinctrl_ops = {
|
||||
static const struct pinctrl_ops qcom_spmi_pmic_pinctrl_ops = {
|
||||
.get_pins_count = qcom_spmi_pmic_pinctrl_get_pins_count,
|
||||
.get_pin_name = qcom_spmi_pmic_pinctrl_get_pin_name,
|
||||
.set_state = pinctrl_generic_set_state,
|
||||
|
||||
@@ -22,7 +22,7 @@
|
||||
|
||||
struct qcom_pcie;
|
||||
|
||||
struct qcom_pcie_ops {
|
||||
static const struct qcom_pcie_ops {
|
||||
int (*config_sid)(struct qcom_pcie *priv);
|
||||
};
|
||||
|
||||
|
||||
@@ -1741,6 +1741,8 @@ static const struct udevice_id qmp_ufs_ids[] = {
|
||||
{ .compatible = "qcom,milos-qmp-ufs-phy", .data = (ulong)&milos_ufsphy_cfg, },
|
||||
{ .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, },
|
||||
{ .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
|
||||
{ .compatible = "qcom,sm6115-qmp-ufs-phy", .data = (ulong)&sm6115_ufsphy_cfg, },
|
||||
{ .compatible = "qcom,sm6125-qmp-ufs-phy", .data = (ulong)&sm6115_ufsphy_cfg, },
|
||||
{ .compatible = "qcom,sm6350-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
|
||||
{ .compatible = "qcom,sm7150-qmp-ufs-phy", .data = (ulong)&sm7150_ufsphy_cfg },
|
||||
{ .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg },
|
||||
|
||||
@@ -133,6 +133,14 @@ config PINCTRL_QCOM_SM6115
|
||||
Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC,
|
||||
as well as the associated GPIO driver.
|
||||
|
||||
config PINCTRL_QCOM_SM6125
|
||||
bool "Qualcomm SM6125 Pinctrl"
|
||||
default y if PINCTRL_QCOM_GENERIC
|
||||
select PINCTRL_QCOM
|
||||
help
|
||||
Say Y here to enable support for pinctrl on the Snapdragon SM6125 SoC,
|
||||
as well as the associated GPIO driver.
|
||||
|
||||
config PINCTRL_QCOM_SM6350
|
||||
bool "Qualcomm SM6350 Pinctrl"
|
||||
default y if PINCTRL_QCOM_GENERIC
|
||||
|
||||
@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_SDM670) += pinctrl-sdm670.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_SM6125) += pinctrl-sm6125.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_SM6350) += pinctrl-sm6350.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_SM7150) += pinctrl-sm7150.o
|
||||
obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
|
||||
|
||||
@@ -0,0 +1,147 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Pinctrl driver for Qualcomm SM6125
|
||||
*
|
||||
* (C) Copyright 2026 Biswapriyo Nath <nathbappai@gmail.com>
|
||||
*
|
||||
* Based on Linux Kernel driver
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
|
||||
#include "pinctrl-qcom.h"
|
||||
|
||||
#define TLMM_BASE 0x00500000
|
||||
#define WEST (0x00500000 - TLMM_BASE) /* 0x0 */
|
||||
#define SOUTH (0x00900000 - TLMM_BASE) /* 0x400000 */
|
||||
#define EAST (0x00d00000 - TLMM_BASE) /* 0x800000 */
|
||||
|
||||
#define MAX_PIN_NAME_LEN 32
|
||||
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
|
||||
|
||||
static const struct pinctrl_function msm_pinctrl_functions[] = {
|
||||
{ "qup04", 1 },
|
||||
{ "gpio", 0 },
|
||||
};
|
||||
|
||||
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
|
||||
{ \
|
||||
.name = pg_name, \
|
||||
.ctl_reg = ctl, \
|
||||
.io_reg = 0, \
|
||||
.pull_bit = pull, \
|
||||
.drv_bit = drv, \
|
||||
.oe_bit = -1, \
|
||||
.in_bit = -1, \
|
||||
.out_bit = -1, \
|
||||
}
|
||||
|
||||
#define UFS_RESET(pg_name, offset) \
|
||||
{ \
|
||||
.name = pg_name, \
|
||||
.ctl_reg = offset, \
|
||||
.io_reg = offset + 0x4, \
|
||||
.pull_bit = 3, \
|
||||
.drv_bit = 0, \
|
||||
.oe_bit = -1, \
|
||||
.in_bit = -1, \
|
||||
.out_bit = 0, \
|
||||
}
|
||||
|
||||
static const struct msm_special_pin_data msm_special_pins_data[] = {
|
||||
[0] = UFS_RESET("ufs_reset", 0x190000),
|
||||
[1] = SDC_QDSD_PINGROUP("sdc1_rclk", WEST + 0x18d000, 15, 0),
|
||||
[2] = SDC_QDSD_PINGROUP("sdc1_clk", WEST + 0x18d000, 13, 6),
|
||||
[3] = SDC_QDSD_PINGROUP("sdc1_cmd", WEST + 0x18d000, 11, 3),
|
||||
[4] = SDC_QDSD_PINGROUP("sdc1_data", WEST + 0x18d000, 9, 0),
|
||||
[5] = SDC_QDSD_PINGROUP("sdc2_clk", SOUTH + 0x58b000, 14, 6),
|
||||
[6] = SDC_QDSD_PINGROUP("sdc2_cmd", SOUTH + 0x58b000, 11, 3),
|
||||
[7] = SDC_QDSD_PINGROUP("sdc2_data", SOUTH + 0x58b000, 9, 0),
|
||||
};
|
||||
|
||||
static const unsigned int sm6125_pin_offsets[] = {
|
||||
[0] = WEST, [1] = WEST, [2] = WEST, [3] = WEST,
|
||||
[4] = WEST, [5] = WEST, [6] = WEST, [7] = WEST,
|
||||
[8] = WEST, [9] = WEST, [10] = EAST, [11] = EAST,
|
||||
[12] = EAST, [13] = EAST, [14] = WEST, [15] = WEST,
|
||||
[16] = WEST, [17] = WEST, [18] = EAST, [19] = EAST,
|
||||
[20] = EAST, [21] = EAST, [22] = WEST, [23] = WEST,
|
||||
[24] = WEST, [25] = WEST, [26] = WEST, [27] = WEST,
|
||||
[28] = WEST, [29] = WEST, [30] = WEST, [31] = WEST,
|
||||
[32] = WEST, [33] = WEST, [34] = SOUTH, [35] = SOUTH,
|
||||
[36] = SOUTH, [37] = SOUTH, [38] = EAST, [39] = EAST,
|
||||
[40] = EAST, [41] = EAST, [42] = EAST, [43] = EAST,
|
||||
[44] = SOUTH, [45] = SOUTH, [46] = SOUTH, [47] = SOUTH,
|
||||
[48] = SOUTH, [49] = SOUTH, [50] = SOUTH, [51] = SOUTH,
|
||||
[52] = SOUTH, [53] = SOUTH, [54] = SOUTH, [55] = SOUTH,
|
||||
[56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH,
|
||||
[60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH,
|
||||
[64] = SOUTH, [65] = SOUTH, [66] = SOUTH, [67] = SOUTH,
|
||||
[68] = SOUTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH,
|
||||
[72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH,
|
||||
[76] = SOUTH, [77] = SOUTH, [78] = SOUTH, [79] = SOUTH,
|
||||
[80] = SOUTH, [81] = SOUTH, [82] = SOUTH, [83] = SOUTH,
|
||||
[84] = SOUTH, [85] = SOUTH, [86] = SOUTH, [87] = WEST,
|
||||
[88] = WEST, [89] = WEST, [90] = WEST, [91] = WEST,
|
||||
[92] = WEST, [93] = WEST, [94] = SOUTH, [95] = SOUTH,
|
||||
[96] = SOUTH, [97] = SOUTH, [98] = SOUTH, [99] = SOUTH,
|
||||
[100] = SOUTH, [101] = SOUTH, [102] = SOUTH, [103] = SOUTH,
|
||||
[104] = EAST, [105] = EAST, [106] = EAST, [107] = EAST,
|
||||
[108] = EAST, [109] = EAST, [110] = EAST, [111] = EAST,
|
||||
[112] = EAST, [113] = EAST, [114] = EAST, [115] = EAST,
|
||||
[116] = EAST, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH,
|
||||
[120] = SOUTH, [121] = EAST, [122] = EAST, [123] = EAST,
|
||||
[124] = EAST, [125] = EAST, [126] = EAST, [127] = EAST,
|
||||
[128] = EAST, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH,
|
||||
[132] = SOUTH,
|
||||
};
|
||||
|
||||
static const char *sm6125_get_function_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
return msm_pinctrl_functions[selector].name;
|
||||
}
|
||||
|
||||
static const char *sm6125_get_pin_name(struct udevice *dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
if (selector >= 133 && selector <= 140)
|
||||
snprintf(pin_name, MAX_PIN_NAME_LEN,
|
||||
msm_special_pins_data[selector - 133].name);
|
||||
else
|
||||
snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
|
||||
|
||||
return pin_name;
|
||||
}
|
||||
|
||||
static int sm6125_get_function_mux(__maybe_unused unsigned int pin,
|
||||
unsigned int selector)
|
||||
{
|
||||
return msm_pinctrl_functions[selector].val;
|
||||
}
|
||||
|
||||
static struct msm_pinctrl_data sm6125_data = {
|
||||
.pin_data = {
|
||||
.pin_offsets = sm6125_pin_offsets,
|
||||
.pin_count = 141,
|
||||
.special_pins_start = 133,
|
||||
.special_pins_data = msm_special_pins_data,
|
||||
},
|
||||
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
|
||||
.get_function_name = sm6125_get_function_name,
|
||||
.get_function_mux = sm6125_get_function_mux,
|
||||
.get_pin_name = sm6125_get_pin_name,
|
||||
};
|
||||
|
||||
static const struct udevice_id msm_pinctrl_ids[] = {
|
||||
{ .compatible = "qcom,sm6125-tlmm", .data = (ulong)&sm6125_data },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pinctrl_sm6125) = {
|
||||
.name = "pinctrl_sm6125",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = msm_pinctrl_ids,
|
||||
.ops = &msm_pinctrl_ops,
|
||||
.bind = msm_pinctrl_bind,
|
||||
};
|
||||
@@ -55,6 +55,7 @@
|
||||
#define SE_UART_RX_PARITY_CFG 0x2a8
|
||||
|
||||
#define DEF_TX_WM 2
|
||||
#define DEF_RX_WM 2
|
||||
/* GENI_FORCE_DEFAULT_REG fields */
|
||||
|
||||
#define UART_START_READ 0x1
|
||||
@@ -345,6 +346,7 @@ static void qcom_geni_serial_start_rx(struct udevice *dev)
|
||||
|
||||
geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
|
||||
|
||||
writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG);
|
||||
setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
|
||||
setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
|
||||
}
|
||||
@@ -373,6 +375,7 @@ static void msm_geni_serial_setup_rx(struct udevice *dev)
|
||||
|
||||
geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
|
||||
|
||||
writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG);
|
||||
setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
|
||||
setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
|
||||
}
|
||||
@@ -616,6 +619,7 @@ static inline void _debug_uart_init(void)
|
||||
phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
|
||||
|
||||
geni_serial_init(&init_dev);
|
||||
writel(DEF_RX_WM, base + SE_GENI_RX_WATERMARK_REG);
|
||||
geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE);
|
||||
qcom_geni_serial_start_tx(base);
|
||||
}
|
||||
|
||||
+36
-18
@@ -30,6 +30,7 @@
|
||||
#define UFS_CPU_MAX_BANDWIDTH 819200
|
||||
|
||||
static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable);
|
||||
static u32 ufs_qcom_get_core_clk_unipro_max_freq(struct ufs_hba *hba);
|
||||
|
||||
static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv)
|
||||
{
|
||||
@@ -47,17 +48,6 @@ static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ufs_qcom_init_clks(struct ufs_qcom_priv *priv)
|
||||
{
|
||||
int err;
|
||||
struct udevice *dev = priv->hba->dev;
|
||||
|
||||
err = clk_get_bulk(dev, &priv->clks);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
|
||||
{
|
||||
@@ -557,10 +547,45 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable)
|
||||
static int ufs_qcom_init(struct ufs_hba *hba)
|
||||
{
|
||||
struct ufs_qcom_priv *priv = dev_get_priv(hba->dev);
|
||||
struct udevice *dev = hba->dev;
|
||||
struct clk clk;
|
||||
u32 max_freq;
|
||||
long rate;
|
||||
int err;
|
||||
|
||||
priv->hba = hba;
|
||||
|
||||
/* Get maximum frequency for core_clk_unipro from device tree */
|
||||
max_freq = ufs_qcom_get_core_clk_unipro_max_freq(hba);
|
||||
|
||||
/* Get and configure core_clk_unipro */
|
||||
err = clk_get_by_name(dev, "core_clk_unipro", &clk);
|
||||
if (err) {
|
||||
dev_err(dev, "Failed to get core_clk_unipro: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
rate = clk_set_rate(&clk, max_freq);
|
||||
if (rate < 0) {
|
||||
dev_err(dev, "Failed to set core_clk_unipro rate to %u Hz: %ld\n",
|
||||
max_freq, rate);
|
||||
}
|
||||
|
||||
/* Get all clocks */
|
||||
err = clk_get_bulk(dev, &priv->clks);
|
||||
if (err) {
|
||||
dev_err(dev, "clk_get_bulk failed: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Enable clocks */
|
||||
err = ufs_qcom_enable_clks(priv);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to enable clocks: %d\n", err);
|
||||
clk_release_bulk(&priv->clks);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* setup clocks */
|
||||
ufs_qcom_setup_clocks(hba, true, PRE_CHANGE);
|
||||
|
||||
@@ -579,14 +604,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
|
||||
priv->hw_ver.minor,
|
||||
priv->hw_ver.step);
|
||||
|
||||
err = ufs_qcom_init_clks(priv);
|
||||
if (err) {
|
||||
dev_err(hba->dev, "failed to initialize clocks, err:%d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
ufs_qcom_advertise_quirks(hba);
|
||||
ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user