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treewide: move bi_dram[] from bd to gd

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Currently, the bi_dram[] information is stored in the board info
structure (bd). Because bd is only valid after reserve_board(),
dram_init_banksize() must be called late in the initialization process.
This limitation is problematic, as it forces us to rely on a variety of
bespoke functions to determine board RAM, bank memory sizes, and other
early setup requirements.

By moving bi_dram[] into the global data (gd), we can run it earlier.
This is particularly convenient since boards define their own
dram_init_banksize() routines, which do not always rely on parsing
Device Tree (DT) memory nodes.

Additionally, U-Boot defaults to relocating to the top of the first memory
bank. While boards currently use custom functions to override this
behavior, having the DRAM bank information available earlier in gd makes
relocating to a different bank trivial and standardizes the process.

Reviewed-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Michal Simek <michal.simek@amd.com> # Versal Gen 2 Vek385
Tested-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
This commit is contained in:
Ilias Apalodimas
2026-06-24 18:13:24 -06:00
committed by Tom Rini
parent 47e9c542ee
commit 1174c99ab4
167 changed files with 705 additions and 712 deletions
Download Patch File Download Diff File Expand all files Collapse all files
api/api_platform.c
+2 -2
View File
@@ -21,8 +21,8 @@ int platform_sys_info(struct sys_info *si)
si->clk_cpu = gd->cpu_clk;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
platform_set_mr(si, gd->bd->bi_dram[i].start,
gd->bd->bi_dram[i].size, MR_ATTR_DRAM);
platform_set_mr(si, gd->dram[i].start,
gd->dram[i].size, MR_ATTR_DRAM);
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
arch/arm/cpu/armv8/cache_v8.c
+3 -3
View File
@@ -69,9 +69,9 @@ int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs)
}
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
mem_map[index].virt = gd->bd->bi_dram[i].start;
mem_map[index].phys = gd->bd->bi_dram[i].start;
mem_map[index].size = gd->bd->bi_dram[i].size;
mem_map[index].virt = gd->dram[i].start;
mem_map[index].phys = gd->dram[i].start;
mem_map[index].size = gd->dram[i].size;
mem_map[index].attrs = attrs;
index++;
}
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+59 -59
View File
@@ -538,16 +538,16 @@ static inline void final_mmu_setup(void)
*/
switch (final_map[index].virt) {
case CFG_SYS_FSL_DRAM_BASE1:
final_map[index].virt = gd->bd->bi_dram[0].start;
final_map[index].phys = gd->bd->bi_dram[0].start;
final_map[index].size = gd->bd->bi_dram[0].size;
final_map[index].virt = gd->dram[0].start;
final_map[index].phys = gd->dram[0].start;
final_map[index].size = gd->dram[0].size;
break;
#ifdef CFG_SYS_FSL_DRAM_BASE2
case CFG_SYS_FSL_DRAM_BASE2:
#if (CONFIG_NR_DRAM_BANKS >= 2)
final_map[index].virt = gd->bd->bi_dram[1].start;
final_map[index].phys = gd->bd->bi_dram[1].start;
final_map[index].size = gd->bd->bi_dram[1].size;
final_map[index].virt = gd->dram[1].start;
final_map[index].phys = gd->dram[1].start;
final_map[index].size = gd->dram[1].size;
#else
final_map[index].size = 0;
#endif
@@ -556,9 +556,9 @@ static inline void final_mmu_setup(void)
#ifdef CFG_SYS_FSL_DRAM_BASE3
case CFG_SYS_FSL_DRAM_BASE3:
#if (CONFIG_NR_DRAM_BANKS >= 3)
final_map[index].virt = gd->bd->bi_dram[2].start;
final_map[index].phys = gd->bd->bi_dram[2].start;
final_map[index].size = gd->bd->bi_dram[2].size;
final_map[index].virt = gd->dram[2].start;
final_map[index].phys = gd->dram[2].start;
final_map[index].size = gd->dram[2].size;
#else
final_map[index].size = 0;
#endif
@@ -1396,10 +1396,10 @@ static int tfa_dram_init_banksize(void)
}
debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2);
gd->bd->bi_dram[i].start = res.a1;
gd->bd->bi_dram[i].size = res.a2;
gd->dram[i].start = res.a1;
gd->dram[i].size = res.a2;
dram_size -= gd->bd->bi_dram[i].size;
dram_size -= gd->dram[i].size;
i++;
} while (dram_size);
@@ -1410,24 +1410,24 @@ static int tfa_dram_init_banksize(void)
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bd->bi_dram[2].size >=
board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[2].start +
gd->bd->bi_dram[2].size -
board_reserve_ram_top(gd->bd->bi_dram[2].size);
if (gd->dram[2].size >=
board_reserve_ram_top(gd->dram[2].size)) {
gd->arch.resv_ram = gd->dram[2].start +
gd->dram[2].size -
board_reserve_ram_top(gd->dram[2].size);
} else
#endif
{
if (gd->bd->bi_dram[1].size >=
board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[1].start +
gd->bd->bi_dram[1].size -
board_reserve_ram_top(gd->bd->bi_dram[1].size);
} else if (gd->bd->bi_dram[0].size >
board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size -
board_reserve_ram_top(gd->bd->bi_dram[0].size);
if (gd->dram[1].size >=
board_reserve_ram_top(gd->dram[1].size)) {
gd->arch.resv_ram = gd->dram[1].start +
gd->dram[1].size -
board_reserve_ram_top(gd->dram[1].size);
} else if (gd->dram[0].size >
board_reserve_ram_top(gd->dram[0].size)) {
gd->arch.resv_ram = gd->dram[0].start +
gd->dram[0].size -
board_reserve_ram_top(gd->dram[0].size);
}
}
#endif /* CONFIG_RESV_RAM */
@@ -1464,30 +1464,30 @@ int dram_init_banksize(void)
}
#endif
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[1].size = gd->ram_size -
gd->dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
gd->dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
gd->dram[1].size = gd->ram_size -
CFG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
if (gd->dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
gd->dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
gd->dram[2].size = gd->dram[1].size -
CONFIG_SYS_DDR_BLOCK2_SIZE;
gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
gd->dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
}
#endif
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].size = gd->ram_size;
}
#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->bd->bi_dram[0].size >
if (gd->dram[0].size >
CFG_SYS_MEM_RESERVE_SECURE) {
gd->bd->bi_dram[0].size -=
gd->dram[0].size -=
CFG_SYS_MEM_RESERVE_SECURE;
gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size;
gd->arch.secure_ram = gd->dram[0].start +
gd->dram[0].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
}
@@ -1496,24 +1496,24 @@ int dram_init_banksize(void)
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bd->bi_dram[2].size >=
board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[2].start +
gd->bd->bi_dram[2].size -
board_reserve_ram_top(gd->bd->bi_dram[2].size);
if (gd->dram[2].size >=
board_reserve_ram_top(gd->dram[2].size)) {
gd->arch.resv_ram = gd->dram[2].start +
gd->dram[2].size -
board_reserve_ram_top(gd->dram[2].size);
} else
#endif
{
if (gd->bd->bi_dram[1].size >=
board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[1].start +
gd->bd->bi_dram[1].size -
board_reserve_ram_top(gd->bd->bi_dram[1].size);
} else if (gd->bd->bi_dram[0].size >
board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
gd->arch.resv_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size -
board_reserve_ram_top(gd->bd->bi_dram[0].size);
if (gd->dram[1].size >=
board_reserve_ram_top(gd->dram[1].size)) {
gd->arch.resv_ram = gd->dram[1].start +
gd->dram[1].size -
board_reserve_ram_top(gd->dram[1].size);
} else if (gd->dram[0].size >
board_reserve_ram_top(gd->dram[0].size)) {
gd->arch.resv_ram = gd->dram[0].start +
gd->dram[0].size -
board_reserve_ram_top(gd->dram[0].size);
}
}
#endif /* CONFIG_RESV_RAM */
@@ -1535,8 +1535,8 @@ int dram_init_banksize(void)
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
NULL, NULL, NULL);
if (dp_ddr_size) {
gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
gd->bd->bi_dram[2].size = dp_ddr_size;
gd->dram[2].start = CONFIG_SYS_DP_DDR_BASE;
gd->dram[2].size = dp_ddr_size;
} else {
puts("Not detected");
}
@@ -1567,8 +1567,8 @@ void lmb_arch_add_memory(void)
if (i == 2)
continue; /* skip DP-DDR */
#endif
ram_start = gd->bd->bi_dram[i].start;
ram_size = gd->bd->bi_dram[i].size;
ram_start = gd->dram[i].start;
ram_size = gd->dram[i].size;
#ifdef CONFIG_RESV_RAM
if (gd->arch.resv_ram >= ram_start &&
gd->arch.resv_ram < ram_start + ram_size)
arch/arm/lib/bootm-fdt.c
+2 -3
View File
@@ -35,14 +35,13 @@ int arch_fixup_fdt(void *blob)
{
__maybe_unused int ret = 0;
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT)
struct bd_info *bd = gd->bd;
int bank;
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = bd->bi_dram[bank].start;
size[bank] = bd->bi_dram[bank].size;
start[bank] = gd->dram[bank].start;
size[bank] = gd->dram[bank].size;
#ifdef CONFIG_ARMV7_NONSEC
ret = armv7_apply_memory_carveout(&start[bank], &size[bank]);
if (ret)
arch/arm/lib/bootm.c
+2 -2
View File
@@ -64,8 +64,8 @@ static void setup_memory_tags(struct bd_info *bd)
params->hdr.tag = ATAG_MEM;
params->hdr.size = tag_size (tag_mem32);
params->u.mem.start = bd->bi_dram[i].start;
params->u.mem.size = bd->bi_dram[i].size;
params->u.mem.start = gd->dram[i].start;
params->u.mem.size = gd->dram[i].size;
params = tag_next (params);
}
arch/arm/lib/cache-cp15.c
+4 -5
View File
@@ -94,17 +94,16 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
__weak void dram_bank_mmu_setup(int bank)
{
struct bd_info *bd = gd->bd;
int i;
/* bd->bi_dram is available only after relocation */
/* gd->dram is available only after relocation */
if ((gd->flags & GD_FLG_RELOC) == 0)
return;
debug("%s: bank: %d\n", __func__, bank);
for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
(bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
for (i = gd->dram[bank].start >> MMU_SECTION_SHIFT;
i < (gd->dram[bank].start >> MMU_SECTION_SHIFT) +
(gd->dram[bank].size >> MMU_SECTION_SHIFT);
i++)
set_section_dcache(i, DCACHE_DEFAULT_OPTION);
}
arch/arm/lib/image.c
+1 -1
View File
@@ -69,7 +69,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3)))
dst = image - text_offset;
else
dst = gd->bd->bi_dram[0].start;
dst = gd->dram[0].start;
*relocated_addr = ALIGN(dst, SZ_2M) + text_offset;
arch/arm/mach-airoha/an7581/init.c
+4 -4
View File
@@ -23,12 +23,12 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = gd->ram_base;
gd->bd->bi_dram[0].size = get_effective_memsize();
gd->dram[0].start = gd->ram_base;
gd->dram[0].size = get_effective_memsize();
if (gd->ram_size > SZ_2G) {
gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G;
gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
gd->dram[1].start = gd->ram_base + SZ_2G;
gd->dram[1].size = gd->ram_size - SZ_2G;
}
return 0;
arch/arm/mach-apple/board.c
+2 -2
View File
@@ -807,8 +807,8 @@ void build_mem_map(void)
;
/* Align RAM mapping to page boundaries */
base = gd->bd->bi_dram[0].start;
size = gd->bd->bi_dram[0].size;
base = gd->dram[0].start;
size = gd->dram[0].size;
size += (base - ALIGN_DOWN(base, SZ_4K));
base = ALIGN_DOWN(base, SZ_4K);
size = ALIGN(size, SZ_4K);
arch/arm/mach-davinci/misc.c
+2 -2
View File
@@ -33,8 +33,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = gd->ram_size;
return 0;
}
arch/arm/mach-imx/ele_ahab.c
+3 -4
View File
@@ -311,12 +311,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
static inline bool check_in_dram(ulong addr)
{
int i;
struct bd_info *bd = gd->bd;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
if (addr >= bd->bi_dram[i].start &&
addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
if (gd->dram[i].size) {
if (addr >= gd->dram[i].start &&
addr < (gd->dram[i].start + gd->dram[i].size))
return true;
}
}
arch/arm/mach-imx/imx8/ahab.c
+3 -4
View File
@@ -111,12 +111,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
static inline bool check_in_dram(ulong addr)
{
int i;
struct bd_info *bd = gd->bd;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
if (addr >= bd->bi_dram[i].start &&
addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
if (gd->dram[i].size) {
if (addr >= gd->dram[i].start &&
addr < (gd->dram[i].start + gd->dram[i].size))
return true;
}
}
arch/arm/mach-imx/imx8/cpu.c
+20 -20
View File
@@ -604,18 +604,18 @@ static void dram_bank_sort(int current_bank)
phys_size_t size;
while (current_bank > 0) {
if (gd->bd->bi_dram[current_bank - 1].start >
gd->bd->bi_dram[current_bank].start) {
start = gd->bd->bi_dram[current_bank - 1].start;
size = gd->bd->bi_dram[current_bank - 1].size;
if (gd->dram[current_bank - 1].start >
gd->dram[current_bank].start) {
start = gd->dram[current_bank - 1].start;
size = gd->dram[current_bank - 1].size;
gd->bd->bi_dram[current_bank - 1].start =
gd->bd->bi_dram[current_bank].start;
gd->bd->bi_dram[current_bank - 1].size =
gd->bd->bi_dram[current_bank].size;
gd->dram[current_bank - 1].start =
gd->dram[current_bank].start;
gd->dram[current_bank - 1].size =
gd->dram[current_bank].size;
gd->bd->bi_dram[current_bank].start = start;
gd->bd->bi_dram[current_bank].size = size;
gd->dram[current_bank].start = start;
gd->dram[current_bank].size = size;
}
current_bank--;
}
@@ -643,24 +643,24 @@ int dram_init_banksize(void)
continue;
if (start >= phys_sdram_1_start && start <= end1) {
gd->bd->bi_dram[i].start = start;
gd->dram[i].start = start;
if ((end + 1) <= end1)
gd->bd->bi_dram[i].size =
gd->dram[i].size =
end - start + 1;
else
gd->bd->bi_dram[i].size = end1 - start;
gd->dram[i].size = end1 - start;
dram_bank_sort(i);
i++;
} else if (start >= phys_sdram_2_start && start <= end2) {
gd->bd->bi_dram[i].start = start;
gd->dram[i].start = start;
if ((end + 1) <= end2)
gd->bd->bi_dram[i].size =
gd->dram[i].size =
end - start + 1;
else
gd->bd->bi_dram[i].size = end2 - start;
gd->dram[i].size = end2 - start;
dram_bank_sort(i);
i++;
@@ -670,10 +670,10 @@ int dram_init_banksize(void)
/* If error, set to the default value */
if (!i) {
gd->bd->bi_dram[0].start = phys_sdram_1_start;
gd->bd->bi_dram[0].size = phys_sdram_1_size;
gd->bd->bi_dram[1].start = phys_sdram_2_start;
gd->bd->bi_dram[1].size = phys_sdram_2_size;
gd->dram[0].start = phys_sdram_1_start;
gd->dram[0].size = phys_sdram_1_size;
gd->dram[1].start = phys_sdram_2_start;
gd->dram[1].size = phys_sdram_2_size;
}
return 0;
arch/arm/mach-imx/imx8m/soc.c
+12 -12
View File
@@ -224,11 +224,11 @@ void enable_caches(void)
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8m_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
if (gd->dram[i].start == 0)
break;
imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
imx8m_mem_map[entry].phys = gd->dram[i].start;
imx8m_mem_map[entry].virt = gd->dram[i].start;
imx8m_mem_map[entry].size = gd->dram[i].size;
imx8m_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
@@ -290,24 +290,24 @@ int dram_init_banksize(void)
sdram_b2_size = 0;
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
gd->dram[bank].start = PHYS_SDRAM;
if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
gd->dram[bank].size = optee_start - gd->dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
}
gd->bd->bi_dram[bank].start = optee_start + optee_size;
gd->bd->bi_dram[bank].size = PHYS_SDRAM +
sdram_b1_size - gd->bd->bi_dram[bank].start;
gd->dram[bank].start = optee_start + optee_size;
gd->dram[bank].size = PHYS_SDRAM +
sdram_b1_size - gd->dram[bank].start;
}
} else {
gd->bd->bi_dram[bank].size = sdram_b1_size;
gd->dram[bank].size = sdram_b1_size;
}
if (sdram_b2_size) {
@@ -315,8 +315,8 @@ int dram_init_banksize(void)
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
return -1;
}
gd->bd->bi_dram[bank].start = 0x100000000UL;
gd->bd->bi_dram[bank].size = sdram_b2_size;
gd->dram[bank].start = 0x100000000UL;
gd->dram[bank].size = sdram_b2_size;
}
return 0;
arch/arm/mach-imx/imx8ulp/soc.c
+10 -10
View File
@@ -512,11 +512,11 @@ void enable_caches(void)
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
if (gd->dram[i].start == 0)
break;
imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start;
imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start;
imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size;
imx8ulp_arm64_mem_map[entry].phys = gd->dram[i].start;
imx8ulp_arm64_mem_map[entry].virt = gd->dram[i].start;
imx8ulp_arm64_mem_map[entry].size = gd->dram[i].size;
imx8ulp_arm64_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size);
@@ -568,24 +568,24 @@ int dram_init_banksize(void)
if (ret)
return ret;
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
gd->dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
gd->dram[bank].size = optee_start - gd->dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
}
gd->bd->bi_dram[bank].start = optee_start + optee_size;
gd->bd->bi_dram[bank].size = PHYS_SDRAM +
sdram_size - gd->bd->bi_dram[bank].start;
gd->dram[bank].start = optee_start + optee_size;
gd->dram[bank].size = PHYS_SDRAM +
sdram_size - gd->dram[bank].start;
}
} else {
gd->bd->bi_dram[bank].size = sdram_size;
gd->dram[bank].size = sdram_size;
}
return 0;
arch/arm/mach-imx/imx9/scmi/soc.c
+12 -12
View File
@@ -356,11 +356,11 @@ void enable_caches(void)
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx9_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
if (gd->dram[i].start == 0)
break;
imx9_mem_map[entry].phys = gd->bd->bi_dram[i].start;
imx9_mem_map[entry].virt = gd->bd->bi_dram[i].start;
imx9_mem_map[entry].size = gd->bd->bi_dram[i].size;
imx9_mem_map[entry].phys = gd->dram[i].start;
imx9_mem_map[entry].virt = gd->dram[i].start;
imx9_mem_map[entry].size = gd->dram[i].size;
imx9_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx9_mem_map[entry].phys, imx9_mem_map[entry].size);
@@ -453,24 +453,24 @@ int dram_init_banksize(void)
sdram_b2_size = 0;
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
gd->dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
gd->dram[bank].size = optee_start - gd->dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
}
gd->bd->bi_dram[bank].start = optee_start + optee_size;
gd->bd->bi_dram[bank].size = PHYS_SDRAM +
sdram_b1_size - gd->bd->bi_dram[bank].start;
gd->dram[bank].start = optee_start + optee_size;
gd->dram[bank].size = PHYS_SDRAM +
sdram_b1_size - gd->dram[bank].start;
}
} else {
gd->bd->bi_dram[bank].size = sdram_b1_size;
gd->dram[bank].size = sdram_b1_size;
}
if (sdram_b2_size) {
@@ -478,8 +478,8 @@ int dram_init_banksize(void)
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
return -1;
}
gd->bd->bi_dram[bank].start = 0x100000000UL;
gd->bd->bi_dram[bank].size = sdram_b2_size;
gd->dram[bank].start = 0x100000000UL;
gd->dram[bank].size = sdram_b2_size;
}
return 0;
arch/arm/mach-imx/imx9/soc.c
+12 -12
View File
@@ -367,11 +367,11 @@ void enable_caches(void)
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx93_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
if (gd->dram[i].start == 0)
break;
imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start;
imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start;
imx93_mem_map[entry].size = gd->bd->bi_dram[i].size;
imx93_mem_map[entry].phys = gd->dram[i].start;
imx93_mem_map[entry].virt = gd->dram[i].start;
imx93_mem_map[entry].size = gd->dram[i].size;
imx93_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx93_mem_map[entry].phys, imx93_mem_map[entry].size);
@@ -445,24 +445,24 @@ int dram_init_banksize(void)
sdram_b2_size = 0;
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
gd->dram[bank].start = PHYS_SDRAM;
if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
gd->dram[bank].size = optee_start - gd->dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
}
gd->bd->bi_dram[bank].start = optee_start + optee_size;
gd->bd->bi_dram[bank].size = PHYS_SDRAM +
sdram_b1_size - gd->bd->bi_dram[bank].start;
gd->dram[bank].start = optee_start + optee_size;
gd->dram[bank].size = PHYS_SDRAM +
sdram_b1_size - gd->dram[bank].start;
}
} else {
gd->bd->bi_dram[bank].size = sdram_b1_size;
gd->dram[bank].size = sdram_b1_size;
}
if (sdram_b2_size) {
@@ -470,8 +470,8 @@ int dram_init_banksize(void)
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
return -1;
}
gd->bd->bi_dram[bank].start = 0x100000000UL;
gd->bd->bi_dram[bank].size = sdram_b2_size;
gd->dram[bank].start = 0x100000000UL;
gd->dram[bank].size = sdram_b2_size;
}
return 0;
arch/arm/mach-imx/mx5/mx53_dram.c
+4 -4
View File
@@ -35,11 +35,11 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
gd->dram[1].start = PHYS_SDRAM_2;
gd->dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
return 0;
}
arch/arm/mach-imx/spl.c
+2 -2
View File
@@ -375,8 +375,8 @@ void *spl_load_simple_fit_fix_load(const void *fit)
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = imx_ddr_size();
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = imx_ddr_size();
return 0;
}
arch/arm/mach-k3/k3-ddr.c
+2 -2
View File
@@ -59,8 +59,8 @@ void fixup_memory_node(struct spl_image_info *spl_image)
dram_init_banksize();
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = gd->bd->bi_dram[bank].start;
size[bank] = gd->bd->bi_dram[bank].size;
start[bank] = gd->dram[bank].start;
size[bank] = gd->dram[bank].size;
}
ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
arch/arm/mach-mvebu/alleycat5/cpu.c
+2 -2
View File
@@ -138,8 +138,8 @@ int alleycat5_dram_init_banksize(void)
/*
* Config single DRAM bank
*/
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = gd->ram_size;
return 0;
}
arch/arm/mach-mvebu/armada3700/cpu.c
+5 -5
View File
@@ -256,7 +256,7 @@ int a3700_dram_init_banksize(void)
* build_mem_map.
*/
if (last_end == dram_wins[win].base) {
gd->bd->bi_dram[bank - 1].size += size;
gd->dram[bank - 1].size += size;
last_end += size;
} else {
if (bank == CONFIG_NR_DRAM_BANKS) {
@@ -264,8 +264,8 @@ int a3700_dram_init_banksize(void)
return -ENOBUFS;
}
gd->bd->bi_dram[bank].start = dram_wins[win].base;
gd->bd->bi_dram[bank].size = size;
gd->dram[bank].start = dram_wins[win].base;
gd->dram[bank].size = size;
last_end = dram_wins[win].base + size;
++bank;
}
@@ -276,8 +276,8 @@ int a3700_dram_init_banksize(void)
* the rest with zeros.
*/
for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {
gd->bd->bi_dram[bank].start = 0;
gd->bd->bi_dram[bank].size = 0;
gd->dram[bank].start = 0;
gd->dram[bank].size = 0;
}
return 0;
arch/arm/mach-mvebu/armada8k/dram.c
+5 -5
View File
@@ -38,16 +38,16 @@ int a8k_dram_init_banksize(void)
*/
phys_size_t max_bank0_size = SZ_4G - SZ_1G;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size <= max_bank0_size) {
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].size = gd->ram_size;
return 0;
}
gd->bd->bi_dram[0].size = max_bank0_size;
gd->dram[0].size = max_bank0_size;
if (CONFIG_NR_DRAM_BANKS > 1) {
gd->bd->bi_dram[1].start = SZ_4G;
gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
gd->dram[1].start = SZ_4G;
gd->dram[1].size = gd->ram_size - max_bank0_size;
}
return 0;
arch/arm/mach-mvebu/dram.c
+3 -3
View File
@@ -294,11 +294,11 @@ int dram_init_banksize(void)
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
gd->dram[i].start = mvebu_sdram_bar(i);
gd->dram[i].size = mvebu_sdram_bs(i);
/* Clip the banksize to 1GiB if it exceeds the max size */
size += gd->bd->bi_dram[i].size;
size += gd->dram[i].size;
if (size > MVEBU_SDRAM_SIZE_MAX)
mvebu_sdram_bs_set(i, 0x40000000);
}
arch/arm/mach-omap2/am33xx/board.c
+2 -2
View File
@@ -80,8 +80,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = gd->ram_size;
return 0;
}
arch/arm/mach-omap2/omap-cache.c
+2 -3
View File
@@ -53,11 +53,10 @@ void enable_caches(void)
void dram_bank_mmu_setup(int bank)
{
struct bd_info *bd = gd->bd;
int i;
u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
u32 start = gd->dram[bank].start >> MMU_SECTION_SHIFT;
u32 size = gd->dram[bank].size >> MMU_SECTION_SHIFT;
u32 end = start + size;
debug("%s: bank: %d\n", __func__, bank);
arch/arm/mach-omap2/omap3/emif4.c
+4 -4
View File
@@ -150,10 +150,10 @@ int dram_init_banksize(void)
size0 = get_sdr_cs_size(CS0);
size1 = get_sdr_cs_size(CS1);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[0].size = size0;
gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->dram[1].size = size1;
return 0;
}
arch/arm/mach-omap2/omap3/sdrc.c
+4 -4
View File
@@ -222,10 +222,10 @@ int dram_init_banksize(void)
size0 = get_sdr_cs_size(CS0);
size1 = get_sdr_cs_size(CS1);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[0].size = size0;
gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->dram[1].size = size1;
return 0;
}
arch/arm/mach-owl/soc.c
+2 -2
View File
@@ -50,8 +50,8 @@ int dram_init(void)
/* This is called after dram_init() so use get_ram_size result */
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = gd->ram_size;
return 0;
}
arch/arm/mach-renesas/memmap-gen3.c
+4 -4
View File
@@ -70,8 +70,8 @@ void enable_caches(void)
/* Generate entires for DRAM in 32bit address space */
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start = gd->bd->bi_dram[bank].start;
size = gd->bd->bi_dram[bank].size;
start = gd->dram[bank].start;
size = gd->dram[bank].size;
/* Skip empty DRAM banks */
if (!size)
@@ -114,8 +114,8 @@ void enable_caches(void)
/* Generate entires for DRAM in 64bit address space */
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start = gd->bd->bi_dram[bank].start;
size = gd->bd->bi_dram[bank].size;
start = gd->dram[bank].start;
size = gd->dram[bank].size;
/* Skip empty DRAM banks */
if (!size)
arch/arm/mach-renesas/memmap-rzg2l.c
+2 -2
View File
@@ -67,8 +67,8 @@ void enable_caches(void)
/* Generate entries for DRAM in 32bit address space */
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start = gd->bd->bi_dram[bank].start;
size = gd->bd->bi_dram[bank].size;
start = gd->dram[bank].start;
size = gd->dram[bank].size;
/* Skip empty DRAM banks */
if (!size)
arch/arm/mach-rockchip/rk3588/rk3588.c
+4 -4
View File
@@ -243,14 +243,14 @@ int arch_cpu_init(void)
int rockchip_dram_init_banksize_fixup(struct bd_info *bd)
{
size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size;
size_t ram_top = gd->dram[1].start + gd->dram[1].size;
if (ram_top > DRAM_GAP_START) {
bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start;
gd->dram[1].size = DRAM_GAP_START - gd->dram[1].start;
if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) {
bd->bi_dram[2].start = DRAM_GAP_END;
bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start;
gd->dram[2].start = DRAM_GAP_END;
gd->dram[2].size = ram_top - gd->dram[2].start;
}
}
arch/arm/mach-rockchip/sdram.c
+21 -21
View File
@@ -171,7 +171,7 @@ static int rockchip_dram_init_banksize(void)
/*
* Rockchip guaranteed DDR_MEM is ordered so no need to worry about
* bi_dram order.
* dram order.
*/
for (i = 0, j = 0; i < ddr_info->count; i++, j++) {
phys_size_t size = ddr_info->bank[(i + ddr_info->count)];
@@ -261,8 +261,8 @@ static int rockchip_dram_init_banksize(void)
* split the region in two, one for before the
* reserved memory area and one for after.
*/
gd->bd->bi_dram[j].start = start_addr;
gd->bd->bi_dram[j].size = rsrv_start - start_addr;
gd->dram[j].start = start_addr;
gd->dram[j].size = rsrv_start - start_addr;
j++;
@@ -281,8 +281,8 @@ static int rockchip_dram_init_banksize(void)
return -ENOMEM;
}
gd->bd->bi_dram[j].start = start_addr;
gd->bd->bi_dram[j].size = size;
gd->dram[j].start = start_addr;
gd->dram[j].size = size;
}
return 0;
@@ -309,15 +309,15 @@ int dram_init_banksize(void)
ret);
/* Reserve 2M for ATF bl31 */
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
gd->dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
gd->dram[0].size = top - gd->dram[0].start;
/* Add usable memory beyond the blob of space for peripheral near 4GB */
if (ram_top > SZ_4G && top < SZ_4G) {
gd->bd->bi_dram[1].start = SZ_4G;
gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start;
gd->dram[1].start = SZ_4G;
gd->dram[1].size = ram_top - gd->dram[1].start;
} else if (ram_top > SZ_4G && top == SZ_4G) {
gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start;
gd->dram[0].size = ram_top - gd->dram[0].start;
}
#else
#ifdef CONFIG_SPL_OPTEE_IMAGE
@@ -327,23 +327,23 @@ int dram_init_banksize(void)
TRUST_PARAMETER_OFFSET);
if (tos_parameter->tee_mem.flags == 1) {
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = tos_parameter->tee_mem.phy_addr
- CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
gd->dram[1].start = tos_parameter->tee_mem.phy_addr +
tos_parameter->tee_mem.size;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
gd->dram[1].size = top - gd->dram[1].start;
} else {
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = 0x8400000;
/* Reserve 32M for OPTEE with TA */
gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0x2000000;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
gd->dram[1].start = CFG_SYS_SDRAM_BASE
+ gd->dram[0].size + 0x2000000;
gd->dram[1].size = top - gd->dram[1].start;
}
#else
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = top - gd->dram[0].start;
#endif
#endif
arch/arm/mach-snapdragon/board.c
+8 -8
View File
@@ -73,19 +73,19 @@ static int ddr_bank_cmp(const void *v1, const void *v2)
}
/* This has to be done post-relocation since gd->bd isn't preserved */
static void qcom_configure_bi_dram(void)
static void qcom_configure_dram(void)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start;
gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size;
gd->dram[i].start = prevbl_ddr_banks[i].start;
gd->dram[i].size = prevbl_ddr_banks[i].size;
}
}
int dram_init_banksize(void)
{
qcom_configure_bi_dram();
qcom_configure_dram();
return 0;
}
@@ -594,15 +594,15 @@ static void build_mem_map(void)
*/
mem_map[0].phys = 0x1000;
mem_map[0].virt = mem_map[0].phys;
mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys;
mem_map[0].size = gd->dram[0].start - mem_map[0].phys;
mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN;
for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) {
mem_map[i].phys = gd->bd->bi_dram[j].start;
for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; i++, j++) {
mem_map[i].phys = gd->dram[j].start;
mem_map[i].virt = mem_map[i].phys;
mem_map[i].size = gd->bd->bi_dram[j].size;
mem_map[i].size = gd->dram[j].size;
mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
PTE_BLOCK_INNER_SHARE;
}
arch/arm/mach-socfpga/board.c
+2 -3
View File
@@ -202,11 +202,10 @@ void board_prep_linux(struct bootm_headers *images)
void lmb_arch_add_memory(void)
{
int i;
struct bd_info *bd = gd->bd;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
if (bd->bi_dram[i].size)
lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size);
if (gd->dram[i].size)
lmb_add(gd->dram[i].start, gd->dram[i].size);
}
}
#endif
arch/arm/mach-socfpga/misc_arria10.c
+3 -4
View File
@@ -246,7 +246,6 @@ int qspi_flash_software_reset(void)
void dram_bank_mmu_setup(int bank)
{
struct bd_info *bd = gd->bd;
u32 start, size;
int i;
@@ -261,11 +260,11 @@ void dram_bank_mmu_setup(int bank)
* The default implementation of this function allows the DRAM dcache
* to be enabled only after relocation. However, to speed up ECC
* initialization, we want to be able to enable DRAM dcache before
* relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
* relocation, so we don't check GD_FLG_RELOC (this assumes gd->dram
* is set first).
*/
start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
start = gd->dram[bank].start >> MMU_SECTION_SHIFT;
size = gd->dram[bank].size >> MMU_SECTION_SHIFT;
for (i = start; i < start + size; i++)
set_section_dcache(i, DCACHE_DEFAULT_OPTION);
}
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+2 -2
View File
@@ -825,8 +825,8 @@ static int init_device(struct stm32prog_data *data,
dev->mtd = mtd;
break;
case STM32PROG_RAM:
first_addr = gd->bd->bi_dram[0].start;
last_addr = first_addr + gd->bd->bi_dram[0].size;
first_addr = gd->dram[0].start;
last_addr = first_addr + gd->dram[0].size;
dev->erase_size = 1;
break;
default:
arch/arm/mach-stm32mp/stm32mp1/cpu.c
+3 -4
View File
@@ -52,7 +52,6 @@ u32 get_bootauth(void)
*/
void dram_bank_mmu_setup(int bank)
{
struct bd_info *bd = gd->bd;
int i;
phys_addr_t start;
phys_addr_t addr;
@@ -67,9 +66,9 @@ void dram_bank_mmu_setup(int bank)
size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
#endif
} else if (gd->flags & GD_FLG_RELOC) {
/* bd->bi_dram is available only after relocation */
start = bd->bi_dram[bank].start;
size = bd->bi_dram[bank].size;
/* gd->dram is available only after relocation */
start = gd->dram[bank].start;
size = gd->dram[bank].size;
use_lmb = true;
} else {
/* mark cacheable and executable the beggining of the DDR */
arch/arm/mach-tegra/board2.c
+7 -7
View File
@@ -393,18 +393,18 @@ int dram_init_banksize(void)
/* fall back to default DRAM bank size computation */
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = usable_ram_size_below_4g();
#ifdef CONFIG_PHYS_64BIT
if (gd->ram_size > SZ_2G) {
gd->bd->bi_dram[1].start = 0x100000000;
gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
gd->dram[1].start = 0x100000000;
gd->dram[1].size = gd->ram_size - SZ_2G;
} else
#endif
{
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
gd->dram[1].start = 0;
gd->dram[1].size = 0;
}
return 0;
@@ -418,7 +418,7 @@ int dram_init_banksize(void)
* carve-out, as mentioned above.
*
* This function is called before dram_init_banksize(), so we can't simply
* return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
* return gd->dram[1].start + gd->dram[1].size.
*/
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
arch/arm/mach-tegra/cboot.c
+2 -2
View File
@@ -185,8 +185,8 @@ int cboot_dram_init_banksize(void)
}
for (i = 0; i < ram_bank_count; i++) {
gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;
gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
gd->dram[i].start = tegra_mem_map[1 + i].virt;
gd->dram[i].size = tegra_mem_map[1 + i].size;
}
return 0;
arch/arm/mach-uniphier/dram_init.c
+3 -3
View File
@@ -280,9 +280,9 @@ int dram_init_banksize(void)
return ret;
for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
if (i < ARRAY_SIZE(gd->bd->bi_dram)) {
gd->bd->bi_dram[i].start = dram_map[i].base;
gd->bd->bi_dram[i].size = dram_map[i].size;
if (i < ARRAY_SIZE(gd->dram)) {
gd->dram[i].start = dram_map[i].base;
gd->dram[i].size = dram_map[i].size;
}
if (!dram_map[i].size)
arch/arm/mach-uniphier/fdt-fixup.c
+5 -3
View File
@@ -4,6 +4,7 @@
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include <asm/global_data.h>
#include <fdt_support.h>
#include <fdtdec.h>
#include <jffs2/load_kernel.h>
@@ -20,6 +21,7 @@
*/
static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned long rsv_addr;
const unsigned long rsv_size = 64;
int i, ret;
@@ -28,11 +30,11 @@ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd)
uniphier_get_soc_id() != UNIPHIER_LD20_ID)
return 0;
for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) {
if (!bd->bi_dram[i].size)
for (i = 0; i < ARRAY_SIZE(gd->dram); i++) {
if (!gd->dram[i].size)
continue;
rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size;
rsv_addr = gd->dram[i].start + gd->dram[i].size;
rsv_addr -= rsv_size;
ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
arch/arm/mach-versal-net/cpu.c
+4 -4
View File
@@ -69,12 +69,12 @@ void mem_map_fill(void)
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Zero size means no more DDR that's this is end */
if (!gd->bd->bi_dram[i].size)
if (!gd->dram[i].size)
break;
versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
versal_mem_map[banks].virt = gd->dram[i].start;
versal_mem_map[banks].phys = gd->dram[i].start;
versal_mem_map[banks].size = gd->dram[i].size;
versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE;
banks = banks + 1;
arch/arm/mach-versal/cpu.c
+8 -8
View File
@@ -82,21 +82,21 @@ void mem_map_fill(void)
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Zero size means no more DDR that's this is end */
if (!gd->bd->bi_dram[i].size)
if (!gd->dram[i].size)
break;
#if defined(CONFIG_VERSAL_NO_DDR)
if (gd->bd->bi_dram[i].start < 0x80000000UL ||
gd->bd->bi_dram[i].start > 0x100000000UL) {
if (gd->dram[i].start < 0x80000000UL ||
gd->dram[i].start > 0x100000000UL) {
printf("Ignore caches over %llx/%llx\n",
gd->bd->bi_dram[i].start,
gd->bd->bi_dram[i].size);
gd->dram[i].start,
gd->dram[i].size);
continue;
}
#endif
versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
versal_mem_map[banks].virt = gd->dram[i].start;
versal_mem_map[banks].phys = gd->dram[i].start;
versal_mem_map[banks].size = gd->dram[i].size;
versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE;
banks = banks + 1;
arch/arm/mach-versal2/cpu.c
+3 -4
View File
@@ -109,7 +109,7 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks)
* fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info
*
* Transfers DRAM bank information from the global versal2_mem_map[]
* array to bd->bi_dram[] for passing memory configuration to the
* array to gd->dram[] for passing memory configuration to the
* Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical
* address and size are copied.
*
@@ -119,15 +119,14 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks)
*/
void fill_bd_mem_info(void)
{
struct bd_info *bd = gd->bd;
int banks = VERSAL2_MEM_MAP_USED;
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
if (!versal2_mem_map[banks].size)
break;
bd->bi_dram[i].start = versal2_mem_map[banks].phys;
bd->bi_dram[i].size = versal2_mem_map[banks].size;
gd->dram[i].start = versal2_mem_map[banks].phys;
gd->dram[i].size = versal2_mem_map[banks].size;
banks++;
}
}
arch/arm/mach-zynqmp/cpu.c
+4 -4
View File
@@ -92,12 +92,12 @@ void mem_map_fill(void)
#if !defined(CONFIG_ZYNQMP_NO_DDR)
for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Zero size means no more DDR that's this is end */
if (!gd->bd->bi_dram[i].size)
if (!gd->dram[i].size)
break;
zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
zynqmp_mem_map[banks].virt = gd->dram[i].start;
zynqmp_mem_map[banks].phys = gd->dram[i].start;
zynqmp_mem_map[banks].size = gd->dram[i].size;
zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE;
banks = banks + 1;
arch/mips/mach-octeon/dram.c
+2 -2
View File
@@ -41,8 +41,8 @@ int dram_init(void)
* No DDR init yet -> run in L2 cache
*/
gd->ram_size = (4 << 20);
gd->bd->bi_dram[0].size = gd->ram_size;
gd->bd->bi_dram[1].size = 0;
gd->dram[0].size = gd->ram_size;
gd->dram[1].size = 0;
}
return 0;
arch/riscv/cpu/k1/dram.c
+6 -6
View File
@@ -56,12 +56,12 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G);
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G);
if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) {
gd->bd->bi_dram[1].start = 0x100000000;
gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
gd->dram[1].start = 0x100000000;
gd->dram[1].size = gd->ram_size - SZ_2G;
}
return 0;
@@ -82,8 +82,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
start[i] = gd->bd->bi_dram[i].start;
size[i] = gd->bd->bi_dram[i].size;
start[i] = gd->dram[i].start;
size[i] = gd->dram[i].size;
}
return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
arch/sandbox/cpu/spl.c
+2 -2
View File
@@ -131,8 +131,8 @@ SPL_LOAD_IMAGE_METHOD("sandbox_image", 7, BOOT_DEVICE_BOARD, load_from_image);
int dram_init_banksize(void)
{
/* These are necessary so TFTP can use LMBs to check its load address */
gd->bd->bi_dram[0].start = gd->ram_base;
gd->bd->bi_dram[0].size = get_effective_memsize();
gd->dram[0].start = gd->ram_base;
gd->dram[0].size = get_effective_memsize();
return 0;
}
arch/x86/cpu/coreboot/sdram.c
+2 -2
View File
@@ -91,8 +91,8 @@ int dram_init_banksize(void)
struct memrange *memrange = &lib_sysinfo.memrange[i];
if (memrange->type == CB_MEM_RAM) {
gd->bd->bi_dram[j].start = memrange->base;
gd->bd->bi_dram[j].size = memrange->size;
gd->dram[j].start = memrange->base;
gd->dram[j].size = memrange->size;
j++;
if (j >= CONFIG_NR_DRAM_BANKS)
break;
arch/x86/cpu/efi/payload.c
+2 -2
View File
@@ -123,8 +123,8 @@ int dram_init_banksize(void)
if (desc->type != EFI_CONVENTIONAL_MEMORY ||
(desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20)
continue;
gd->bd->bi_dram[num_banks].start = desc->physical_start;
gd->bd->bi_dram[num_banks].size = desc->num_pages <<
gd->dram[num_banks].start = desc->physical_start;
gd->dram[num_banks].size = desc->num_pages <<
EFI_PAGE_SHIFT;
num_banks++;
}
arch/x86/cpu/efi/sdram.c
+2 -2
View File
@@ -24,8 +24,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = efi_get_ram_base();
gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE;
gd->dram[0].start = efi_get_ram_base();
gd->dram[0].size = CONFIG_EFI_RAM_SIZE;
return 0;
}
arch/x86/cpu/intel_common/mrc.c
+2 -2
View File
@@ -67,8 +67,8 @@ void mrc_common_dram_init_banksize(void)
if (area->start >= 1ULL << 32)
continue;
gd->bd->bi_dram[num_banks].start = area->start;
gd->bd->bi_dram[num_banks].size = area->size;
gd->dram[num_banks].start = area->start;
gd->dram[num_banks].size = area->size;
num_banks++;
}
}
arch/x86/cpu/ivybridge/sdram_nop.c
+2 -2
View File
@@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = 1ULL << 31;
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = 0;
gd->dram[0].size = gd->ram_size;
return 0;
}
arch/x86/cpu/qemu/dram.c
+4 -4
View File
@@ -69,13 +69,13 @@ int dram_init_banksize(void)
{
u64 high_mem_size;
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = qemu_get_low_memory_size();
gd->dram[0].start = 0;
gd->dram[0].size = qemu_get_low_memory_size();
high_mem_size = qemu_get_high_memory_size();
if (high_mem_size) {
gd->bd->bi_dram[1].start = SZ_4G;
gd->bd->bi_dram[1].size = high_mem_size;
gd->dram[1].start = SZ_4G;
gd->dram[1].size = high_mem_size;
}
return 0;
arch/x86/cpu/quark/dram.c
+2 -2
View File
@@ -169,8 +169,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = 0;
gd->dram[0].size = gd->ram_size;
return 0;
}
arch/x86/cpu/slimbootloader/sdram.c
+2 -2
View File
@@ -129,8 +129,8 @@ int dram_init_banksize(void)
return 0;
/* simply use a single bank to have whole size for now */
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = 0;
gd->dram[0].size = gd->ram_size;
return 0;
}
arch/x86/cpu/tangier/sdram.c
+2 -2
View File
@@ -160,8 +160,8 @@ static int sfi_get_bank_size(void)
if (mentry->type != SFI_MEM_CONV)
continue;
gd->bd->bi_dram[bank].start = mentry->phys_start;
gd->bd->bi_dram[bank].size = mentry->pages << 12;
gd->dram[bank].start = mentry->phys_start;
gd->dram[bank].size = mentry->pages << 12;
bank++;
}
arch/x86/lib/bootm.c
+2 -3
View File
@@ -43,14 +43,13 @@ void bootm_announce_and_cleanup(void)
#if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
int arch_fixup_memory_node(void *blob)
{
struct bd_info *bd = gd->bd;
int bank;
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = bd->bi_dram[bank].start;
size[bank] = bd->bi_dram[bank].size;
start[bank] = gd->dram[bank].start;
size[bank] = gd->dram[bank].size;
}
return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
arch/x86/lib/fsp/fsp_dram.c
+9 -9
View File
@@ -64,8 +64,8 @@ int dram_init_banksize(void)
update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2);
if (!ll_boot_init()) {
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = 0;
gd->dram[0].size = gd->ram_size;
if (update_mtrr)
mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
@@ -89,21 +89,21 @@ int dram_init_banksize(void)
mtrr_top = max(mtrr_top,
res_desc->phys_start + res_desc->len);
} else {
gd->bd->bi_dram[bank].start = res_desc->phys_start;
gd->bd->bi_dram[bank].size = res_desc->len;
gd->dram[bank].start = res_desc->phys_start;
gd->dram[bank].size = res_desc->len;
if (update_mtrr)
mtrr_add_request(MTRR_TYPE_WRBACK,
res_desc->phys_start,
res_desc->len);
log_debug("ram %llx %llx\n",
gd->bd->bi_dram[bank].start,
gd->bd->bi_dram[bank].size);
gd->dram[bank].start,
gd->dram[bank].size);
}
}
/* Add the memory below 4GB */
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = low_end;
gd->dram[0].start = 0;
gd->dram[0].size = low_end;
/*
* Set up an MTRR to the top of low, reserved memory. This is necessary
@@ -184,7 +184,7 @@ unsigned int install_e820_map(unsigned int max_entries,
#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
int handoff_arch_save(struct spl_handoff *ho)
{
ho->arch.usable_ram_top = gd->bd->bi_dram[0].size;
ho->arch.usable_ram_top = gd->dram[0].size;
ho->arch.hob_list = gd->arch.hob_list;
return 0;
board/CZ.NIC/turris_1x/turris_1x.c
+21 -21
View File
@@ -42,9 +42,9 @@ int dram_init_banksize(void)
static_assert(CONFIG_NR_DRAM_BANKS >= 3);
gd->bd->bi_dram[0].start = gd->ram_base;
gd->bd->bi_dram[0].size = get_effective_memsize();
size -= gd->bd->bi_dram[0].size;
gd->dram[0].start = gd->ram_base;
gd->dram[0].size = get_effective_memsize();
size -= gd->dram[0].size;
/* Note: This address space is not mapped via TLB entries in U-Boot */
@@ -68,16 +68,16 @@ int dram_init_banksize(void)
if (size > 0) {
/* Free space between PCIe bus 3 MEM and NOR */
gd->bd->bi_dram[1].start = 0xc0200000;
gd->bd->bi_dram[1].size = min(size, 0xef000000 - gd->bd->bi_dram[1].start);
size -= gd->bd->bi_dram[1].size;
gd->dram[1].start = 0xc0200000;
gd->dram[1].size = min(size, 0xef000000 - gd->dram[1].start);
size -= gd->dram[1].size;
}
if (size > 0) {
/* Free space between NOR and NAND */
gd->bd->bi_dram[2].start = 0xf0000000;
gd->bd->bi_dram[2].size = min(size, 0xff800000 - gd->bd->bi_dram[2].start);
size -= gd->bd->bi_dram[2].size;
gd->dram[2].start = 0xf0000000;
gd->dram[2].size = min(size, 0xff800000 - gd->dram[2].start);
size -= gd->dram[2].size;
}
#else
puts("\n\n!!! TODO: fix sdcard >2GB RAM\n\n\n");
@@ -231,8 +231,8 @@ void ft_memory_setup(void *blob, struct bd_info *bd)
if (!env_get("bootm_low") && !env_get("bootm_size")) {
for (count = 0; count < CONFIG_NR_DRAM_BANKS; count++) {
start[count] = gd->bd->bi_dram[count].start;
size[count] = gd->bd->bi_dram[count].size;
start[count] = gd->dram[count].start;
size[count] = gd->dram[count].size;
if (!size[count])
break;
}
@@ -452,13 +452,13 @@ static void recalculate_used_pcie_mem(void)
size = gd->ram_size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
size -= gd->bd->bi_dram[i].size;
size -= gd->dram[i].size;
if (size == 0)
return;
e = find_law_by_addr_id(CFG_SYS_PCIE3_MEM_PHYS, LAW_TRGT_IF_PCIE_3);
if (e.index < 0 && gd->bd->bi_dram[1].size > 0) {
if (e.index < 0 && gd->dram[1].size > 0) {
/*
* If there is no LAW for PCIe 3 MEM then 3rd PCIe controller
* is inactive, which is the case for Turris 1.0 boards. So
@@ -471,8 +471,8 @@ static void recalculate_used_pcie_mem(void)
printf("Reserving unused ");
print_size(bank_size, "");
printf(" of PCIe 3 MEM for DDR RAM\n");
gd->bd->bi_dram[1].start -= bank_size;
gd->bd->bi_dram[1].size += bank_size;
gd->dram[1].start -= bank_size;
gd->dram[1].size += bank_size;
size -= bank_size;
if (size == 0)
return;
@@ -534,9 +534,9 @@ static void recalculate_used_pcie_mem(void)
printf("Reserving unused ");
print_size(free_size2, "");
printf(" of PCIe 2 MEM for DDR RAM\n");
gd->bd->bi_dram[i].start = free_start2;
gd->bd->bi_dram[i].size = min(size, free_size2);
size -= gd->bd->bi_dram[i].start;
gd->dram[i].start = free_start2;
gd->dram[i].size = min(size, free_size2);
size -= gd->dram[i].start;
i++;
if (size == 0)
return;
@@ -548,9 +548,9 @@ static void recalculate_used_pcie_mem(void)
printf("Reserving unused ");
print_size(free_size1, "");
printf(" of PCIe 1 MEM for DDR RAM\n");
gd->bd->bi_dram[i].start = free_start1;
gd->bd->bi_dram[i].size = min(size, free_size1);
size -= gd->bd->bi_dram[i].size;
gd->dram[i].start = free_start1;
gd->dram[i].size = min(size, free_size1);
size -= gd->dram[i].size;
i++;
if (size == 0)
return;
board/armltd/corstone1000/corstone1000.c
+2 -2
View File
@@ -86,8 +86,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
board/armltd/integrator/integrator.c
+2 -2
View File
@@ -137,7 +137,7 @@ int misc_init_r (void)
int dram_init (void)
{
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
@@ -170,7 +170,7 @@ extern void dram_query(void);
PHYS_SDRAM_1_SIZE);
#endif /* CM_SPD_DETECT */
/* We only have one bank of RAM, set it to whatever was detected */
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].size = gd->ram_size;
return 0;
}
board/armltd/total_compute/total_compute.c
+3 -3
View File
@@ -89,9 +89,9 @@ void build_mem_map(void)
* The first node is for I/O device, start from node 1 for
* updating DRAM info.
*/
mem_map[i + 1].virt = gd->bd->bi_dram[i].start;
mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
mem_map[i + 1].size = gd->bd->bi_dram[i].size;
mem_map[i + 1].virt = gd->dram[i].start;
mem_map[i + 1].phys = gd->dram[i].start;
mem_map[i + 1].size = gd->dram[i].size;
mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE;
}
board/armltd/vexpress/vexpress_common.c
+4 -4
View File
@@ -79,11 +79,11 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size =
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[0].size =
get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size =
gd->dram[1].start = PHYS_SDRAM_2;
gd->dram[1].size =
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
return 0;
board/atmel/common/video_display.c
+1 -1
View File
@@ -40,7 +40,7 @@ int at91_video_show_board_info(void)
dram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
dram_size += gd->bd->bi_dram[i].size;
dram_size += gd->dram[i].size;
nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
board/atmel/sam9x60_curiosity/sam9x60_curiosity.c
+1 -1
View File
@@ -66,7 +66,7 @@ int misc_init_r(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
board_leds_init();
board/atmel/sam9x75_curiosity/sam9x75_curiosity.c
+1 -1
View File
@@ -45,7 +45,7 @@ void board_debug_uart_init(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
return 0;
}
board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
+1 -1
View File
@@ -64,7 +64,7 @@ void board_debug_uart_init(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
rgb_leds_init();
board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
+1 -1
View File
@@ -58,7 +58,7 @@ void board_debug_uart_init(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
rgb_leds_init();
board/atmel/sama5d29_curiosity/sama5d29_curiosity.c
+1 -1
View File
@@ -65,7 +65,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
rgb_leds_init();
board/atmel/sama5d2_xplained/sama5d2_xplained.c
+1 -1
View File
@@ -63,7 +63,7 @@ void board_debug_uart_init(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
rgb_leds_init();
board/atmel/sama7d65_curiosity/sama7d65_curiosity.c
+1 -1
View File
@@ -52,7 +52,7 @@ void board_debug_uart_init(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
board_leds_init();
board/atmel/sama7g54_curiosity/sama7g54_curiosity.c
+1 -1
View File
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
// Address of boot parameters
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
return 0;
}
board/axiado/scm3005/scm3005.c
+2 -2
View File
@@ -96,8 +96,8 @@ int dram_init(void)
*/
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = CFG_SYS_SDRAM_SIZE;
return 0;
}
board/broadcom/bcmns3/ns3.c
+2 -2
View File
@@ -176,8 +176,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
gd->bd->bi_dram[0].size = SZ_16M;
gd->dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
gd->dram[0].size = SZ_16M;
return 0;
}
board/compulab/cm_fx6/cm_fx6.c
+14 -14
View File
@@ -666,34 +666,34 @@ int misc_init_r(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[1].start = PHYS_SDRAM_2;
switch (gd->ram_size) {
case 0x10000000: /* DDR_16BIT_256MB */
gd->bd->bi_dram[0].size = 0x10000000;
gd->bd->bi_dram[1].size = 0;
gd->dram[0].size = 0x10000000;
gd->dram[1].size = 0;
break;
case 0x20000000: /* DDR_32BIT_512MB */
gd->bd->bi_dram[0].size = 0x20000000;
gd->bd->bi_dram[1].size = 0;
gd->dram[0].size = 0x20000000;
gd->dram[1].size = 0;
break;
case 0x40000000:
if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
gd->bd->bi_dram[0].size = 0x20000000;
gd->bd->bi_dram[1].size = 0x20000000;
gd->dram[0].size = 0x20000000;
gd->dram[1].size = 0x20000000;
} else { /* DDR_64BIT_1GB */
gd->bd->bi_dram[0].size = 0x40000000;
gd->bd->bi_dram[1].size = 0;
gd->dram[0].size = 0x40000000;
gd->dram[1].size = 0;
}
break;
case 0x80000000: /* DDR_64BIT_2GB */
gd->bd->bi_dram[0].size = 0x40000000;
gd->bd->bi_dram[1].size = 0x40000000;
gd->dram[0].size = 0x40000000;
gd->dram[1].size = 0x40000000;
break;
case 0xEFF00000: /* DDR_64BIT_4GB */
gd->bd->bi_dram[0].size = 0x70000000;
gd->bd->bi_dram[1].size = 0x7FF00000;
gd->dram[0].size = 0x70000000;
gd->dram[1].size = 0x7FF00000;
break;
}
board/elgin/elgin_rv1108/elgin_rv1108.c
+2 -2
View File
@@ -66,8 +66,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = 0x60000000;
gd->bd->bi_dram[0].size = 0x8000000;
gd->dram[0].start = 0x60000000;
gd->dram[0].size = 0x8000000;
return 0;
}
board/esd/meesc/meesc.c
+2 -2
View File
@@ -141,8 +141,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
gd->dram[0].start = PHYS_SDRAM;
gd->dram[0].size = PHYS_SDRAM_SIZE;
return 0;
}
board/friendlyarm/nanopi2/board.c
+5 -5
View File
@@ -532,17 +532,17 @@ int dram_init_banksize(void)
/* set global data memory */
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = CFG_SYS_SDRAM_SIZE;
/* Number of Row: 14 bits */
if ((reg_val >> 28) == 14)
gd->bd->bi_dram[0].size -= 0x20000000;
gd->dram[0].size -= 0x20000000;
/* Number of Memory Chips */
if ((reg_val & 0x3) > 1) {
gd->bd->bi_dram[1].start = 0x80000000;
gd->bd->bi_dram[1].size = 0x40000000;
gd->dram[1].start = 0x80000000;
gd->dram[1].size = 0x40000000;
}
return 0;
}
board/ge/mx53ppd/mx53ppd.c
+4 -4
View File
@@ -71,11 +71,11 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = mx53_dram_size[0];
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[0].size = mx53_dram_size[0];
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = mx53_dram_size[1];
gd->dram[1].start = PHYS_SDRAM_2;
gd->dram[1].size = mx53_dram_size[1];
return 0;
}
board/hisilicon/hikey/hikey.c
+12 -12
View File
@@ -456,23 +456,23 @@ int dram_init_banksize(void)
* 0x3e00,0000 - 0x3fff,ffff: OP-TEE
*/
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = 0x05e00000;
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[0].size = 0x05e00000;
gd->bd->bi_dram[1].start = 0x05f00000;
gd->bd->bi_dram[1].size = 0x00001000;
gd->dram[1].start = 0x05f00000;
gd->dram[1].size = 0x00001000;
gd->bd->bi_dram[2].start = 0x05f02000;
gd->bd->bi_dram[2].size = 0x00efd000;
gd->dram[2].start = 0x05f02000;
gd->dram[2].size = 0x00efd000;
gd->bd->bi_dram[3].start = 0x06e00000;
gd->bd->bi_dram[3].size = 0x0060f000;
gd->dram[3].start = 0x06e00000;
gd->dram[3].size = 0x0060f000;
gd->bd->bi_dram[4].start = 0x07410000;
gd->bd->bi_dram[4].size = 0x1aaf0000;
gd->dram[4].start = 0x07410000;
gd->dram[4].size = 0x1aaf0000;
gd->bd->bi_dram[5].start = 0x22000000;
gd->bd->bi_dram[5].size = 0x1c000000;
gd->dram[5].start = 0x22000000;
gd->dram[5].size = 0x1c000000;
return 0;
}
board/hisilicon/hikey960/hikey960.c
+2 -2
View File
@@ -74,8 +74,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[0].size = gd->ram_size;
return 0;
}
board/hisilicon/poplar/poplar.c
+2 -2
View File
@@ -87,8 +87,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
gd->dram[0].start = KERNEL_TEXT_OFFSET;
gd->dram[0].size = gd->ram_size - gd->dram[0].start;
return 0;
}
board/k+p/kp_imx53/kp_imx53.c
+2 -2
View File
@@ -39,8 +39,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
board/keymile/pg-wcom-ls102xa/ddr.c
+2 -2
View File
@@ -84,8 +84,8 @@ int fsl_initdram(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = gd->ram_size;
return 0;
}
board/kontron/sl28/sl28.c
+2 -2
View File
@@ -175,8 +175,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < nbanks; i++) {
base[i] = gd->bd->bi_dram[i].start;
size[i] = gd->bd->bi_dram[i].size;
base[i] = gd->dram[i].start;
size[i] = gd->dram[i].size;
}
fdt_fixup_memory_banks(blob, base, size, nbanks);
board/kontron/sl28/spl_atf.c
+3 -3
View File
@@ -36,9 +36,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start;
dram_regions_info.region[i].size = gd->bd->bi_dram[i].size;
dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size;
dram_regions_info.region[i].addr = gd->dram[i].start;
dram_regions_info.region[i].size = gd->dram[i].size;
dram_regions_info.total_dram_size += gd->dram[i].size;
}
bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry,
board/liebherr/btt/btt.c
+1 -1
View File
@@ -239,7 +239,7 @@ int spl_start_uboot(void)
static const char *get_board_name(void)
{
if (gd->bd->bi_dram[0].size == SZ_128M)
if (gd->dram[0].size == SZ_128M)
return STR_BTTC;
return STR_BTT3;
board/menlo/m53menlo/m53menlo.c
+4 -4
View File
@@ -69,11 +69,11 @@ int dram_init(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = mx53_dram_size[0];
gd->dram[0].start = PHYS_SDRAM_1;
gd->dram[0].size = mx53_dram_size[0];
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = mx53_dram_size[1];
gd->dram[1].start = PHYS_SDRAM_2;
gd->dram[1].size = mx53_dram_size[1];
return 0;
}
board/nuvoton/arbel_evb/arbel_evb.c
+13 -13
View File
@@ -57,7 +57,7 @@ int dram_init_banksize(void)
{
phys_size_t ram_size = gd->ram_size;
gd->bd->bi_dram[0].start = 0;
gd->dram[0].start = 0;
#if defined(CONFIG_SYS_MEM_TOP_HIDE)
ram_size += CONFIG_SYS_MEM_TOP_HIDE;
@@ -69,25 +69,25 @@ int dram_init_banksize(void)
case DRAM_1GB_SIZE:
case DRAM_2GB_ECC_SIZE:
case DRAM_2GB_SIZE:
gd->bd->bi_dram[0].size = ram_size;
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
gd->dram[0].size = ram_size;
gd->dram[1].start = 0;
gd->dram[1].size = 0;
break;
case DRAM_4GB_ECC_SIZE:
gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
gd->dram[0].size = DRAM_2GB_SIZE;
gd->dram[1].start = DRAM_4GB_SIZE;
gd->dram[1].size = DRAM_2GB_SIZE -
(DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
break;
case DRAM_4GB_SIZE:
gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
gd->dram[0].size = DRAM_2GB_SIZE;
gd->dram[1].start = DRAM_4GB_SIZE;
gd->dram[1].size = DRAM_2GB_SIZE;
break;
default:
gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
gd->dram[0].size = DRAM_1GB_SIZE;
gd->dram[1].start = 0;
gd->dram[1].size = 0;
break;
}
board/nxp/imxrt1020-evk/imxrt1020-evk.c
+1 -1
View File
@@ -73,7 +73,7 @@ u32 spl_boot_device(void)
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
return 0;
}
board/nxp/imxrt1050-evk/imxrt1050-evk.c
+1 -1
View File
@@ -78,7 +78,7 @@ u32 spl_boot_device(void)
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
return 0;
}
board/nxp/imxrt1170-evk/imxrt1170-evk.c
+1 -1
View File
@@ -73,7 +73,7 @@ u32 spl_boot_device(void)
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
gd->bd->bi_boot_params = gd->dram[0].start + 0x100;
return 0;
}
board/nxp/ls1021aqds/ddr.c
+2 -2
View File
@@ -192,8 +192,8 @@ int fsl_initdram(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
gd->dram[0].start = CFG_SYS_SDRAM_BASE;
gd->dram[0].size = gd->ram_size;
return 0;
}
board/nxp/ls1028a/ls1028a.c
+5 -5
View File
@@ -149,7 +149,7 @@ int board_early_init_f(void)
void detail_board_ddr_info(void)
{
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_size(gd->dram[0].size + gd->dram[1].size, "");
print_ddr_info(0);
}
@@ -202,10 +202,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
ft_cpu_setup(blob, bd);
/* fixup DT for the two GPP DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
base[0] = gd->dram[0].start;
size[0] = gd->dram[0].size;
base[1] = gd->dram[1].start;
size[1] = gd->dram[1].size;
#ifdef CONFIG_RESV_RAM
/* reduce size if reserved memory is within this bank */
board/nxp/ls1043aqds/ls1043aqds.c
+4 -4
View File
@@ -542,10 +542,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
u8 reg;
/* fixup DT for the two DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
base[0] = gd->dram[0].start;
size[0] = gd->dram[0].size;
base[1] = gd->dram[1].start;
size[1] = gd->dram[1].size;
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
board/nxp/ls1043ardb/ls1043ardb.c
+4 -4
View File
@@ -305,10 +305,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
u64 size[CONFIG_NR_DRAM_BANKS];
/* fixup DT for the two DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
base[0] = gd->dram[0].start;
size[0] = gd->dram[0].size;
base[1] = gd->dram[1].start;
size[1] = gd->dram[1].size;
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
board/nxp/ls1046afrwy/ls1046afrwy.c
+4 -4
View File
@@ -198,10 +198,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
u64 size[CONFIG_NR_DRAM_BANKS];
/* fixup DT for the two DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
base[0] = gd->dram[0].start;
size[0] = gd->dram[0].size;
base[1] = gd->dram[1].start;
size[1] = gd->dram[1].size;
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
board/nxp/ls1046aqds/ls1046aqds.c
+4 -4
View File
@@ -426,10 +426,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
u8 reg;
/* fixup DT for the two DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
base[0] = gd->dram[0].start;
size[0] = gd->dram[0].size;
base[1] = gd->dram[1].start;
size[1] = gd->dram[1].size;
fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);

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