Ilias ApalodimasandTom Rini
1174c99ab4
Currently, the bi_dram[] information is stored in the board info structure (bd). Because bd is only valid after reserve_board(), dram_init_banksize() must be called late in the initialization process. This limitation is problematic, as it forces us to rely on a variety of bespoke functions to determine board RAM, bank memory sizes, and other early setup requirements. By moving bi_dram[] into the global data (gd), we can run it earlier. This is particularly convenient since boards define their own dram_init_banksize() routines, which do not always rely on parsing Device Tree (DT) memory nodes. Additionally, U-Boot defaults to relocating to the top of the first memory bank. While boards currently use custom functions to override this behavior, having the DRAM bank information available earlier in gd makes relocating to a different bank trivial and standardizes the process. Reviewed-by: Anshul Dalal <anshuld@ti.com> Tested-by: Michal Simek <michal.simek@amd.com> # Versal Gen 2 Vek385 Tested-by: Anshul Dalal <anshuld@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Tested-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
129 lines
3.0 KiB
C
129 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).
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*/
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#include <config.h>
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#include <dm.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/spin_table.h>
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#include <asm/system.h>
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#include <fdt_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region axiado_ax3005_mem_map[] = {
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{ /* Peripherals including UART */
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x4A000000UL, /* 0 to 0x4A000000: peripherals */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN },
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{ .virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE },
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{
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0,
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}
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};
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struct mm_region *mem_map = axiado_ax3005_mem_map;
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/*
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* Accept any FIT configuration name - the board loads a single FIT image
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* and the first matching config is used.
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*/
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int board_fit_config_name_match(const char *name)
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{
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return 0;
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}
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/*
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* ft_board_setup - restore cpu-release-addr after relocation
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*
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* arch_fixup_fdt() / spin_table_update_dt() overwrites cpu-release-addr
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* with U-Boot's relocated address. Restore the pre-relocation physical
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* address so secondary cores spin on the correct location.
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*/
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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int cpus_offset, offset;
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const char *prop;
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int ret;
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u64 cpu_release_addr = (u64)&spin_table_cpu_release_addr - gd->reloc_off;
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cpus_offset = fdt_path_offset(blob, "/cpus");
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if (cpus_offset < 0)
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return 0;
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for (offset = fdt_first_subnode(blob, cpus_offset); offset >= 0;
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offset = fdt_next_subnode(blob, offset)) {
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prop = fdt_getprop(blob, offset, "device_type", NULL);
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if (!prop || strcmp(prop, "cpu"))
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continue;
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prop = fdt_getprop(blob, offset, "enable-method", NULL);
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if (!prop || strcmp(prop, "spin-table"))
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continue;
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ret = fdt_setprop_u64(blob, offset, "cpu-release-addr",
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cpu_release_addr);
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if (ret) {
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printf("WARNING: Failed to restore cpu-release-addr\n");
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return ret;
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}
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}
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return 0;
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}
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/*
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* dram_init - DDR is initialized by firmware, just setting size
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*/
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
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CFG_SYS_SDRAM_SIZE);
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return 0;
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}
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/*
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* the SOC uses single bank, non-interleaving
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*/
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int dram_init_banksize(void)
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{
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gd->dram[0].start = CFG_SYS_SDRAM_BASE;
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gd->dram[0].size = CFG_SYS_SDRAM_SIZE;
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return 0;
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}
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/*
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* timer_init - enable the AX3005 platform system timer
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*
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* CNTFRQ_EL0 is already set by arch/arm/cpu/armv8/start.S using
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* CONFIG_COUNTER_FREQUENCY from the defconfig.
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*
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* SYS_TIMER_CTRL (0x48016000) is the AX3005 system timer control
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* register — writing SYS_TIMER_ENABLE starts the counter that feeds
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* the ARM generic timer.
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*/
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int timer_init(void)
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{
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writel(SYS_TIMER_ENABLE, SYS_TIMER_CTRL);
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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void reset_cpu(void)
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{
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/* For later ARM_PSCI_FW or watchdog reset */
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}
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