a risc-v simulator
hardware | ||
src | ||
tests | ||
.clang-format | ||
.gitignore | ||
LICENSE | ||
Makefile | ||
README.md |
vriscv - a risc-v simulator
Linux and the BBL bootloader can be downloaded, built, and ran on the simulator using:
make run
Unit tests
Unit tests can be compiled and run using :
make tests
Resources used
RISC-V Specifications:
- https://five-embeddev.com/riscv-isa-manual/latest/instr-table.html (instruction table)
- https://five-embeddev.com/riscv-isa-manual/latest/priv-instr-table.html (privileged instructions)
Device Tree Source :
Juraj's Blog, mostly:
- https://jborza.com/post/2021-04-04-riscv-supervisor-mode/
- https://jborza.com/emulation/2021/04/22/ecalls-and-syscalls.html
RISC-V SBI Specifications:
Buildroot fork for nommu linux: