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Makefile can now build linux/bbl

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vhaudiquet 2023-11-02 18:54:57 +01:00
parent d6af840ed1
commit c423e6a2aa
3 changed files with 2144 additions and 2 deletions
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34
Makefile
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@ -4,6 +4,9 @@ CFLAGS=-O3 -Wall -I src
LDFLAGS=-lpthread
BUILD_DIR=build
# Risc-V toolchain
RV_LINUX_CCPREFIX=riscv32-unknown-linux-gnu-
C_FILES := $(shell find src/ -name '*.c')
all: $(BUILD_DIR)/$(NAME)
@ -21,10 +24,37 @@ $(BUILD_DIR):
clean:
rm -rf $(BUILD_DIR)
rungdb: all
echo $(shell objdump -h ../riscv-pk/build/bbl | grep .payload | awk '{print $4}')
$(BUILD_DIR)/linux:
cd $(BUILD_DIR) && git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git --depth 1 -b v6.6
$(BUILD_DIR)/linux/.config: hardware/linux.config
cp hardware/linux.config $(BUILD_DIR)/linux/.config
$(BUILD_DIR)/linux/vmlinux: $(BUILD_DIR)/linux/.config | $(BUILD_DIR)/linux
cd $(BUILD_DIR)/linux/ && make ARCH=riscv CROSS_COMPILE=$(RV_LINUX_CCPREFIX) -j7 vmlinux
$(BUILD_DIR)/riscv-pk:
cd $(BUILD_DIR) && git clone https://github.com/riscv-software-src/riscv-pk --depth 1
$(BUILD_DIR)/riscv-pk/build: | $(BUILD_DIR)/riscv-pk
mkdir $(BUILD_DIR)/riscv-pk/build
$(BUILD_DIR)/riscv-pk/build/bbl: $(BUILD_DIR)/linux/vmlinux hardware/vriscv.dts | $(BUILD_DIR)/riscv-pk/build
cd $(BUILD_DIR)/riscv-pk/build && ../configure \
--prefix=$(CURDIR)/$(BUILD_DIR)/riscv-pk/build/prefix \
--host=riscv32-unknown-elf \
--with-arch=rv32ima_zicsr_zifencei --with-abi=ilp32 \
--with-dts=../../../hardware/vriscv.dts \
--with-payload=../../linux/vmlinux
cd $(BUILD_DIR)/riscv-pk/build && make && make install
.PHONY: run
.SILENT: run
run: all
./$(BUILD_DIR)/$(NAME)
run: all $(BUILD_DIR)/riscv-pk/build/bbl
./$(BUILD_DIR)/$(NAME) -m4096 $(BUILD_DIR)/riscv-pk/build/bbl
.PHONY: tests
.SILENT: tests

2038
hardware/linux.config Normal file
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74
hardware/vriscv.dts Normal file
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@ -0,0 +1,74 @@
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "riscv-virtio";
model = "riscv-virtio,qemu";
chosen {
bootargs = "debug keep_bootcon earlycon=sbi console=sbi";
stdout-path = "/uart0@3000000";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <10000000>;
cpu0: cpu@0 {
device_type = "cpu";
reg = <0>;
compatible = "riscv";
riscv,isa = "riscv,sv32";
clock-frequency = <10000000>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
ram: memory@0 {
device_type = "memory";
reg = <0x0 0xFFFFFFFF>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
clint0: clint@2000000 {
#interrupt-cells = <1>;
compatible = "riscv,clint0";
reg = <0x2000000 0xC000>;
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7>;
};
// /* FIXME: This is probably not correct for now */
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,plic0";
reg = <0xC000000 0x4000000>;
interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>;
riscv,ndev = <1>;
riscv,max-priority = <7>;
};
// uart0: serial@3000000 {
// interrupts = <0xa>;
// interrupt-parent = <&plic0>;
// clock-frequency = <0x384000>;
// reg = <0x3000000 0x1>;
// compatible = "simple-uart";
// };
};
uart0: serial@3000000 {
clock-frequency = <0x384000>;
reg = <0x3000000 0x1>;
compatible = "sifive,uart0";
};
};