a risc-v simulator
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vhaudiquet 2d33e50074 Define CSR STATUS bits, std functions on exception 11 months ago
src Define CSR STATUS bits, std functions on exception 11 months ago
tests Changed SW/LW test 11 months ago
.clang-format Initial commit 12 months ago
.gitignore Initial commit 12 months ago
Makefile Added unit testing 12 months ago
README.md Added resource, fixed memaccess 11 months ago

README.md

vriscv - a risc-v simulator

Unit tests

Unit tests can be compiled and run using :

make tests

Resources used

RISC-V Specifications:

Device Tree Source :

Juraj's Blog, mostly:

RISC-V SBI Specifications:

Buildroot fork for nommu linux: