Changed SW/LW test

This commit is contained in:
vhaudiquet 2023-10-12 18:16:28 +02:00
parent 9742c89270
commit c286beb1e1

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@ -8,7 +8,9 @@ _start:
addi t1, zero, 0xBA
sw t1, 4(t0)
# Load Word at 0x104 in t0
# Load Word at 0x104 in t0 and t2, using 2 different addressing modes
addi t2, t0, 8
lw t2, -4(t2)
lw t0, 4(t0)
# Compare
@ -17,5 +19,9 @@ _start:
ebreak
good:
beq t0, t2, xtragood
ebreak
xtragood:
addi a0, zero, 0
ebreak