Changed SW/LW test
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@ -8,7 +8,9 @@ _start:
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addi t1, zero, 0xBA
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sw t1, 4(t0)
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# Load Word at 0x104 in t0
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# Load Word at 0x104 in t0 and t2, using 2 different addressing modes
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addi t2, t0, 8
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lw t2, -4(t2)
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lw t0, 4(t0)
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# Compare
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@ -17,5 +19,9 @@ _start:
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ebreak
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good:
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beq t0, t2, xtragood
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ebreak
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xtragood:
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addi a0, zero, 0
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ebreak
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