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Balaji SelvanathanandCasey Connolly a50e32bae6 configs: qcs615/qcs9100: Enable watchdog autostart 
Enable watchdog autostart for QCS615 and QCS9100 platforms to ensure
the watchdog timer is automatically started during U-Boot
initialization.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260526-wdt-v1-1-8236040fe56a@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-06-10 13:36:18 +02:00
Balaji SelvanathanandCasey Connolly 6d2bcb6398 ufs: qcom: Remove redundant POST_CHANGE clock setup call 
The ufs_qcom_init() function was calling ufs_qcom_setup_clocks() with
POST_CHANGE twice. The first call after setting PA_TXHSADAPTTYPE
correctly enables the device reference clock. The second call after
ufs_qcom_advertise_quirks() is redundant as the clock is already
enabled.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-7-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-05-18 11:04:14 +02:00
Balaji SelvanathanandCasey Connolly 83edbe9426 drivers: ufs: qcom: Initialize and enable clocks before hardware access 
Move UFS clock initialization and enabling before hardware setup
to ensure clocks are running when accessing UFS registers.

Previously, U-Boot depended on earlier bootloader stages to
initialize UFS clocks. When these bootloaders failed to do so,
UFS registers became inaccessible, causing initialization to fail.
This change makes U-Boot initialize and enable UFS clocks early
in the init sequence, removing the dependency on previous
bootloaders.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-6-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-05-18 11:04:14 +02:00
Balaji SelvanathanandCasey Connolly 7e670b7d6e clk: qcom: sc7280: Add UFS clock support 
Add UFS clock support for sc7280 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-05-18 11:04:13 +02:00
Balaji SelvanathanandCasey Connolly 213edfd645 clk: qcom: qcs615: Add UFS clock support 
Add UFS clock support for qcs615 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-05-18 11:04:13 +02:00
Balaji SelvanathanandCasey Connolly 4b1580e060 clk: qcom: sa8775p: Add UFS clock support 
Add UFS clock support for SA8775P including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-05-18 11:04:13 +02:00
Balaji SelvanathanandCasey Connolly be1dc88b4a clk: qcom: clk-stub: Add compatibles for QCS615/SA8775P 
Add RPMH clock compatible strings for QCS615 and SA8775P
SoCs to enable clock framework support on these platforms.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-2-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-05-18 11:04:13 +02:00
Balaji SelvanathanandCasey Connolly 40b43c94d2 clk: stub: Sort compatible strings alphabetically 
Reorder compatible strings in stub_clk_ids to maintain alphabetical
order for easier maintenance.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-1-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-05-18 11:04:13 +02:00
Balaji SelvanathanandMarek Vasut cc8195b13b usb: dwc3: Fix crash on fastboot exit due to incorrect memory free 
The dwc3_free_one_event_buffer() function incorrectly called free()
on event buffer structures allocated with devm_kzalloc(). This
caused heap corruption and a synchronous abort when exiting
fastboot mode via "fastboot continue".

Device-managed memory is automatically freed when the device is
removed, so manual deallocation causes the heap allocator to access
corrupted metadata.

Fixes: 884b10e86a ("usb: dwc3: core: fix memory leaks in event buffer cleanup")
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Marek Vasut <marek.vasut+usb@mailbox.org>
 2026-05-09 02:26:58 +02:00
Balaji SelvanathanandTom Rini 34a44dad74 Revert "scsi: sync cache on write" 
While the SYNC_CACHE approach prevents data loss during board resets,
it causes system hangs during large sparse image flashing operations.
This will be replaced with a FUA (Force Unit Access) approach in future
commit, which achieves the same data integrity goal more efficiently.

This reverts commit ffe4e6ab42.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2026-04-27 13:44:06 -06:00
Balaji SelvanathanandCasey Connolly 40be682633 dts: qcs6490-rb3gen2: Remove USB controller dr_mode override 
Remove the USB controller dr_mode override from the u-boot device
tree. The upstream Linux device tree already configures the USB
controller with dr_mode = "otg", which supports both host and
peripheral modes including fastboot.

The previous override to "host" mode prevented fastboot from working
as it requires peripheral mode support. By removing this override,
the upstream OTG configuration is inherited, enabling fastboot while
maintaining host mode capability through the usb-role-switch
property.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260324-kodiak_dts-v2-1-243c28a3ffb9@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-04-27 12:38:44 +02:00
Balaji SelvanathanandCasey Connolly c3d00f1827 MAINTAINERS: Add entry for Qualcomm PHY drivers 
Add the file pattern for Qualcomm PHY drivers to the MAINTAINERS file.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20251203110735.1959862-7-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-04-27 12:38:44 +02:00
Balaji SelvanathanandCasey Connolly b20d13e4e6 configs: qcm6490: Enable super-speed USB support 
Enable the QMP Combo PHY driver to allow super-speed USB
operation on QCM6490 platforms.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20251203110735.1959862-6-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-04-27 12:38:44 +02:00
Balaji SelvanathanandCasey Connolly 5ebc47d984 arch: arm: mach-snapdragon: Auto-detect USB SSPHY driver support 
Automatically detect super-speed USB PHY driver availability and
skip the USB speed fixup if driver is available, eliminating the need
for manual configuration.

Previously, U-Boot unconditionally limited USB to high-speed mode
on all Qualcomm platforms because most lacked super-speed PHY
drivers.

This change implements runtime detection that checks if a PHY
driver exists for the super-speed PHY node referenced by the DWC3
controller. The fixup is automatically skipped when a compatible
driver is found, allowing the hardware to operate at full
capability. Platforms without super-speed PHY drivers continue to
receive the fixup automatically.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
[casey: rebased on flat-dwc3 dt support + fix Balaji's signoff]
[casey: make erroneous printf() a debug() again]
Link: https://patch.msgid.link/20251203110735.1959862-5-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-04-27 12:38:44 +02:00
Balaji SelvanathanandCasey Connolly 2c93971ba3 drivers: phy: qcom: Add QMP USB3-DP Combo PHY driver 
Add support for the Qualcomm QMP USB3-DP Combo PHY found on
SC7280 and QCM6490 platforms. This driver currently implements
USB3 super-speed functionality of the combo PHY.

The QMP Combo PHY is a dual-mode PHY
that can operate in either USB3 mode or DisplayPort mode. This
initial implementation focuses on USB3 mode to enable Super-Speed
USB support.

Taken from Linux commit 3d25d46a255a ("pmdomain: qcom: rpmhpd: Add rpmhpd support for SM8750")

This patch is dependent on this patch: https://lore.kernel.org/u-boot/20251112164204.1557934-1-aswin.murugan@oss.qualcomm.com/

Enabled and tested the driver on Qualcomm RB3 Gen2 (QCS6490) board.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20251203110735.1959862-4-balaji.selvanathan@oss.qualcomm.com
[casey: fix unused variable warning]
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-04-27 12:33:30 +02:00
Balaji SelvanathanandCasey Connolly 6de333b5ca drivers: usb: dwc3: Add delay after core soft reset 
Add a 100 ms delay after clearing the core soft reset bit to ensure
the DWC3 controller has sufficient time to complete its reset
sequence before subsequent register accesses.

Without this delay, USB initialization can fail on some Qualcomm
platforms, particularly when using super-speed capable PHYs like
the QMP USB3-DP Combo PHY on SC7280/QCM6490.

Taken from Linux commit f88359e1588b ("usb: dwc3: core: Do core softreset when switch mode")

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20251203110735.1959862-3-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-04-27 12:33:30 +02:00
Balaji SelvanathanandCasey Connolly c808ab5fed drivers: clk: qcom: sc7280: Add USB3 PHY pipe clock 
Add support for GCC_USB3_PRIM_PHY_PIPE_CLK which is required by
the USB3 PHY on SC7280/QCM6490 platforms.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20251203110735.1959862-2-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-04-27 12:33:30 +02:00
Balaji SelvanathanandCasey Connolly bf119f79b5 power-domain: Add QCOM RPMH Power Domain Driver Support 
Added support for Qualcomm RPMH power domain driver, responsible
for managing power domains on Qualcomm SoCs. This is a port of
the Linux RPMHPD driver [1] and sa8775p related changes. The
power domain driver currently has support to power on and off
MMCX power domain of sa8775p; support for other soc entries power
domains are stubbed, in future, the required soc support can be
added.

[1]:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pmdomain/qcom/rpmhpd.c?id=3d25d46a255a83f94d7d4d4216f38aafc8e116b

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260213111009.1254360-2-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-04-27 12:33:29 +02:00
Balaji SelvanathanandCasey Connolly 0f265c20a5 phy: qcom: qusb2: Add QCS615 QUSB2 PHY support 
Add support for QCS615 QUSB2 PHY by introducing platform-specific
initialization table and register layout. The implementation reuses
the IPQ6018 register layout and defines QCS615-specific tuning
parameters for proper USB PHY operation.

Taken from Linux commit 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615")

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260213-talos_usb-v1-3-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-03-24 11:35:06 +01:00
Balaji SelvanathanandCasey Connolly c4169dfa1d clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support 
Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615
clock driver. This clock is required for proper PHY operation
and eliminates clock-related warnings during USB initialization.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260213-talos_usb-v1-2-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-03-24 11:34:58 +01:00
Balaji SelvanathanandCasey Connolly c4f40d0925 clk: qcom: qcs615: Add GCC_USB3_PRIM_CLKREF_CLK support 
Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver.
This clock is referenced in the device tree USB node but was not
implemented in U-Boot, causing "Clock 152 not found" warnings during
fastboot run.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260213-talos_usb-v1-1-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-03-24 11:34:58 +01:00
Balaji SelvanathanandCasey Connolly f4886799a0 clk: qcom: sa8775p: Fix USB clock configuration and add resets 
Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")

Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260113065856.3287772-1-balaji.selvanathan@oss.qualcomm.com
[casey: indentation fix]
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-01-14 16:25:09 +01:00
Balaji SelvanathanandCasey Connolly cb07205adb configs: Fix fastboot buffer address for QCS615 and QCM6490 boards 
The default value of CONFIG_FASTBOOT_BUF_ADDR is 0, which causes
NULL pointer dereference during fastboot commands when users dont
provide "-l" option in fastboot usb command.

Set it to safe and sufficiently large region in RAM
of the QCS615 and QCM6490 boards, to prevent crashes.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260107095038.2491697-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-01-14 16:25:09 +01:00
Balaji SelvanathanandCasey Connolly 7f1a1fa051 configs: qcom_qcs615: Correct debug UART clock frequency 
Adjust the debug UART clock frequency from 14745600 Hz to 7372800 Hz
for the QCS615 platform. This correction ensures proper UART
communication timing and resolves baud rate miscalculations
that affects early boot console output.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20251119152312.4175482-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-01-14 16:25:09 +01:00
Balaji SelvanathanandCasey Connolly fe3b827a59 usb: gadget: Kconfig: Correct Qualcomm config name used 
Correct ARCH_QCOM to ARCH_SNAPDRAGON as ARCH_QCOM is outdated/unused
config. Using ARCH_QCOM was causing USB fastboot mode to fail.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Acked-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20251224044747.3898137-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-01-14 16:17:48 +01:00
Balaji SelvanathanandCasey Connolly 68daf96a90 configs: qcom_qcs9100: Fix fastboot buffer address for QCS9100 board 
The default value of CONFIG_FASTBOOT_BUF_ADDR is 0, which causes
NULL pointer dereference during fastboot commands.

Set it to 0xdb300000, a safe and sufficiently large region in RAM
of the QCS9100 board, to prevent crashes and ensure reliable
fastboot functionality.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20250630070040.734486-3-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-01-14 16:17:48 +01:00
Balaji SelvanathanandCasey Connolly 83d9b5a740 configs: Rename qcs9100_defconfig to qcom_qcs9100_defconfig 
To align with the naming convention used for Qualcomm platforms in
U-Boot, renamed the defconfig file from qcs9100_defconfig to
qcom_qcs9100_defconfig.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20250630070040.734486-2-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-01-14 16:17:48 +01:00
Balaji SelvanathanandCasey Connolly fba8fc4a96 usb: dwc3: qcom: Add delays in UTMI clock selection for Qscratch 
Added delays before and after setting the PIPE_UTMI_CLK_SEL and
PIPE3_PHYSTATUS_SW bits in the Qscratch GENERAL_CFG register
during UTMI clock selection for DWC3 on Qualcomm platforms.

These delays help ensure proper timing and stability of the UTMI
clock switching sequence, potentially avoiding race conditions or
unstable PHY behavior during initialization.

Tested on platforms using Qscratch-based DWC3 PHY configuration.

This change is taken from this Linux kernel implementation:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/usb/dwc3/dwc3-qcom.c?id=a4333c3a6ba9ca9cff50a3c1d1bf193dc5489e1c

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://patch.msgid.link/20250627045244.2225303-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2026-01-14 16:17:48 +01:00
Balaji SelvanathanandTom Rini c0add00398 drivers: scsi: fix double decrement of block count in 64-bit LBA path 
The scsi_read function incorrectly decrements the block count twice
when handling large disks that trigger the CONFIG_SYS_64BIT_LBA code
path (reads beyond block 268,435,455). The variable 'blks' was being
decremented both inside the 64-bit LBA block and after the successful
scsi_exec() call, causing incorrect block count tracking and data
abort errors on large capacity disks.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Tested-by: Tony Dinh <mibodhi@gmail.com>
 2025-12-22 16:19:39 -06:00
Balaji SelvanathanandTom Rini b32dda3450 drivers: scsi: fix inaccurate block count reporting in scsi operations 
The 'blks' variable in scsi_read/write/erase functions is updated
regardless of pass/fail of the scsi operation . If the scsi operation
fails, 'blkcnt' is updated using an incorrect value of 'blks'. This
wrong 'blkcnt' is returned to the caller and it assumes all blocks were
processed correctly.

Fix this by updating the 'blks' variable only if the scsi operation
succeeds.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
 2025-08-07 11:14:23 -06:00
Balaji SelvanathanandHeinrich Schuchardt 9fe50b5a0a doc: board: qualcomm: document Dragonwing IQ8 board building/flashing 
Introducing documentation support for Qualcomm Dragonwing IQ8 QCS8300
board. Documents the build and flashing steps.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
 2025-07-19 12:35:20 +02:00
Balaji SelvanathanandCasey Connolly 9cd3118e4a watchdog: qcom-wdt: Drop read check on write-only WDT_EN register 
On some Qualcomm platforms, such as Dragonwing boards, the WDT_EN
register is write-only. Reading it back after enabling the watchdog
can return invalid data or cause unexpected behavior.

In particular, the check:
  if (readl(wdt_addr(wdt, WDT_EN)) != 1)
may fail even though the watchdog is correctly enabled and running.
This leads to misleading error messages and unnecessary failures.

Removing the read check ensures compatibility and avoids false
negatives on platforms where WDT_EN is not readable.

This work builds upon this previous submission:
https://lore.kernel.org/u-boot/20250625094607.1348494-1-gopinath.sekar@oss.qualcomm.com/

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Link: https://lore.kernel.org/r/20250701065738.1644669-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2025-07-14 15:35:24 +02:00
Balaji SelvanathanandTom Rini 5afb01b2ab configs: add qcom_qcs8300_defconfig 
Introduce a defconfig for QCS8300 based boards.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-7-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2025-06-24 07:54:49 -06:00
Balaji SelvanathanandTom Rini 1c6f9b4558 qcom_defconfig: Enable QCS8300 clock driver 
Enable the QCS8300 clock driver in Qualcomm defconfig.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-6-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2025-06-24 07:54:49 -06:00
Balaji SelvanathanandTom Rini b661d7c96b phy: qcom: Enable QMP UFS PHY driver for QCS8300 
Enable QMP phy for QCS8300, referenced from Linux.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-5-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2025-06-24 07:54:23 -06:00
Balaji SelvanathanandTom Rini 57f232607b clk/qcom: qcs8300: Add GCC clock driver for QCS8300 
* Port Linux's gcc-qcs8300.c driver to U-Boot for basic bring-up.

* Enable QCS8300 clocks in qcom_defconfig.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-4-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2025-06-24 07:54:03 -06:00
Balaji SelvanathanandTom Rini 8e29f5adcc dts: qcs8300-ride-u-boot.dtsi: Add memory entry to bootup 
Added the memory entry to bootup.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-3-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2025-06-24 07:54:03 -06:00
Balaji SelvanathanandTom Rini e71cfbbae6 doc: board: qualcomm: document Dragonwing board building/flashing 
Introducing documentation support for Qualcomm Dragonwing series
boards. Documents the build and flashing steps.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-2-quic_bselvana@quicinc.com
[Casey: add dragonwing to board/qualcomm/index.rst]
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2025-06-24 07:54:03 -06:00
Balaji SelvanathanandCasey Connolly 35811a7b0d drivers: watchdog: qcom: Add timeout configuration support in watchdog 
This patch enhances the Qualcomm watchdog driver by introducing
support for dynamic timeout configuration. Specifically:

- Calculates and sets the bark and bite timeout values based on
  the clock rate and the requested timeout in milliseconds.
- Adds retrieval of the watchdog clock rate during probe using
  the common clock framework.
- Adds a default timeout value for ARCH_SNAPDRAGON
  in WATCHDOG_TIMEOUT_MSECS.

These changes improve the configurability and accuracy of the
watchdog timer on Qualcomm platforms.

This work builds upon the previous submission:
https://lore.kernel.org/all/20250422-b4-qcom-wdt-v3-1-730d4d5a858d@paulsajna.com/

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250527124926.128413-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
 2025-06-23 18:50:39 +02:00