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vhaudiquet f52699a8bf Multithread gdbstub and execution, with cont/halt
2023-10-08 17:42:44 +02:00
src
Multithread gdbstub and execution, with cont/halt
2023-10-08 17:42:44 +02:00
.clang-format
Initial commit
2023-10-04 21:28:18 +02:00
.gitignore
Initial commit
2023-10-04 21:28:18 +02:00
Makefile
Make CPU code thread safe
2023-10-08 16:40:03 +02:00
README.md
Debugging instructions (system mostly)
2023-10-05 11:16:06 +02:00

README.md

vriscv - a risc-v simulator

Resources used

Juraj's Blog, mostly:

  • https://jborza.com/post/2021-04-04-riscv-supervisor-mode/
  • https://jborza.com/emulation/2021/04/22/ecalls-and-syscalls.html

RISC-V SBI Specifications:

  • https://github.com/riscv-non-isa/riscv-sbi-doc/releases

Buildroot fork for nommu linux:

  • https://github.com/regymm/buildroot
Description
a risc-v simulator
Readme 462 KiB
Languages
C 92.7%
Assembly 4%
Makefile 2.4%
Shell 0.9%
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