a risc-v simulator
src | ||
.clang-format | ||
.gitignore | ||
Makefile | ||
README.md |
vriscv - a risc-v simulator
Resources used
Juraj's Blog, mostly:
- https://jborza.com/post/2021-04-04-riscv-supervisor-mode/
- https://jborza.com/emulation/2021/04/22/ecalls-and-syscalls.html
RISC-V SBI Specifications:
Buildroot fork for nommu linux: