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a risc-v simulator
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Fix JALR implementation (rd=rs1 edge case) 		12 months ago
src Fix JALR implementation (rd=rs1 edge case) 12 months ago
.clang-format Initial commit 12 months ago
.gitignore Initial commit 12 months ago
Makefile Initial commit 12 months ago
README.md Debugging instructions (system mostly) 12 months ago

README.md

vriscv - a risc-v simulator

Resources used

Juraj's Blog, mostly:

RISC-V SBI Specifications:

Buildroot fork for nommu linux: