a risc-v simulator
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vriscv/src/main.c

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1.2 KiB

#include "vriscv.h"
#include "memory/memory.h"
#include "bootloader/bootloader.h"
#include "cpu/rv32cpu.h"
#include "gdbstub/gdbstub.h"
char* CURRENT_NAME;
int main(int argc, char** argv)
{
CURRENT_NAME = argc ? argv[0] : NAME;
parse_options(argc, argv);
// Initialize the memory
mem_init();
// Bootload the file passed as argument
uint32_t entry_point = bootload(file_path);
// Initialize the CPU
cpu_init();
cpu0->pc = entry_point;
if(gdbstub)
{
gdbstub_start();
gdbstub_wait_for_connection();
}
// CPU simulation : create cpu0 thread
if(!gdbstub) cpu0->sim_ticks_left = -1; // Simulate forever
pthread_t cpu0_thread;
pthread_create(&cpu0_thread, 0, (void*) cpu_loop, cpu0);
// Wait for the simulation to end
if(gdbstub)
{
pthread_join(cpu0_thread, 0);
gdbstub_stop();
}
else
{
while(1)
{
pthread_mutex_lock(&cpu0_mutex);
pthread_cond_wait(&cpu0->sim_condition, &cpu0_mutex);
if(!cpu0->sim_ticks_left && cpu0->sim_ticks_done > 0)
{
// Simulation ended
break;
}
pthread_mutex_unlock(&cpu0_mutex);
}
fprintf(stderr, "Simulation ended in a non-debug environment\n");
return cpu0->regs.a0;
}
return 0;
}