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13 lines
356 B
13 lines
356 B
# vriscv - a risc-v simulator
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## Resources used
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Juraj's Blog, mostly:
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- https://jborza.com/post/2021-04-04-riscv-supervisor-mode/
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- https://jborza.com/emulation/2021/04/22/ecalls-and-syscalls.html
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RISC-V SBI Specifications:
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- https://github.com/riscv-non-isa/riscv-sbi-doc/releases
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Buildroot fork for nommu linux:
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- https://github.com/regymm/buildroot
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