a risc-v simulator

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vhaudiquet 13f7f21b49 Added CSRRW/CSRRS basic support ... For now we allow all write/read in all CSR (just an array)		12 months ago
..
bootloader	Initial commit	12 months ago
cpu	Added CSRRW/CSRRS basic support	12 months ago
gdbstub	gdbstub: added REUSEADDR/PORT and socket closing	12 months ago
memory	Make CPU and memory thread-safe	12 months ago
main.c	gdbstub: added REUSEADDR/PORT and socket closing	12 months ago
option.c	Added 'trace' option	12 months ago
vriscv.h	Added 'trace' option	12 months ago