lrw/scw reservation

master
vhaudiquet 11 months ago
parent 9dd57071ce
commit efbf73f6b5
  1. 12
      src/cpu/rv32cpu.c
  2. 1
      src/cpu/rv32cpu.h

@ -636,13 +636,19 @@ static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction)
case FUNC75_LRW: case FUNC75_LRW:
// Load-Reserved Word // Load-Reserved Word
cpu->regs.x[instruction->rd] = mem_read32(address); cpu->regs.x[instruction->rd] = mem_read32(address);
// TODO register reservation set that subsumes the bytes in word cpu->load_reservation = address;
break; break;
case FUNC75_SCW: case FUNC75_SCW:
// Store-Conditional Word // Store-Conditional Word
// TODO succeed only if the reservation is still valid and the reservation set contains the bytes written if(cpu->load_reservation == address)
{
mem_write32(address, cpu->regs.x[instruction->rs2]); mem_write32(address, cpu->regs.x[instruction->rs2]);
cpu->regs.x[instruction->rd] = 0; // TODO write 1 in rd on failure cpu->regs.x[instruction->rd] = 0; // Write 0 in rd on success
}
else
{
cpu->regs.x[instruction->rd] = 1; // Write 1 in rd on failure
}
break; break;
case FUNC75_AMOSWAPW: case FUNC75_AMOSWAPW:
// Atomic Memory Operation SWAP Word // Atomic Memory Operation SWAP Word

@ -200,6 +200,7 @@ typedef struct RV32_CPU
uint32_t csr[CSR_COUNT]; uint32_t csr[CSR_COUNT];
rvcpu_privilege_mode_t privilege_mode; rvcpu_privilege_mode_t privilege_mode;
uint32_t load_reservation;
// Simulation data // Simulation data
ssize_t sim_ticks_left; // -1 : simulate forever ssize_t sim_ticks_left; // -1 : simulate forever

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