Makefile can now build linux/bbl
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								hardware/linux.config
									
									
									
									
									
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										2038
									
								
								hardware/linux.config
									
									
									
									
									
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								hardware/vriscv.dts
									
									
									
									
									
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										74
									
								
								hardware/vriscv.dts
									
									
									
									
									
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							@@ -0,0 +1,74 @@
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/dts-v1/;
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/ {
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    #address-cells = <1>;
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    #size-cells = <1>;
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    compatible = "riscv-virtio";
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    model = "riscv-virtio,qemu";
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    chosen {
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        bootargs = "debug keep_bootcon earlycon=sbi console=sbi";
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        stdout-path = "/uart0@3000000";
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    };
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    cpus {
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        #address-cells = <1>;
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        #size-cells = <0>;
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        timebase-frequency = <10000000>;
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        cpu0: cpu@0 {
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            device_type = "cpu";
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            reg = <0>;
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            compatible = "riscv";
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            riscv,isa = "riscv,sv32";
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            clock-frequency = <10000000>;
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            cpu0_intc: interrupt-controller {
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                #interrupt-cells = <1>;
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                compatible = "riscv,cpu-intc";
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                interrupt-controller;
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            };
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        };
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    };
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    ram: memory@0 {
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        device_type = "memory";
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        reg = <0x0 0xFFFFFFFF>;
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    };
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    soc {
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        #address-cells = <1>;
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        #size-cells = <1>;
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        compatible = "simple-bus";
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        ranges;
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        clint0: clint@2000000 {
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            #interrupt-cells = <1>;
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            compatible = "riscv,clint0";
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            reg = <0x2000000 0xC000>;
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            interrupts-extended =  <&cpu0_intc 3 &cpu0_intc 7>;
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        };
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        // /* FIXME: This is probably not correct for now */
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        plic0: interrupt-controller@c000000 {
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            #interrupt-cells = <1>;
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            interrupt-controller;
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            compatible = "riscv,plic0";
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            reg = <0xC000000 0x4000000>;
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            interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>;
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            riscv,ndev = <1>;
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            riscv,max-priority = <7>;
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        };
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        // uart0: serial@3000000 {
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        //     interrupts = <0xa>;
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        //     interrupt-parent = <&plic0>;
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        //     clock-frequency = <0x384000>;
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        //     reg = <0x3000000 0x1>;
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        //     compatible = "simple-uart";
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        // };
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    };
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    uart0: serial@3000000 {
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        clock-frequency = <0x384000>;
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        reg = <0x3000000 0x1>;
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        compatible = "sifive,uart0";
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    };
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};
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