vhaudiquet/vriscv
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Changed SW/LW test

Browse Source
This commit is contained in:
Valentin Haudiquet 2023-10-12 18:16:28 +02:00
parent 9742c89270
commit c286beb1e1
1 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
tests/swlw.s
View File

@ -8,7 +8,9 @@ _start:
addi t1, zero, 0xBA addi t1, zero, 0xBA
sw t1, 4(t0) sw t1, 4(t0)
# Load Word at 0x104 in t0 # Load Word at 0x104 in t0 and t2, using 2 different addressing modes
addi t2, t0, 8
lw t2, -4(t2)
lw t0, 4(t0) lw t0, 4(t0)
# Compare # Compare
@ -17,5 +19,9 @@ _start:
ebreak ebreak
good: good:
beq t0, t2, xtragood
ebreak
xtragood:
addi a0, zero, 0 addi a0, zero, 0
ebreak ebreak