vhaudiquet/vriscv
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix JALR implementation (rd=rs1 edge case)

Browse Source
This commit is contained in:
Valentin Haudiquet
2023-10-05 20:55:48 +02:00
parent 57dfd9cb76
commit bb1427f77b
1 changed files with 3 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/rv32cpu.c
View File

@@ -140,10 +140,12 @@ static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction)
case OPCODE_JALR:
{
// Jump And Link Register
cpu->regs.x[instruction->rd] = cpu->pc + 4;
uint32_t old_pc = cpu->pc;
// Sign extend immediate from 12 bits to 32 bits
uint32_t immediate = (instruction->immediate & 0xFFF) | (instruction->immediate & 0x800 ? 0xFFFFF000 : 0);
cpu->pc = ((cpu->regs.x[instruction->rs1] + immediate) & 0xFFFFFFFE) - 4;
// Save old pc
cpu->regs.x[instruction->rd] = old_pc + 4;
break;
}
case OPCODE_BRANCH: