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CPU privilege modes

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This commit is contained in:
vhaudiquet 2023-10-20 12:02:50 +02:00
parent 082d2dcd4f
commit b3f915dcb5
2 changed files with 22 additions and 10 deletions
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7
src/cpu/rv32cpu.c
View File

@ -45,6 +45,7 @@ void cpu_init()
pthread_mutex_init(&cpu0_mutex, 0);
pthread_cond_init(&cpu0->sim_condition, 0);
cpu0->regs.zero = 0;
cpu0->privilege_mode = MACHINE;
}
static void cpu_decode(raw_instruction_t raw_instruction, instruction_t* output)
@ -523,8 +524,10 @@ static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction)
fprintf(stderr, "SRET: We don't support that.\n");
break;
case IMM_MRET:
// Act like a normal ret/jalr, with destination address being CSR_MEPC content
fprintf(stderr, "Warning: MRET: We don't support privilege mode change\n");
// Ret to destination address : CSR_MEPC content
// Change privilege mode to SUPERVISOR
// TODO : Pop lower-privilege interrupt enable and privilege mode stack
cpu->privilege_mode = SUPERVISOR;
cpu->pc = cpu->csr[CSR_MEPC] - 4;
break;
default:

25
src/cpu/rv32cpu.h
View File

@ -7,13 +7,20 @@
#include "csr.h"
typedef enum RVCPU_PRIVILEGE_MODE
{
USER,
SUPERVISOR,
MACHINE
} rvcpu_privilege_mode_t;
/*
* This is a structure encoding for the registers of
* the rv32 cpu.
* It allows access of register x0 using :
* structname.x0, structname.zero, structname.x[0]
* This way, access can be really flexible
*/
* This is a structure encoding for the registers of
* the rv32 cpu.
* It allows access of register x0 using :
* structname.x0, structname.zero, structname.x[0]
* This way, access can be really flexible
*/
typedef struct RV32_CPU_REGS
{
union
@ -188,10 +195,12 @@ typedef struct RV32_CPU_REGS
typedef struct RV32_CPU
{
// CPU values
rv32_cpu_regs_t regs;
uint32_t pc;
rv32_cpu_regs_t regs;
uint32_t pc;
uint32_t csr[CSR_COUNT];
rvcpu_privilege_mode_t privilege_mode;
// Simulation data
ssize_t sim_ticks_left; // -1 : simulate forever
size_t sim_ticks_done;