Initial commit
Added base code, can run ELF files and simulate RV32I instructions
This commit is contained in:
452
src/cpu/rv32cpu.c
Normal file
452
src/cpu/rv32cpu.c
Normal file
@@ -0,0 +1,452 @@
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#include "rv32cpu.h"
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#include "instruction.h"
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#include "memory/memory.h"
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#include "memory/mmu/mmu.h"
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#include "vriscv.h"
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#include <stdlib.h>
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#include <stdio.h>
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rv32_cpu_t* cpu0;
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typedef union RAW_INSTRUCTION
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{
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uint32_t data;
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struct
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{
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uint8_t opcode : 7;
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uint16_t rd : 5;
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uint16_t func3 : 3;
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uint16_t rs1 : 5;
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uint16_t rs2 : 5;
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uint16_t func7 : 7;
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} __attribute__((packed));
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} __attribute__((packed)) raw_instruction_t;
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typedef struct INSTRUCTION
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{
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uint8_t opcode;
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uint32_t immediate;
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uint8_t func3;
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uint8_t func7;
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uint8_t rd;
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uint8_t rs1;
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uint8_t rs2;
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} instruction_t;
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void cpu_init()
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{
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cpu0 = malloc(sizeof(rv32_cpu_t));
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cpu0->regs.zero = 0;
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}
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static void cpu_decode(raw_instruction_t raw_instruction, instruction_t* output)
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{
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output->opcode = raw_instruction.opcode;
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output->immediate = 0;
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output->func3 = raw_instruction.func3;
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output->func7 = raw_instruction.func7;
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output->rd = raw_instruction.rd;
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output->rs1 = raw_instruction.rs1;
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output->rs2 = raw_instruction.rs2;
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// Decode immediate, and make sure opcode is correct
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switch(raw_instruction.opcode)
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{
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// U-type instructions
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case OPCODE_LUI:
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case OPCODE_AUIPC:
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output->immediate = raw_instruction.data & 0xFFFFF000;
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break;
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// J-type instructions
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case OPCODE_JAL:
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// Last bit (31) of data is immediate bit 20
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output->immediate = (raw_instruction.data & 0x80000000) >> 11;
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// Then following 10 bits (30-21) are immediate bits 10-1
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output->immediate |= (raw_instruction.data & 0x7FE00000) >> 20;
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// Following bit (20) is immediate bit 11
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output->immediate |= (raw_instruction.data & 0x200000) >> 10;
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// Last bits (19-12) are immediate bits 19-12
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output->immediate |= (raw_instruction.data & 0xFF000);
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break;
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// I-type instructions
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case OPCODE_JALR:
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case OPCODE_LOAD:
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case OPCODE_ARITHLOG_IMM:
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case OPCODE_SYSTEM:
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// Bits 31-20 are immediate bits 11-0
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output->immediate = (raw_instruction.data & 0xFFF00000) >> 20;
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break;
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// B-type instructions
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case OPCODE_BRANCH:
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// Last bit (31) of data is immediate bit 12
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output->immediate = (raw_instruction.data & 0x80000000) >> 19;
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// Then following 6 bits (30-25) are immediate bits 10-5
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output->immediate |= (raw_instruction.data & 0x7E000000) >> 20;
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// On rd field, last 4 bits (4:1) are immediate bits 4:1
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output->immediate |= (raw_instruction.rd & 0x1E);
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// On rd field, first bit (0) is immediate bit 11
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output->immediate |= (raw_instruction.rd & 0x01) << 11;
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break;
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// R-type instructions
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case OPCODE_ARITHLOG:
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break;
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// S-type instructions
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case OPCODE_STORE:
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// Bits 31-25 (func7) are immediate bits 11:5
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output->immediate = raw_instruction.func7 << 5;
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// Bits of rd are immediate bits 4:0
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output->immediate |= raw_instruction.rd;
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break;
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default:
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fprintf(stderr, "Error: Unknown instruction opcode 0x%x, could not decode\n", raw_instruction.opcode);
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exit(EXIT_FAILURE);
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break;
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}
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}
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static void cpu_execute(rv32_cpu_t* cpu, instruction_t* instruction)
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{
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switch(instruction->opcode)
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{
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case OPCODE_LUI:
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{
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// Load Upper Immediate (load immediate(31:12 bits) in rd)
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if(instruction->rd)
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cpu->regs.x[instruction->rd] = instruction->immediate;
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break;
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}
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case OPCODE_AUIPC:
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{
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// Add Upper Immediate to PC
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if(instruction->rd)
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cpu->regs.x[instruction->rd] = instruction->immediate + cpu->pc;
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break;
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}
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case OPCODE_JAL:
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{
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// Jump And Link
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if(instruction->rd)
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cpu->regs.x[instruction->rd] = cpu->pc + 4;
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// Sign extend immediate from 21 bits to 32 bits
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uint32_t immediate = (instruction->immediate & 0x1FFFFF) | (instruction->immediate & 0x100000 ? 0xFFE00000 : 0);
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cpu->pc += immediate - 4;
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break;
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}
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case OPCODE_JALR:
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{
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// Jump And Link Register
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if(instruction->rd)
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cpu->regs.x[instruction->rd] = cpu->pc + 4;
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// Sign extend immediate from 12 bits to 32 bits
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uint32_t immediate = (instruction->immediate & 0xFFF) | (instruction->immediate & 0x800 ? 0xFFFFF000 : 0);
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cpu->pc = ((cpu->regs.x[instruction->rs1] + immediate) & 0xFFFFFFFE) - 4;
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break;
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}
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case OPCODE_BRANCH:
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{
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// Branches ; to know which one, we must analyse func3
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// Sign extend immediate from 13 bits to 32 bits
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uint32_t immediate = (instruction->immediate & 0xFFF) | (instruction->immediate & 0x1000 ? 0xFFFFE000 : 0);
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immediate -= 4;
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switch(instruction->func3)
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{
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case FUNC3_BEQ:
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// Branch EQual
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if(cpu->regs.x[instruction->rs1] == cpu->regs.x[instruction->rs2])
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cpu->pc = immediate;
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break;
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case FUNC3_BNE:
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// Branch Not Equal
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if(cpu->regs.x[instruction->rs1] != cpu->regs.x[instruction->rs2])
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cpu->pc = immediate;
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break;
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case FUNC3_BLT:
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// Branch Less Than
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if(((int32_t) cpu->regs.x[instruction->rs1]) < ((int32_t) cpu->regs.x[instruction->rs2]))
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cpu->pc = immediate;
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break;
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case FUNC3_BLTU:
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// Branch Less Than Unsigned
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if(cpu->regs.x[instruction->rs1] < cpu->regs.x[instruction->rs2])
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cpu->pc = immediate;
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break;
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case FUNC3_BGE:
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// Branch Greater Equal
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if(((int32_t) cpu->regs.x[instruction->rs1]) >= ((int32_t) cpu->regs.x[instruction->rs2]))
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cpu->pc = immediate;
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break;
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case FUNC3_BGEU:
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// Branch Greater Equal Unsigned
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if(cpu->regs.x[instruction->rs1] >= cpu->regs.x[instruction->rs2])
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cpu->pc = immediate;
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break;
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default:
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fprintf(stderr, "FATAL: Unknown func3 0x%x for branch instruction, could not execute\n", instruction->func3);
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exit(EXIT_FAILURE);
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break;
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}
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break;
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}
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case OPCODE_LOAD:
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{
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// Loads ; to know which one, we must analyse func3
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// Sign extend immediate from 12 bits to 32 bits
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uint32_t immediate = (instruction->immediate & 0xFFF) | (instruction->immediate & 0x800 ? 0xFFFFF000 : 0);
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uint32_t address = cpu->regs.x[instruction->rs1] + immediate;
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switch(instruction->func3)
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{
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case FUNC3_LB:
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// Load Byte (8-bits)
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cpu->regs.x[instruction->rd] = memory[mmu_translate(address)];
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// Sign extend from 8 bits to 32 bits
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cpu->regs.x[instruction->rd] |= (cpu->regs.x[instruction->rd] & 0x80 ? 0xFFFFFF00 : 0);
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break;
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case FUNC3_LH:
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// Load Halfword (16-bits)
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cpu->regs.x[instruction->rd] = *((uint16_t*) &memory[mmu_translate(address)]);
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// Sign extend from 16 bits to 32 bits
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cpu->regs.x[instruction->rd] |= (cpu->regs.x[instruction->rd] & 0x8000 ? 0xFFFF0000 : 0);
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break;
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case FUNC3_LW:
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// Load Word (32-bits)
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cpu->regs.x[instruction->rd] = *((uint32_t*) &memory[mmu_translate(address)]);
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break;
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case FUNC3_LBU:
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// Load Byte Unsigned (8-bits)
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cpu->regs.x[instruction->rd] = memory[mmu_translate(address)];
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break;
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case FUNC3_LHU:
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// Load Halfword Unsigned (16-bits)
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cpu->regs.x[instruction->rd] = *((uint16_t*) &memory[mmu_translate(address)]);
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break;
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default:
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fprintf(stderr, "FATAL: Unknown func3 0x%x for load instruction, could not execute\n", instruction->func3);
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exit(EXIT_FAILURE);
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break;
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}
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break;
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}
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case OPCODE_STORE:
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{
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// Store ; to know which one, we must analyse func3
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// Sign extend immediate from 12 bits to 32 bits
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uint32_t immediate = (instruction->immediate & 0xFFF) | (instruction->immediate & 0x800 ? 0xFFFFF000 : 0);
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uint32_t address = cpu->regs.x[instruction->rs1] + immediate;
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switch(instruction->func3)
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{
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case FUNC3_SB:
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// Store Byte (8-bits)
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memory[mmu_translate(address)] = cpu->regs.x[instruction->rs2] & 0xFF;
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break;
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case FUNC3_SH:
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// Store Halfword (16-bits)
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*((uint16_t*) &memory[mmu_translate(address)]) = cpu->regs.x[instruction->rs2] & 0xFFFF;
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break;
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case FUNC3_SW:
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// Store Word (32-bits)
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*((uint32_t*) &memory[mmu_translate(address)]) = cpu->regs.x[instruction->rs2];
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break;
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default:
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fprintf(stderr, "FATAL: Unknown func3 0x%x for store instruction, could not execute\n", instruction->func3);
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exit(EXIT_FAILURE);
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break;
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}
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break;
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}
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case OPCODE_ARITHLOG_IMM:
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{
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// Arithmetic and logic instructions on immediate values
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// To find out which operation, we must analyse func3
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// Sign extend immediate from 12 bits to 32 bits
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uint32_t immediate = (instruction->immediate & 0xFFF) | (instruction->immediate & 0x800 ? 0xFFFFF000 : 0);
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switch(instruction->func3)
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{
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case FUNC3_ADDI:
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// ADD Immediate
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] + immediate;
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break;
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case FUNC3_SLTI:
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// Set Less Than Immediate
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if(((int32_t) cpu->regs.x[instruction->rs1]) < ((int32_t) immediate))
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cpu->regs.x[instruction->rd] = 1;
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else
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cpu->regs.x[instruction->rd] = 0;
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break;
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case FUNC3_SLTIU:
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// Set Less Than Immediate Unsigned
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if(cpu->regs.x[instruction->rs1] < immediate)
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cpu->regs.x[instruction->rd] = 1;
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else
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cpu->regs.x[instruction->rd] = 0;
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break;
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case FUNC3_XORI:
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// XOR Immediate
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] ^ immediate;
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break;
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case FUNC3_ORI:
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// OR Immediate
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] | immediate;
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break;
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case FUNC3_ANDI:
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// AND Immediate
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] & immediate;
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break;
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case FUNC3_SLLI:
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// Sign-extend immediate in rs2 from 5 bits to 32 bits
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immediate = (cpu->regs.x[instruction->rs2] & 0x1F) | (cpu->regs.x[instruction->rs2] & 0x10 ? 0xFFFFFFE0 : 0);
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] << immediate;
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break;
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case FUNC3_SRLI_SRAI:
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// Sign-extend immediate in rs2 from 5 bits to 32 bits
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immediate = (cpu->regs.x[instruction->rs2] & 0x1F) | (cpu->regs.x[instruction->rs2] & 0x10 ? 0xFFFFFFE0 : 0);
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// Analyse func7 to know which is it
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switch(instruction->func7)
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{
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case FUNC7_SRLI:
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] >> immediate;
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break;
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case FUNC7_SRAI:
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// Arithmetic slide
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uint32_t sign_bit = cpu->regs.x[instruction->rs1] & 0x80000000;
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] >> immediate;
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if(sign_bit)
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cpu->regs.x[instruction->rd] |= ~(0xFFFFFFFF >> immediate);
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break;
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default:
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fprintf(stderr, "FATAL: Unknown func7 0x%x for arithlog immediate SRLI/SRAI instruction, could not execute\n", instruction->func7);
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exit(EXIT_FAILURE);
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break;
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}
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break;
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default:
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fprintf(stderr, "FATAL: Unknown func3 0x%x for arithlog immediate instruction, could not execute\n", instruction->func3);
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exit(EXIT_FAILURE);
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break;
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}
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break;
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}
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case OPCODE_ARITHLOG:
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{
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// Arithmetic and logic instructions
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// To find out which operation, we must analyse func3 and func7
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switch(instruction->func3)
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{
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case FUNC3_ADD_SUB:
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switch(instruction->func7)
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{
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case FUNC7_ADD:
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] + cpu->regs.x[instruction->rs2];
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break;
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case FUNC7_SUB:
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] - cpu->regs.x[instruction->rs2];
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break;
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default:
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fprintf(stderr, "FATAL: Unknown func7 0x%x for arithlog ADD/SUB instruction, could not execute\n", instruction->func7);
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exit(EXIT_FAILURE);
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break;
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}
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break;
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case FUNC3_SLL:
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// Slide Left Logical
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uint32_t sll_value = cpu->regs.x[instruction->rs2] & 0x1F;
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] << sll_value;
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break;
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case FUNC3_SLT:
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// Set Less Than
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if(((int32_t) cpu->regs.x[instruction->rs1]) < ((int32_t) cpu->regs.x[instruction->rs2]))
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cpu->regs.x[instruction->rd] = 1;
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else
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cpu->regs.x[instruction->rd] = 0;
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break;
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case FUNC3_SLTIU:
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// Set Less Than Unsigned
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if(cpu->regs.x[instruction->rs1] < cpu->regs.x[instruction->rs2])
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cpu->regs.x[instruction->rd] = 1;
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else
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cpu->regs.x[instruction->rd] = 0;
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break;
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case FUNC3_XOR:
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] ^ cpu->regs.x[instruction->rs2];
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break;
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case FUNC3_OR:
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] | cpu->regs.x[instruction->rs2];
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break;
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case FUNC3_AND:
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] & cpu->regs.x[instruction->rs2];
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break;
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case FUNC3_SRL_SRA:
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switch(instruction->func7)
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{
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case FUNC7_SRL:
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// Slide Right Logical
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uint32_t srl_value = cpu->regs.x[instruction->rs2] & 0x1F;
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] >> srl_value;
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break;
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case FUNC7_SRA:
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// Slide Right Arithmetical
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uint32_t sra_value = cpu->regs.x[instruction->rs2] & 0x1F;
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uint32_t sign_bit = cpu->regs.x[instruction->rs1] & 0x80000000;
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cpu->regs.x[instruction->rd] = cpu->regs.x[instruction->rs1] >> sra_value;
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if(sign_bit)
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cpu->regs.x[instruction->rd] |= ~(0xFFFFFFFF >> sra_value);
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break;
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default:
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fprintf(stderr, "FATAL: Unknown func7 0x%x for arithlog SRL/SRA instruction, could not execute\n", instruction->func7);
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exit(EXIT_FAILURE);
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break;
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}
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break;
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default:
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fprintf(stderr, "FATAL: Unknown func3 0x%x for arithlog instruction, could not execute\n", instruction->func3);
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exit(EXIT_FAILURE);
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break;
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}
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break;
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}
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case OPCODE_NOP:
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{
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// TODO : Implement PAUSE, FENCE, FENCE.TSO
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break;
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}
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case OPCODE_SYSTEM:
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{
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// TODO : Implement ECALL, EBREAK
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break;
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}
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default:
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fprintf(stderr, "FATAL: Unknown instruction opcode 0x%x while executing; how could this decode ?\n", instruction->opcode);
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exit(EXIT_FAILURE);
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break;
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}
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}
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void cpu_loop(rv32_cpu_t* cpu)
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{
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while(1)
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{
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||||
// Fetch
|
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raw_instruction_t raw_instruction;
|
||||
if(cpu->pc > memory_size - 4)
|
||||
{
|
||||
fprintf(stderr, "Error: instruction fetch: pc is out of addressable memory\n");
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
raw_instruction.data = *((uint32_t*) (&memory[cpu->pc]));
|
||||
|
||||
// Decode
|
||||
instruction_t instruction;
|
||||
cpu_decode(raw_instruction, &instruction);
|
||||
|
||||
// Execute
|
||||
cpu_execute(cpu, &instruction);
|
||||
|
||||
cpu->pc += 4;
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user