Initial commit

Added base code, can run ELF files and simulate RV32I instructions

README.md

@@ -0,0 +1,10 @@
+# vriscv - a risc-v simulator
+
+## Resources used
+
+Juraj's Blog, mostly:
+- https://jborza.com/post/2021-04-04-riscv-supervisor-mode/
+- https://jborza.com/emulation/2021/04/22/ecalls-and-syscalls.html
+
+Buildroot fork for nommu linux:
+- https://github.com/regymm/buildroot