Files
u-boot-krane/drivers
Julien StephanandDavid Lechner 6a77840b2f clk: mediatek: mt8188: fix top0 gate polarity
Gates in top0_cg_regs are active-high. The GATE_TOP0/GATE_TOP0E macros
set CLK_GATE_NO_SETCLR flags, which treat them as active-low. Enabling
the clock is currently disabling them.

Switch both macros to CLK_GATE_NO_SETCLR_INV to use the correct
active-high semantics.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Fixes: 11f3cc4632 ("clk: mediatek: add MT8188 clock driver")
Link: https://patch.msgid.link/20260728-mt8188-clk-fix-top0-gate-polarity-v1-1-56bc92ba6055@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-08-05 15:05:37 -05:00
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