Merge tag 'v2026.07-rc5' into next

Prepare v2026.07-rc5
2026-06-22 16:42:41 -06:00
parent 298d44464d f072620dc9
commit 9f16b258e5
111 changed files with 25651 additions and 8865 deletions
@@ -16,6 +16,9 @@
 *.dtb
 *.dtbo
 *.dtb.S
+*.dtb.clean.dts
+*.dtb.diff
+*.dtb.full.dts
 *.elf
 *.exe
 *.fit
@@ -26,7 +26,7 @@
      . /tmp/venv/bin/activate;
      pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
        -r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
-        labgrid setuptools
+        labgrid==25.0.1 setuptools
    # Acquire and turn on the exporter.
    - labgrid-client reserve --wait board=${LABGRID_EXPORTER} &&
      labgrid-client -p ${LABGRID_EXPORTER} acquire &&
@@ -548,7 +548,8 @@ config REMAKE_ELF

 config BUILD_TARGET
 	string "Build target special images"
-	default "u-boot-elf.srec" if RCAR_64
+	default "u-boot-elf.shdr" if RCAR_64 && RCAR_64_RSIP
+	default "u-boot-elf.srec" if RCAR_64 && !RCAR_64_RSIP
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
 	default "u-boot-with-spl.imx" if (ARCH_MX6 || ARCH_MX7) && SPL
@@ -3,7 +3,7 @@
 VERSION = 2026
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc5
 NAME =

 # *DOCUMENTATION*
@@ -2612,6 +2612,7 @@ clean: $(clean-dirs)
 		\( -name '*.[aios]' -o -name '*.ko' -o -name '.*.cmd' \
 		-o -name '*.ko.*' -o -name '*.su' -o -name '*.pyc' \
 		-o -name '*.dtb' -o -name '*.dtbo' -o -name '*.dtb.S' -o -name '*.dt.yaml' \
+		-o -name '*.dtb.clean.dts' -o -name '*.dtb.full.dts' -o -name '*.dtb.diff' \
 		-o -name '*.dwo' -o -name '*.lst' \
 		-o -name '*.su' -o -name '*.mod' -o -name '*.usyms' \
 		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
@@ -26,7 +26,7 @@ MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg
 #
 quiet_cmd_mkivt_mxs = MXSIVT  $@
 cmd_mkivt_mxs =								\
-	sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ;		\
+	sz=`expr \`stat -c "%s" $<\` + 64 + 3904 + 128` ;		\
 	echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" |	\
 	tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev |	\
 	sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@
@@ -34,15 +34,15 @@ cmd_mkivt_mxs =								\
 # Align binary to 64B
 quiet_cmd_mkalign_mxs = MXSALGN $@
 cmd_mkalign_mxs =							\
-	dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null &&			\
-	mv $@ $^
+	dd if=$< of=$@ ibs=64 conv=sync 2>/dev/null &&			\
+	mv $@ $<

 # Assemble the CSF file
 quiet_cmd_mkcsfreq_mxs = MXSCSFR $@
 cmd_mkcsfreq_mxs =							\
-	ivt=$(word 1,$^) ;						\
-	bin=$(word 2,$^) ;						\
-	csf=$(word 3,$^) ;						\
+	ivt=$(word 1,$(real-prereqs)) ;					\
+	bin=$(word 2,$(real-prereqs)) ;					\
+	csf=$(word 3,$(real-prereqs)) ;					\
 	sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" |		\
 		sed '/^\#\#Blocks/ d' > $@ ;				\
 	echo "  Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \
@@ -50,7 +50,7 @@ cmd_mkcsfreq_mxs =							\

 # Sign files
 quiet_cmd_mkcst_mxs = MXSCST  $@
-cmd_mkcst_mxs = cst -o $@ < $^						\
+cmd_mkcst_mxs = cst -o $@ < $<						\
 	$(if $(KBUILD_VERBOSE:1=), >/dev/null)

 spl/u-boot-spl.ivt: spl/u-boot-spl.bin FORCE
@@ -46,12 +46,6 @@ dtb-$(CONFIG_MACH_S900) += \
 dtb-$(CONFIG_MACH_S700) += \
 	s700-cubieboard7.dtb

-dtb-$(CONFIG_ROCKCHIP_RK3128) += \
-	rk3128-evb.dtb
-
-dtb-$(CONFIG_ROCKCHIP_RK322X) += \
-	rk3229-evb.dtb
-
 dtb-$(CONFIG_ROCKCHIP_RK3368) += \
 	rk3368-sheep.dtb \
 	rk3368-geekbox.dtb \
@@ -12,6 +12,9 @@
 		reg = <0x0 0x80000000 0x0 0x20000000>;
 	};

+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
 };

 	&sdhc {
@@ -6,7 +6,7 @@
 /dts-v1/;

 #include "k3-am68-sk-base-board.dts"
-#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
+#include "k3-am68-ddr-sk-lp4-4266.dtsi"
 #include "k3-j721s2-ddr.dtsi"
 #include "k3-am68-sk-base-board-u-boot.dtsi"
 #include "k3-j721s2-r5.dtsi"
@@ -6,7 +6,7 @@
 /dts-v1/;

 #include "k3-am69-sk.dts"
-#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
+#include "k3-am69-ddr-sk-lp4-4266.dtsi"
 #include "k3-j784s4-ddr.dtsi"
 #include "k3-am69-sk-u-boot.dtsi"
 #include "k3-j784s4-r5.dtsi"
@@ -1,14 +1,22 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
- * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0
- * This file was generated on 06/01/2021
+ * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated with the following tool revisions:
+ *     - SysConfig: Revision 1.25.0+4268
+ *     - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0
+ * This file was generated on Thu Oct 30 2025 13:11:41 GMT+0530 (India Standard Time)
 */

-#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FHS_CNT 5
 #define DDRSS_PLL_FREQUENCY_0 27500000
-#define DDRSS_PLL_FREQUENCY_1 666500000
-#define DDRSS_PLL_FREQUENCY_2 666500000
+#define DDRSS_PLL_FREQUENCY_1 800000000
+#define DDRSS_PLL_FREQUENCY_2 800000000
+
+#define DDR_REG0_SIZE_MSB 0x00000000
+#define DDR_REG0_SIZE_LSB 0x80000000
+#define DDR_REG1_SIZE_MSB 0x00000000
+#define DDR_REG1_SIZE_LSB 0x80000000
+

 #define DDRSS_CTL_00_DATA 0x00000B00
 #define DDRSS_CTL_01_DATA 0x00000000
@@ -21,16 +29,16 @@
 #define DDRSS_CTL_08_DATA 0x0001ADAF
 #define DDRSS_CTL_09_DATA 0x00000005
 #define DDRSS_CTL_10_DATA 0x0000006E
-#define DDRSS_CTL_11_DATA 0x000411AB
-#define DDRSS_CTL_12_DATA 0x0028B0AB
+#define DDRSS_CTL_11_DATA 0x0004E200
+#define DDRSS_CTL_12_DATA 0x0030D400
 #define DDRSS_CTL_13_DATA 0x00000005
-#define DDRSS_CTL_14_DATA 0x00000A6B
-#define DDRSS_CTL_15_DATA 0x000411AB
-#define DDRSS_CTL_16_DATA 0x0028B0AB
+#define DDRSS_CTL_14_DATA 0x00000C80
+#define DDRSS_CTL_15_DATA 0x0004E200
+#define DDRSS_CTL_16_DATA 0x0030D400
 #define DDRSS_CTL_17_DATA 0x00000005
-#define DDRSS_CTL_18_DATA 0x00000A6B
+#define DDRSS_CTL_18_DATA 0x00000C80
 #define DDRSS_CTL_19_DATA 0x01010000
-#define DDRSS_CTL_20_DATA 0x02011001
+#define DDRSS_CTL_20_DATA 0x01011001
 #define DDRSS_CTL_21_DATA 0x02010000
 #define DDRSS_CTL_22_DATA 0x00020100
 #define DDRSS_CTL_23_DATA 0x0000000B
@@ -38,66 +46,66 @@
 #define DDRSS_CTL_25_DATA 0x00000000
 #define DDRSS_CTL_26_DATA 0x00000000
 #define DDRSS_CTL_27_DATA 0x03020200
-#define DDRSS_CTL_28_DATA 0x00003636
+#define DDRSS_CTL_28_DATA 0x00004040
 #define DDRSS_CTL_29_DATA 0x00100000
 #define DDRSS_CTL_30_DATA 0x00000000
 #define DDRSS_CTL_31_DATA 0x00000000
 #define DDRSS_CTL_32_DATA 0x00000000
 #define DDRSS_CTL_33_DATA 0x00000000
 #define DDRSS_CTL_34_DATA 0x040C0000
-#define DDRSS_CTL_35_DATA 0x0C300C30
+#define DDRSS_CTL_35_DATA 0x0E400E40
 #define DDRSS_CTL_36_DATA 0x00050804
 #define DDRSS_CTL_37_DATA 0x09040008
-#define DDRSS_CTL_38_DATA 0x0D000204
-#define DDRSS_CTL_39_DATA 0x113C0057
-#define DDRSS_CTL_40_DATA 0x0D00291B
-#define DDRSS_CTL_41_DATA 0x113C0057
-#define DDRSS_CTL_42_DATA 0x2000291B
+#define DDRSS_CTL_38_DATA 0x14000304
+#define DDRSS_CTL_39_DATA 0x15480068
+#define DDRSS_CTL_40_DATA 0x14004220
+#define DDRSS_CTL_41_DATA 0x15480068
+#define DDRSS_CTL_42_DATA 0x20004220
 #define DDRSS_CTL_43_DATA 0x000A0A09
-#define DDRSS_CTL_44_DATA 0x0400078A
-#define DDRSS_CTL_45_DATA 0x130E0B04
-#define DDRSS_CTL_46_DATA 0x0A00B6D0
-#define DDRSS_CTL_47_DATA 0x130E0B0A
-#define DDRSS_CTL_48_DATA 0x0A00B6D0
-#define DDRSS_CTL_49_DATA 0x0203040A
-#define DDRSS_CTL_50_DATA 0x1C040500
-#define DDRSS_CTL_51_DATA 0x081D1C1D
+#define DDRSS_CTL_44_DATA 0x040003C5
+#define DDRSS_CTL_45_DATA 0x17100D04
+#define DDRSS_CTL_46_DATA 0x0C006DB0
+#define DDRSS_CTL_47_DATA 0x17100D0C
+#define DDRSS_CTL_48_DATA 0x0C006DB0
+#define DDRSS_CTL_49_DATA 0x0203040C
+#define DDRSS_CTL_50_DATA 0x21060500
+#define DDRSS_CTL_51_DATA 0x08222122
 #define DDRSS_CTL_52_DATA 0x14000E0A
-#define DDRSS_CTL_53_DATA 0x02010A0A
-#define DDRSS_CTL_54_DATA 0x01010002
-#define DDRSS_CTL_55_DATA 0x04383808
-#define DDRSS_CTL_56_DATA 0x041F1F04
-#define DDRSS_CTL_57_DATA 0x00001F1F
+#define DDRSS_CTL_53_DATA 0x03010A0A
+#define DDRSS_CTL_54_DATA 0x01010003
+#define DDRSS_CTL_55_DATA 0x0442420A
+#define DDRSS_CTL_56_DATA 0x04252504
+#define DDRSS_CTL_57_DATA 0x00002525
 #define DDRSS_CTL_58_DATA 0x00010100
 #define DDRSS_CTL_59_DATA 0x03010000
 #define DDRSS_CTL_60_DATA 0x00001008
-#define DDRSS_CTL_61_DATA 0x000000CE
-#define DDRSS_CTL_62_DATA 0x00000176
-#define DDRSS_CTL_63_DATA 0x00001448
-#define DDRSS_CTL_64_DATA 0x00000176
-#define DDRSS_CTL_65_DATA 0x00001448
+#define DDRSS_CTL_61_DATA 0x00000068
+#define DDRSS_CTL_62_DATA 0x000001C0
+#define DDRSS_CTL_63_DATA 0x00000C28
+#define DDRSS_CTL_64_DATA 0x000001C0
+#define DDRSS_CTL_65_DATA 0x00000C28
 #define DDRSS_CTL_66_DATA 0x00000005
 #define DDRSS_CTL_67_DATA 0x00040000
-#define DDRSS_CTL_68_DATA 0x005D0012
-#define DDRSS_CTL_69_DATA 0x005D0282
-#define DDRSS_CTL_70_DATA 0x00400282
+#define DDRSS_CTL_68_DATA 0x00700005
+#define DDRSS_CTL_69_DATA 0x0070017E
+#define DDRSS_CTL_70_DATA 0x0040017E
 #define DDRSS_CTL_71_DATA 0x00120103
-#define DDRSS_CTL_72_DATA 0x000A0005
-#define DDRSS_CTL_73_DATA 0x1F08000A
-#define DDRSS_CTL_74_DATA 0x0505011F
+#define DDRSS_CTL_72_DATA 0x000C0005
+#define DDRSS_CTL_73_DATA 0x2408000C
+#define DDRSS_CTL_74_DATA 0x05050124
 #define DDRSS_CTL_75_DATA 0x0301030A
-#define DDRSS_CTL_76_DATA 0x03130A07
-#define DDRSS_CTL_77_DATA 0x0A070301
-#define DDRSS_CTL_78_DATA 0x00010313
+#define DDRSS_CTL_76_DATA 0x03170C08
+#define DDRSS_CTL_77_DATA 0x0C080301
+#define DDRSS_CTL_78_DATA 0x00010317
 #define DDRSS_CTL_79_DATA 0x00100010
-#define DDRSS_CTL_80_DATA 0x01800180
-#define DDRSS_CTL_81_DATA 0x01800180
+#define DDRSS_CTL_80_DATA 0x01CC01CC
+#define DDRSS_CTL_81_DATA 0x01CC01CC
 #define DDRSS_CTL_82_DATA 0x03050505
 #define DDRSS_CTL_83_DATA 0x03010303
-#define DDRSS_CTL_84_DATA 0x14070A07
-#define DDRSS_CTL_85_DATA 0x03030A03
-#define DDRSS_CTL_86_DATA 0x14070A07
-#define DDRSS_CTL_87_DATA 0x03030A03
+#define DDRSS_CTL_84_DATA 0x18080C08
+#define DDRSS_CTL_85_DATA 0x03030C03
+#define DDRSS_CTL_86_DATA 0x18080C08
+#define DDRSS_CTL_87_DATA 0x03030C03
 #define DDRSS_CTL_88_DATA 0x03010000
 #define DDRSS_CTL_89_DATA 0x00010000
 #define DDRSS_CTL_90_DATA 0x00000000
@@ -112,27 +120,27 @@
 #define DDRSS_CTL_99_DATA 0x00000000
 #define DDRSS_CTL_100_DATA 0x00040005
 #define DDRSS_CTL_101_DATA 0x00000000
-#define DDRSS_CTL_102_DATA 0x00003380
-#define DDRSS_CTL_103_DATA 0x00003380
-#define DDRSS_CTL_104_DATA 0x00003380
-#define DDRSS_CTL_105_DATA 0x00003380
-#define DDRSS_CTL_106_DATA 0x00003380
+#define DDRSS_CTL_102_DATA 0x000018C0
+#define DDRSS_CTL_103_DATA 0x000018C0
+#define DDRSS_CTL_104_DATA 0x000018C0
+#define DDRSS_CTL_105_DATA 0x000018C0
+#define DDRSS_CTL_106_DATA 0x000018C0
 #define DDRSS_CTL_107_DATA 0x00000000
-#define DDRSS_CTL_108_DATA 0x000005A2
-#define DDRSS_CTL_109_DATA 0x00051200
-#define DDRSS_CTL_110_DATA 0x00051200
-#define DDRSS_CTL_111_DATA 0x00051200
-#define DDRSS_CTL_112_DATA 0x00051200
-#define DDRSS_CTL_113_DATA 0x00051200
+#define DDRSS_CTL_108_DATA 0x000002B5
+#define DDRSS_CTL_109_DATA 0x00030A00
+#define DDRSS_CTL_110_DATA 0x00030A00
+#define DDRSS_CTL_111_DATA 0x00030A00
+#define DDRSS_CTL_112_DATA 0x00030A00
+#define DDRSS_CTL_113_DATA 0x00030A00
 #define DDRSS_CTL_114_DATA 0x00000000
-#define DDRSS_CTL_115_DATA 0x00008DF8
-#define DDRSS_CTL_116_DATA 0x00051200
-#define DDRSS_CTL_117_DATA 0x00051200
-#define DDRSS_CTL_118_DATA 0x00051200
-#define DDRSS_CTL_119_DATA 0x00051200
-#define DDRSS_CTL_120_DATA 0x00051200
+#define DDRSS_CTL_115_DATA 0x00005518
+#define DDRSS_CTL_116_DATA 0x00030A00
+#define DDRSS_CTL_117_DATA 0x00030A00
+#define DDRSS_CTL_118_DATA 0x00030A00
+#define DDRSS_CTL_119_DATA 0x00030A00
+#define DDRSS_CTL_120_DATA 0x00030A00
 #define DDRSS_CTL_121_DATA 0x00000000
-#define DDRSS_CTL_122_DATA 0x00008DF8
+#define DDRSS_CTL_122_DATA 0x00005518
 #define DDRSS_CTL_123_DATA 0x00000000
 #define DDRSS_CTL_124_DATA 0x00000000
 #define DDRSS_CTL_125_DATA 0x00000000
@@ -141,8 +149,8 @@
 #define DDRSS_CTL_128_DATA 0x00000000
 #define DDRSS_CTL_129_DATA 0x00000000
 #define DDRSS_CTL_130_DATA 0x00000000
-#define DDRSS_CTL_131_DATA 0x07030500
-#define DDRSS_CTL_132_DATA 0x00030703
+#define DDRSS_CTL_131_DATA 0x08030500
+#define DDRSS_CTL_132_DATA 0x00030803
 #define DDRSS_CTL_133_DATA 0x0A090000
 #define DDRSS_CTL_134_DATA 0x0A090701
 #define DDRSS_CTL_135_DATA 0x0900000E
@@ -177,31 +185,31 @@
 #define DDRSS_CTL_164_DATA 0x000B0000
 #define DDRSS_CTL_165_DATA 0x000E0006
 #define DDRSS_CTL_166_DATA 0x000E0404
-#define DDRSS_CTL_167_DATA 0x0086010B
-#define DDRSS_CTL_168_DATA 0x0A0A014E
-#define DDRSS_CTL_169_DATA 0x010B014E
-#define DDRSS_CTL_170_DATA 0x014E0086
-#define DDRSS_CTL_171_DATA 0x014E0A0A
+#define DDRSS_CTL_167_DATA 0x00A00140
+#define DDRSS_CTL_168_DATA 0x0C0C0190
+#define DDRSS_CTL_169_DATA 0x01400190
+#define DDRSS_CTL_170_DATA 0x019000A0
+#define DDRSS_CTL_171_DATA 0x01900C0C
 #define DDRSS_CTL_172_DATA 0x00000000
 #define DDRSS_CTL_173_DATA 0x00000000
 #define DDRSS_CTL_174_DATA 0x00000000
-#define DDRSS_CTL_175_DATA 0x24C40084
-#define DDRSS_CTL_176_DATA 0x2B0024C4
-#define DDRSS_CTL_177_DATA 0x00002B2B
+#define DDRSS_CTL_175_DATA 0x2DD40084
+#define DDRSS_CTL_176_DATA 0xEB002DD4
+#define DDRSS_CTL_177_DATA 0x0000EBEB
 #define DDRSS_CTL_178_DATA 0x36000000
 #define DDRSS_CTL_179_DATA 0x27270036
 #define DDRSS_CTL_180_DATA 0x0F0F0000
 #define DDRSS_CTL_181_DATA 0x15000000
 #define DDRSS_CTL_182_DATA 0x00841515
-#define DDRSS_CTL_183_DATA 0x24C424C4
-#define DDRSS_CTL_184_DATA 0x2B2B2B00
+#define DDRSS_CTL_183_DATA 0x2DD42DD4
+#define DDRSS_CTL_184_DATA 0xEBEBEB00
 #define DDRSS_CTL_185_DATA 0x00000000
 #define DDRSS_CTL_186_DATA 0x00363600
 #define DDRSS_CTL_187_DATA 0x00002727
 #define DDRSS_CTL_188_DATA 0x00000F0F
 #define DDRSS_CTL_189_DATA 0x15151500
 #define DDRSS_CTL_190_DATA 0x00000020
-#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x01000000
 #define DDRSS_CTL_192_DATA 0x00000001
 #define DDRSS_CTL_193_DATA 0x00000000
 #define DDRSS_CTL_194_DATA 0x01000000
@@ -239,17 +247,17 @@
 #define DDRSS_CTL_226_DATA 0x00000000
 #define DDRSS_CTL_227_DATA 0x15110000
 #define DDRSS_CTL_228_DATA 0x00040C18
-#define DDRSS_CTL_229_DATA 0x00000000
-#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_229_DATA 0xF000C000
+#define DDRSS_CTL_230_DATA 0x0000F000
 #define DDRSS_CTL_231_DATA 0x00000000
 #define DDRSS_CTL_232_DATA 0x00000000
-#define DDRSS_CTL_233_DATA 0x00000000
-#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0xC0000000
+#define DDRSS_CTL_234_DATA 0xF000F000
 #define DDRSS_CTL_235_DATA 0x00000000
 #define DDRSS_CTL_236_DATA 0x00000000
 #define DDRSS_CTL_237_DATA 0x00000000
-#define DDRSS_CTL_238_DATA 0x00000000
-#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0xF000C000
+#define DDRSS_CTL_239_DATA 0x0000F000
 #define DDRSS_CTL_240_DATA 0x00000000
 #define DDRSS_CTL_241_DATA 0x00000000
 #define DDRSS_CTL_242_DATA 0x00030000
@@ -271,13 +279,13 @@
 #define DDRSS_CTL_258_DATA 0x00370040
 #define DDRSS_CTL_259_DATA 0x00020008
 #define DDRSS_CTL_260_DATA 0x00400100
-#define DDRSS_CTL_261_DATA 0x00280536
+#define DDRSS_CTL_261_DATA 0x00300640
 #define DDRSS_CTL_262_DATA 0x01000200
-#define DDRSS_CTL_263_DATA 0x05360040
-#define DDRSS_CTL_264_DATA 0x00000028
-#define DDRSS_CTL_265_DATA 0x00430003
-#define DDRSS_CTL_266_DATA 0x01000043
-#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x06400040
+#define DDRSS_CTL_264_DATA 0x00000030
+#define DDRSS_CTL_265_DATA 0x00500003
+#define DDRSS_CTL_266_DATA 0x01000050
+#define DDRSS_CTL_267_DATA 0x03030303
 #define DDRSS_CTL_268_DATA 0x01010000
 #define DDRSS_CTL_269_DATA 0x00000202
 #define DDRSS_CTL_270_DATA 0x00000FFF
@@ -301,14 +309,14 @@
 #define DDRSS_CTL_288_DATA 0x00000000
 #define DDRSS_CTL_289_DATA 0x00000000
 #define DDRSS_CTL_290_DATA 0x03030300
-#define DDRSS_CTL_291_DATA 0x00000001
+#define DDRSS_CTL_291_DATA 0x00010101
 #define DDRSS_CTL_292_DATA 0x00000000
 #define DDRSS_CTL_293_DATA 0x00000000
 #define DDRSS_CTL_294_DATA 0x00000000
 #define DDRSS_CTL_295_DATA 0x00000000
 #define DDRSS_CTL_296_DATA 0x00000000
-#define DDRSS_CTL_297_DATA 0x00000000
-#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS_CTL_298_DATA 0x00000FFF
 #define DDRSS_CTL_299_DATA 0x00000000
 #define DDRSS_CTL_300_DATA 0x00000000
 #define DDRSS_CTL_301_DATA 0x00000000
@@ -328,15 +336,15 @@
 #define DDRSS_CTL_315_DATA 0x01000101
 #define DDRSS_CTL_316_DATA 0x01010001
 #define DDRSS_CTL_317_DATA 0x00010101
-#define DDRSS_CTL_318_DATA 0x05070703
-#define DDRSS_CTL_319_DATA 0x0A081414
-#define DDRSS_CTL_320_DATA 0x0009030A
-#define DDRSS_CTL_321_DATA 0x080C030F
-#define DDRSS_CTL_322_DATA 0x080C0306
-#define DDRSS_CTL_323_DATA 0x0C090006
-#define DDRSS_CTL_324_DATA 0x0100000C
-#define DDRSS_CTL_325_DATA 0x05020501
-#define DDRSS_CTL_326_DATA 0x00000002
+#define DDRSS_CTL_318_DATA 0x05080803
+#define DDRSS_CTL_319_DATA 0x0C081C1C
+#define DDRSS_CTL_320_DATA 0x0009030C
+#define DDRSS_CTL_321_DATA 0x090B030F
+#define DDRSS_CTL_322_DATA 0x090B0306
+#define DDRSS_CTL_323_DATA 0x0B090006
+#define DDRSS_CTL_324_DATA 0x0100000B
+#define DDRSS_CTL_325_DATA 0x06030601
+#define DDRSS_CTL_326_DATA 0x00000003
 #define DDRSS_CTL_327_DATA 0x00000000
 #define DDRSS_CTL_328_DATA 0x00010000
 #define DDRSS_CTL_329_DATA 0x00280D00
@@ -397,32 +405,32 @@
 #define DDRSS_CTL_384_DATA 0x00000000
 #define DDRSS_CTL_385_DATA 0x00000000
 #define DDRSS_CTL_386_DATA 0x00000000
-#define DDRSS_CTL_387_DATA 0x2E2E1B00
+#define DDRSS_CTL_387_DATA 0x33331B00
 #define DDRSS_CTL_388_DATA 0x000A0000
-#define DDRSS_CTL_389_DATA 0x0000019C
+#define DDRSS_CTL_389_DATA 0x000000C6
 #define DDRSS_CTL_390_DATA 0x00000200
 #define DDRSS_CTL_391_DATA 0x00000200
 #define DDRSS_CTL_392_DATA 0x00000200
 #define DDRSS_CTL_393_DATA 0x00000200
-#define DDRSS_CTL_394_DATA 0x000004D4
-#define DDRSS_CTL_395_DATA 0x00001018
+#define DDRSS_CTL_394_DATA 0x00000270
+#define DDRSS_CTL_395_DATA 0x000007BC
 #define DDRSS_CTL_396_DATA 0x00000204
-#define DDRSS_CTL_397_DATA 0x00002890
+#define DDRSS_CTL_397_DATA 0x00001850
 #define DDRSS_CTL_398_DATA 0x00000200
 #define DDRSS_CTL_399_DATA 0x00000200
 #define DDRSS_CTL_400_DATA 0x00000200
 #define DDRSS_CTL_401_DATA 0x00000200
-#define DDRSS_CTL_402_DATA 0x000079B0
-#define DDRSS_CTL_403_DATA 0x000195A0
-#define DDRSS_CTL_404_DATA 0x0000080E
-#define DDRSS_CTL_405_DATA 0x00002890
+#define DDRSS_CTL_402_DATA 0x000048F0
+#define DDRSS_CTL_403_DATA 0x0000F320
+#define DDRSS_CTL_404_DATA 0x00000A14
+#define DDRSS_CTL_405_DATA 0x00001850
 #define DDRSS_CTL_406_DATA 0x00000200
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x00000200
 #define DDRSS_CTL_409_DATA 0x00000200
-#define DDRSS_CTL_410_DATA 0x000079B0
-#define DDRSS_CTL_411_DATA 0x000195A0
-#define DDRSS_CTL_412_DATA 0x0202080E
+#define DDRSS_CTL_410_DATA 0x000048F0
+#define DDRSS_CTL_411_DATA 0x0000F320
+#define DDRSS_CTL_412_DATA 0x02020A14
 #define DDRSS_CTL_413_DATA 0x03030202
 #define DDRSS_CTL_414_DATA 0x00000022
 #define DDRSS_CTL_415_DATA 0x00000000
@@ -433,13 +441,13 @@
 #define DDRSS_CTL_420_DATA 0x00000000
 #define DDRSS_CTL_421_DATA 0x00030000
 #define DDRSS_CTL_422_DATA 0x0007001F
-#define DDRSS_CTL_423_DATA 0x0013002B
-#define DDRSS_CTL_424_DATA 0x0013002B
+#define DDRSS_CTL_423_DATA 0x0016002E
+#define DDRSS_CTL_424_DATA 0x0016002E
 #define DDRSS_CTL_425_DATA 0x00000000
 #define DDRSS_CTL_426_DATA 0x00000000
 #define DDRSS_CTL_427_DATA 0x02000000
 #define DDRSS_CTL_428_DATA 0x01000404
-#define DDRSS_CTL_429_DATA 0x05120512
+#define DDRSS_CTL_429_DATA 0x071A071A
 #define DDRSS_CTL_430_DATA 0x00000105
 #define DDRSS_CTL_431_DATA 0x00010101
 #define DDRSS_CTL_432_DATA 0x00010101
@@ -448,8 +456,8 @@
 #define DDRSS_CTL_435_DATA 0x02000201
 #define DDRSS_CTL_436_DATA 0x02010000
 #define DDRSS_CTL_437_DATA 0x00000200
-#define DDRSS_CTL_438_DATA 0x18060000
-#define DDRSS_CTL_439_DATA 0x00000118
+#define DDRSS_CTL_438_DATA 0x1E060000
+#define DDRSS_CTL_439_DATA 0x0000011E
 #define DDRSS_CTL_440_DATA 0xFFFFFFFF
 #define DDRSS_CTL_441_DATA 0xFFFFFFFF
 #define DDRSS_CTL_442_DATA 0x00000000
@@ -482,8 +490,8 @@
 #define DDRSS_PI_09_DATA 0x00000000
 #define DDRSS_PI_10_DATA 0x00000000
 #define DDRSS_PI_11_DATA 0x00000000
-#define DDRSS_PI_12_DATA 0x00000007
-#define DDRSS_PI_13_DATA 0x00010002
+#define DDRSS_PI_12_DATA 0x00000003
+#define DDRSS_PI_13_DATA 0x00010001
 #define DDRSS_PI_14_DATA 0x0800000F
 #define DDRSS_PI_15_DATA 0x00000103
 #define DDRSS_PI_16_DATA 0x00000005
@@ -516,7 +524,7 @@
 #define DDRSS_PI_43_DATA 0x00000000
 #define DDRSS_PI_44_DATA 0x00000000
 #define DDRSS_PI_45_DATA 0x000F0F00
-#define DDRSS_PI_46_DATA 0x00000017
+#define DDRSS_PI_46_DATA 0x00000019
 #define DDRSS_PI_47_DATA 0x000007D0
 #define DDRSS_PI_48_DATA 0x00000300
 #define DDRSS_PI_49_DATA 0x00000000
@@ -531,18 +539,18 @@
 #define DDRSS_PI_58_DATA 0x00000000
 #define DDRSS_PI_59_DATA 0x00000000
 #define DDRSS_PI_60_DATA 0x0A0A140A
-#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_61_DATA 0x10020201
 #define DDRSS_PI_62_DATA 0x00020805
 #define DDRSS_PI_63_DATA 0x01000404
 #define DDRSS_PI_64_DATA 0x00000000
 #define DDRSS_PI_65_DATA 0x00000000
-#define DDRSS_PI_66_DATA 0x00000100
-#define DDRSS_PI_67_DATA 0x0001010F
+#define DDRSS_PI_66_DATA 0x01000100
+#define DDRSS_PI_67_DATA 0x0102020F
 #define DDRSS_PI_68_DATA 0x00340000
 #define DDRSS_PI_69_DATA 0x00000000
 #define DDRSS_PI_70_DATA 0x00000000
 #define DDRSS_PI_71_DATA 0x0000FFFF
-#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_72_DATA 0x01000000
 #define DDRSS_PI_73_DATA 0x00080100
 #define DDRSS_PI_74_DATA 0x02000200
 #define DDRSS_PI_75_DATA 0x01000100
@@ -631,104 +639,104 @@
 #define DDRSS_PI_158_DATA 0x00000000
 #define DDRSS_PI_159_DATA 0x00000401
 #define DDRSS_PI_160_DATA 0x00000000
-#define DDRSS_PI_161_DATA 0x00010000
-#define DDRSS_PI_162_DATA 0x00000000
-#define DDRSS_PI_163_DATA 0x1B1B0200
+#define DDRSS_PI_161_DATA 0x05010000
+#define DDRSS_PI_162_DATA 0x00000001
+#define DDRSS_PI_163_DATA 0x20200201
 #define DDRSS_PI_164_DATA 0x00000034
-#define DDRSS_PI_165_DATA 0x00000051
-#define DDRSS_PI_166_DATA 0x00020051
+#define DDRSS_PI_165_DATA 0x0000005C
+#define DDRSS_PI_166_DATA 0x0002005C
 #define DDRSS_PI_167_DATA 0x02000200
-#define DDRSS_PI_168_DATA 0x300C0C04
-#define DDRSS_PI_169_DATA 0x0010300C
-#define DDRSS_PI_170_DATA 0x000000CE
-#define DDRSS_PI_171_DATA 0x00000176
-#define DDRSS_PI_172_DATA 0x00001448
-#define DDRSS_PI_173_DATA 0x00000176
-#define DDRSS_PI_174_DATA 0x04001448
+#define DDRSS_PI_168_DATA 0x400E0C04
+#define DDRSS_PI_169_DATA 0x0010400E
+#define DDRSS_PI_170_DATA 0x00000068
+#define DDRSS_PI_171_DATA 0x000001C0
+#define DDRSS_PI_172_DATA 0x00000C28
+#define DDRSS_PI_173_DATA 0x000001C0
+#define DDRSS_PI_174_DATA 0x04000C28
 #define DDRSS_PI_175_DATA 0x01010404
-#define DDRSS_PI_176_DATA 0x00001501
+#define DDRSS_PI_176_DATA 0x00001500
 #define DDRSS_PI_177_DATA 0x00150015
 #define DDRSS_PI_178_DATA 0x01000100
 #define DDRSS_PI_179_DATA 0x00000100
 #define DDRSS_PI_180_DATA 0x00000000
 #define DDRSS_PI_181_DATA 0x01010101
-#define DDRSS_PI_182_DATA 0x00000101
-#define DDRSS_PI_183_DATA 0x00000100
-#define DDRSS_PI_184_DATA 0x00000100
-#define DDRSS_PI_185_DATA 0x0E040100
-#define DDRSS_PI_186_DATA 0x0808020E
+#define DDRSS_PI_182_DATA 0x00010000
+#define DDRSS_PI_183_DATA 0x00010100
+#define DDRSS_PI_184_DATA 0x00010100
+#define DDRSS_PI_185_DATA 0x14040100
+#define DDRSS_PI_186_DATA 0x0A0A0214
 #define DDRSS_PI_187_DATA 0x00040402
 #define DDRSS_PI_188_DATA 0x000D0035
-#define DDRSS_PI_189_DATA 0x00198041
-#define DDRSS_PI_190_DATA 0x00198041
-#define DDRSS_PI_191_DATA 0x01010101
-#define DDRSS_PI_192_DATA 0x0002000E
-#define DDRSS_PI_193_DATA 0x0002014E
-#define DDRSS_PI_194_DATA 0x0100014E
+#define DDRSS_PI_189_DATA 0x001C0044
+#define DDRSS_PI_190_DATA 0x001C0044
+#define DDRSS_PI_191_DATA 0x01000101
+#define DDRSS_PI_192_DATA 0x0003000E
+#define DDRSS_PI_193_DATA 0x00030190
+#define DDRSS_PI_194_DATA 0x01000190
 #define DDRSS_PI_195_DATA 0x000F000F
-#define DDRSS_PI_196_DATA 0x014F0100
-#define DDRSS_PI_197_DATA 0x0100014F
-#define DDRSS_PI_198_DATA 0x014F014F
-#define DDRSS_PI_199_DATA 0x32103200
-#define DDRSS_PI_200_DATA 0x01013210
+#define DDRSS_PI_196_DATA 0x01910100
+#define DDRSS_PI_197_DATA 0x01000191
+#define DDRSS_PI_198_DATA 0x01910191
+#define DDRSS_PI_199_DATA 0x2F1B3200
+#define DDRSS_PI_200_DATA 0x01012F1B
 #define DDRSS_PI_201_DATA 0x0A070601
-#define DDRSS_PI_202_DATA 0x140D080D
-#define DDRSS_PI_203_DATA 0x140D0810
-#define DDRSS_PI_204_DATA 0x0000C010
+#define DDRSS_PI_202_DATA 0x180F090D
+#define DDRSS_PI_203_DATA 0x180F0911
+#define DDRSS_PI_204_DATA 0x0000C011
 #define DDRSS_PI_205_DATA 0x00C01000
 #define DDRSS_PI_206_DATA 0x00C01000
 #define DDRSS_PI_207_DATA 0x00021000
-#define DDRSS_PI_208_DATA 0x001C000E
-#define DDRSS_PI_209_DATA 0x001C014E
-#define DDRSS_PI_210_DATA 0x0011014E
+#define DDRSS_PI_208_DATA 0x001E000E
+#define DDRSS_PI_209_DATA 0x001E0190
+#define DDRSS_PI_210_DATA 0x00110190
 #define DDRSS_PI_211_DATA 0x32000056
-#define DDRSS_PI_212_DATA 0x00000301
-#define DDRSS_PI_213_DATA 0x005A002A
+#define DDRSS_PI_212_DATA 0x00000101
+#define DDRSS_PI_213_DATA 0x005E0030
 #define DDRSS_PI_214_DATA 0x03013212
-#define DDRSS_PI_215_DATA 0x00002A00
-#define DDRSS_PI_216_DATA 0x3212005A
-#define DDRSS_PI_217_DATA 0x09000301
-#define DDRSS_PI_218_DATA 0x04010504
-#define DDRSS_PI_219_DATA 0x040006C9
+#define DDRSS_PI_215_DATA 0x00003000
+#define DDRSS_PI_216_DATA 0x3212005E
+#define DDRSS_PI_217_DATA 0x09000001
+#define DDRSS_PI_218_DATA 0x06010504
+#define DDRSS_PI_219_DATA 0x04000364
 #define DDRSS_PI_220_DATA 0x0A032001
-#define DDRSS_PI_221_DATA 0x1C1F0B0A
-#define DDRSS_PI_222_DATA 0x00001D12
-#define DDRSS_PI_223_DATA 0x3C00A488
-#define DDRSS_PI_224_DATA 0x13142005
-#define DDRSS_PI_225_DATA 0x1C1F0B0E
-#define DDRSS_PI_226_DATA 0x00001D12
-#define DDRSS_PI_227_DATA 0x3C00A488
-#define DDRSS_PI_228_DATA 0x13142005
-#define DDRSS_PI_229_DATA 0x00019C0E
-#define DDRSS_PI_230_DATA 0x00001018
-#define DDRSS_PI_231_DATA 0x00002890
-#define DDRSS_PI_232_DATA 0x000195A0
-#define DDRSS_PI_233_DATA 0x00002890
-#define DDRSS_PI_234_DATA 0x000195A0
-#define DDRSS_PI_235_DATA 0x01800010
-#define DDRSS_PI_236_DATA 0x03030180
+#define DDRSS_PI_221_DATA 0x21250D0A
+#define DDRSS_PI_222_DATA 0x00002216
+#define DDRSS_PI_223_DATA 0x480062B8
+#define DDRSS_PI_224_DATA 0x17182006
+#define DDRSS_PI_225_DATA 0x21250D10
+#define DDRSS_PI_226_DATA 0x00002216
+#define DDRSS_PI_227_DATA 0x480062B8
+#define DDRSS_PI_228_DATA 0x17182006
+#define DDRSS_PI_229_DATA 0x0000C610
+#define DDRSS_PI_230_DATA 0x000007BC
+#define DDRSS_PI_231_DATA 0x00001850
+#define DDRSS_PI_232_DATA 0x0000F320
+#define DDRSS_PI_233_DATA 0x00001850
+#define DDRSS_PI_234_DATA 0x0000F320
+#define DDRSS_PI_235_DATA 0x01CC0010
+#define DDRSS_PI_236_DATA 0x030301CC
 #define DDRSS_PI_237_DATA 0x002AF803
 #define DDRSS_PI_238_DATA 0x0001ADAF
 #define DDRSS_PI_239_DATA 0x00000005
 #define DDRSS_PI_240_DATA 0x0000006E
 #define DDRSS_PI_241_DATA 0x00000010
-#define DDRSS_PI_242_DATA 0x000411AB
+#define DDRSS_PI_242_DATA 0x0004E200
 #define DDRSS_PI_243_DATA 0x0001ADAF
 #define DDRSS_PI_244_DATA 0x00000005
-#define DDRSS_PI_245_DATA 0x00000A6B
-#define DDRSS_PI_246_DATA 0x00000180
-#define DDRSS_PI_247_DATA 0x000411AB
+#define DDRSS_PI_245_DATA 0x00000C80
+#define DDRSS_PI_246_DATA 0x000001CC
+#define DDRSS_PI_247_DATA 0x0004E200
 #define DDRSS_PI_248_DATA 0x0001ADAF
 #define DDRSS_PI_249_DATA 0x00000005
-#define DDRSS_PI_250_DATA 0x00000A6B
-#define DDRSS_PI_251_DATA 0x01000180
+#define DDRSS_PI_250_DATA 0x00000C80
+#define DDRSS_PI_251_DATA 0x010001CC
 #define DDRSS_PI_252_DATA 0x00370040
 #define DDRSS_PI_253_DATA 0x00010008
-#define DDRSS_PI_254_DATA 0x05360040
-#define DDRSS_PI_255_DATA 0x00010028
-#define DDRSS_PI_256_DATA 0x05360040
-#define DDRSS_PI_257_DATA 0x00000328
-#define DDRSS_PI_258_DATA 0x00430043
+#define DDRSS_PI_254_DATA 0x06400040
+#define DDRSS_PI_255_DATA 0x00010030
+#define DDRSS_PI_256_DATA 0x06400040
+#define DDRSS_PI_257_DATA 0x00000330
+#define DDRSS_PI_258_DATA 0x00500050
 #define DDRSS_PI_259_DATA 0x08040404
 #define DDRSS_PI_260_DATA 0x00000055
 #define DDRSS_PI_261_DATA 0x55083C5A
@@ -745,29 +753,29 @@
 #define DDRSS_PI_272_DATA 0x00080804
 #define DDRSS_PI_273_DATA 0x00000000
 #define DDRSS_PI_274_DATA 0x00000000
-#define DDRSS_PI_275_DATA 0x002B0084
+#define DDRSS_PI_275_DATA 0x00EB0084
 #define DDRSS_PI_276_DATA 0x00150000
-#define DDRSS_PI_277_DATA 0x362B24C4
+#define DDRSS_PI_277_DATA 0x36EB2DD4
 #define DDRSS_PI_278_DATA 0x00150F27
-#define DDRSS_PI_279_DATA 0x362B24C4
+#define DDRSS_PI_279_DATA 0x36EB2DD4
 #define DDRSS_PI_280_DATA 0x00150F27
-#define DDRSS_PI_281_DATA 0x002B0084
+#define DDRSS_PI_281_DATA 0x00EB0084
 #define DDRSS_PI_282_DATA 0x00150000
-#define DDRSS_PI_283_DATA 0x362B24C4
+#define DDRSS_PI_283_DATA 0x36EB2DD4
 #define DDRSS_PI_284_DATA 0x00150F27
-#define DDRSS_PI_285_DATA 0x362B24C4
+#define DDRSS_PI_285_DATA 0x36EB2DD4
 #define DDRSS_PI_286_DATA 0x00150F27
-#define DDRSS_PI_287_DATA 0x002B0084
+#define DDRSS_PI_287_DATA 0x00EB0084
 #define DDRSS_PI_288_DATA 0x00150000
-#define DDRSS_PI_289_DATA 0x362B24C4
+#define DDRSS_PI_289_DATA 0x36EB2DD4
 #define DDRSS_PI_290_DATA 0x00150F27
-#define DDRSS_PI_291_DATA 0x362B24C4
+#define DDRSS_PI_291_DATA 0x36EB2DD4
 #define DDRSS_PI_292_DATA 0x00150F27
-#define DDRSS_PI_293_DATA 0x002B0084
+#define DDRSS_PI_293_DATA 0x00EB0084
 #define DDRSS_PI_294_DATA 0x00150000
-#define DDRSS_PI_295_DATA 0x362B24C4
+#define DDRSS_PI_295_DATA 0x36EB2DD4
 #define DDRSS_PI_296_DATA 0x00150F27
-#define DDRSS_PI_297_DATA 0x362B24C4
+#define DDRSS_PI_297_DATA 0x36EB2DD4
 #define DDRSS_PI_298_DATA 0x00150F27
 #define DDRSS_PI_299_DATA 0x00000000

@@ -783,7 +791,7 @@
 #define DDRSS_PHY_09_DATA 0x00000000
 #define DDRSS_PHY_10_DATA 0x00000000
 #define DDRSS_PHY_11_DATA 0x01000001
-#define DDRSS_PHY_12_DATA 0x00000100
+#define DDRSS_PHY_12_DATA 0x00000200
 #define DDRSS_PHY_13_DATA 0x000800C0
 #define DDRSS_PHY_14_DATA 0x060100CC
 #define DDRSS_PHY_15_DATA 0x00030066
@@ -802,9 +810,9 @@
 #define DDRSS_PHY_28_DATA 0x2A000000
 #define DDRSS_PHY_29_DATA 0x00000808
 #define DDRSS_PHY_30_DATA 0x0F000000
-#define DDRSS_PHY_31_DATA 0x00000F0F
-#define DDRSS_PHY_32_DATA 0x10200000
-#define DDRSS_PHY_33_DATA 0x0C002007
+#define DDRSS_PHY_31_DATA 0x00000F08
+#define DDRSS_PHY_32_DATA 0x10400000
+#define DDRSS_PHY_33_DATA 0x0C002006
 #define DDRSS_PHY_34_DATA 0x00000000
 #define DDRSS_PHY_35_DATA 0x00000000
 #define DDRSS_PHY_36_DATA 0x55555555
@@ -871,20 +879,20 @@
 #define DDRSS_PHY_97_DATA 0x00050010
 #define DDRSS_PHY_98_DATA 0x51517041
 #define DDRSS_PHY_99_DATA 0x31C06000
-#define DDRSS_PHY_100_DATA 0x07AB0340
+#define DDRSS_PHY_100_DATA 0x07AB01AB
 #define DDRSS_PHY_101_DATA 0x00C0C001
-#define DDRSS_PHY_102_DATA 0x09080001
+#define DDRSS_PHY_102_DATA 0x0B0A0101
 #define DDRSS_PHY_103_DATA 0x10001000
-#define DDRSS_PHY_104_DATA 0x0C063E42
-#define DDRSS_PHY_105_DATA 0x0F0C2701
+#define DDRSS_PHY_104_DATA 0x0C073E42
+#define DDRSS_PHY_105_DATA 0x0F0C2D01
 #define DDRSS_PHY_106_DATA 0x01000140
-#define DDRSS_PHY_107_DATA 0x04000420
+#define DDRSS_PHY_107_DATA 0x0C000420
 #define DDRSS_PHY_108_DATA 0x00000198
 #define DDRSS_PHY_109_DATA 0x0A0000D0
 #define DDRSS_PHY_110_DATA 0x00030200
 #define DDRSS_PHY_111_DATA 0x02800000
 #define DDRSS_PHY_112_DATA 0x80800000
-#define DDRSS_PHY_113_DATA 0x00092010
+#define DDRSS_PHY_113_DATA 0x000B2010
 #define DDRSS_PHY_114_DATA 0x76543210
 #define DDRSS_PHY_115_DATA 0x00000008
 #define DDRSS_PHY_116_DATA 0x02800280
@@ -901,8 +909,8 @@
 #define DDRSS_PHY_127_DATA 0x00A000A0
 #define DDRSS_PHY_128_DATA 0x00A000A0
 #define DDRSS_PHY_129_DATA 0x00A000A0
-#define DDRSS_PHY_130_DATA 0x01C400A0
-#define DDRSS_PHY_131_DATA 0x01A00003
+#define DDRSS_PHY_130_DATA 0x011900A0
+#define DDRSS_PHY_131_DATA 0x01A00004
 #define DDRSS_PHY_132_DATA 0x00000000
 #define DDRSS_PHY_133_DATA 0x00000000
 #define DDRSS_PHY_134_DATA 0x00080200
@@ -1039,7 +1047,7 @@
 #define DDRSS_PHY_265_DATA 0x00000000
 #define DDRSS_PHY_266_DATA 0x00000000
 #define DDRSS_PHY_267_DATA 0x01000001
-#define DDRSS_PHY_268_DATA 0x00000100
+#define DDRSS_PHY_268_DATA 0x00000200
 #define DDRSS_PHY_269_DATA 0x000800C0
 #define DDRSS_PHY_270_DATA 0x060100CC
 #define DDRSS_PHY_271_DATA 0x00030066
@@ -1058,9 +1066,9 @@
 #define DDRSS_PHY_284_DATA 0x2A000000
 #define DDRSS_PHY_285_DATA 0x00000808
 #define DDRSS_PHY_286_DATA 0x0F000000
-#define DDRSS_PHY_287_DATA 0x00000F0F
-#define DDRSS_PHY_288_DATA 0x10200000
-#define DDRSS_PHY_289_DATA 0x0C002007
+#define DDRSS_PHY_287_DATA 0x00000F08
+#define DDRSS_PHY_288_DATA 0x10400000
+#define DDRSS_PHY_289_DATA 0x0C002006
 #define DDRSS_PHY_290_DATA 0x00000000
 #define DDRSS_PHY_291_DATA 0x00000000
 #define DDRSS_PHY_292_DATA 0x55555555
@@ -1127,20 +1135,20 @@
 #define DDRSS_PHY_353_DATA 0x00050010
 #define DDRSS_PHY_354_DATA 0x51517041
 #define DDRSS_PHY_355_DATA 0x31C06000
-#define DDRSS_PHY_356_DATA 0x07AB0340
+#define DDRSS_PHY_356_DATA 0x07AB01AB
 #define DDRSS_PHY_357_DATA 0x00C0C001
-#define DDRSS_PHY_358_DATA 0x09080001
+#define DDRSS_PHY_358_DATA 0x0B0A0101
 #define DDRSS_PHY_359_DATA 0x10001000
-#define DDRSS_PHY_360_DATA 0x0C063E42
-#define DDRSS_PHY_361_DATA 0x0F0C2701
+#define DDRSS_PHY_360_DATA 0x0C073E42
+#define DDRSS_PHY_361_DATA 0x0F0C2D01
 #define DDRSS_PHY_362_DATA 0x01000140
-#define DDRSS_PHY_363_DATA 0x04000420
+#define DDRSS_PHY_363_DATA 0x0C000420
 #define DDRSS_PHY_364_DATA 0x00000198
 #define DDRSS_PHY_365_DATA 0x0A0000D0
 #define DDRSS_PHY_366_DATA 0x00030200
 #define DDRSS_PHY_367_DATA 0x02800000
 #define DDRSS_PHY_368_DATA 0x80800000
-#define DDRSS_PHY_369_DATA 0x00092010
+#define DDRSS_PHY_369_DATA 0x000B2010
 #define DDRSS_PHY_370_DATA 0x76543210
 #define DDRSS_PHY_371_DATA 0x00000008
 #define DDRSS_PHY_372_DATA 0x02800280
@@ -1157,8 +1165,8 @@
 #define DDRSS_PHY_383_DATA 0x00A000A0
 #define DDRSS_PHY_384_DATA 0x00A000A0
 #define DDRSS_PHY_385_DATA 0x00A000A0
-#define DDRSS_PHY_386_DATA 0x01C400A0
-#define DDRSS_PHY_387_DATA 0x01A00003
+#define DDRSS_PHY_386_DATA 0x011900A0
+#define DDRSS_PHY_387_DATA 0x01A00004
 #define DDRSS_PHY_388_DATA 0x00000000
 #define DDRSS_PHY_389_DATA 0x00000000
 #define DDRSS_PHY_390_DATA 0x00080200
@@ -1295,7 +1303,7 @@
 #define DDRSS_PHY_521_DATA 0x00000000
 #define DDRSS_PHY_522_DATA 0x00000000
 #define DDRSS_PHY_523_DATA 0x01000001
-#define DDRSS_PHY_524_DATA 0x00000100
+#define DDRSS_PHY_524_DATA 0x00000200
 #define DDRSS_PHY_525_DATA 0x000800C0
 #define DDRSS_PHY_526_DATA 0x060100CC
 #define DDRSS_PHY_527_DATA 0x00030066
@@ -1314,9 +1322,9 @@
 #define DDRSS_PHY_540_DATA 0x2A000000
 #define DDRSS_PHY_541_DATA 0x00000808
 #define DDRSS_PHY_542_DATA 0x0F000000
-#define DDRSS_PHY_543_DATA 0x00000F0F
-#define DDRSS_PHY_544_DATA 0x10200000
-#define DDRSS_PHY_545_DATA 0x0C002007
+#define DDRSS_PHY_543_DATA 0x00000F08
+#define DDRSS_PHY_544_DATA 0x10400000
+#define DDRSS_PHY_545_DATA 0x0C002006
 #define DDRSS_PHY_546_DATA 0x00000000
 #define DDRSS_PHY_547_DATA 0x00000000
 #define DDRSS_PHY_548_DATA 0x55555555
@@ -1383,20 +1391,20 @@
 #define DDRSS_PHY_609_DATA 0x00050010
 #define DDRSS_PHY_610_DATA 0x51517041
 #define DDRSS_PHY_611_DATA 0x31C06000
-#define DDRSS_PHY_612_DATA 0x07AB0340
+#define DDRSS_PHY_612_DATA 0x07AB01AB
 #define DDRSS_PHY_613_DATA 0x00C0C001
-#define DDRSS_PHY_614_DATA 0x09080001
+#define DDRSS_PHY_614_DATA 0x0B0A0101
 #define DDRSS_PHY_615_DATA 0x10001000
-#define DDRSS_PHY_616_DATA 0x0C063E42
-#define DDRSS_PHY_617_DATA 0x0F0C2701
+#define DDRSS_PHY_616_DATA 0x0C073E42
+#define DDRSS_PHY_617_DATA 0x0F0C2D01
 #define DDRSS_PHY_618_DATA 0x01000140
-#define DDRSS_PHY_619_DATA 0x04000420
+#define DDRSS_PHY_619_DATA 0x0C000420
 #define DDRSS_PHY_620_DATA 0x00000198
 #define DDRSS_PHY_621_DATA 0x0A0000D0
 #define DDRSS_PHY_622_DATA 0x00030200
 #define DDRSS_PHY_623_DATA 0x02800000
 #define DDRSS_PHY_624_DATA 0x80800000
-#define DDRSS_PHY_625_DATA 0x00092010
+#define DDRSS_PHY_625_DATA 0x000B2010
 #define DDRSS_PHY_626_DATA 0x76543210
 #define DDRSS_PHY_627_DATA 0x00000008
 #define DDRSS_PHY_628_DATA 0x02800280
@@ -1413,8 +1421,8 @@
 #define DDRSS_PHY_639_DATA 0x00A000A0
 #define DDRSS_PHY_640_DATA 0x00A000A0
 #define DDRSS_PHY_641_DATA 0x00A000A0
-#define DDRSS_PHY_642_DATA 0x01C400A0
-#define DDRSS_PHY_643_DATA 0x01A00003
+#define DDRSS_PHY_642_DATA 0x011900A0
+#define DDRSS_PHY_643_DATA 0x01A00004
 #define DDRSS_PHY_644_DATA 0x00000000
 #define DDRSS_PHY_645_DATA 0x00000000
 #define DDRSS_PHY_646_DATA 0x00080200
@@ -1551,7 +1559,7 @@
 #define DDRSS_PHY_777_DATA 0x00000000
 #define DDRSS_PHY_778_DATA 0x00000000
 #define DDRSS_PHY_779_DATA 0x01000001
-#define DDRSS_PHY_780_DATA 0x00000100
+#define DDRSS_PHY_780_DATA 0x00000200
 #define DDRSS_PHY_781_DATA 0x000800C0
 #define DDRSS_PHY_782_DATA 0x060100CC
 #define DDRSS_PHY_783_DATA 0x00030066
@@ -1570,9 +1578,9 @@
 #define DDRSS_PHY_796_DATA 0x2A000000
 #define DDRSS_PHY_797_DATA 0x00000808
 #define DDRSS_PHY_798_DATA 0x0F000000
-#define DDRSS_PHY_799_DATA 0x00000F0F
-#define DDRSS_PHY_800_DATA 0x10200000
-#define DDRSS_PHY_801_DATA 0x0C002007
+#define DDRSS_PHY_799_DATA 0x00000F08
+#define DDRSS_PHY_800_DATA 0x10400000
+#define DDRSS_PHY_801_DATA 0x0C002006
 #define DDRSS_PHY_802_DATA 0x00000000
 #define DDRSS_PHY_803_DATA 0x00000000
 #define DDRSS_PHY_804_DATA 0x55555555
@@ -1639,20 +1647,20 @@
 #define DDRSS_PHY_865_DATA 0x00050010
 #define DDRSS_PHY_866_DATA 0x51517041
 #define DDRSS_PHY_867_DATA 0x31C06000
-#define DDRSS_PHY_868_DATA 0x07AB0340
+#define DDRSS_PHY_868_DATA 0x07AB01AB
 #define DDRSS_PHY_869_DATA 0x00C0C001
-#define DDRSS_PHY_870_DATA 0x09080001
+#define DDRSS_PHY_870_DATA 0x0B0A0101
 #define DDRSS_PHY_871_DATA 0x10001000
-#define DDRSS_PHY_872_DATA 0x0C063E42
-#define DDRSS_PHY_873_DATA 0x0F0C2701
+#define DDRSS_PHY_872_DATA 0x0C073E42
+#define DDRSS_PHY_873_DATA 0x0F0C2D01
 #define DDRSS_PHY_874_DATA 0x01000140
-#define DDRSS_PHY_875_DATA 0x04000420
+#define DDRSS_PHY_875_DATA 0x0C000420
 #define DDRSS_PHY_876_DATA 0x00000198
 #define DDRSS_PHY_877_DATA 0x0A0000D0
 #define DDRSS_PHY_878_DATA 0x00030200
 #define DDRSS_PHY_879_DATA 0x02800000
 #define DDRSS_PHY_880_DATA 0x80800000
-#define DDRSS_PHY_881_DATA 0x00092010
+#define DDRSS_PHY_881_DATA 0x000B2010
 #define DDRSS_PHY_882_DATA 0x76543210
 #define DDRSS_PHY_883_DATA 0x00000008
 #define DDRSS_PHY_884_DATA 0x02800280
@@ -1669,8 +1677,8 @@
 #define DDRSS_PHY_895_DATA 0x00A000A0
 #define DDRSS_PHY_896_DATA 0x00A000A0
 #define DDRSS_PHY_897_DATA 0x00A000A0
-#define DDRSS_PHY_898_DATA 0x01C400A0
-#define DDRSS_PHY_899_DATA 0x01A00003
+#define DDRSS_PHY_898_DATA 0x011900A0
+#define DDRSS_PHY_899_DATA 0x01A00004
 #define DDRSS_PHY_900_DATA 0x00000000
 #define DDRSS_PHY_901_DATA 0x00000000
 #define DDRSS_PHY_902_DATA 0x00080200
@@ -1810,7 +1818,7 @@
 #define DDRSS_PHY_1036_DATA 0x00000080
 #define DDRSS_PHY_1037_DATA 0x00DCBA98
 #define DDRSS_PHY_1038_DATA 0x03000000
-#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1039_DATA 0x00200001
 #define DDRSS_PHY_1040_DATA 0x00000000
 #define DDRSS_PHY_1041_DATA 0x00000000
 #define DDRSS_PHY_1042_DATA 0x00000000
@@ -1826,7 +1834,7 @@
 #define DDRSS_PHY_1052_DATA 0x00000033
 #define DDRSS_PHY_1053_DATA 0x00543210
 #define DDRSS_PHY_1054_DATA 0x003F0000
-#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1055_DATA 0x000F3F3F
 #define DDRSS_PHY_1056_DATA 0x20202003
 #define DDRSS_PHY_1057_DATA 0x00202020
 #define DDRSS_PHY_1058_DATA 0x20008008
@@ -1835,7 +1843,7 @@
 #define DDRSS_PHY_1061_DATA 0x00000000
 #define DDRSS_PHY_1062_DATA 0x00000000
 #define DDRSS_PHY_1063_DATA 0x00000000
-#define DDRSS_PHY_1064_DATA 0x000205BB
+#define DDRSS_PHY_1064_DATA 0x000305CC
 #define DDRSS_PHY_1065_DATA 0x00030000
 #define DDRSS_PHY_1066_DATA 0x00000300
 #define DDRSS_PHY_1067_DATA 0x00000300
@@ -1844,8 +1852,8 @@
 #define DDRSS_PHY_1070_DATA 0x00000300
 #define DDRSS_PHY_1071_DATA 0x42080010
 #define DDRSS_PHY_1072_DATA 0x0000803E
-#define DDRSS_PHY_1073_DATA 0x00000001
-#define DDRSS_PHY_1074_DATA 0x01000102
+#define DDRSS_PHY_1073_DATA 0x00000004
+#define DDRSS_PHY_1074_DATA 0x01000002
 #define DDRSS_PHY_1075_DATA 0x00008000
 #define DDRSS_PHY_1076_DATA 0x00000000
 #define DDRSS_PHY_1077_DATA 0x00000000
@@ -2074,14 +2082,14 @@
 #define DDRSS_PHY_1300_DATA 0x00040101
 #define DDRSS_PHY_1301_DATA 0x0000010F
 #define DDRSS_PHY_1302_DATA 0x00000000
-#define DDRSS_PHY_1303_DATA 0x0000FFFF
+#define DDRSS_PHY_1303_DATA 0x00000064
 #define DDRSS_PHY_1304_DATA 0x00000000
 #define DDRSS_PHY_1305_DATA 0x01010000
 #define DDRSS_PHY_1306_DATA 0x01080402
 #define DDRSS_PHY_1307_DATA 0x01200F02
 #define DDRSS_PHY_1308_DATA 0x00194280
 #define DDRSS_PHY_1309_DATA 0x00000004
-#define DDRSS_PHY_1310_DATA 0x00052000
+#define DDRSS_PHY_1310_DATA 0x00042000
 #define DDRSS_PHY_1311_DATA 0x00000000
 #define DDRSS_PHY_1312_DATA 0x00000000
 #define DDRSS_PHY_1313_DATA 0x00000000
@@ -2165,10 +2173,10 @@
 #define DDRSS_PHY_1391_DATA 0x00000000
 #define DDRSS_PHY_1392_DATA 0x00000000
 #define DDRSS_PHY_1393_DATA 0x0001F7C0
-#define DDRSS_PHY_1394_DATA 0x00000002
+#define DDRSS_PHY_1394_DATA 0x00000003
 #define DDRSS_PHY_1395_DATA 0x00000000
 #define DDRSS_PHY_1396_DATA 0x00001142
-#define DDRSS_PHY_1397_DATA 0x010207AB
+#define DDRSS_PHY_1397_DATA 0x040207AB
 #define DDRSS_PHY_1398_DATA 0x01000080
 #define DDRSS_PHY_1399_DATA 0x03900390
 #define DDRSS_PHY_1400_DATA 0x03900390
@@ -2177,20 +2185,23 @@
 #define DDRSS_PHY_1403_DATA 0x00000390
 #define DDRSS_PHY_1404_DATA 0x00000390
 #define DDRSS_PHY_1405_DATA 0x00000005
-#define DDRSS_PHY_1406_DATA 0x01813FBB
-#define DDRSS_PHY_1407_DATA 0x000000BB
+#define DDRSS_PHY_1406_DATA 0x01813FCC
+#define DDRSS_PHY_1407_DATA 0x000000CC
 #define DDRSS_PHY_1408_DATA 0x0C000DFF
 #define DDRSS_PHY_1409_DATA 0x30000DFF
 #define DDRSS_PHY_1410_DATA 0x3F0DFF11
 #define DDRSS_PHY_1411_DATA 0x000100F0
-#define DDRSS_PHY_1412_DATA 0x780DFFBB
+#define DDRSS_PHY_1412_DATA 0x780DFFCC
 #define DDRSS_PHY_1413_DATA 0x00007E31
 #define DDRSS_PHY_1414_DATA 0x000CBF11
-#define DDRSS_PHY_1415_DATA 0x01770010
+#define DDRSS_PHY_1415_DATA 0x01990010
 #define DDRSS_PHY_1416_DATA 0x000CBF11
-#define DDRSS_PHY_1417_DATA 0x01770010
+#define DDRSS_PHY_1417_DATA 0x01990010
 #define DDRSS_PHY_1418_DATA 0x3F0DFF11
-#define DDRSS_PHY_1419_DATA 0x017700F0
+#define DDRSS_PHY_1419_DATA 0x00EF00F0
 #define DDRSS_PHY_1420_DATA 0x3F0DFF11
 #define DDRSS_PHY_1421_DATA 0x01FF00F0
 #define DDRSS_PHY_1422_DATA 0x20040006
+
+
+
@@ -6,7 +6,7 @@
 /dts-v1/;

 #include "k3-j7200-common-proc-board.dts"
-#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
+#include "k3-j7200-ddr-evm-lp4-3200.dtsi"
 #include "k3-j721e-ddr.dtsi"
 #include "k3-j7200-common-proc-board-u-boot.dtsi"
 #include "k3-j7200-r5.dtsi"
@@ -65,10 +65,20 @@
 		syscon = <&ctl>;
 	};

+	ram@b8940000 {	/* RT-VRAM */
+		compatible = "renesas,r8a78000-rtvram";
+		reg = <0 0xb8940000 0 0xf000>;
+	};
+
 	scp@c1340000 {
 		compatible = "renesas,r8a78000-rproc";
 		reg = <0 0xc1340000 0 0x80000>;
 	};
+
+	ram@e9800000 {	/* DBSC5 */
+		compatible = "renesas,r8a78000-dbsc";
+		reg = <0 0xe9800000 0 0x1000000>;
+	};
 };

 &cpg {
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-
-#include "rk3128.dtsi"
-
-/ {
-	model = "Rockchip RK3128 Evaluation board";
-	compatible = "rockchip,rk3128-evb", "rockchip,rk3128";
-
-	chosen {
-		stdout-path = &uart2;
-	};
-
-	memory@60000000 {
-		device_type = "memory";
-		reg = <0x60000000 0x40000000>;
-	};
-
-	vcc5v0_otg: vcc5v0-otg-drv {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_otg";
-		gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&otg_vbus_drv>;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	vcc5v0_host: vcc5v0-host-drv {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_host";
-		gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&host_vbus_drv>;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-	};
-};
-
-&emmc {
-	fifo-mode;
-	status = "okay";
-};
-
-&i2c1 {
-	status = "okay";
-
-	hym8563: hym8563@51 {
-		compatible = "haoyu,hym8563";
-		reg = <0x51>;
-		#clock-cells = <0>;
-		clock-frequency = <32768>;
-		clock-output-names = "xin32k";
-	};
-};
-
-&u2phy {
-	status = "okay";
-};
-
-&u2phy_otg {
-	status = "okay";
-};
-
-&u2phy_host {
-	status = "okay";
-};
-
-&usb_host_ehci {
-	status = "okay";
-};
-
-&usb_host_ohci {
-	status = "okay";
-};
-
-&usb_otg {
-	vbus-supply = <&vcc5v0_otg>;
-	status = "okay";
-};
-
-&pinctrl {
-	usb_otg {
-		otg_vbus_drv: host-vbus-drv {
-			rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	usb_host {
-		host_vbus_drv: host-vbus-drv {
-			rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
@@ -1,780 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/clock/rk3128-cru.h>
-
-/ {
-	compatible = "rockchip,rk3128";
-	rockchip,sram = <&sram>;
-	interrupt-parent = <&gic>;
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		gpio0 = &gpio0;
-		gpio1 = &gpio1;
-		gpio2 = &gpio2;
-		gpio3 = &gpio3;
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		i2c2 = &i2c2;
-		i2c3 = &i2c3;
-		spi0 = &spi0;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		mmc0 = &emmc;
-		mmc1 = &sdmmc;
-	};
-
-	arm-pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		enable-method = "rockchip,rk3128-smp";
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x0>;
-			operating-points = <
-				/* KHz    uV */
-				 816000 1000000
-			>;
-			#cooling-cells = <2>; /* min followed by max */
-			clock-latency = <40000>;
-			clocks = <&cru ARMCLK>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x1>;
-		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x2>;
-		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x3>;
-		};
-	};
-
-	cpu_axi_bus: cpu_axi_bus {
-		compatible = "rockchip,cpu_axi_bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		qos {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			crypto {
-				reg = <0x10128080 0x20>;
-			};
-
-			core {
-				reg = <0x1012a000 0x20>;
-			};
-
-			peri {
-				reg = <0x1012c000 0x20>;
-			};
-
-			gpu {
-				reg = <0x1012d000 0x20>;
-			};
-
-			vpu {
-				reg = <0x1012e000 0x20>;
-			};
-
-			rga {
-				reg = <0x1012f000 0x20>;
-			};
-			ebc {
-				reg = <0x1012f080 0x20>;
-			};
-
-			iep {
-				reg = <0x1012f100 0x20>;
-			};
-
-			lcdc {
-				reg = <0x1012f180 0x20>;
-				rockchip,priority = <3 3>;
-			};
-
-			vip {
-				reg = <0x1012f200 0x20>;
-				rockchip,priority = <3 3>;
-			};
-		};
-
-		msch {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			msch@10128000 {
-				reg = <0x10128000 0x20>;
-				rockchip,read-latency = <0x3f>;
-			};
-		};
-	};
-
-	psci {
-		compatible      = "arm,psci";
-		method          = "smc";
-		cpu_suspend     = <0x84000001>;
-		cpu_off         = <0x84000002>;
-		cpu_on          = <0x84000003>;
-		migrate         = <0x84000005>;
-	};
-
-	amba {
-		compatible = "arm,amba-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		interrupt-parent = <&gic>;
-		ranges;
-
-		pdma: dma-controller@20078000 {
-			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x20078000 0x4000>;
-			arm,pl330-broken-no-flushp;//2
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-			#dma-cells = <1>;
-			clocks = <&cru ACLK_DMAC>;
-			clock-names = "apb_pclk";
-		};
-	};
-
-	xin24m: xin24m {
-		compatible = "fixed-clock";
-		clock-frequency = <24000000>;
-		clock-output-names = "xin24m";
-		#clock-cells = <0>;
-	};
-
-	xin12m: xin12m {
-		compatible = "fixed-clock";
-		clock-frequency = <12000000>;
-		clock-output-names = "xin12m";
-		#clock-cells = <0>;
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		arm,cpu-registers-not-fw-configured;
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		clock-frequency = <24000000>;
-	};
-
-	timer@20044000 {
-		compatible = "arm,armv7-timer";
-		reg = <0x20044000 0xb8>;
-		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,broadcast = <1>;
-	};
-
-	watchdog: watchdog@2004c000 {
-		compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
-		reg = <0x2004c000 0x100>;
-		clocks = <&cru PCLK_WDT>;
-		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,irq = <1>;
-		rockchip,timeout = <60>;
-		rockchip,atboot = <1>;
-		rockchip,debug = <0>;
-	};
-
-	reset: reset@20000110 {
-		compatible = "rockchip,reset";
-		reg = <0x20000110 0x24>;
-		#reset-cells = <1>;
-	};
-
-	nandc: nand-controller@10500000 {
-		compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
-		reg = <0x10500000 0x4000>;
-		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
-		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
-		clock-names = "ahb", "nfc";
-	};
-
-	cru: clock-controller@20000000 {
-		compatible = "rockchip,rk3128-cru";
-		reg = <0x20000000 0x1000>;
-		clocks = <&xin24m>;
-		clock-names = "xin24m";
-		rockchip,grf = <&grf>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-		assigned-clocks = <&cru PLL_GPLL>;
-		assigned-clock-rates = <594000000>;
-	};
-
-	uart0: serial@20060000 {
-		compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
-		reg = <0x20060000 0x100>;
-		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
-		clock-names = "baudclk", "apb_pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
-		dmas = <&pdma 2>, <&pdma 3>;
-		#dma-cells = <2>;
-	};
-
-	uart1: serial@20064000 {
-		compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
-		reg = <0x20064000 0x100>;
-		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
-		clock-names = "baudclk", "apb_pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart1_xfer>;
-		dmas = <&pdma 4>, <&pdma 5>;
-		#dma-cells = <2>;
-	};
-
-	uart2: serial@20068000 {
-		compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
-		reg = <0x20068000 0x100>;
-		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
-		clock-names = "baudclk", "apb_pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart2_xfer>;
-		dmas = <&pdma 6>, <&pdma 7>;
-		#dma-cells = <2>;
-	};
-
-	saradc: saradc@2006c000 {
-		compatible = "rockchip,saradc";
-		reg = <0x2006c000 0x100>;
-		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-		#io-channel-cells = <1>;
-		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
-		clock-names = "saradc", "apb_pclk";
-		resets = <&cru SRST_SARADC>;
-		reset-names = "saradc-apb";
-		status = "disabled";
-	};
-
-	pwm0: pwm@20050000 {
-		compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
-		reg = <0x20050000 0x10>;
-		#pwm-cells = <3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm0_pin>;
-		clocks = <&cru PCLK_PWM>;
-	};
-
-	pwm1: pwm@20050010 {
-		compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
-		reg = <0x20050010 0x10>;
-		#pwm-cells = <3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm1_pin>;
-		clocks = <&cru PCLK_PWM>;
-	};
-
-	pwm2: pwm@20050020 {
-		compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
-		reg = <0x20050020 0x10>;
-		#pwm-cells = <3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm2_pin>;
-		clocks = <&cru PCLK_PWM>;
-	};
-
-	pwm3: pwm@20050030 {
-		compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
-		reg = <0x20050030 0x10>;
-		#pwm-cells = <3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm3_pin>;
-		clocks = <&cru PCLK_PWM>;
-	};
-
-	sram: sram@10080400 {
-		compatible = "rockchip,rk3128-smp-sram", "mmio-sram";
-		reg = <0x10080400 0x1C00>;
-		map-exec;
-		map-cacheable;
-	};
-
-	pmu: syscon@100a0000 {
-		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
-		reg = <0x100a0000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-
-	gic: interrupt-controller@10139000 {
-		compatible = "arm,gic-400";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
-		reg = <0x10139000 0x1000>,
-		      <0x1013a000 0x1000>,
-		      <0x1013c000 0x2000>,
-		      <0x1013e000 0x2000>;
-		interrupts = <GIC_PPI 9 0xf04>;
-	};
-
-	u2phy: usb2phy {
-		compatible = "rockchip,rk3128-usb2phy";
-		reg = <0x017c 0x0c>;
-		rockchip,grf = <&grf>;
-		clocks = <&cru SCLK_OTGPHY0>;
-		clock-names = "phyclk";
-		#clock-cells = <0>;
-		clock-output-names = "usb480m_phy";
-		status = "disabled";
-
-		u2phy_otg: otg-port {
-			#phy-cells = <0>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "otg-bvalid", "otg-id",
-					  "linestate";
-			status = "disabled";
-		};
-
-		u2phy_host: host-port {
-			#phy-cells = <0>;
-			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "linestate";
-			status = "disabled";
-		};
-	};
-
-	usb_otg: usb@10180000 {
-		compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
-		reg = <0x10180000 0x40000>;
-		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_OTG>;
-		clock-names = "otg";
-		dr_mode = "otg";
-		phys = <&u2phy_otg>;
-		phy-names = "usb2-phy";
-		status = "disabled";
-	};
-
-	usb_host_ehci: usb@101c0000 {
-		compatible = "generic-ehci";
-		reg = <0x101c0000 0x20000>;
-		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-		phys = <&u2phy_host>;
-		phy-names = "usb";
-		status = "disabled";
-	};
-
-	usb_host_ohci: usb@101e0000 {
-		compatible = "generic-ohci";
-		reg = <0x101e0000 0x20000>;
-		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-		phys = <&u2phy_host>;
-		phy-names = "usb";
-		status = "disabled";
-	};
-
-	sdmmc: mmc@10214000 {
-		compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0x10214000 0x4000>;
-		max-frequency = <150000000>;
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
-			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		fifo-depth = <0x100>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
-		bus-width = <4>;
-		status = "disabled";
-	};
-
-	emmc: mmc@1021c000 {
-		compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0x1021c000 0x4000>;
-		max-frequency = <150000000>;
-		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
-			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		bus-width = <8>;
-		default-sample-phase = <158>;
-		num-slots = <1>;
-		fifo-depth = <0x100>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-		resets = <&cru SRST_EMMC>;
-		reset-names = "reset";
-		status = "disabled";
-	};
-
-	i2c0: i2c@20072000 {
-		compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
-		reg = <20072000 0x1000>;
-		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "i2c";
-		clocks = <&cru PCLK_I2C0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c0_xfer>;
-	};
-
-	i2c1: i2c@20056000 {
-		compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
-		reg = <0x20056000 0x1000>;
-		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "i2c";
-		clocks = <&cru PCLK_I2C1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c1_xfer>;
-	};
-
-	i2c2: i2c@2005a000 {
-		compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
-		reg = <0x2005a000 0x1000>;
-		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "i2c";
-		clocks = <&cru PCLK_I2C2>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c2_xfer>;
-	};
-
-	i2c3: i2c@2005e000 {
-		compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
-		reg = <0x2005e000 0x1000>;
-		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "i2c";
-		clocks = <&cru PCLK_I2C3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c3_xfer>;
-	};
-
-	spi0: spi@20074000 {
-		compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
-		reg = <0x20074000 0x1000>;
-		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
-		rockchip,spi-src-clk = <0>;
-		num-cs = <2>;
-		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
-		clock-names = "spiclk", "apb_pclk";
-		dmas = <&pdma 8>, <&pdma 9>;
-		#dma-cells = <2>;
-		dma-names = "tx", "rx";
-	};
-
-	grf: syscon@20008000 {
-		compatible = "rockchip,rk3128-grf", "syscon";
-		reg = <0x20008000 0x1000>;
-	};
-
-	pinctrl: pinctrl@20008000 {
-		compatible = "rockchip,rk3128-pinctrl";
-		reg = <0x20008000 0xA8>,
-		      <0x200080A8 0x4C>,
-		      <0x20008118 0x20>,
-		      <0x20008100 0x04>;
-		reg-names = "base", "mux", "pull", "drv";
-		rockchip,grf = <&grf>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		gpio0: gpio@2007c000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x2007c000 0x100>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO0>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio1: gpio@20080000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x20080000 0x100>;
-			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO1>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio2: gpio@20084000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x20084000 0x100>;
-			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO2>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio3: gpio@20088000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x20088000 0x100>;
-			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		pcfg_pull_up: pcfg-pull-up {
-			bias-pull-up;
-		};
-
-		pcfg_pull_down: pcfg-pull-down {
-			bias-pull-down;
-		};
-
-		pcfg_pull_none: pcfg-pull-none {
-			bias-disable;
-		};
-
-		emmc {
-			/*
-			 * We run eMMC at max speed; bump up drive strength.
-			 * We also have external pulls, so disable the internal ones.
-			 */
-
-			emmc_clk: emmc-clk {
-				rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
-			};
-
-			emmc_cmd: emmc-cmd {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-
-			emmc_pwren: emmc-pwren {
-				rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>;
-			};
-
-			emmc_bus8: emmc-bus8 {
-				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
-						<1 RK_PD1 2 &pcfg_pull_none>,
-						<1 RK_PD2 2 &pcfg_pull_none>,
-						<1 RK_PD3 2 &pcfg_pull_none>,
-						<1 RK_PD4 2 &pcfg_pull_none>,
-						<1 RK_PD5 2 &pcfg_pull_none>,
-						<1 RK_PD6 2 &pcfg_pull_none>,
-						<1 RK_PD7 2 &pcfg_pull_none>;
-			};
-		};
-
-		nandc{
-			nandc_ale:nandc-ale {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_cle:nandc-cle {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_wrn:nandc-wrn {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_rdn:nandc-rdn {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_rdy:nandc-rdy {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_cs0:nandc-cs0 {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			nandc_data: nandc-data {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart0 {
-			uart0_xfer: uart0-xfer {
-				rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>,
-						<0 RK_PC1 1 &pcfg_pull_none>;
-			};
-
-			uart0_cts: uart0-cts {
-				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
-			};
-
-			uart0_rts: uart0-rts {
-				rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart1 {
-			uart1_xfer: uart1-xfer {
-				rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>,
-						<2 RK_PC7 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart2 {
-			uart2_xfer: uart2-xfer {
-				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>,
-						<1 RK_PC3 2 &pcfg_pull_none>;
-			};
-		};
-
-		sdmmc {
-			sdmmc_clk: sdmmc-clk {
-				rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
-			};
-
-			sdmmc_cmd: sdmmc-cmd {
-				rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;
-			};
-
-			sdmmc_wp: sdmmc-wp {
-				rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;
-			};
-
-			sdmmc_pwren: sdmmc-pwren {
-				rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;
-			};
-
-			sdmmc_bus4: sdmmc-bus4 {
-				rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,
-						<1 RK_PC3 1 &pcfg_pull_up>,
-						<1 RK_PC4 1 &pcfg_pull_up>,
-						<1 RK_PC5 1 &pcfg_pull_up>;
-			};
-		};
-
-		pwm0 {
-			pwm0_pin: pwm0-pin {
-				rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
-			};
-		};
-
-		pwm1 {
-			pwm1_pin: pwm1-pin {
-				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
-			};
-		};
-
-		pwm2 {
-			pwm2_pin: pwm2-pin {
-				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
-			};
-		};
-
-		pwm3 {
-			pwm3_pin: pwm3-pin {
-				rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c0 {
-			i2c0_xfer: i2c0-xfer {
-				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
-						<0 RK_PA1 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c1 {
-			i2c1_xfer: i2c1-xfer {
-				rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
-						<0 RK_PA3 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c2 {
-			i2c2_xfer: i2c2-xfer {
-				rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
-						<2 RK_PC5 3 &pcfg_pull_none>;
-			};
-		};
-
-		i2c3 {
-			i2c3_xfer: i2c3-xfer {
-				rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
-						<0 RK_PA7 1 &pcfg_pull_none>;
-			};
-		};
-
-		spi0 {
-			spi0_txd_mux0:spi0-txd-mux0 {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-
-			spi0_rxd_mux0:spi0-rxd-mux0 {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-
-			spi0_clk_mux0:spi0-clk-mux0 {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-
-			spi0_cs0_mux0:spi0-cs0-mux0 {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-
-			spi0_cs1_mux0:spi0-cs1-mux0 {
-				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
-			};
-		};
-
-	};
-};
@@ -1,256 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include "rk3229.dtsi"
-
-/ {
-	model = "Rockchip RK3229 Evaluation board";
-	compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
-
-	aliases {
-		mmc0 = &emmc;
-	};
-
-	memory@60000000 {
-		device_type = "memory";
-		reg = <0x60000000 0x40000000>;
-	};
-
-	dc_12v: dc-12v-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "dc_12v";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-	};
-
-	ext_gmac: ext_gmac {
-		compatible = "fixed-clock";
-		clock-frequency = <125000000>;
-		clock-output-names = "ext_gmac";
-		#clock-cells = <0>;
-	};
-
-	vcc_host: vcc-host-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&host_vbus_drv>;
-		regulator-name = "vcc_host";
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vcc_sys>;
-	};
-
-	vcc_phy: vcc-phy-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		regulator-name = "vcc_phy";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vccio_1v8>;
-	};
-
-	vcc_sys: vcc-sys-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&dc_12v>;
-	};
-
-	vccio_1v8: vccio-1v8-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vccio_1v8";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-		vin-supply = <&vcc_sys>;
-	};
-
-	vccio_3v3: vccio-3v3-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vccio_3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-		vin-supply = <&vcc_sys>;
-	};
-
-	vdd_arm: vdd-arm-regulator {
-		compatible = "pwm-regulator";
-		pwms = <&pwm1 0 25000 1>;
-		pwm-supply = <&vcc_sys>;
-		regulator-name = "vdd_arm";
-		regulator-min-microvolt = <950000>;
-		regulator-max-microvolt = <1400000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vdd_log: vdd-log-regulator {
-		compatible = "pwm-regulator";
-		pwms = <&pwm2 0 25000 1>;
-		pwm-supply = <&vcc_sys>;
-		regulator-name = "vdd_log";
-		regulator-min-microvolt = <1000000>;
-		regulator-max-microvolt = <1300000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		autorepeat;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwr_key>;
-
-		power_key: power-key {
-			label = "GPIO Key Power";
-			gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_POWER>;
-			debounce-interval = <100>;
-			wakeup-source;
-		};
-	};
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
-	cap-mmc-highspeed;
-	non-removable;
-	status = "okay";
-};
-
-&gmac {
-	assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
-	assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
-	clock_in_out = "input";
-	phy-supply = <&vcc_phy>;
-	phy-mode = "rgmii";
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>;
-	snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	snps,reset-delays-us = <0 10000 1000000>;
-	tx_delay = <0x30>;
-	rx_delay = <0x10>;
-	status = "okay";
-};
-
-&io_domains {
-	status = "okay";
-
-	vccio1-supply = <&vccio_3v3>;
-	vccio2-supply = <&vccio_1v8>;
-	vccio4-supply = <&vccio_3v3>;
-};
-
-&pinctrl {
-	keys {
-		pwr_key: pwr-key {
-			rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	usb {
-		host_vbus_drv: host-vbus-drv {
-			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pwm1 {
-	status = "okay";
-};
-
-&pwm2 {
-	status = "okay";
-};
-
-&tsadc {
-	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&u2phy0 {
-	status = "okay";
-
-	u2phy0_otg: otg-port {
-		status = "okay";
-	};
-
-	u2phy0_host: host-port {
-		phy-supply = <&vcc_host>;
-		status = "okay";
-	};
-};
-
-&u2phy1 {
-	status = "okay";
-
-	u2phy1_otg: otg-port {
-		phy-supply = <&vcc_host>;
-		status = "okay";
-	};
-
-	u2phy1_host: host-port {
-		phy-supply = <&vcc_host>;
-		status = "okay";
-	};
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
-};
-
-&usb_host1_ohci {
-	status = "okay";
-};
-
-&usb_host2_ehci {
-	status = "okay";
-};
-
-&usb_host2_ohci {
-	status = "okay";
-};
-
-&usb_otg {
-	status = "okay";
-};
@@ -1,52 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include "rk322x.dtsi"
-
-/ {
-	compatible = "rockchip,rk3229";
-
-	/delete-node/ opp-table0;
-
-	cpu0_opp_table: opp-table-0 {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp-408000000 {
-			opp-hz = /bits/ 64 <408000000>;
-			opp-microvolt = <950000>;
-			clock-latency-ns = <40000>;
-			opp-suspend;
-		};
-		opp-600000000 {
-			opp-hz = /bits/ 64 <600000000>;
-			opp-microvolt = <975000>;
-		};
-		opp-816000000 {
-			opp-hz = /bits/ 64 <816000000>;
-			opp-microvolt = <1000000>;
-		};
-		opp-1008000000 {
-			opp-hz = /bits/ 64 <1008000000>;
-			opp-microvolt = <1175000>;
-		};
-		opp-1200000000 {
-			opp-hz = /bits/ 64 <1200000000>;
-			opp-microvolt = <1275000>;
-		};
-		opp-1296000000 {
-			opp-hz = /bits/ 64 <1296000000>;
-			opp-microvolt = <1325000>;
-		};
-		opp-1392000000 {
-			opp-hz = /bits/ 64 <1392000000>;
-			opp-microvolt = <1375000>;
-		};
-		opp-1464000000 {
-			opp-hz = /bits/ 64 <1464000000>;
-			opp-microvolt = <1400000>;
-		};
-	};
-};
@@ -12,7 +12,7 @@
 	};

 	chosen {
-		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci, &ufshc;
 	};

 	dmc {
@@ -81,6 +81,17 @@
 	bootph-some-ram;
 };

+#ifdef CONFIG_SPL_UFS_SUPPORT
+&gpio4 {
+	/* This is specifically for GPIO4_D0, which is the only 1.2V capable
+	 * pin on RK3576 available for use as the UFS device reset, thus
+	 * &gpio4 is required for booting from UFS on RK3576.
+	 */
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+#endif
+
 &ioc_grf {
 	bootph-all;
 };
@@ -89,6 +100,11 @@
 	bootph-some-ram;
 };

+&pcfg_pull_down {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
 &pcfg_pull_none {
 	bootph-all;
 };
@@ -172,6 +188,21 @@
 	bootph-pre-ram;
 };

+&ufshc {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&ufs_refclk {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&ufs_rstgpio {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
 &xin24m {
 	bootph-all;
 };
@@ -19,33 +19,6 @@
 	bootph-some-ram;
 };

-&i2c4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c4m1_xfer>;
-	status = "okay";
-
-	usbc0: usb-typec@22 {
-		compatible = "fcs,fusb302";
-		reg = <0x22>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		status = "okay";
-
-		usb_con: connector {
-			compatible = "usb-c-connector";
-			label = "USB-C";
-			data-role = "dual";
-			power-role = "sink";
-			try-power-role = "sink";
-			op-sink-microwatt = <1000000>;
-			sink-pdos =
-				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>,
-				<PDO_VAR(5000, 20000, 5000)>;
-		};
-	};
-};
-
 &saradc {
 	bootph-pre-ram;
 	vdd-microvolts = <1800000>;
@@ -63,20 +36,6 @@
 	};
 };

-&u2phy0 {
-	status = "okay";
-};
-
-&u2phy0_otg {
-	status = "okay";
-};
-
-&usbdp_phy0 {
-	status = "okay";
-};
-
-&usb_host0_xhci {
-	dr_mode = "peripheral";
-	maximum-speed = "high-speed";
+&usbc0 {
 	status = "okay";
 };
@@ -51,6 +51,7 @@ enum {
 	BROM_BOOTSOURCE_SPINOR = 3,
 	BROM_BOOTSOURCE_SPINAND = 4,
 	BROM_BOOTSOURCE_SD = 5,
+	BROM_BOOTSOURCE_UFS = 7,
 	BROM_BOOTSOURCE_I2C = 8,
 	BROM_BOOTSOURCE_SPI = 9,
 	BROM_BOOTSOURCE_USB = 10,
@@ -222,6 +222,20 @@ enum {
 	REF_CLK0_OUT_PLL_DIV_SHIFT	= 0,
 	REF_CLK0_OUT_PLL_DIV_MASK	= 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT,

+	/* CRU_CLK_SEL36_CON */
+	CLK_REFCLKO25M_GMAC0_DIV_SHIFT	= 0,
+	CLK_REFCLKO25M_GMAC0_DIV_MASK	= 0x7f << CLK_REFCLKO25M_GMAC0_DIV_SHIFT,
+	CLK_REFCLKO25M_GMAC0_SEL_SHIFT	= 7,
+	CLK_REFCLKO25M_GMAC0_SEL_MASK	= 1 << CLK_REFCLKO25M_GMAC0_SEL_SHIFT,
+	CLK_REFCLKO25M_GMAC0_SEL_GPLL	= 0,
+	CLK_REFCLKO25M_GMAC0_SEL_CPLL	= 1,
+	CLK_REFCLKO25M_GMAC1_DIV_SHIFT	= 8,
+	CLK_REFCLKO25M_GMAC1_DIV_MASK	= 0x7f << CLK_REFCLKO25M_GMAC1_DIV_SHIFT,
+	CLK_REFCLKO25M_GMAC1_SEL_SHIFT	= 15,
+	CLK_REFCLKO25M_GMAC1_SEL_MASK	= 1 << CLK_REFCLKO25M_GMAC1_SEL_SHIFT,
+	CLK_REFCLKO25M_GMAC1_SEL_GPLL	= 0,
+	CLK_REFCLKO25M_GMAC1_SEL_CPLL	= 1,
+
 	/* CRU_CLK_SEL55_CON */
 	ACLK_BUS_ROOT_SEL_SHIFT		= 9,
 	ACLK_BUS_ROOT_SEL_MASK		= 1 << ACLK_BUS_ROOT_SEL_SHIFT,
@@ -11,12 +11,14 @@ config R8A779A0
 config R8A779F0
 	bool "Renesas SoC R8A779F0"
 	select GICV3
+	select GICV3_SUPPORT_GIC600
 	imply CLK_R8A779F0
 	imply PINCTRL_PFC_R8A779F0

 config R8A779G0
 	bool "Renesas SoC R8A779G0"
 	select GICV3
+	select GICV3_SUPPORT_GIC600
 	select BINMAN
 	select SUPPORT_SPL
 	imply SPL
@@ -33,6 +35,7 @@ config R8A779G0
 config R8A779H0
 	bool "Renesas SoC R8A779H0"
 	select GICV3
+	select GICV3_SUPPORT_GIC600
 	imply CLK_R8A779H0
 	imply PINCTRL_PFC_R8A779H0

@@ -2,6 +2,7 @@ if RCAR_GEN5

 config RCAR_64_RSIP
 	bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)"
+	select LMB_ARCH_MEM_MAP
 	select SKIP_RELOCATE_CODE
 	select TMU_TIMER
 	help
@@ -50,6 +50,8 @@ quiet_cmd_srec_cat = SRECCAT $@
 quiet_cmd_srec_shdr_cat = SRECCAT $@
      cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \
 			-Output_Block_Size 16 \
+			-DISable Data_Count \
+			-Execution_Start_Address 0x18400000 \
 			-generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \
 			-generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \
 			-generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \
@@ -65,6 +65,7 @@ config ROCKCHIP_RK3066
 config ROCKCHIP_RK3128
 	bool "Support Rockchip RK3128"
 	select CPU_V7A
+	imply OF_UPSTREAM
 	imply ROCKCHIP_COMMON_BOARD
 	help
 	  The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
@@ -108,6 +109,7 @@ config ROCKCHIP_RK322X
 	select TPL_OF_LIBFDT
 	select TPL_HAVE_INIT_STACK if TPL
 	select SPL_DRIVERS_MISC
+	imply OF_UPSTREAM
 	imply ROCKCHIP_COMMON_BOARD
 	imply SPL_SERIAL
 	imply SPL_ROCKCHIP_COMMON_BOARD
@@ -10,6 +10,12 @@ S:	Maintained
 F:	arch/arm/dts/rk3576-nanopi-m5*
 F:	configs/nanopi-m5-rk3576_defconfig

+NANOPI-R76S-RK3576
+M:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	arch/arm/dts/rk3576-nanopi-r76s*
+F:	configs/nanopi-r76s-rk3576_defconfig
+
 OMNI3576-RK3576
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
@@ -49,6 +49,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
 	[BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0",
 	[BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0",
 	[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
+	[BROM_BOOTSOURCE_UFS] = "/soc/ufshc@2a2d0000",
 };

 static struct mm_region rk3576_mem_map[] = {
@@ -76,6 +76,9 @@ static int spl_node_to_boot_device(int node)
 	if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
 		return BOOT_DEVICE_SPI;

+	if (!uclass_find_device_by_of_offset(UCLASS_UFS, node, &parent))
+		return BOOT_DEVICE_UFS;
+
 	return -1;
 }

@@ -231,6 +234,17 @@ int spl_decode_boot_device(u32 boot_device, char *buf, size_t buflen)
 		return -ENODEV;
 	}

+	if (boot_device == BOOT_DEVICE_UFS) {
+		ret = uclass_find_device(UCLASS_UFS, 0, &dev);
+		if (ret) {
+			debug("%s: could not find device for UFS: %d\n",
+			      __func__, ret);
+			return ret;
+		}
+
+		return ofnode_get_path(dev_ofnode(dev), buf, buflen);
+	}
+
 #if CONFIG_IS_ENABLED(BLK)
 	dev_num = (boot_device == BOOT_DEVICE_MMC1) ? 0 : 1;

@@ -5,9 +5,5 @@ F:	board/edgeble/neural-compute-module-6
 F:	include/configs/neural-compute-module-6.h
 F:	configs/neu6a-io-rk3588_defconfig
 F:	configs/neu6b-io-rk3588_defconfig
-F:	arch/arm/dts/rk3588-edgeble-neu6a.dtsi
-F:	arch/arm/dts/rk3588-edgeble-neu6a-io.dts
-F:	arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi
-F:	arch/arm/dts/rk3588-edgeble-neu6b.dtsi
-F:	arch/arm/dts/rk3588-edgeble-neu6b-io.dts
-F:	arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi
+F:	arch/arm/dts/rk3588-edgeble-neu6a-io*
+F:	arch/arm/dts/rk3588-edgeble-neu6b-io*
@@ -4,5 +4,4 @@ S:	Maintained
 F:	board/hardkernel/odroid_m1/
 F:	include/configs/odroid_m1.h
 F:	configs/odroid-m1-rk3568_defconfig
-F:	arch/arm/dts/rk3568-odroid-m1.dts
-F:	arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi
+F:	arch/arm/dts/rk3568-odroid-m1*
@@ -7,8 +7,8 @@
 # Add 4096 bytes of zeroes to u-boot.bin
 quiet_cmd_mkalign_eds = EDSALGN $@
 cmd_mkalign_eds =							\
-	dd if=$^ of=$@ bs=4k seek=1 2>/dev/null &&			\
-	mv $@ $^
+	dd if=$< of=$@ bs=4k seek=1 2>/dev/null &&			\
+	mv $@ $<

 INPUTS-y += u-boot-align.bin
 u-boot-align.bin: u-boot.bin FORCE
@@ -3,4 +3,4 @@ M:	Jacobe Zang <jacobe.zang@wesion.com>
 S:	Maintained
 F:	configs/khadas-edge2-rk3588s_defconfig
 F:	include/configs/khadas-edge2-rk3588s.h
-F:	dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts
+F:	arch/arm/dts/rk3588s-khadas-edge2*
@@ -9,26 +9,11 @@ F:	configs/quartz64-b-rk3566_defconfig
 F:	configs/soquartz-blade-rk3566_defconfig
 F:	configs/soquartz-cm4-rk3566_defconfig
 F:	configs/soquartz-model-a-rk3566_defconfig
-F:	arch/arm/dts/rk3566-quartz64-a.dts
-F:	arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
-F:	arch/arm/dts/rk3566-quartz64-b.dts
-F:	arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
-F:	arch/arm/dts/rk3566-soquartz.dtsi
-F:	arch/arm/dts/rk3566-soquartz-u-boot.dtsi
-F:	arch/arm/dts/rk3566-soquartz-blade.dts
-F:	arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
-F:	arch/arm/dts/rk3566-soquartz-cm4.dts
-F:	arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi
-F:	arch/arm/dts/rk3566-soquartz-model-a.dts
-F:	arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
+F:	arch/arm/dts/rk3566-quartz64*
+F:	arch/arm/dts/rk3566-soquartz*

 PINETAB2-RK3566
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/pinetab2-rk3566_defconfig
-F:	arch/arm/dts/rk3566-pinetab2.dtsi
-F:	arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
-F:	arch/arm/dts/rk3566-pinetab2-v0.1.dts
-F:	arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi
-F:	arch/arm/dts/rk3566-pinetab2-v2.0.dts
-F:	arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi
+F:	arch/arm/dts/rk3566-pinetab2*
@@ -4,5 +4,4 @@ S:	Maintained
 F:	board/pine64/quartzpro64-rk3588
 F:	include/configs/quartzpro64-rk3588.h
 F:	configs/quartzpro64-rk3588_defconfig
-F:	arch/arm/dts/rk3588-quartzpro64.dts
-F:	arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
+F:	arch/arm/dts/rk3588-quartzpro64*
@@ -4,4 +4,4 @@ CONFIG_TEXT_BASE=0x0
 # CONFIG_REMAKE_ELF is not set
 CONFIG_POSITION_INDEPENDENT=y
 CONFIG_INIT_SP_RELATIVE=y
-CONFIG_SYS_INIT_SP_BSS_OFFSET=524288
+CONFIG_SYS_INIT_SP_BSS_OFFSET=0x80000
@@ -39,7 +39,7 @@ bootmenu_5=Reset device=reset
 bootmenu_6=Dump clocks=clk dump; pause
 bootmenu_7=Dump environment=printenv; pause
 bootmenu_8=Board info=bdinfo; pause
-bootmenu_9=Dump bootargs=fdt print /chosen bootargs; pause
+bootmenu_9=Dump bootargs=fdt addr $fdt_addr_r; fdt print /chosen bootargs; pause
 bootmenu_10=Power off=poweroff

 # Allow holding the volume down button while U-Boot loads to enter
@@ -5,5 +5,4 @@ S:	Maintained
 F:	board/radxa/rock5a-rk3588s
 F:	include/configs/rock5a-rk3588s.h
 F:	configs/rock5a-rk3588s_defconfig
-F:	arch/arm/dts/rk3588s-rock-5a.dts
-F:	arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi
+F:	arch/arm/dts/rk3588s-rock-5a*
@@ -18,6 +18,12 @@
 #include <mapmem.h>
 #include <spl.h>

+#define APMU_BASE			0xe6170000U
+#define CL0GRP3_BIT			BIT(3)
+#define CL1GRP3_BIT			BIT(7)
+#define RTGRP3_BIT			BIT(19)
+#define APMU_ACC_ENB_FOR_ARM_CPU	(CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
+
 #define CNTCR_EN	BIT(0)

 #ifdef CONFIG_SPL_BUILD
@@ -47,6 +53,18 @@ void board_init_f(ulong dummy)
 	struct udevice *dev;
 	int ret;

+	/* Unlock CPG access */
+	writel(0x5A5AFFFF, CPGWPR);
+	writel(0xA5A50000, CPGWPCR);
+	init_generic_timer();
+
+	/* Define for Work Around of APMU */
+	writel(0x00ff00ff, APMU_BASE + 0x10);
+	writel(0x00ff00ff, APMU_BASE + 0x14);
+	writel(0x00ff00ff, APMU_BASE + 0x18);
+	writel(0x00ff00ff, APMU_BASE + 0x1c);
+	clrbits_le32(APMU_BASE + 0x68, BIT(29));
+
 	if (CONFIG_IS_ENABLED(OF_CONTROL)) {
 		ret = spl_early_init();
 		if (ret) {
@@ -76,29 +94,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
 	return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0);
 }

-#define APMU_BASE 0xe6170000U
-#define CL0GRP3_BIT			BIT(3)
-#define CL1GRP3_BIT			BIT(7)
-#define RTGRP3_BIT			BIT(19)
-#define APMU_ACC_ENB_FOR_ARM_CPU	(CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
-
-int mach_cpu_init(void)
-{
-	/* Unlock CPG access */
-	writel(0x5A5AFFFF, CPGWPR);
-	writel(0xA5A50000, CPGWPCR);
-	init_generic_timer();
-
-	/* Define for Work Around of APMU */
-	writel(0x00ff00ff, APMU_BASE + 0x10);
-	writel(0x00ff00ff, APMU_BASE + 0x14);
-	writel(0x00ff00ff, APMU_BASE + 0x18);
-	writel(0x00ff00ff, APMU_BASE + 0x1c);
-	clrbits_le32(APMU_BASE + 0x68, BIT(29));
-
-	return 0;
-}
-
 void reset_cpu(void)
 {
 }
@@ -904,6 +904,24 @@ static void mfis_unprotect(void)
 	writel(MFIS_CODEVALUE, MFIS_WPCNTR);
 }

+/**
+ * rsip_write_reg() - Write RSIP control register
+ * @reg: Register to write
+ * @val: Value to set in the register
+ */
+static void rsip_write_reg(const u32 reg, const int val)
+{
+	for (;;) {
+		writel(RSIP_CTL_PROT0PCMD_WREN, RSIP_CTL_PROT0PCMD);
+		writel(val, reg);
+		writel(~val, reg);
+		writel(val, reg);
+
+		if (readl(RSIP_CTL_PROT0PS) != RSIP_CTL_PROT0PS_ERR)
+			break;
+	}
+}
+
 /**
 * rsip_irq_setup() - Configure RSIP interrupts
 */
@@ -1353,6 +1371,26 @@ int mach_cpu_init(void)
 	return 0;
 }

+int board_early_init_r(void)
+{
+	u32 remaptmp = readl(RSIP_CTL_ESICREMAP0);
+	struct udevice *dev;
+	int ret;
+
+	/* Remap DDR PHY during DRAM init. */
+	rsip_write_reg(RSIP_CTL_ESICREMAP0, 0xe0000000);
+
+	/* Start DBSC5 */
+	ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e9800000", &dev);
+	if (ret)
+		printf("DBSC5 init failed: %d\n", ret);
+
+	/* Restore remapping. */
+	rsip_write_reg(RSIP_CTL_ESICREMAP0, remaptmp);
+
+	return 0;
+}
+
 /**
 * board_debug_uart_init() - Initialize all HSCIF
 */
@@ -1407,3 +1445,14 @@ void __weak reset_cpu(void)
 	writel(RST_KCPROT_DIS, RST_RESKCPROT0);
 	writel(0x1, RST_SWSRES1A);
 }
+
+/**
+ * lmb_arch_add_memory() - Add memory to LMB
+ *
+ * Add the window to a subset of 32bit DRAM are into LMB,
+ * to make it possible to TFTP into it.
+ */
+void lmb_arch_add_memory(void)
+{
+	lmb_add(0x60000000, 0x40000000);
+}
@@ -5,7 +5,7 @@

 #include <asm/io.h>
 #include <compiler.h>
-#include <dbsc5.h>
+#include <r8a779g0-dbsc5.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <spl.h>
@@ -1,7 +1,6 @@
 EVB-RK3229
 M:      Kever Yang <kever.yang@rock-chips.com>
 S:      Maintained
-F:	arch/arm/dts/rk3229-evb.dts
 F:	arch/arm/dts/rk3229-evb-u-boot.dtsi
 F:      board/rockchip/evb_rk3229
 F:      include/configs/evb_rk3229.h
@@ -4,8 +4,7 @@ S:      Maintained
 F:      board/rockchip/evb_rk3328
 F:      include/configs/evb_rk3328.h
 F:      configs/evb-rk3328_defconfig
-F:      arch/arm/dts/rk3328-evb.dts
-F:      arch/arm/dts/rk3328-evb-u-boot.dtsi
+F:      arch/arm/dts/rk3328-evb*

 GENERIC-RK3328
 M:	Jonas Karlman <jonas@kwiboo.se>
@@ -17,14 +16,12 @@ NANOPI-R2C-RK3328
 M:      Tianling Shen <cnsztl@gmail.com>
 S:      Maintained
 F:      configs/nanopi-r2c-rk3328_defconfig
-F:      arch/arm/dts/rk3328-nanopi-r2c.dts
 F:      arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi

 NANOPI-R2C-PLUS-RK3328
 M:      Tianling Shen <cnsztl@gmail.com>
 S:      Maintained
 F:      configs/nanopi-r2c-plus-rk3328_defconfig
-F:      arch/arm/dts/rk3328-nanopi-r2c-plus.dts
 F:      arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi

 NANOPI-R2S-RK3328
@@ -32,7 +29,6 @@ M:      David Bauer <mail@david-bauer.net>
 S:      Maintained
 F:      configs/nanopi-r2s-rk3328_defconfig
 F:      arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
-F:      arch/arm/dts/rk3328-nanopi-r2s.dts

 NANOPI-R2S-PLUS-RK3328
 M:      Jonas Karlman <jonas@kwiboo.se>
@@ -44,14 +40,12 @@ ORANGEPI-R1-PLUS-RK3328
 M:      Tianling Shen <cnsztl@gmail.com>
 S:      Maintained
 F:      configs/orangepi-r1-plus-rk3328_defconfig
-F:      arch/arm/dts/rk3328-orangepi-r1-plus.dts
 F:      arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi

 ORANGEPI-R1-PLUS-LTS-RK3328
 M:      Tianling Shen <cnsztl@gmail.com>
 S:      Maintained
 F:      configs/orangepi-r1-plus-lts-rk3328_defconfig
-F:      arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
 F:      arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi

 ROC-RK3328-CC
@@ -60,16 +54,14 @@ M:      Chen-Yu Tsai <wens@csie.org>
 R:      Jonas Karlman <jonas@kwiboo.se>
 S:      Maintained
 F:      configs/roc-cc-rk3328_defconfig
-F:      arch/arm/dts/rk3328-roc-cc.dts
-F:      arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+F:      arch/arm/dts/rk3328-roc-cc*

 ROCK64-RK3328
 M:      Matwey V. Kornilov <matwey.kornilov@gmail.com>
 R:      Jonas Karlman <jonas@kwiboo.se>
 S:      Maintained
 F:      configs/rock64-rk3328_defconfig
-F:      arch/arm/dts/rk3328-rock64.dts
-F:      arch/arm/dts/rk3328-rock64-u-boot.dtsi
+F:      arch/arm/dts/rk3328-rock64*

 ROCKPIE-RK3328
 M:      Banglang Huang <banglang.huang@foxmail.com>
@@ -24,9 +24,7 @@ KHADAS-EDGE
 M:	Nick Xie <nick@khadas.com>
 S:	Maintained
 F:	configs/khadas-edge-rk3399_defconfig
-F:	arch/arm/dts/rk3399-khadas-edge.dts
-F:	arch/arm/dts/rk3399-khadas-edge.dtsi
-F:	arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
+F:	arch/arm/dts/rk3399-khadas-edge*

 KHADAS-EDGE-CAPTAIN
 M:	Nick Xie <nick@khadas.com>
@@ -56,8 +54,7 @@ NANOPI-M4
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	configs/nanopi-m4-rk3399_defconfig
-F:	arch/arm/dts/rk3399-nanopi-m4.dts
-F:	arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
+F:	arch/arm/dts/rk3399-nanopi-m4*

 NANOPI-M4-2GB
 M:	Jagan Teki <jagan@amarulasolutions.com>
@@ -2,8 +2,7 @@ BANANAPI-BPI-R2-PRO
 M:	Frank Wunderlich <frank-w@public-files.de>
 S:	Maintained
 F:	configs/bpi-r2-pro-rk3568_defconfig
-F:	arch/arm/dts/rk3568-bpi-r2-pro.dts
-F:	arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
+F:	arch/arm/dts/rk3568-bpi-r2-pro*

 EVB-RK3568
 M:	Joseph Chen <chenjh@rock-chips.com>
@@ -11,78 +10,67 @@ S:	Maintained
 F:	board/rockchip/evb_rk3568
 F:	include/configs/evb_rk3568.h
 F:	configs/evb-rk3568_defconfig
-F:	arch/arm/dts/rk3568-evb-u-boot.dtsi
-F:	arch/arm/dts/rk3568-evb.dts
+F:	arch/arm/dts/rk3568-evb*

 FASTRHINO-R66S-RK3568
 M:	Tianling Shen <cnsztl@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/fastrhino-r66s-rk3568_defconfig
-F:	arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
+F:	arch/arm/dts/rk3568-fastrhino-r66s*

 GENERIC-RK3568
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/generic-rk3568_defconfig
-F:	arch/arm/dts/rk3568-generic.dts
-F:	arch/arm/dts/rk3568-generic-u-boot.dtsi
+F:	arch/arm/dts/rk3568-generic*

 LUBANCAT-2
 M:	Andy Yan <andyshrk@163.com>
 S:	Maintained
 F:	configs/lubancat-2-rk3568_defconfig
-F:	arch/arm/dts/rk3568-lubancat-2.dts
-F:	arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
+F:	arch/arm/dts/rk3568-lubancat-2*

 NANOPI-R3S
 M:	Tianling Shen <cnsztl@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/nanopi-r3s-rk3566_defconfig
-F:	arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
+F:	arch/arm/dts/rk3566-nanopi-r3s*

 NANOPI-R5C
 M:	Tianling Shen <cnsztl@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/nanopi-r5c-rk3568_defconfig
-F:	arch/arm/dts/rk3568-nanopi-r5c.dts
-F:	arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
+F:	arch/arm/dts/rk3568-nanopi-r5c*

 NANOPI-R5S
 M:	Tianling Shen <cnsztl@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/nanopi-r5s-rk3568_defconfig
-F:	arch/arm/dts/rk3568-nanopi-r5s.dts
-F:	arch/arm/dts/rk3568-nanopi-r5s.dtsi
-F:	arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
+F:	arch/arm/dts/rk3568-nanopi-r5s*

 RADXA-CM3-IO
 M:	Jagan Teki <jagan@amarulasolutions.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/radxa-cm3-io-rk3566_defconfig
-F:	arch/arm/dts/rk3566-radxa-cm3.dtsi
-F:	arch/arm/dts/rk3566-radxa-cm3-io.dts
-F:	arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+F:	arch/arm/dts/rk3566-radxa-cm3-io*

 RADXA-E25
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/radxa-e25-rk3568_defconfig
-F:	arch/arm/dts/rk3568-radxa-cm3i.dtsi
-F:	arch/arm/dts/rk3568-radxa-e25.dts
-F:	arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
+F:	arch/arm/dts/rk3568-radxa-e25*

 ROCK-3A
 M:	Akash Gajjar <gajjar04akash@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/rock-3a-rk3568_defconfig
-F:	arch/arm/dts/rk3568-rock-3a.dts
-F:	arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+F:	arch/arm/dts/rk3568-rock-3a*

 ROCK-3B
 M:	Jonas Karlman <jonas@kwiboo.se>
@@ -94,11 +82,11 @@ ROCK-3C
 M:	Jonas Karlman <jonas@kwiboo.se>
 M:	Maxim Moskalets <maximmosk4@gmail.com>
 S:	Maintained
-F:	arch/arm/dts/rk3566-rock-3c-u-boot.dtsi
+F:	arch/arm/dts/rk3566-rock-3c*
 F:	configs/rock-3c-rk3566_defconfig

 LCKFB-TaishanPi
 M:	Jiehui He <jiehui.he@foxmail.com>
 S:	Maintained
 F:	configs/lckfb-tspi-rk3566_defconfig
-F:	arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi
+F:	arch/arm/dts/rk3566-lckfb-tspi*
@@ -2,16 +2,13 @@ COOLPI-4B-RK3588S
 M:	Andy Yan <andyshrk@163.com>
 S:	Maintained
 F:	configs/coolpi-4b-rk3588s_defconfig
-F:	arch/arm/dts/rk3588s-coolpi-4b.dts
-F:	arch/arm/dts/rk3588s-coolpi-u-boot.dtsi
+F:	arch/arm/dts/rk3588s-coolpi-4b*

 COOLPI-CM5-EVB-RK3588
 M:	Andy Yan <andyshrk@163.com>
 S:	Maintained
 F:	configs/coolpi-cm5-evb-rk3588_defconfig
-F:	arch/arm/dts/rk3588-coolpi-cm5.dtsi
-F:	arch/arm/dts/rk3588-coolpi-cm5-evb.dts
-F:	arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
+F:	arch/arm/dts/rk3588-coolpi-cm5-evb*

 EVB-RK3588
 M:	Kever Yang <kever.yang@rock-chips.com>
@@ -19,15 +16,13 @@ S:	Maintained
 F:	board/rockchip/evb_rk3588
 F:	include/configs/evb_rk3588.h
 F:	configs/evb-rk3588_defconfig
-F:	arch/arm/dts/rk3588-evb1-v10.dts
-F:	arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
+F:	arch/arm/dts/rk3588-evb1-v10*

 GENERIC-RK3588
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/generic-rk3588_defconfig
-F:	arch/arm/dts/rk3588-generic.dts
-F:	arch/arm/dts/rk3588-generic-u-boot.dtsi
+F:	arch/arm/dts/rk3588-generic*

 MNT-REFORM2-RK3588
 M:	Peter Robinson <pbrobinson@gmail.com>
@@ -38,24 +33,22 @@ ORANGEPI-5-RK3588
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/orangepi-5-rk3588s_defconfig
-F:	arch/arm/dts/rk3588s-orangepi-5.dts
 F:	arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi

 ORANGEPI-5-MAX-RK3588
 M:	Ilya Katsnelson <me@0upti.me>
 S:	Maintained
 F:	configs/orangepi-5-max-rk3588_defconfig
-F:	arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi
+F:	arch/arm/dts/rk3588-orangepi-5-max*

 ORANGEPI-5-PLUS-RK3588
 M:	Jonas Karlman <jonas@kwiboo.se>
 S:	Maintained
 F:	configs/orangepi-5-plus-rk3588_defconfig
-F:	arch/arm/dts/rk3588-orangepi-5-plus.dts
-F:	arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi
+F:	arch/arm/dts/rk3588-orangepi-5-plus*

 ORANGEPI-5-RK3588-ULTRA
 M:	Niu Zhihong <zhihong@nzhnb.com>
 S:	Maintained
 F:	configs/orangepi-5-ultra-rk3588_defconfig
-F:	arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi
+F:	arch/arm/dts/rk3588-orangepi-5-ultra*
@@ -4,5 +4,4 @@ S:	Maintained
 F:	board/rockchip/toybrick_rk3588
 F:	include/configs/toybrick_rk3588.h
 F:	configs/toybrick-rk3588_defconfig
-F:	arch/arm/dts/rk3588-toybrick-x0.dts
-F:	arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi
+F:	arch/arm/dts/rk3588-toybrick-x0*
@@ -4,6 +4,4 @@ S:	Maintained
 F:	board/turing/turing-rk1-rk3588
 F:	include/configs/turing-rk1-rk3588.h
 F:	configs/turing-rk1-rk3588_defconfig
-F:	arch/arm/dts/rk3588-turing-rk1.dts
-F:	arch/arm/dts/rk3588-turing-rk1.dtsi
-F:	arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi
+F:	arch/arm/dts/rk3588-turing-rk1*
@@ -3,4 +3,4 @@ M:	Niu Zhihong <zhihong@nzhnb.com>
 S:	Maintained
 F:	board/xunlong/orangepi-5-rk3588-ultra
 F:	configs/orangepi-5-ultra-rk3588_defconfig
-F:	arch/arm/dts/rk3588-orangepi-5-ultra.dts
+F:	arch/arm/dts/rk3588-orangepi-5-ultra*
@@ -289,11 +289,14 @@ int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info,
 	slot = -1;
 	for (i = 0; i < abc->nb_slot; ++i) {
 		if (abc->slot_info[i].verity_corrupted ||
-		    !abc->slot_info[i].tries_remaining) {
+		    (!abc->slot_info[i].tries_remaining &&
+		     !abc->slot_info[i].successful_boot)) {
 			log_debug("ANDROID: unbootable slot %d tries: %d, ",
 				  i, abc->slot_info[i].tries_remaining);
-			log_debug("corrupt: %d\n",
+			log_debug("corrupt: %d, ",
 				  abc->slot_info[i].verity_corrupted);
+			log_debug("successful: %d\n",
+				  abc->slot_info[i].successful_boot);
 			continue;
 		}
 		log_debug("ANDROID: bootable slot %d pri: %d, tries: %d, ",
@@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_OFFSET=0x0
-CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3128-evb"
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3128=y
 CONFIG_SYS_BOOTM_LEN=0x4000000
@@ -18,7 +18,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000
 # CONFIG_DEBUG_UART_BOARD_INIT is not set
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rk3128-evb.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3128-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_GPT=y
@@ -9,7 +9,7 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x61100000
 CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3229-evb"
 CONFIG_ROCKCHIP_RK322X=y
 CONFIG_TARGET_EVB_RK3229=y
 CONFIG_SPL_STACK_R_ADDR=0x60600000
@@ -24,7 +24,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_USE_PREBOOT=y
-CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3229-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x100000
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
 CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-nanopi-m5"
@@ -19,8 +20,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-nanopi-m5.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_UFS_SUPPORT=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MEMINFO_MAP=y
 CONFIG_CMD_ADC=y
@@ -30,6 +33,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MISC=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_ROCKUSB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
@@ -63,6 +67,7 @@ CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
+CONFIG_SCSI=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
@@ -75,4 +80,6 @@ CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_UFS=y
+CONFIG_UFS_ROCKCHIP=y
 CONFIG_ERRNO_STR=y
@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-nanopi-r76s"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-nanopi-r76s.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
@@ -108,6 +108,9 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
 CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DA8XX_GPIO=y
 CONFIG_DM_I2C=y
@@ -169,7 +172,6 @@ CONFIG_SPL_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
-CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_SPL_DFU=y
 # CONFIG_WATCHDOG is not set
 # CONFIG_WATCHDOG_AUTOSTART is not set
@@ -22,3 +22,5 @@ CONFIG_REMAKE_ELF=y
 CONFIG_TEXT_BASE=0x9fc00000

 CONFIG_FASTBOOT_BUF_ADDR=0xa1600000
+
+CONFIG_WATCHDOG_AUTOSTART=y
@@ -14,3 +14,5 @@ CONFIG_ENV_IS_IN_SCSI=y
 CONFIG_ENV_SCSI_PART_UUID="71cb9cd0-acf1-b6cb-ad91-be9572fe11a9"
 # CONFIG_ENV_IS_DEFAULT is not set
 # CONFIG_ENV_IS_NOWHERE is not set
+
+CONFIG_WATCHDOG_AUTOSTART=y
@@ -17,9 +17,14 @@ CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET=0xa0000000

 CONFIG_ARCH_CPU_INIT=y
 CONFIG_BAUDRATE=1843200
-CONFIG_BOOTCOMMAND=""
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_BOOTCOMMAND="run rsip_ipl_boot_ca0"
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_CMD_IMI=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x80000000
+CONFIG_CMD_PSTORE_RECORD_SIZE=0x400
+CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x8000
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_DM_DMA=y
@@ -37,6 +42,7 @@ CONFIG_PHY_R8A78000_MP_PHY=y
 CONFIG_PHY_TI_DP83869=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_RAM=y
+CONFIG_RAM_RENESAS_DBSC5=y
 CONFIG_REMOTEPROC_RENESAS_RSIP=y
 CONFIG_RENESAS_ETHER_SWITCH=y
 CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
 CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-rock-4d"
@@ -19,8 +20,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-rock-4d.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_UFS_SUPPORT=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_MEMINFO_MAP=y
 CONFIG_CMD_ADC=y
@@ -30,6 +33,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MISC=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_RNG=y
@@ -56,6 +60,7 @@ CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_RK8XX=y
+CONFIG_SCSI=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
@@ -65,4 +70,6 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
+CONFIG_UFS=y
+CONFIG_UFS_ROCKCHIP=y
 CONFIG_ERRNO_STR=y
@@ -44,6 +44,7 @@ CONFIG_LOG=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 # CONFIG_BOARD_INIT is not set
+CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x30000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
@@ -45,6 +45,7 @@ CONFIG_LOG=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 # CONFIG_BOARD_INIT is not set
 CONFIG_BOARD_LATE_INIT=y
+CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x30000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
@@ -212,6 +212,11 @@ or initiate a reboot::

 and once the client comes back, the board should reset.

+It's possible to interrupt the fastboot command using Ctrl-c::
+
+   => fastboot usb 0
+   Operation aborted.
+
 You can also specify a kernel image to boot. You have to either specify
 the an image in Android format *or* pass a binary kernel and let the
 fastboot client wrap the Android suite around it. On OMAP for instance you
@@ -120,6 +120,12 @@ Renesas is a SoC solutions provider for automotive and industrial applications.
     - arm64
     - rcar3_ulcb_defconfig

+   * -
+     - Geist
+     - R8A779MD (M3Le)
+     - arm64
+     - r8a779md_geist_defconfig
+
   * -
     - Eagle
     - R8A77970 (V3M)
@@ -186,6 +192,24 @@ Renesas is a SoC solutions provider for automotive and industrial applications.
     - arm64
     - r8a779g3_sparrowhawk_defconfig

+   * -
+     - Gray Hawk
+     - R8A779H0 (V4M)
+     - arm64
+     - r8a779h0_grayhawk_defconfig
+
+   * - R-Car Gen5
+     - Ironhide (Cortex-A720AE application core)
+     - R8A78000 (X5H)
+     - arm64
+     - r8a78000_ironhide_defconfig
+
+   * -
+     - Ironhide (Cortex-M33 RSIP boot core)
+     - R8A78000 (X5H)
+     - arm64
+     - r8a78000_ironhide_cm33_defconfig
+
   * - RZ/G2 Family
     - Beacon EmbeddedWorks RZ/G2M SoM
     - R8A774A1 (RZ/G2M)
@@ -231,13 +255,13 @@ Renesas is a SoC solutions provider for automotive and industrial applications.
   * - :doc:`RZ/N1 Family <rzn1>`
     - Schneider RZ/N1D board
     - R9A06G032 (RZ/N1D)
-     - arm64
+     - arm
     - rzn1_snarc_defconfig

   * -
     - Schneider RZ/N1S board
     - R9A06G033 (RZ/N1S)
-     - arm64
+     - arm
     - rzn1_snarc_defconfig

 Build
@@ -143,6 +143,7 @@ List of mainline supported Rockchip boards:
     - ArmSoM Sige5 (sige5-rk3576)
     - Firefly ROC-RK3576-PC (roc-pc-rk3576)
     - FriendlyElec NanoPi M5 (nanopi-m5-rk3576)
+     - FriendlyElec NanoPi R76S (nanopi-r76s-rk3576)
     - Generic RK3576 (generic-rk3576)
     - Luckfox Omni3576 (omni3576-rk3576)
     - Radxa ROCK 4D (rock-4d-rk3576)
@@ -651,6 +651,17 @@ Refer (:ref:`U-boot ARMV8 build <k3_rst_include_start_build_steps_uboot>`)
   This will need to be explicitly disabled by changing the boot_targets to
   disallow fallback during testing.

+DDR Configuration
+-----------------
+
+The K3 DDRSS driver (drivers/ram/k3-ddrss/k3-ddrss.c) configures the DDR during
+the R5 SPL stage. The driver utilizes an auto-generated configuration file
+containing necessary settings for the DDR. It configures the frequency, timing
+parameters, training algorithms etc. for DDR initialization. The configuration
+DTSI can be generated using the `Sysconfig tool <https://dev.ti.com/sysconfig>`_
+and selecting the software product as "DDR Configuration for \*" as well as the
+required device.
+
 Saving environment
 ------------------

@@ -79,7 +79,7 @@ For the next scheduled release, release candidates were made on:

 * U-Boot |next_ver|-rc4 was released on Mon 08 June 2026.

-.. * U-Boot |next_ver|-rc5 was released on Mon 22 June 2026.
+* U-Boot |next_ver|-rc5 was released on Mon 22 June 2026.

 Please note that the following dates are planned only and may be deviated from
 as needed.
@@ -23,4 +23,4 @@ sphinxcontrib-jquery==4.1
 sphinxcontrib-jsmath==1.0.1
 sphinxcontrib-qthelp==2.0.0
 sphinxcontrib-serializinghtml==2.0.0
-urllib3==2.6.3
+urllib3==2.7.0
@@ -1335,6 +1335,7 @@ static ulong rk3528_clk_get_rate(struct clk *clk)
 					     DPLL);
 		break;

+	case CLK_REF_USB3OTG:
 	case TCLK_EMMC:
 	case TCLK_WDT_NS:
 		rate = OSC_HZ;
@@ -1455,6 +1456,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
 		priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL],
 						      priv->cru, PPLL);
 		break;
+	case CLK_REF_USB3OTG:
 	case TCLK_EMMC:
 	case TCLK_WDT_NS:
 		return (rate == OSC_HZ) ? 0 : -EINVAL;
@@ -1549,6 +1549,24 @@ static ulong rk3576_gmac_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
 		con = readl(&cru->clksel_con[31]);
 		div = (con & CLK_GMAC1_125M_DIV_MASK) >> CLK_GMAC1_125M_DIV_SHIFT;
 		return DIV_TO_RATE(priv->cpll_hz, div);
+	case REFCLKO25M_GMAC0_OUT:
+		con = readl(&cru->clksel_con[36]);
+		div = (con & CLK_REFCLKO25M_GMAC0_DIV_MASK) >> CLK_REFCLKO25M_GMAC0_DIV_SHIFT;
+		src = (con & CLK_REFCLKO25M_GMAC0_SEL_MASK) >> CLK_REFCLKO25M_GMAC0_SEL_SHIFT;
+		if (src == CLK_REFCLKO25M_GMAC0_SEL_CPLL)
+			p_rate = priv->cpll_hz;
+		else
+			p_rate = priv->gpll_hz;
+		return DIV_TO_RATE(p_rate, div);
+	case REFCLKO25M_GMAC1_OUT:
+		con = readl(&cru->clksel_con[36]);
+		div = (con & CLK_REFCLKO25M_GMAC1_DIV_MASK) >> CLK_REFCLKO25M_GMAC1_DIV_SHIFT;
+		src = (con & CLK_REFCLKO25M_GMAC1_SEL_MASK) >> CLK_REFCLKO25M_GMAC1_SEL_SHIFT;
+		if (src == CLK_REFCLKO25M_GMAC1_SEL_CPLL)
+			p_rate = priv->cpll_hz;
+		else
+			p_rate = priv->gpll_hz;
+		return DIV_TO_RATE(p_rate, div);
 	default:
 		return -ENOENT;
 	}
@@ -1608,6 +1626,34 @@ static ulong rk3576_gmac_set_clk(struct rk3576_clk_priv *priv,
 			     CLK_GMAC1_125M_DIV_MASK,
 			     (div - 1) << CLK_GMAC1_125M_DIV_SHIFT);
 		break;
+	case REFCLKO25M_GMAC0_OUT:
+		if (!(priv->gpll_hz % rate)) {
+			src = CLK_REFCLKO25M_GMAC0_SEL_GPLL;
+			div = priv->gpll_hz / rate;
+		} else {
+			src = CLK_REFCLKO25M_GMAC0_SEL_CPLL;
+			div = priv->cpll_hz / rate;
+		}
+		rk_clrsetreg(&cru->clksel_con[36],
+			     CLK_REFCLKO25M_GMAC0_SEL_MASK |
+			     CLK_REFCLKO25M_GMAC0_DIV_MASK,
+			     src << CLK_REFCLKO25M_GMAC0_SEL_SHIFT |
+			     (div - 1) << CLK_REFCLKO25M_GMAC0_DIV_SHIFT);
+		break;
+	case REFCLKO25M_GMAC1_OUT:
+		if (!(priv->gpll_hz % rate)) {
+			src = CLK_REFCLKO25M_GMAC1_SEL_GPLL;
+			div = priv->gpll_hz / rate;
+		} else {
+			src = CLK_REFCLKO25M_GMAC1_SEL_CPLL;
+			div = priv->cpll_hz / rate;
+		}
+		rk_clrsetreg(&cru->clksel_con[36],
+			     CLK_REFCLKO25M_GMAC1_SEL_MASK |
+			     CLK_REFCLKO25M_GMAC1_DIV_MASK,
+			     src << CLK_REFCLKO25M_GMAC1_SEL_SHIFT |
+			     (div - 1) << CLK_REFCLKO25M_GMAC1_DIV_SHIFT);
+		break;
 	default:
 		return -ENOENT;
 	}
@@ -1987,6 +2033,8 @@ static ulong rk3576_clk_get_rate(struct clk *clk)
 	case HCLK_SDIO:
 		rate = rk3576_mmc_get_clk(priv, clk->id);
 		break;
+	case CLK_REF_USB3OTG0:
+	case CLK_REF_USB3OTG1:
 	case TCLK_EMMC:
 	case TCLK_WDT0:
 		rate = OSC_HZ;
@@ -2014,6 +2062,8 @@ static ulong rk3576_clk_get_rate(struct clk *clk)
 	case CLK_GMAC1_PTP_REF:
 	case CLK_GMAC0_125M_SRC:
 	case CLK_GMAC1_125M_SRC:
+	case REFCLKO25M_GMAC0_OUT:
+	case REFCLKO25M_GMAC1_OUT:
 		rate = rk3576_gmac_get_clk(priv, clk->id);
 		break;
 	case CLK_UART_FRAC_0:
@@ -2151,6 +2201,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
 	case HCLK_SDIO:
 		ret = rk3576_mmc_set_clk(priv, clk->id, rate);
 		break;
+	case CLK_REF_USB3OTG0:
+	case CLK_REF_USB3OTG1:
 	case TCLK_EMMC:
 	case TCLK_WDT0:
 		ret = OSC_HZ;
@@ -2193,6 +2245,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
 	case CLK_GMAC1_PTP_REF:
 	case CLK_GMAC0_125M_SRC:
 	case CLK_GMAC1_125M_SRC:
+	case REFCLKO25M_GMAC0_OUT:
+	case REFCLKO25M_GMAC1_OUT:
 		ret = rk3576_gmac_set_clk(priv, clk->id, rate);
 		break;
 	case CLK_UART_FRAC_0:
@@ -263,7 +263,7 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc,
 	/* Write new kernel size to boot image header */
 	hdr->kernel_size = download_bytes;
 	res = blk_dwrite(dev_desc, info.start, hdr_sectors, (void *)hdr);
-	if (res == 0) {
+	if (res != hdr_sectors) {
 		pr_err("cannot writeback boot image header\n");
 		fastboot_fail("cannot write back boot image header", response);
 		return -1;
@@ -275,7 +275,7 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc,
 				      sectors_per_page;
 	res = blk_dwrite(dev_desc, kernel_sector_start, kernel_sectors,
 			 download_buffer);
-	if (res == 0) {
+	if (res != kernel_sectors) {
 		pr_err("cannot write new kernel\n");
 		fastboot_fail("cannot write new kernel", response);
 		return -1;
@@ -287,7 +287,7 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc,
 					     sectors_per_page;
 	res = blk_dwrite(dev_desc, ramdisk_sector_start, ramdisk_sectors,
 			 ramdisk_buffer);
-	if (res == 0) {
+	if (res != ramdisk_sectors) {
 		pr_err("cannot write back original ramdisk\n");
 		fastboot_fail("cannot write back original ramdisk", response);
 		return -1;
@@ -344,7 +344,6 @@ static int qcom_gpio_probe(struct udevice *dev)
 static const struct udevice_id qcom_gpio_ids[] = {
 	{ .compatible = "qcom,pm8916-gpio" },
 	{ .compatible = "qcom,pm8994-gpio" },	/* 22 GPIO's */
-	{ .compatible = "qcom,pm8998-gpio" },
 	{ .compatible = "qcom,pms405-gpio" },
 	{ .compatible = "qcom,pm6125-gpio" },
 	{ .compatible = "qcom,pm8150-gpio" },
@@ -752,6 +752,7 @@ static const struct udevice_id qcom_spmi_pmic_gpio_ids[] = {
 	{ .compatible = "qcom,pm8550b-gpio" },
 	{ .compatible = "qcom,pm8550ve-gpio" },
 	{ .compatible = "qcom,pm8550vs-gpio" },
+	{ .compatible = "qcom,pm8998-gpio" },
 	{ .compatible = "qcom,pmk8550-gpio" },
 	{ .compatible = "qcom,pmr735d-gpio" },
 	{ }
@@ -32,6 +32,8 @@ config MPFS_MBOX
 	bool "Enable MPFS system controller support"
 	depends on DM_MAILBOX && ARCH_RV64I
 	select DEVRES
+	depends on SYSCON
+	depends on REGMAP
 	help
 	  Enable support for the mailboxes that provide a communication
 	  channel with the system controller integrated on PolarFire SoC.
@@ -13,19 +13,21 @@
 #include <dm/device-internal.h>
 #include <dm/device.h>
 #include <dm/device_compat.h>
-#include <dm/devres.h>
 #include <dm/ofnode.h>
 #include <linux/bitops.h>
 #include <linux/compat.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
+#include <linux/err.h>
+#include <linux/errno.h>
 #include <log.h>
 #include <mailbox-uclass.h>
-#include <malloc.h>
 #include <mpfs-mailbox.h>
+#include <regmap.h>
+#include <syscon.h>

 #define SERVICES_CR_OFFSET 0x50u
 #define SERVICES_SR_OFFSET 0x54u
+#define MESSAGE_INT_OFFSET 0x18cu
+#define MAILBOX_REG_OFFSET 0x800u

 #define SERVICE_CR_REQ_MASK 0x1u
 #define SERVICE_SR_BUSY_MASK 0x2u
@@ -35,17 +37,18 @@

 struct mpfs_mbox {
 	struct udevice *dev;
-	void __iomem *ctrl_base;
 	void __iomem *mbox_base;
-	struct mbox_chan *chan;
+	void __iomem *int_reg;
+	struct regmap *control_scb;
+	struct regmap *sysreg_scb;
 };

 static bool mpfs_mbox_busy(struct mbox_chan *chan)
 {
 	struct mpfs_mbox *mbox = dev_get_priv(chan->dev);
-	uint16_t status;
+	u32 status;

-	status = readl(mbox->ctrl_base + SERVICES_SR_OFFSET);
+	regmap_read(mbox->control_scb, SERVICES_SR_OFFSET, &status);

 	return status & SERVICE_SR_BUSY_MASK;
 }
@@ -80,14 +83,15 @@ static int mpfs_mbox_send(struct mbox_chan *chan, const void *data)

 	cmd_shifted = msg->cmd_opcode << SERVICE_CR_COMMAND_SHIFT;
 	cmd_shifted |= SERVICE_CR_REQ_MASK;
-	writel(cmd_shifted, mbox->ctrl_base + SERVICES_CR_OFFSET);
+
+	regmap_write(mbox->control_scb, SERVICES_CR_OFFSET, cmd_shifted);

 	do {
-		value = readl(mbox->ctrl_base + SERVICES_CR_OFFSET);
+		regmap_read(mbox->control_scb, SERVICES_CR_OFFSET, &value);
 	} while (SERVICE_CR_REQ_MASK == (value & SERVICE_CR_REQ_MASK));

 	do {
-		value = readl(mbox->ctrl_base + SERVICES_SR_OFFSET);
+		regmap_read(mbox->control_scb, SERVICES_SR_OFFSET, &value);
 	} while (SERVICE_SR_BUSY_MASK == (value & SERVICE_SR_BUSY_MASK));

 	msg->response->resp_status = (value >> SERVICE_SR_STATUS_SHIFT);
@@ -118,6 +122,11 @@ static int mpfs_mbox_recv(struct mbox_chan *chan, void *data)
 	for (idx = 0; idx < response->resp_size; idx++)
 		*((u8 *)(response->resp_msg) + idx) = readb(mbox->mbox_base + msg->resp_offset  + idx);

+	if (mbox->sysreg_scb)
+		regmap_write(mbox->sysreg_scb, MESSAGE_INT_OFFSET, 0);
+	else
+		writel_relaxed(0, mbox->int_reg);
+
 	return 0;
 }

@@ -126,42 +135,71 @@ static const struct mbox_ops mpfs_mbox_ops = {
 	.recv = mpfs_mbox_recv,
 };

-static int mpfs_mbox_probe(struct udevice *dev)
+/*
+ * Use global compatible lookup instead of phandles, as U-Boot may run
+ * with a reduced or firmware-provided device tree where mailbox syscon
+ * phandle properties are not guaranteed to be present.
+ */
+static int mpfs_mbox_syscon_probe(struct udevice *dev, struct mpfs_mbox *mbox)
 {
-	struct mpfs_mbox *mbox;
-	struct resource regs;
 	ofnode node;
-	int ret;

-	node = dev_ofnode(dev);
+	node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-control-scb");
+	if (!ofnode_valid(node))
+		return -ENODEV;

-	mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
-	if (!mbox)
-		return -ENOMEM;
+	mbox->control_scb = syscon_node_to_regmap(node);
+	if (IS_ERR(mbox->control_scb))
+		return PTR_ERR(mbox->control_scb);

-	ret = ofnode_read_resource(node, 0, &regs);
-	if (ret) {
-		dev_err(dev, "No reg property for controller base\n");
-		return ret;
-	};
+	node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-sysreg-scb");
+	if (!ofnode_valid(node))
+		return -ENODEV;

-	mbox->ctrl_base = devm_ioremap(dev, regs.start, regs.start - regs.end);
+	mbox->sysreg_scb = syscon_node_to_regmap(node);
+	if (IS_ERR(mbox->sysreg_scb))
+		return PTR_ERR(mbox->sysreg_scb);

-	ret = ofnode_read_resource(node, 2, &regs);
-	if (ret) {
-		dev_err(dev, "No reg property for mailbox base\n");
-		return ret;
-	};
-
-	mbox->mbox_base = devm_ioremap(dev, regs.start, regs.start - regs.end);
-
-	mbox->dev = dev;
-	dev_set_priv(dev, mbox);
-	mbox->chan->con_priv = mbox;
+	mbox->mbox_base = dev_read_addr_ptr(dev);
+	if (!mbox->mbox_base)
+		return -EINVAL;

 	return 0;
 }

+static int mpfs_mbox_legacy_probe(struct udevice *dev, struct mpfs_mbox *mbox)
+{
+	int ret;
+
+	ret = regmap_init_mem_index(dev_ofnode(dev), &mbox->control_scb, 0);
+	if (ret)
+		return ret;
+
+	mbox->mbox_base = dev_read_addr_index_ptr(dev, 2);
+	if (!mbox->mbox_base)
+		mbox->mbox_base = dev_read_addr_index_ptr(dev, 0) + MAILBOX_REG_OFFSET;
+
+	mbox->int_reg = dev_read_addr_index_ptr(dev, 1);
+	if (!mbox->int_reg)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int mpfs_mbox_probe(struct udevice *dev)
+{
+	struct mpfs_mbox *mbox = dev_get_priv(dev);
+	int ret;
+
+	mbox->dev = dev;
+
+	ret = mpfs_mbox_syscon_probe(dev, mbox);
+	if (!ret)
+		return 0;
+
+	return mpfs_mbox_legacy_probe(dev, mbox);
+}
+
 static const struct udevice_id mpfs_mbox_ids[] = {
 	{.compatible = "microchip,mpfs-mailbox"},
 	{ }
@@ -174,4 +212,4 @@ U_BOOT_DRIVER(mpfs_mbox) = {
 	.probe = mpfs_mbox_probe,
 	.priv_auto = sizeof(struct mpfs_mbox),
 	.ops = &mpfs_mbox_ops,
-};
+};
@@ -296,57 +296,6 @@ static int rpmh_regulator_vrm_get_value(struct udevice *rdev)
 	return vreg->uv;
 }

-static int rpmh_regulator_is_enabled(struct udevice *rdev)
-{
-	struct rpmh_vreg *vreg = dev_get_priv(rdev);
-	int ret;
-
-	debug("%s: is_enabled %d\n", rdev->name, vreg->enabled);
-
-	if (vreg->enabled < 0) {
-		struct tcs_cmd cmd = {
-			.addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE,
-		};
-		ret = rpmh_regulator_read_data(vreg, &cmd);
-		/*
-		 * Don't override if disabled since we will also vote the right voltage
-		 * while enabling
-		 */
-		if (!ret && cmd.data)
-			vreg->enabled = cmd.data & RPMH_REGULATOR_ENABLE_MASK;
-	}
-
-	return vreg->enabled > 0;
-}
-
-static int rpmh_regulator_set_enable_state(struct udevice *rdev,
-					   bool enable)
-{
-	struct rpmh_vreg *vreg = dev_get_priv(rdev);
-	struct tcs_cmd cmd = {
-		.addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE,
-		.data = enable,
-	};
-	int ret;
-
-	debug("%s: set_enable %d (current %d)\n", rdev->name, enable,
-	      vreg->enabled);
-
-	if (vreg->enabled == -EINVAL &&
-	    vreg->uv != -ENOTRECOVERABLE) {
-		ret = _rpmh_regulator_vrm_set_value(rdev,
-						    vreg->uv, true);
-		if (ret < 0)
-			return ret;
-	}
-
-	ret = rpmh_regulator_send_request(vreg, &cmd, enable);
-	if (!ret)
-		vreg->enabled = enable;
-
-	return ret;
-}
-
 static int rpmh_regulator_vrm_set_mode_bypass(struct rpmh_vreg *vreg,
 					      unsigned int mode, bool bypassed)
 {
@@ -397,6 +346,63 @@ static int rpmh_regulator_vrm_set_mode(struct udevice *rdev,
 	return ret;
 }

+static int rpmh_regulator_is_enabled(struct udevice *rdev)
+{
+	struct rpmh_vreg *vreg = dev_get_priv(rdev);
+	int ret;
+
+	debug("%s: is_enabled %d\n", rdev->name, vreg->enabled);
+
+	if (vreg->enabled < 0) {
+		struct tcs_cmd cmd = {
+			.addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE,
+		};
+		ret = rpmh_regulator_read_data(vreg, &cmd);
+		/*
+		 * Don't override if disabled since we will also vote the right voltage
+		 * while enabling
+		 */
+		if (!ret && cmd.data)
+			vreg->enabled = cmd.data & RPMH_REGULATOR_ENABLE_MASK;
+	}
+
+	return vreg->enabled > 0;
+}
+
+static int rpmh_regulator_set_enable_state(struct udevice *rdev,
+					   bool enable)
+{
+	struct rpmh_vreg *vreg = dev_get_priv(rdev);
+	struct tcs_cmd cmd = {
+		.addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE,
+		.data = enable,
+	};
+	int ret;
+
+	debug("%s: set_enable %d (current %d)\n", rdev->name, enable,
+	      vreg->enabled);
+
+	if (vreg->mode != -EINVAL) {
+		ret = rpmh_regulator_vrm_set_mode_bypass(vreg, vreg->mode, vreg->bypassed);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (vreg->enabled == -EINVAL &&
+	    vreg->uv != -ENOTRECOVERABLE) {
+		ret = _rpmh_regulator_vrm_set_value(rdev,
+						    vreg->uv, true);
+		if (ret < 0)
+			return ret;
+	}
+
+	ret = rpmh_regulator_send_request(vreg, &cmd, enable);
+	if (!ret)
+		vreg->enabled = enable;
+
+	return ret;
+}
+
 static int rpmh_regulator_vrm_get_pmic_mode(struct rpmh_vreg *vreg, int *pmic_mode)
 {
 	struct tcs_cmd cmd = {
@@ -1,7 +1,7 @@
 config RAM_RENESAS_DBSC5
-	bool "Renesas R-Car V4H/V4M DBSC5 controller driver"
-	depends on SPL && RAM && (R8A779G0 || R8A779H0)
+	bool "Renesas R-Car V4H/V4M/X5H DBSC5 controller driver"
+	depends on RAM && (R8A78000 || (SPL && (R8A779G0 || R8A779H0)))
 	default n
 	help
 	  Enable this to support the DBSC5 DRAM controller initialization
-	  on Renesas R8A779G0/R8A779H0 SoCs.
+	  on Renesas R8A779G0/R8A779H0/R8A78000 SoCs.
@@ -1,6 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0+

-ifdef CONFIG_XPL_BUILD
 obj-$(CONFIG_RAM_RENESAS_DBSC5)	+= dbsc5/
-endif
 obj-$(CONFIG_RZN1)	+= rzn1/
@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+

-obj-y	+= dbsc5.o dram.o qos.o rtvram.o
+obj-$(CONFIG_R8A779G0)	+= r8a779g0-dbsc5.o r8a779g0-dram.o qos.o
+obj-$(CONFIG_R8A78000)	+= r8a78000-dbsc5.o r8a78000-dram.o ecc.o
+obj-y	+= rtvram.o
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <ram.h>
+#include <linux/sizes.h>
+
+#define DBSC5_DBSC_CNT			8
+
+#define DBSC_D_BASE(n)			(0xe9900000 + ((n) * 0x4000))
+#define DBSC_A_BASE(n)			(0xe9800000 + ((n) * 0x8000))
+#define DBSYSCNT			0x100
+#define DBACEN				0x200
+#define DBFSINTENB02A			0x7088
+#define DBFSINTENB04A			0x7090
+#define DBFSCONFAXI0			0x7400
+#define DBFSDRAMECCAREA00		0x7450
+#define DBFSCTRL01A			0x7604
+#define DBFSCONF00A			0x7640
+#define DBFSCONF01A			0x7644
+#define DBFSCONF02A			0x7648
+#define DBFSSTAT00A			0x7680
+#define DBFSSTAT01A			0x7684
+
+#define DBSYSCNT_ENABLE			0x1234
+#define DBSYSCNT_DISABLE		0x0
+#define DBACEN_ACCESS_DISABLE		0
+#define DBACEN_ACCESS_ENABLE		1
+
+#define ECM_BASE			0xb89a0000
+#define ECMERRCTLR0			(ECM_BASE + 0x0)
+#define ECMERRINCR0			(ECM_BASE + 0x200)
+#define ECMERROMKR0			(ECM_BASE + 0x600)
+#define ECMERRCTLR6			(ECM_BASE + (0x4 * 6))
+#define ECMERRINCR6			(ECM_BASE + 0x200U + (0x4 * 6))
+#define ECMERROMKR6			(ECM_BASE + 0x600U + (0x4 * 6))
+#define ECMWPCNTR			(ECM_BASE + 0xa00)
+#define ECMWACNTR			(ECM_BASE + 0xa04)
+
+struct renesas_dbsc5_ecc_priv {
+	void __iomem		*regs;
+};
+
+static void ecm_reg_unlock(void)
+{
+	writel(0xacce0001, ECMWPCNTR);
+}
+
+static void ecm_reg_lock(void)
+{
+	writel(0xacce0000, ECMWPCNTR);
+}
+
+static void ecm_reg_write(u32 adr, u32 val)
+{
+	writel(0xacce0000 | (adr & 0xffff), ECMWACNTR);
+	writel(val, adr);
+}
+
+static int renesas_dbsc5_ecc_probe(struct udevice *dev)
+{
+	int i;
+
+	ecm_reg_unlock();
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++) {
+		writel(DBSYSCNT_ENABLE, DBSC_D_BASE(i) + DBSYSCNT);
+		writel(DBSYSCNT_ENABLE, DBSC_A_BASE(i) + DBSYSCNT);
+	}
+
+	ecm_reg_write(ECMERRINCR0, readl(ECMERRINCR0) | 0xAAA);
+	ecm_reg_write(ECMERROMKR0, readl(ECMERROMKR0) | 0xAAA);
+	ecm_reg_write(ECMERRCTLR0, readl(ECMERRCTLR0) | 0xAAA);
+	ecm_reg_write(ECMERRINCR6, readl(ECMERRINCR6) | 0xA000);
+	ecm_reg_write(ECMERROMKR6, readl(ECMERROMKR6) | 0xA000);
+	ecm_reg_write(ECMERRCTLR6, readl(ECMERRCTLR6) | 0xA000);
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++)
+		writel(0xcccc, DBSC_A_BASE(i) + DBFSDRAMECCAREA00);
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++)
+		writel(DBACEN_ACCESS_DISABLE, DBSC_A_BASE(i) + DBACEN);
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++)
+		writel(0, DBSC_A_BASE(i) + DBFSCONF00A);
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++)
+		writel(0, DBSC_A_BASE(i) + DBFSCONF01A);
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++)
+		writel(0xcccb, DBSC_A_BASE(i) + DBFSCONF02A);
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++)
+		writel(0x1, DBSC_A_BASE(i) + DBFSCTRL01A);
+
+	u32 fsstat;
+	do {
+		fsstat = 0x1;
+		for (i = 0; i < DBSC5_DBSC_CNT; i++)
+			fsstat &= readl(DBSC_A_BASE(i) + DBFSSTAT01A);
+	} while (!(fsstat & 0x1));
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++)
+		writel(DBACEN_ACCESS_ENABLE, DBSC_A_BASE(i) + DBACEN);
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++)
+		setbits_le32(DBSC_A_BASE(i) + DBFSCONFAXI0, 0x100);
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++)
+		writel(0xff00ff00, DBSC_A_BASE(i) + DBFSINTENB02A);
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++)
+		writel(0xffffffff, DBSC_A_BASE(i) + DBFSINTENB04A);
+
+	ecm_reg_lock();
+
+	for (i = 0; i < DBSC5_DBSC_CNT; i++) {
+		writel(DBSYSCNT_DISABLE, DBSC_D_BASE(i) + DBSYSCNT);
+		writel(DBSYSCNT_DISABLE, DBSC_A_BASE(i) + DBSYSCNT);
+	}
+
+	return 0;
+}
+
+static int renesas_dbsc5_ecc_of_to_plat(struct udevice *dev)
+{
+	struct renesas_dbsc5_ecc_priv *priv = dev_get_priv(dev);
+
+	priv->regs = dev_read_addr_ptr(dev);
+	if (!priv->regs)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int renesas_dbsc5_ecc_get_info(struct udevice *dev,
+				      struct ram_info *info)
+{
+	struct renesas_dbsc5_ecc_priv *priv = dev_get_priv(dev);
+
+	info->base = (phys_addr_t)priv->regs;
+	info->size = 32 * SZ_1M;
+
+	return 0;
+}
+
+static const struct ram_ops renesas_dbsc5_ecc_ops = {
+	.get_info = renesas_dbsc5_ecc_get_info,
+};
+
+static const struct udevice_id renesas_dbsc5_ecc_ids[] = {
+	{ .compatible = "renesas,r8a78000-ecc" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(renesas_dbsc5_ecc) = {
+	.name		= "dbsc5_ecc",
+	.id		= UCLASS_RAM,
+	.of_match	= renesas_dbsc5_ecc_ids,
+	.of_to_plat	= renesas_dbsc5_ecc_of_to_plat,
+	.ops		= &renesas_dbsc5_ecc_ops,
+	.probe		= renesas_dbsc5_ecc_probe,
+	.priv_auto	= sizeof(struct renesas_dbsc5_ecc_priv),
+};
@@ -9,7 +9,7 @@
 #include <hang.h>
 #include <linux/sizes.h>
 #include <ram.h>
-#include "dbsc5.h"
+#include "r8a779g0-dbsc5.h"

 /* AXMM */
 #define AXMM_ADSPLCR0				0x4008
@@ -10,7 +10,7 @@
 #include <errno.h>
 #include <linux/sizes.h>
 #include <ram.h>
-#include "dbsc5.h"
+#include "r8a779g0-dbsc5.h"

 static int renesas_dbsc5_probe(struct udevice *dev)
 {
@@ -3,8 +3,8 @@
 * Copyright (C) 2024 Renesas Electronics Corp.
 */

-#ifndef __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__
-#define __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__
+#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__
+#define __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__

 /*
 * DBSC5 ... 0xe678_0000..0xe67fffff
@@ -26,4 +26,4 @@ struct renesas_dbsc5_data {
 	const char		*otp_node;
 };

-#endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */
+#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__ */
@@ -4,14 +4,14 @@
 */

 #include <asm/io.h>
-#include <dbsc5.h>
+#include <r8a779g0-dbsc5.h>
 #include <dm.h>
 #include <errno.h>
 #include <hang.h>
 #include <ram.h>
 #include <linux/iopoll.h>
 #include <linux/sizes.h>
-#include "dbsc5.h"
+#include "r8a779g0-dbsc5.h"

 /* Number of array elements in Data Slice */
 #define DDR_PHY_SLICE_REGSET_SIZE_V4H	0x100
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ *
+ * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved.
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <errno.h>
+#include <linux/sizes.h>
+#include <ram.h>
+#include "r8a78000-dbsc5.h"
+
+static int renesas_dbsc5_probe(struct udevice *dev)
+{
+	struct udevice *ddev, *vdev, *edev;
+	int ret;
+
+	ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_dram", &ddev);
+	if (ret)
+		return ret;
+
+	ret = uclass_get_device_by_name(UCLASS_RAM, "ram@b8940000", &vdev);
+	if (ret)
+		return ret;
+
+	ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_ecc", &edev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int renesas_dbsc5_bind(struct udevice *dev)
+{
+	struct udevice *ramdev, *eccdev;
+	struct driver *ramdrv, *eccdrv;
+	int ret;
+
+	ramdrv = lists_driver_lookup_name("dbsc5_dram");
+	if (!ramdrv)
+		return -ENOENT;
+
+	eccdrv = lists_driver_lookup_name("dbsc5_ecc");
+	if (!eccdrv)
+		return -ENOENT;
+
+	ret = device_bind_with_driver_data(dev, ramdrv, "dbsc5_dram",
+					   dev_get_driver_data(dev),
+					   dev_ofnode(dev), &ramdev);
+	if (ret)
+		return ret;
+
+	ret = device_bind_with_driver_data(dev, eccdrv, "dbsc5_ecc", 0,
+					   dev_ofnode(dev), &eccdev);
+	if (ret)
+		device_unbind(ramdev);
+
+	return ret;
+}
+
+static const struct udevice_id renesas_dbsc5_ids[] = {
+	{ .compatible = "renesas,r8a78000-dbsc", },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(renesas_dbsc5) = {
+	.name		= "dbsc5",
+	.id		= UCLASS_NOP,
+	.of_match	= renesas_dbsc5_ids,
+	.bind		= renesas_dbsc5_bind,
+	.probe		= renesas_dbsc5_probe,
+};
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ *
+ * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved.
+ */
+
+#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__
+#define __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__
+
+struct renesas_dbsc5_data {
+	const char		*clock_node;
+	const char		*reset_node;
+	const char		*otp_node;
+};
+
+#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__ */
@@ -13,34 +13,41 @@
 #define RTVRAM_VBUF_CFG			0x6504
 #define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY	(1 << 8)
 #define RTVRAM_VBUF_CFG_VBUF_SIZE_28M	(6 << 0)
+#define RTVRAM_VBUF_CFG_VBUF_SIZE_32M	(7 << 0)
 #define RTVRAM_EXT_MODE			0x8500
 #define RTVRAM_EXT_MODE_EXT		BIT(0)
 #define RTVRAM_VBUF_BADDR		0xC580

-#define RTVRAM_VBUF_NUM			7
-
-#define SDRAM_40BIT_ADDR_TOP		0x0400000000ULL
 #define RTVRAM_VBUF_AREA_SIZE		SZ_4M

 struct renesas_dbsc5_rtvram_priv {
 	void __iomem		*regs;
 };

+struct renesas_dbsc5_rtvram_data {
+	u8	sdram_40bit_addr_top;	/* Left-shift by 32 */
+	u8	vbuf_num;
+	u8	size;
+	u8	size_bit;
+};
+
 static int renesas_dbsc5_rtvram_probe(struct udevice *dev)
 {
 	struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev);
+	struct renesas_dbsc5_rtvram_data *data =
+		(struct renesas_dbsc5_rtvram_data *)dev_get_driver_data(dev);
 	u64 addr;
 	int i;

 	/* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */
-	for (i = 0; i < RTVRAM_VBUF_NUM; i++) {
-		addr = (SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16;
+	for (i = 0; i < data->vbuf_num + 1; i++) {
+		addr = (((u64)(data->sdram_40bit_addr_top) << 32ULL) + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16;
 		writel(lower_32_bits(addr), priv->regs + (RTVRAM_VBUF_BADDR + (4 * i)));
 	}

 	/* Cache Mode: 8-way, VBF size: 28M */
 	setbits_le32(priv->regs + RTVRAM_VBUF_CFG,
-		     RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M);
+		     RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | data->size_bit);

 	/* Change from Compatible Mode to Extended Mode */
 	writel(RTVRAM_EXT_MODE_EXT, priv->regs + RTVRAM_EXT_MODE);
@@ -65,9 +72,11 @@ static int renesas_dbsc5_rtvram_get_info(struct udevice *dev,
 					 struct ram_info *info)
 {
 	struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev);
+	struct renesas_dbsc5_rtvram_data *data =
+		(struct renesas_dbsc5_rtvram_data *)dev_get_driver_data(dev);

 	info->base = (phys_addr_t)priv->regs;
-	info->size = 28 * SZ_1M;
+	info->size = data->size * SZ_1M;

 	return 0;
 }
@@ -76,14 +85,29 @@ static const struct ram_ops renesas_dbsc5_rtvram_ops = {
 	.get_info = renesas_dbsc5_rtvram_get_info,
 };

+struct renesas_dbsc5_rtvram_data gen4_rtvram_data = {
+	.sdram_40bit_addr_top = 0x4,
+	.vbuf_num = 7,
+	.size = 28,
+	.size_bit = RTVRAM_VBUF_CFG_VBUF_SIZE_28M,
+};
+
+struct renesas_dbsc5_rtvram_data gen5_rtvram_data = {
+	.sdram_40bit_addr_top = 0x12,
+	.vbuf_num = 8,
+	.size = 32,
+	.size_bit = RTVRAM_VBUF_CFG_VBUF_SIZE_32M,
+};
+
 static const struct udevice_id renesas_dbsc5_rtvram_ids[] = {
-	{ .compatible = "renesas,r8a779g0-rtvram" },
-	{ .compatible = "renesas,r8a779h0-rtvram" },
+	{ .compatible = "renesas,r8a779g0-rtvram", .data = (ulong)&gen4_rtvram_data },
+	{ .compatible = "renesas,r8a779h0-rtvram", .data = (ulong)&gen4_rtvram_data },
+	{ .compatible = "renesas,r8a78000-rtvram", .data = (ulong)&gen5_rtvram_data },
 	{ /* sentinel */ }
 };

 U_BOOT_DRIVER(renesas_dbsc5_rtvram) = {
-	.name		= "rtvram",
+	.name		= "dbsc5_rtvram",
 	.id		= UCLASS_RAM,
 	.of_match	= renesas_dbsc5_rtvram_ids,
 	.of_to_plat	= renesas_dbsc5_rtvram_of_to_plat,
@@ -116,6 +116,15 @@ config RESET_ROCKCHIP
 	  though is that some reset signals, like I2C or MISC reset multiple
 	  devices.

+config SPL_RESET_ROCKCHIP
+	bool "SPL reset controller driver for Rockchip SoCs"
+	depends on SPL_DM_RESET && ARCH_ROCKCHIP && SPL_CLK
+	default y
+	help
+	  Support for the reset controller on Rockchip SoCs in SPL. Select this
+	  if you observe any reset-related warnings or errors when booting SPL,
+	  such as when using UFS storage
+
 config RESET_HSDK
 	bool "Synopsys HSDK Reset Driver"
 	depends on DM_RESET && TARGET_HSDK
@@ -18,7 +18,7 @@ obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
 obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
 obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
-obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
+obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
@@ -257,7 +257,7 @@ static int sh_serial_of_to_plat(struct udevice *dev)
 	int ret;

 	addr = dev_read_addr(dev);
-	if (!addr)
+	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;

 	plat->base = addr;
@@ -1201,7 +1201,7 @@ static struct usba_ep *usba_udc_pdata(struct usba_platform_data *pdata,
 	struct usba_ep *eps;
 	int i;

-	eps = malloc(sizeof(struct usba_ep) * pdata->num_ep);
+	eps = calloc(pdata->num_ep, sizeof(struct usba_ep));
 	if (!eps) {
 		log_err("failed to alloc eps\n");
 		return NULL;
@@ -134,7 +134,7 @@ int usb_alloc_device(struct usb_device *udev)
 	struct udevice *bus = udev->controller_dev;
 	struct dm_usb_ops *ops = usb_get_ops(bus);

-	/* This is only requird by some controllers - current XHCI */
+	/* This is only required by some controllers - currently XHCI */
 	if (!ops->alloc_device)
 		return 0;

@@ -207,7 +207,7 @@ static int tcpm_pd_transmit(struct udevice *dev,
 	 */
 	timeout_us *= 5;
 	ret = read_poll_timeout(tcpm_transmit_helper, tx_complete,
-				!tx_complete, false, timeout_us, dev);
+				tx_complete, false, timeout_us, dev);
 	if (ret < 0) {
 		dev_err(dev, "TCPM: PD transmit data failed: %d\n", ret);
 		return ret;
@@ -30,10 +30,10 @@ struct udevice;
 * generally very quick to access, e.g. less than 100ms
 * @BOOTDEVP_3_INTERNAL_SLOW: Internal devices which don't need scanning but
 * take a significant fraction of a second to access
- * @BOOTDEVP_4_SCAN_FAST: Extenal devices which need scanning or bus
+ * @BOOTDEVP_4_SCAN_FAST: External devices which need scanning or bus
 * enumeration to find, but this enumeration happens quickly, typically under
 * 100ms
- * @BOOTDEVP_5_SCAN_SLOW: Extenal devices which need scanning or bus
+ * @BOOTDEVP_5_SCAN_SLOW: External devices which need scanning or bus
 * enumeration to find. The enumeration takes significant fraction of a second
 * to complete
 * @BOOTDEVP_6_NET_BASE: Basic network devices which are quickly and easily
@@ -327,7 +327,7 @@ int bootdev_hunt_and_find_by_label(const char *label, struct udevice **devp,
 * Bootdev scanners are used as needed. For example a label "mmc1" results in
 * running the "mmc" bootdrv.
 *
- * @iter: Interation info, containing iter->cur_label
+ * @iter: Iteration info, containing iter->cur_label
 * @devp: New bootdev found, if any was found
 * @method_flagsp: If non-NULL, returns any flags implied by the label
 * (enum bootflow_meth_flags_t), 0 if none
@@ -342,7 +342,7 @@ int bootdev_next_label(struct bootflow_iter *iter, struct udevice **devp,
 * This moves @devp to the next bootdev with the current priority. If there is
 * none, then it moves to the next priority and scans for new bootdevs there.
 *
- * @iter: Interation info, containing iter->cur_prio
+ * @iter: Iteration info, containing iter->cur_prio
 * @devp: On entry this is the previous bootdev that was considered. On exit
 *	this is the new bootdev, if any was found
 * Returns 0 on success (*devp is updated), -ENODEV if there are no more
@@ -26,10 +26,50 @@
 #if defined(CONFIG_RCAR_64_RSIP)
 #define CFG_SYS_TIMER_COUNTER		(TMU_BASE + 0xc)	/* TCNT0 */
 #define CFG_SYS_TIMER_RATE		(133333333 / 4)
-#endif

+/* Environment setting */
+#define CFG_EXTRA_ENV_SETTINGS						\
+	"rsip_ipl_params_base=0x8c100000\0"				\
+	"rsip_ipl_params_optee=0x8c100088\0"				\
+	"rsip_ipl_params_uboot=0x8c100030\0"				\
+	"rsip_ipl_optee_ep=0x8c400000\0"				\
+	"rsip_ipl_tfa_ep=0x8c200000\0"					\
+	"rsip_ipl_uboot_ep=0x8e300000\0"				\
+	"rsip_ipl_params_write="					\
+		"base ${rsip_ipl_params_base} ; "			\
+		"mw 0x00 0 0x9e ; "	/* Clear the area */		\
+		"mw 0x00 0x00300103 ; " /* type, version, size */	\
+		"mw 0x20 0x${rsip_ipl_params_uboot} ; " /* U-Boot descriptor */ \
+		""							\
+		"base ${rsip_ipl_params_uboot} ; "			\
+		"mw 0x00 0x00580101 ; " /* type, version, size */	\
+		"mw 0x04 0x00000001 ; " /* attr */			\
+		"mw 0x08 ${rsip_ipl_uboot_ep} ; " /* U-Boot entry point */ \
+		"mw 0x10 0x000003c5 ; " /* SPSR */			\
+		""							\
+		"base ${rsip_ipl_params_optee} ; "			\
+		"mw 0x00 0x00580201 ; " /* type, version, size */	\
+		"mw 0x04 0x00000008 ; " /* attr */			\
+		"mw 0x08 ${rsip_ipl_optee_ep} ; " /* OPTEE-OS entry point */ \
+		"mw 0x10 0x000003c5 ; " /* SPSR */			\
+		""							\
+		"base 0\0"						\
+	"rsip_ipl_boot_ca0=" /* Start TFA BL31, OPTEE-OS, U-Boot on Cortex-A720AE core 0 */ \
+		"scsi scan && " /* Scan for UFS devices */		\
+		"rproc init && " /* Start remoteproc */			\
+		"rproc load 0 0x344c0000 0x60000 && " /* Load SCP from HF */ \
+		"rproc start 0 && " /* Start SCP */			\
+		"scsi read ${rsip_ipl_uboot_ep} 0x7200 0x100 && " /* Load U-Boot from UFS */ \
+		"scsi read ${rsip_ipl_optee_ep} 0x5200 0x200 && " /* Load OPTEE-OS from UFS */ \
+		"scsi read ${rsip_ipl_tfa_ep} 0x5000 0x40 && " /* Load TFA BL31 from UFS */ \
+		"run rsip_ipl_params_write && " /* Write entry point descriptors */ \
+		"rproc load 13 ${rsip_ipl_tfa_ep} 4 && " /* Set up Cortex-A720AE Core 0 */ \
+		"rproc start 13\0"	/* Start Cortex-A720AE Core 0 */
+
+#else
 /* Environment setting */
 #define CFG_EXTRA_ENV_SETTINGS		\
 	"bootm_size=0x10000000\0"
+#endif

 #endif	/* __RCAR_GEN5_COMMON_H */
--- a/Show More
+++ b/Show More