From 969a1dde3a0913ed00afdbd49abf318ce34dc9af Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 19 May 2026 07:45:41 -0600 Subject: [PATCH 01/65] doc: Update urllib3 version for building The GitHub dependabot tool has reported two "high" priority bug, CVE-2026-44431 and CVE-2026-44432, with this package. Update to the patched version. Reported-by: GitHub dependabot Signed-off-by: Tom Rini --- doc/sphinx/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index c616c75fefc..20a99005d71 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -23,4 +23,4 @@ sphinxcontrib-jquery==4.1 sphinxcontrib-jsmath==1.0.1 sphinxcontrib-qthelp==2.0.0 sphinxcontrib-serializinghtml==2.0.0 -urllib3==2.6.3 +urllib3==2.7.0 From badf7502827bc8f77cb4c572e5186584deea7a89 Mon Sep 17 00:00:00 2001 From: Francesco Valla Date: Sun, 31 May 2026 17:24:23 +0200 Subject: [PATCH 02/65] dtoc: test: add missing escape in help text A single percent sign might be interpreted as a string format directive and shall thus be escaped - doubling it - to actually indicate a percentage. Without the escape, pytest fails to run test_fdt.py with the following error: ValueError: Test coverage failure fdt code coverage: Traceback (most recent call last): File "/usr/lib64/python3.14/argparse.py", line 1748, in _check_help formatter._expand_help(action) ~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^ File "/usr/lib64/python3.14/argparse.py", line 676, in _expand_help return help_string % params ~~~~~~~~~~~~^~~~~~~~ TypeError: %c requires an int or a unicode character, not dict The above exception was the direct cause of the following exception: Traceback (most recent call last): File "/home/user/u-boot/./tools/dtoc/test_fdt", line 1002, in sys.exit(main()) ~~~~^^ File "/home/user/u-boot/./tools/dtoc/test_fdt", line 987, in main parser.add_argument('-T', '--test-coverage', action='store_true', ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ default=False, ^^^^^^^^^^^^^^ help='run tests and check for 100% coverage') ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ File "/usr/lib64/python3.14/argparse.py", line 1562, in add_argument self._check_help(action) ~~~~~~~~~~~~~~~~^^^^^^^^ File "/usr/lib64/python3.14/argparse.py", line 1750, in _check_help raise ValueError('badly formed help string') from exc ValueError: badly formed help string Fixes: 7640b166604e ("test_fdt: Convert to use argparse") Signed-off-by: Francesco Valla --- tools/dtoc/test_fdt.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py index a0bed4e18bb..f141f931a94 100755 --- a/tools/dtoc/test_fdt.py +++ b/tools/dtoc/test_fdt.py @@ -986,7 +986,7 @@ def main(): default=False, help='run tests') parser.add_argument('-T', '--test-coverage', action='store_true', default=False, - help='run tests and check for 100% coverage') + help='run tests and check for 100%% coverage') parser.add_argument('name', nargs='*') args = parser.parse_args() From bc82aa5b4145eba47f57e6f7148e0fa45bc16f51 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 1 Jun 2026 15:20:53 +0200 Subject: [PATCH 03/65] efi_loader: validate PE-COFF relocation data When applying base relocations from a PE-COFF binary all data must be treated as untrusted. Add the following checks to efi_loader_relocate(): * Reject relocation blocks that don't start on a 32-bit aligned address. * Reject relocation blocks whose SizeOfBlock is smaller than the block header, which would cause an unsigned underflow when computing the entry count. * A block with SizeOfBlock == 0 is invalid and does not mark the end of the relocation table. * Reject relocation blocks that extend beyond the end of the relocation section. * Reject individual relocation entries whose target offset, together with the access width, exceeds the mapped image size, preventing out-of-bounds writes. Pass virt_size to efi_loader_relocate() from efi_load_pe() to enable the per-entry bounds check. Reported-by: Anas Cherni Reviewed-by: Simon Glass Reviewed-by: Ilias Apalodimas Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_image_loader.c | 86 +++++++++++++++++++++++++++---- 1 file changed, 75 insertions(+), 11 deletions(-) diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index d002eb0c744..f9a2d2df405 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -108,11 +108,13 @@ void efi_print_image_infos(void *pc) * @rel_size: size of the relocation table in bytes * @efi_reloc: actual load address of the image * @pref_address: preferred load address of the image + * @virt_size: virtual image size as provided in the PE-COFF header * Return: status code */ static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel, - unsigned long rel_size, void *efi_reloc, - unsigned long pref_address) + unsigned long rel_size, void *efi_reloc, + unsigned long pref_address, + unsigned long virt_size) { unsigned long delta = (unsigned long)efi_reloc - pref_address; const IMAGE_BASE_RELOCATION *end; @@ -122,34 +124,95 @@ static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel, return EFI_SUCCESS; end = (const IMAGE_BASE_RELOCATION *)((const char *)rel + rel_size); - while (rel + 1 < end && rel->SizeOfBlock) { + while (rel + 1 < end) { const uint16_t *relocs = (const uint16_t *)(rel + 1); + + /* Each block must start on a 32-bit boundary */ + if (!IS_ALIGNED((uintptr_t)rel, sizeof(uint32_t))) { + log_debug("Relocation block not 32-bit aligned\n"); + return EFI_LOAD_ERROR; + } + /* Relocation block cannot be shorter than its header */ + if (rel->SizeOfBlock < sizeof(*rel)) { + log_debug("Relocation block too small: %u\n", + rel->SizeOfBlock); + return EFI_LOAD_ERROR; + } + /* All relocation entries must be inside the .reloc section */ + if ((const char *)rel + rel->SizeOfBlock > (const char *)end) { + log_debug("Relocation block exceeds relocation data\n"); + return EFI_LOAD_ERROR; + } + /* + * Relocations must be within the virtual address range. + * This also ensures that there is no overflow in the + * entry_offset check below. + */ + if (rel->VirtualAddress > virt_size) { + log_debug("relocation address out of bounds\n"); + return EFI_LOAD_ERROR; + } + i = (rel->SizeOfBlock - sizeof(*rel)) / sizeof(uint16_t); while (i--) { - uint32_t offset = (uint32_t)(*relocs & 0xfff) + - rel->VirtualAddress; + uint32_t entry_offset = *relocs & 0xfff; + unsigned long offset; int type = *relocs >> EFI_PAGE_SHIFT; - uint64_t *x64 = efi_reloc + offset; - uint32_t *x32 = efi_reloc + offset; - uint16_t *x16 = efi_reloc + offset; + uint64_t *x64; + uint32_t *x32; + uint16_t *x16; + + /* + * Relocation address must be within virtual address + * range. + */ + if (entry_offset > virt_size - rel->VirtualAddress) { + log_debug("relocation address out of bounds\n"); + return EFI_LOAD_ERROR; + } + + offset = rel->VirtualAddress + entry_offset; + x64 = efi_reloc + offset; + x32 = efi_reloc + offset; + x16 = efi_reloc + offset; switch (type) { case IMAGE_REL_BASED_ABSOLUTE: break; case IMAGE_REL_BASED_HIGH: + if (sizeof(uint16_t) > virt_size - offset) { + log_debug("relocation address out of bounds\n"); + return EFI_LOAD_ERROR; + } *x16 += ((uint32_t)delta) >> 16; break; case IMAGE_REL_BASED_LOW: + if (sizeof(uint16_t) > virt_size - offset) { + log_debug("relocation address out of bounds\n"); + return EFI_LOAD_ERROR; + } *x16 += (uint16_t)delta; break; case IMAGE_REL_BASED_HIGHLOW: + if (sizeof(uint32_t) > virt_size - offset) { + log_debug("relocation address out of bounds\n"); + return EFI_LOAD_ERROR; + } *x32 += (uint32_t)delta; break; case IMAGE_REL_BASED_DIR64: + if (sizeof(uint64_t) > virt_size - offset) { + log_debug("relocation address out of bounds\n"); + return EFI_LOAD_ERROR; + } *x64 += (uint64_t)delta; break; #ifdef __riscv case IMAGE_REL_BASED_RISCV_HI20: + if (sizeof(uint32_t) > virt_size - offset) { + log_debug("relocation address out of bounds\n"); + return EFI_LOAD_ERROR; + } *x32 = ((*x32 & 0xfffff000) + (uint32_t)delta) | (*x32 & 0x00000fff); break; @@ -163,7 +226,7 @@ static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel, break; #endif default: - log_err("Unknown Relocation off %x type %x\n", + log_err("Unknown Relocation off %lx type %x\n", offset, type); return EFI_LOAD_ERROR; } @@ -970,8 +1033,9 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, /* Run through relocations */ if (efi_loader_relocate(rel, rel_size, efi_reloc, - (unsigned long)image_base) != EFI_SUCCESS) { - efi_free_pages((uintptr_t) efi_reloc, + (unsigned long)image_base, + virt_size) != EFI_SUCCESS) { + efi_free_pages((uintptr_t)efi_reloc, (virt_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT); ret = EFI_LOAD_ERROR; goto err; From 5a1818d54c8abfe8f4f72a3fa370b299b2bfe125 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 5 Nov 2025 01:07:51 +0100 Subject: [PATCH 04/65] usb: typos 'requird', 'current' %s/requird/required/ %s/current XHCI/currently XHCI/ Reviewed-by: Marek Vasut Reviewed-by: Bin Meng Signed-off-by: Heinrich Schuchardt --- drivers/usb/host/usb-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 7247245a702..1c74d6fd39a 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -134,7 +134,7 @@ int usb_alloc_device(struct usb_device *udev) struct udevice *bus = udev->controller_dev; struct dm_usb_ops *ops = usb_get_ops(bus); - /* This is only requird by some controllers - current XHCI */ + /* This is only required by some controllers - currently XHCI */ if (!ops->alloc_device) return 0; From a9c1f2af7178ef6b74053ef427ea68b489895e98 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 10 Mar 2026 01:00:39 +0000 Subject: [PATCH 05/65] clk: rockchip: rk3528: Add CLK_REF_USB3OTG support The CLK_REF_USB3OTG clock is used as reference clock for the DWC3 block. Add simple support to get rate of CLK_REF_USB3OTG clock to fix reference clock period configuration. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3528.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c index bcdc0f930d2..cf8c3a62349 100644 --- a/drivers/clk/rockchip/clk_rk3528.c +++ b/drivers/clk/rockchip/clk_rk3528.c @@ -1335,6 +1335,7 @@ static ulong rk3528_clk_get_rate(struct clk *clk) DPLL); break; + case CLK_REF_USB3OTG: case TCLK_EMMC: case TCLK_WDT_NS: rate = OSC_HZ; @@ -1455,6 +1456,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate) priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru, PPLL); break; + case CLK_REF_USB3OTG: case TCLK_EMMC: case TCLK_WDT_NS: return (rate == OSC_HZ) ? 0 : -EINVAL; From c97c7d5caadc6d2d87764162171d1a1bdc206803 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 10 Mar 2026 01:02:13 +0000 Subject: [PATCH 06/65] clk: rockchip: rk3576: Add CLK_REF_USB3OTGx support The CLK_REF_USB3OTGx clocks are used as reference clocks for the two DWC3 blocks. Add simple support to get rate of CLK_REF_USB3OTGx clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3576.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index 1026af27ca1..dd8b59356ef 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -1987,6 +1987,8 @@ static ulong rk3576_clk_get_rate(struct clk *clk) case HCLK_SDIO: rate = rk3576_mmc_get_clk(priv, clk->id); break; + case CLK_REF_USB3OTG0: + case CLK_REF_USB3OTG1: case TCLK_EMMC: case TCLK_WDT0: rate = OSC_HZ; @@ -2151,6 +2153,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate) case HCLK_SDIO: ret = rk3576_mmc_set_clk(priv, clk->id, rate); break; + case CLK_REF_USB3OTG0: + case CLK_REF_USB3OTG1: case TCLK_EMMC: case TCLK_WDT0: ret = OSC_HZ; From 3d294c01858f738e4bf52f90c111fc8e601e7819 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 9 Mar 2026 21:37:06 +0000 Subject: [PATCH 07/65] rockchip: rk3588-rock-5b: Remove USB-C controller from u-boot.dtsi The commit 12049db76437 ("rockchip: rk3588-rock-5b: Add USB-C controller to u-boot.dtsi") added the USB-C controller node to the ROCK 5B board u-boot.dtsi, this and related usb nodes are now part of upstream DT. Remove the upstream USB-C controller related DT nodes from u-boot.dtsi, including the temporary used dr_mode and maximum-speed props of the usb_host0_xhci node. Only usbc0 status = "okay" is kept ensuring USB-C power delivery continues to work as intended. Signed-off-by: Jonas Karlman Reviewed-by: Sebastian Reichel Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 43 +------------------------ 1 file changed, 1 insertion(+), 42 deletions(-) diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index e07b549c767..ddc177344eb 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -19,33 +19,6 @@ bootph-some-ram; }; -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m1_xfer>; - status = "okay"; - - usbc0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio3>; - interrupts = ; - pinctrl-names = "default"; - status = "okay"; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "sink"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - , - ; - }; - }; -}; - &saradc { bootph-pre-ram; vdd-microvolts = <1800000>; @@ -63,20 +36,6 @@ }; }; -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; +&usbc0 { status = "okay"; }; From 82a5b5f7ca494e643f9bf1454c620dd2b271fdbc Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 10 Mar 2026 00:06:05 +0000 Subject: [PATCH 08/65] board: rockchip: Add FriendlyElec NanoPi R76S The NanoPi R76S (as "R76S") is an open-sourced mini IoT gateway device with two 2.5G, designed and developed by FriendlyElec. Features tested on a NanoPi R76S 2411: - SD-card boot - eMMC boot - LEDs and button - PCIe/Ethernet - USB host Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3576/MAINTAINERS | 6 +++ configs/nanopi-r76s-rk3576_defconfig | 60 +++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 3 files changed, 67 insertions(+) create mode 100644 configs/nanopi-r76s-rk3576_defconfig diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS index 393edd3984c..79cf9e97f70 100644 --- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -10,6 +10,12 @@ S: Maintained F: arch/arm/dts/rk3576-nanopi-m5* F: configs/nanopi-m5-rk3576_defconfig +NANOPI-R76S-RK3576 +M: Jonas Karlman +S: Maintained +F: arch/arm/dts/rk3576-nanopi-r76s* +F: configs/nanopi-r76s-rk3576_defconfig + OMNI3576-RK3576 M: Jonas Karlman S: Maintained diff --git a/configs/nanopi-r76s-rk3576_defconfig b/configs/nanopi-r76s-rk3576_defconfig new file mode 100644 index 00000000000..af149dc4ba5 --- /dev/null +++ b/configs/nanopi-r76s-rk3576_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-nanopi-r76s" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-nanopi-r76s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 141071f528a..a31ee7100b9 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -143,6 +143,7 @@ List of mainline supported Rockchip boards: - ArmSoM Sige5 (sige5-rk3576) - Firefly ROC-RK3576-PC (roc-pc-rk3576) - FriendlyElec NanoPi M5 (nanopi-m5-rk3576) + - FriendlyElec NanoPi R76S (nanopi-r76s-rk3576) - Generic RK3576 (generic-rk3576) - Luckfox Omni3576 (omni3576-rk3576) - Radxa ROCK 4D (rock-4d-rk3576) From 1165c206c2fb1b755de42854109d4d6443018305 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Wed, 11 Mar 2026 17:30:58 +0400 Subject: [PATCH 09/65] reset: rockchip: make device resets available in SPL Enable the Rockchip reset controller driver in SPL to allow resetting attached devices like UFS during early boot. Reviewed-by: Jonas Karlman Signed-off-by: Alexey Charkov --- drivers/reset/Kconfig | 9 +++++++++ drivers/reset/Makefile | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 485f907b041..e7c0870c918 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -116,6 +116,15 @@ config RESET_ROCKCHIP though is that some reset signals, like I2C or MISC reset multiple devices. +config SPL_RESET_ROCKCHIP + bool "SPL reset controller driver for Rockchip SoCs" + depends on SPL_DM_RESET && ARCH_ROCKCHIP && SPL_CLK + default y + help + Support for the reset controller on Rockchip SoCs in SPL. Select this + if you observe any reset-related warnings or errors when booting SPL, + such as when using UFS storage + config RESET_HSDK bool "Synopsys HSDK Reset Driver" depends on DM_RESET && TARGET_HSDK diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index c369bdb3d6c..2c83f858895 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o -obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o +obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o From 9941ec2c5cf73a890bbb896516b383eec9c00657 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Wed, 11 Mar 2026 17:30:59 +0400 Subject: [PATCH 10/65] rockchip: spl: Add support for booting from UFS Add the required architecture-specific lookups to enable U-boot SPL to load images from UFS storage devices on Rockchip RK3576, which has a boot ROM capable of loading the SPL image from UFS. Reviewed-by: Jonas Karlman Signed-off-by: Alexey Charkov --- arch/arm/dts/rk3576-u-boot.dtsi | 33 +++++++++++++++++++- arch/arm/include/asm/arch-rockchip/bootrom.h | 1 + arch/arm/mach-rockchip/rk3576/rk3576.c | 1 + arch/arm/mach-rockchip/spl-boot-order.c | 14 +++++++++ 4 files changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index 018c9cc8d69..8db9495c6d4 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -12,7 +12,7 @@ }; chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci, &ufshc; }; dmc { @@ -81,6 +81,17 @@ bootph-some-ram; }; +#ifdef CONFIG_SPL_UFS_SUPPORT +&gpio4 { + /* This is specifically for GPIO4_D0, which is the only 1.2V capable + * pin on RK3576 available for use as the UFS device reset, thus + * &gpio4 is required for booting from UFS on RK3576. + */ + bootph-pre-ram; + bootph-some-ram; +}; +#endif + &ioc_grf { bootph-all; }; @@ -89,6 +100,11 @@ bootph-some-ram; }; +&pcfg_pull_down { + bootph-pre-ram; + bootph-some-ram; +}; + &pcfg_pull_none { bootph-all; }; @@ -172,6 +188,21 @@ bootph-pre-ram; }; +&ufshc { + bootph-pre-ram; + bootph-some-ram; +}; + +&ufs_refclk { + bootph-pre-ram; + bootph-some-ram; +}; + +&ufs_rstgpio { + bootph-pre-ram; + bootph-some-ram; +}; + &xin24m { bootph-all; }; diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index b15938c021d..f9ecb6858f0 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -51,6 +51,7 @@ enum { BROM_BOOTSOURCE_SPINOR = 3, BROM_BOOTSOURCE_SPINAND = 4, BROM_BOOTSOURCE_SD = 5, + BROM_BOOTSOURCE_UFS = 7, BROM_BOOTSOURCE_I2C = 8, BROM_BOOTSOURCE_SPI = 9, BROM_BOOTSOURCE_USB = 10, diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index c17ba418ced..1def4e87971 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -49,6 +49,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0", [BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0", [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", + [BROM_BOOTSOURCE_UFS] = "/soc/ufshc@2a2d0000", }; static struct mm_region rk3576_mem_map[] = { diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 6572dde29f6..d2dd5e10935 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -76,6 +76,9 @@ static int spl_node_to_boot_device(int node) if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) return BOOT_DEVICE_SPI; + if (!uclass_find_device_by_of_offset(UCLASS_UFS, node, &parent)) + return BOOT_DEVICE_UFS; + return -1; } @@ -231,6 +234,17 @@ int spl_decode_boot_device(u32 boot_device, char *buf, size_t buflen) return -ENODEV; } + if (boot_device == BOOT_DEVICE_UFS) { + ret = uclass_find_device(UCLASS_UFS, 0, &dev); + if (ret) { + debug("%s: could not find device for UFS: %d\n", + __func__, ret); + return ret; + } + + return ofnode_get_path(dev_ofnode(dev), buf, buflen); + } + #if CONFIG_IS_ENABLED(BLK) dev_num = (boot_device == BOOT_DEVICE_MMC1) ? 0 : 1; From b00307e3c04248a009b4b92dc3233d871ecce80f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 11 Mar 2026 17:31:00 +0400 Subject: [PATCH 11/65] rockchip: rk3576-rock-4d: Enable UFS support The Radxa ROCK 4D has a eMMC 5.1 / UFS 2.0 module connector. Enable UFS related Kconfig options to support booting from UFS storage on ROCK 4D. Signed-off-by: Jonas Karlman Signed-off-by: Alexey Charkov Reviewed-by: Kever Yang --- configs/rock-4d-rk3576_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/rock-4d-rk3576_defconfig b/configs/rock-4d-rk3576_defconfig index d332cef8d21..7228a9d879a 100644 --- a/configs/rock-4d-rk3576_defconfig +++ b/configs/rock-4d-rk3576_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-rock-4d" @@ -19,8 +20,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-rock-4d.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_UFS_SUPPORT=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_ADC=y @@ -30,6 +33,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MISC=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_UFS=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_RNG=y @@ -56,6 +60,7 @@ CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_RK8XX=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -65,4 +70,6 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_UFS=y +CONFIG_UFS_ROCKCHIP=y CONFIG_ERRNO_STR=y From f7deed714cd93e3f9000bb2e438e24a319a0e6a0 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Wed, 11 Mar 2026 17:31:01 +0400 Subject: [PATCH 12/65] rockchip: rk3576-nanopi-m5: Enable UFS support NanoPi M5 supports UFS modules to be inserted into its eMMC/UFS slot, using the on-chip UFS controller inside the RK3576 SoC. Enable respective drivers in its default config to be able to load kernels from UFS. Signed-off-by: Alexey Charkov Reviewed-by: Kever Yang --- configs/nanopi-m5-rk3576_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/nanopi-m5-rk3576_defconfig b/configs/nanopi-m5-rk3576_defconfig index 4a097d043d7..88b6d0f9e86 100644 --- a/configs/nanopi-m5-rk3576_defconfig +++ b/configs/nanopi-m5-rk3576_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-nanopi-m5" @@ -19,8 +20,10 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-nanopi-m5.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_UFS_SUPPORT=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_ADC=y @@ -30,6 +33,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MISC=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_UFS=y CONFIG_CMD_USB=y CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -63,6 +67,7 @@ CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_RK8XX=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -75,4 +80,6 @@ CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_UFS=y +CONFIG_UFS_ROCKCHIP=y CONFIG_ERRNO_STR=y From 3336e85b6a303663723436ca15dc5ea5ed5358e0 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 7 May 2026 20:37:50 +0200 Subject: [PATCH 13/65] rockchip: Switch rk3128 boards to upstream devicetree Switch rk3128 boards to upstream devicetree. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 3 - arch/arm/dts/rk3128-evb.dts | 99 ---- arch/arm/dts/rk3128.dtsi | 780 ------------------------- arch/arm/mach-rockchip/Kconfig | 1 + configs/evb-rk3128_defconfig | 4 +- include/dt-bindings/clock/rk3128-cru.h | 273 --------- 6 files changed, 3 insertions(+), 1157 deletions(-) delete mode 100644 arch/arm/dts/rk3128-evb.dts delete mode 100644 arch/arm/dts/rk3128.dtsi delete mode 100644 include/dt-bindings/clock/rk3128-cru.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cf9046f6056..69824bf59b7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -45,9 +45,6 @@ dtb-$(CONFIG_MACH_S900) += \ dtb-$(CONFIG_MACH_S700) += \ s700-cubieboard7.dtb -dtb-$(CONFIG_ROCKCHIP_RK3128) += \ - rk3128-evb.dtb - dtb-$(CONFIG_ROCKCHIP_RK322X) += \ rk3229-evb.dtb diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts deleted file mode 100644 index 93291d78734..00000000000 --- a/arch/arm/dts/rk3128-evb.dts +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rk3128.dtsi" - -/ { - model = "Rockchip RK3128 Evaluation board"; - compatible = "rockchip,rk3128-evb", "rockchip,rk3128"; - - chosen { - stdout-path = &uart2; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vcc5v0_otg: vcc5v0-otg-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_host: vcc5v0-host-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&emmc { - fifo-mode; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; - -&usb_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&pinctrl { - usb_otg { - otg_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi deleted file mode 100644 index 3253c640341..00000000000 --- a/arch/arm/dts/rk3128.dtsi +++ /dev/null @@ -1,780 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3128"; - rockchip,sram = <&sram>; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - spi0 = &spi0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3128-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - }; - - cpu_axi_bus: cpu_axi_bus { - compatible = "rockchip,cpu_axi_bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - qos { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - crypto { - reg = <0x10128080 0x20>; - }; - - core { - reg = <0x1012a000 0x20>; - }; - - peri { - reg = <0x1012c000 0x20>; - }; - - gpu { - reg = <0x1012d000 0x20>; - }; - - vpu { - reg = <0x1012e000 0x20>; - }; - - rga { - reg = <0x1012f000 0x20>; - }; - ebc { - reg = <0x1012f080 0x20>; - }; - - iep { - reg = <0x1012f100 0x20>; - }; - - lcdc { - reg = <0x1012f180 0x20>; - rockchip,priority = <3 3>; - }; - - vip { - reg = <0x1012f200 0x20>; - rockchip,priority = <3 3>; - }; - }; - - msch { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - msch@10128000 { - reg = <0x10128000 0x20>; - rockchip,read-latency = <0x3f>; - }; - }; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - migrate = <0x84000005>; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - ranges; - - pdma: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - arm,pl330-broken-no-flushp;//2 - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin12m: xin12m { - compatible = "fixed-clock"; - clock-frequency = <12000000>; - clock-output-names = "xin12m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - ; - clock-frequency = <24000000>; - }; - - timer@20044000 { - compatible = "arm,armv7-timer"; - reg = <0x20044000 0xb8>; - interrupts = ; - rockchip,broadcast = <1>; - }; - - watchdog: watchdog@2004c000 { - compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; - reg = <0x2004c000 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - rockchip,irq = <1>; - rockchip,timeout = <60>; - rockchip,atboot = <1>; - rockchip,debug = <0>; - }; - - reset: reset@20000110 { - compatible = "rockchip,reset"; - reg = <0x20000110 0x24>; - #reset-cells = <1>; - }; - - nandc: nand-controller@10500000 { - compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; - reg = <0x10500000 0x4000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; - clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; - clock-names = "ahb", "nfc"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3128-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - uart0: serial@20060000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - dmas = <&pdma 2>, <&pdma 3>; - #dma-cells = <2>; - }; - - uart1: serial@20064000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20064000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - dmas = <&pdma 4>, <&pdma 5>; - #dma-cells = <2>; - }; - - uart2: serial@20068000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20068000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - dmas = <&pdma 6>, <&pdma 7>; - #dma-cells = <2>; - }; - - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - pwm0: pwm@20050000 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050000 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; - }; - - pwm1: pwm@20050010 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050010 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; - }; - - sram: sram@10080400 { - compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; - reg = <0x10080400 0x1C00>; - map-exec; - map-cacheable; - }; - - pmu: syscon@100a0000 { - compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; - reg = <0x100a0000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - gic: interrupt-controller@10139000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - reg = <0x10139000 0x1000>, - <0x1013a000 0x1000>, - <0x1013c000 0x2000>, - <0x1013e000 0x2000>; - interrupts = ; - }; - - u2phy: usb2phy { - compatible = "rockchip,rk3128-usb2phy"; - reg = <0x017c 0x0c>; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "usb480m_phy"; - status = "disabled"; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host_ehci: usb@101c0000 { - compatible = "generic-ehci"; - reg = <0x101c0000 0x20000>; - interrupts = ; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host_ohci: usb@101e0000 { - compatible = "generic-ohci"; - reg = <0x101e0000 0x20000>; - interrupts = ; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - sdmmc: mmc@10214000 { - compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10214000 0x4000>; - max-frequency = <150000000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - bus-width = <4>; - status = "disabled"; - }; - - emmc: mmc@1021c000 { - compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x1021c000 0x4000>; - max-frequency = <150000000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <8>; - default-sample-phase = <158>; - num-slots = <1>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - i2c0: i2c@20072000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <20072000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - }; - - i2c1: i2c@20056000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x20056000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - }; - - i2c2: i2c@2005a000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - }; - - i2c3: i2c@2005e000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005e000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - }; - - spi0: spi@20074000 { - compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; - reg = <0x20074000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; - rockchip,spi-src-clk = <0>; - num-cs = <2>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&pdma 8>, <&pdma 9>; - #dma-cells = <2>; - dma-names = "tx", "rx"; - }; - - grf: syscon@20008000 { - compatible = "rockchip,rk3128-grf", "syscon"; - reg = <0x20008000 0x1000>; - }; - - pinctrl: pinctrl@20008000 { - compatible = "rockchip,rk3128-pinctrl"; - reg = <0x20008000 0xA8>, - <0x200080A8 0x4C>, - <0x20008118 0x20>, - <0x20008100 0x04>; - reg-names = "base", "mux", "pull", "drv"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@2007c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2007c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20088000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20088000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, - <1 RK_PD1 2 &pcfg_pull_none>, - <1 RK_PD2 2 &pcfg_pull_none>, - <1 RK_PD3 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>, - <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD6 2 &pcfg_pull_none>, - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - nandc{ - nandc_ale:nandc-ale { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_cle:nandc-cle { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_wrn:nandc-wrn { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_rdn:nandc-rdn { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_rdy:nandc-rdy { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_cs0:nandc-cs0 { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_data: nandc-data { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>, - <0 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>, - <2 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>; - }; - - sdmmc_wp: sdmmc-wp { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>; - }; - - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>, - <1 RK_PC3 1 &pcfg_pull_up>, - <1 RK_PC4 1 &pcfg_pull_up>, - <1 RK_PC5 1 &pcfg_pull_up>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, - <2 RK_PC5 3 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_txd_mux0:spi0-txd-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_rxd_mux0:spi0-rxd-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_clk_mux0:spi0-clk-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_cs0_mux0:spi0-cs0-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_cs1_mux0:spi0-cs1-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - }; - - }; -}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 108713488af..02737c62df0 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -65,6 +65,7 @@ config ROCKCHIP_RK3066 config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" select CPU_V7A + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD help The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index e23f3352fa0..2d53adc0c1e 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x0 -CONFIG_DEFAULT_DEVICE_TREE="rk3128-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3128-evb" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3128=y CONFIG_SYS_BOOTM_LEN=0x4000000 @@ -18,7 +18,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 # CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_DEBUG_UART=y CONFIG_FIT=y -CONFIG_DEFAULT_FDT_FILE="rk3128-evb.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3128-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_GPT=y diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h deleted file mode 100644 index 6a47825dac5..00000000000 --- a/include/dt-bindings/clock/rk3128-cru.h +++ /dev/null @@ -1,273 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. - * Author: Elaine - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define ARMCLK 5 -#define PLL_GPLL_DIV2 6 -#define PLL_GPLL_DIV3 7 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S0 80 -#define SCLK_I2S1 81 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_SARADC 91 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_VOP 122 -#define SCLK_MAC_SRC 124 -#define SCLK_MAC 126 -#define SCLK_MAC_REFOUT 127 -#define SCLK_MAC_REF 128 -#define SCLK_MAC_RX 129 -#define SCLK_MAC_TX 130 -#define SCLK_HEVC_CORE 134 -#define SCLK_RGA 135 -#define SCLK_CRYPTO 138 -#define SCLK_TSP 139 -#define SCLK_OTGPHY0 142 -#define SCLK_OTGPHY1 143 -#define SCLK_DDRC 144 -#define SCLK_PVTM_FUNC 145 -#define SCLK_PVTM_CORE 146 -#define SCLK_PVTM_GPU 147 -#define SCLK_MIPI_24M 148 -#define SCLK_PVTM 149 -#define SCLK_CIF_SRC 150 -#define SCLK_CIF_OUT_SRC 151 -#define SCLK_CIF_OUT 152 -#define SCLK_SFC 153 -#define SCLK_USB480M 154 - -/* dclk gates */ -#define DCLK_VOP 190 -#define DCLK_EBC 191 - -/* aclk gates */ -#define ACLK_VIO0 192 -#define ACLK_VIO1 193 -#define ACLK_DMAC 194 -#define ACLK_CPU 195 -#define ACLK_VEPU 196 -#define ACLK_VDPU 197 -#define ACLK_CIF 198 -#define ACLK_IEP 199 -#define ACLK_LCDC0 204 -#define ACLK_RGA 205 -#define ACLK_PERI 210 -#define ACLK_VOP 211 -#define ACLK_GMAC 212 -#define ACLK_GPU 213 - -/* pclk gates */ -#define PCLK_SARADC 318 -#define PCLK_WDT 319 -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_VIO_H2P 324 -#define PCLK_MIPI 325 -#define PCLK_EFUSE 326 -#define PCLK_HDMI 327 -#define PCLK_ACODEC 328 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_SPI0 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_TSADC 344 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_CPU 354 -#define PCLK_PERI 363 -#define PCLK_GMAC 367 -#define PCLK_PMU_PRE 368 -#define PCLK_SIM_CARD 369 - -/* hclk gates */ -#define HCLK_SPDIF 440 -#define HCLK_GPS 441 -#define HCLK_USBHOST 442 -#define HCLK_I2S_8CH 443 -#define HCLK_I2S_2CH 444 -#define HCLK_VOP 452 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_CPU 460 -#define HCLK_VEPU 461 -#define HCLK_VDPU 462 -#define HCLK_LCDC0 463 -#define HCLK_EBC 465 -#define HCLK_VIO 466 -#define HCLK_RGA 467 -#define HCLK_IEP 468 -#define HCLK_VIO_H2P 469 -#define HCLK_CIF 470 -#define HCLK_HOST2 473 -#define HCLK_OTG 474 -#define HCLK_TSP 475 -#define HCLK_CRYPTO 476 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_ACLK_CORE 13 -#define SRST_STRC_SYS_A 14 -#define SRST_L2C 15 - -#define SRST_CPUSYS_H 18 -#define SRST_AHB2APBSYS_H 19 -#define SRST_SPDIF 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_PERI_NIU 23 -#define SRST_I2S_2CH 24 -#define SRST_I2S_8CH 25 -#define SRST_GPU_PVTM 26 -#define SRST_FUNC_PVTM 27 -#define SRST_CORE_PVTM 29 -#define SRST_EFUSE_P 30 -#define SRST_ACODEC_P 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_MIPIPHY_P 36 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 -#define SRST_SFC 47 - -#define SRST_PWM 48 -#define SRST_DAP_PO 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_CRYPTO 53 -#define SRST_GRF 55 -#define SRST_GMAC 56 -#define SRST_PERIPH_SYS_A 57 -#define SRST_PERIPH_SYS_H 58 -#define SRST_PERIPH_SYS_P 59 -#define SRST_SMART_CARD 60 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA 64 -#define SRST_GPS 67 -#define SRST_NANDC 68 -#define SRST_USBOTG0 69 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_OTGC1 74 -#define SRST_DDRMSCH 79 - -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI 84 -#define SRST_WDT 86 -#define SRST_SARADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 -#define SRST_TSP 92 -#define SRST_TSP_CLKIN 93 -#define SRST_HOST0_ECHI 94 - -#define SRST_HDMI_P 96 -#define SRST_VIO_ARBI_H 97 -#define SRST_VIO0_A 98 -#define SRST_VIO_BUS_H 99 -#define SRST_VOP_A 100 -#define SRST_VOP_H 101 -#define SRST_VOP_D 102 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_USBPOR 105 -#define SRST_IEP_A 106 -#define SRST_IEP_H 107 -#define SRST_RGA_A 108 -#define SRST_RGA_H 109 -#define SRST_CIF0 110 -#define SRST_PMU 111 - -#define SRST_VCODEC_A 112 -#define SRST_VCODEC_H 113 -#define SRST_VIO1_A 114 -#define SRST_HEVC_CORE 115 -#define SRST_VCODEC_NIU_A 116 -#define SRST_PMU_NIU_P 117 -#define SRST_LCDC0_S 119 -#define SRST_GPU 120 -#define SRST_GPU_NIU_A 122 -#define SRST_EBC_A 123 -#define SRST_EBC_H 124 - -#define SRST_CORE_DBG 128 -#define SRST_DBG_P 129 -#define SRST_TIMER0 130 -#define SRST_TIMER1 131 -#define SRST_TIMER2 132 -#define SRST_TIMER3 133 -#define SRST_TIMER4 134 -#define SRST_TIMER5 135 -#define SRST_VIO_H2P 136 -#define SRST_VIO_MIPI_DSI 137 - -#endif From 924f87b995fa6b451656df17f3b6be20a3cf9c4e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 7 May 2026 20:38:03 +0200 Subject: [PATCH 14/65] rockchip: Switch rk3229 boards to upstream devicetree Switch rk3229 boards to upstream devicetree. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 3 - arch/arm/dts/rk3229-evb.dts | 256 ----- arch/arm/dts/rk3229.dtsi | 52 - arch/arm/dts/rk322x.dtsi | 1293 ------------------------ arch/arm/mach-rockchip/Kconfig | 1 + board/rockchip/evb_rk3229/MAINTAINERS | 1 - configs/evb-rk3229_defconfig | 4 +- include/dt-bindings/clock/rk3228-cru.h | 287 ------ 8 files changed, 3 insertions(+), 1894 deletions(-) delete mode 100644 arch/arm/dts/rk3229-evb.dts delete mode 100644 arch/arm/dts/rk3229.dtsi delete mode 100644 arch/arm/dts/rk322x.dtsi delete mode 100644 include/dt-bindings/clock/rk3228-cru.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 69824bf59b7..2b65cd9105c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -45,9 +45,6 @@ dtb-$(CONFIG_MACH_S900) += \ dtb-$(CONFIG_MACH_S700) += \ s700-cubieboard7.dtb -dtb-$(CONFIG_ROCKCHIP_RK322X) += \ - rk3229-evb.dtb - dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts deleted file mode 100644 index 797476e8bef..00000000000 --- a/arch/arm/dts/rk3229-evb.dts +++ /dev/null @@ -1,256 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include "rk3229.dtsi" - -/ { - model = "Rockchip RK3229 Evaluation board"; - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - - aliases { - mmc0 = &emmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - ext_gmac: ext_gmac { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vccio_1v8>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vccio_1v8: vccio-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vccio_3v3: vccio-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vdd_arm: vdd-arm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - gpio_keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power_key: power-key { - label = "GPIO Key Power"; - gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - cap-mmc-highspeed; - non-removable; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_3v3>; - vccio2-supply = <&vccio_1v8>; - vccio4-supply = <&vccio_3v3>; -}; - -&pinctrl { - keys { - pwr_key: pwr-key { - rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_ehci { - status = "okay"; -}; - -&usb_host2_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3229.dtsi b/arch/arm/dts/rk3229.dtsi deleted file mode 100644 index c340fb30e77..00000000000 --- a/arch/arm/dts/rk3229.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include "rk322x.dtsi" - -/ { - compatible = "rockchip,rk3229"; - - /delete-node/ opp-table0; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1325000>; - }; - opp-1392000000 { - opp-hz = /bits/ 64 <1392000000>; - opp-microvolt = <1375000>; - }; - opp-1464000000 { - opp-hz = /bits/ 64 <1464000000>; - opp-microvolt = <1400000>; - }; - }; -}; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi deleted file mode 100644 index 8eed9e3a92e..00000000000 --- a/arch/arm/dts/rk322x.dtsi +++ /dev/null @@ -1,1293 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &spi0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - enable-method = "psci"; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - resets = <&cru SRST_CORE2>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - resets = <&cru SRST_CORE3>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - i2s1: i2s1@100b0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100b0000 0x4000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; - dmas = <&pdma 14>, <&pdma 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s0: i2s0@100c0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100c0000 0x4000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; - dmas = <&pdma 11>, <&pdma 12>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spdif: spdif@100d0000 { - compatible = "rockchip,rk3228-spdif"; - reg = <0x100d0000 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; - clock-names = "mclk", "hclk"; - dmas = <&pdma 10>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - i2s2: i2s2@100e0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100e0000 0x4000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; - dmas = <&pdma 0>, <&pdma 1>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - grf: syscon@11000000 { - compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; - reg = <0x11000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,rk3228-io-voltage-domain"; - status = "disabled"; - }; - - power: power-controller { - compatible = "rockchip,rk3228-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3228_PD_VIO { - reg = ; - clocks = <&cru ACLK_HDCP>, - <&cru SCLK_HDCP>, - <&cru ACLK_IEP>, - <&cru HCLK_IEP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>, - <&cru SCLK_RGA>; - pm_qos = <&qos_hdcp>, - <&qos_iep>, - <&qos_rga_r>, - <&qos_rga_w>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_VOP { - reg = ; - clocks =<&cru ACLK_VOP>, - <&cru DCLK_VOP>, - <&cru HCLK_VOP>; - pm_qos = <&qos_vop>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_VPU { - reg = ; - clocks = <&cru ACLK_VPU>, - <&cru HCLK_VPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_RKVDEC { - reg = ; - clocks = <&cru ACLK_RKVDEC>, - <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - pm_qos = <&qos_rkvdec_r>, - <&qos_rkvdec_w>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; - - u2phy0: usb2phy@760 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0760 0x0c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - #clock-cells = <0>; - status = "disabled"; - - u2phy0_otg: otg-port { - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy0_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - u2phy1: usb2phy@800 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0800 0x0c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - #clock-cells = <0>; - status = "disabled"; - - u2phy1_otg: otg-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy1_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - uart0: serial@11010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11010000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11020000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11030000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - efuse: efuse@11040000 { - compatible = "rockchip,rk3228-efuse"; - reg = <0x11040000 0x20>; - clocks = <&cru PCLK_EFUSE_256>; - clock-names = "pclk_efuse"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - efuse_id: id@7 { - reg = <0x7 0x10>; - }; - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11060000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11070000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11080000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - spi0: spi@11090000 { - compatible = "rockchip,rk3228-spi"; - reg = <0x11090000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; - status = "disabled"; - }; - - wdt: watchdog@110a0000 { - compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; - reg = <0x110a0000 0x100>; - interrupts = ; - clocks = <&cru PCLK_CPU>; - status = "disabled"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - timer: timer@110c0000 { - compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; - reg = <0x110c0000 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - cru: clock-controller@110e0000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x110e0000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - <&cru PLL_GPLL>, <&cru ARMCLK>, - <&cru PLL_CPLL>, <&cru ACLK_PERI>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>; - assigned-clock-rates = - <594000000>, <816000000>, - <500000000>, <150000000>, - <150000000>, <75000000>, - <150000000>, <150000000>, - <75000000>; - }; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>, - <&cpu1 THERMAL_NO_LIMIT 6>, - <&cpu2 THERMAL_NO_LIMIT 6>, - <&cpu3 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <32768>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - hdmi_phy: hdmi-phy@12030000 { - compatible = "rockchip,rk3228-hdmi-phy"; - reg = <0x12030000 0x10000>; - clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; - clock-names = "sysclk", "refoclk", "refpclk"; - #clock-cells = <0>; - clock-output-names = "hdmiphy_phy"; - #phy-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@20000000 { - compatible = "rockchip,rk3228-mali", "arm,mali-400"; - reg = <0x20000000 0x10000>; - interrupts = , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - power-domains = <&power RK3228_PD_GPU>; - resets = <&cru SRST_GPU_A>; - status = "disabled"; - }; - - vpu: video-codec@20020000 { - compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; - reg = <0x20020000 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3228_PD_VPU>; - }; - - vpu_mmu: iommu@20020800 { - compatible = "rockchip,iommu"; - reg = <0x20020800 0x100>; - interrupts = ; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VPU>; - #iommu-cells = <0>; - }; - - vdec: video-codec@20030000 { - compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; - reg = <0x20030000 0x480>; - interrupts = ; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - clock-names = "axi", "ahb", "cabac", "core"; - assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - assigned-clock-rates = <300000000>, <300000000>; - iommus = <&vdec_mmu>; - power-domains = <&power RK3228_PD_RKVDEC>; - }; - - vdec_mmu: iommu@20030480 { - compatible = "rockchip,iommu"; - reg = <0x20030480 0x40>, <0x200304c0 0x40>; - interrupts = ; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_RKVDEC>; - #iommu-cells = <0>; - }; - - vop: vop@20050000 { - compatible = "rockchip,rk3228-vop"; - reg = <0x20050000 0x1ffc>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - power-domains = <&power RK3228_PD_VOP>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@20053f00 { - compatible = "rockchip,iommu"; - reg = <0x20053f00 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VOP>; - #iommu-cells = <0>; - status = "disabled"; - }; - - rga: rga@20060000 { - compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; - reg = <0x20060000 0x1000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk", "hclk", "sclk"; - power-domains = <&power RK3228_PD_VIO>; - resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; - reset-names = "core", "axi", "ahb"; - }; - - iep_mmu: iommu@20070800 { - compatible = "rockchip,iommu"; - reg = <0x20070800 0x100>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@200a0000 { - compatible = "rockchip,rk3228-dw-hdmi"; - reg = <0x200a0000 0x20000>; - reg-io-width = <4>; - interrupts = ; - assigned-clocks = <&cru SCLK_HDMI_PHY>; - assigned-clock-parents = <&hdmi_phy>; - clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; - clock-names = "isfr", "iahb", "cec"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; - resets = <&cru SRST_HDMI_P>; - reset-names = "hdmi"; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - }; - - sdmmc: mmc@30000000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30000000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "disabled"; - }; - - sdio: mmc@30010000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30010000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; - status = "disabled"; - }; - - emmc: mmc@30020000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30020000 0x4000>; - interrupts = ; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <8>; - rockchip,default-sample-phase = <158>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - usb_otg: usb@30040000 { - compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30040000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host0_ehci: usb@30080000 { - compatible = "generic-ehci"; - reg = <0x30080000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@300a0000 { - compatible = "generic-ohci"; - reg = <0x300a0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@300c0000 { - compatible = "generic-ehci"; - reg = <0x300c0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@300e0000 { - compatible = "generic-ohci"; - reg = <0x300e0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ehci: usb@30100000 { - compatible = "generic-ehci"; - reg = <0x30100000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ohci: usb@30120000 { - compatible = "generic-ohci"; - reg = <0x30120000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rk3228-gmac"; - reg = <0x30200000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - qos_iep: qos@31030080 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030080 0x20>; - }; - - qos_rga_w: qos@31030100 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030100 0x20>; - }; - - qos_hdcp: qos@31030180 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030180 0x20>; - }; - - qos_rga_r: qos@31030200 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030200 0x20>; - }; - - qos_vpu: qos@31040000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31040000 0x20>; - }; - - qos_gpu: qos@31050000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31050000 0x20>; - }; - - qos_vop: qos@31060000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31060000 0x20>; - }; - - qos_rkvdec_r: qos@31070000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31070000 0x20>; - }; - - qos_rkvdec_w: qos@31070080 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31070080 0x20>; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, - <1 RK_PD1 2 &pcfg_pull_none>, - <1 RK_PD2 2 &pcfg_pull_none>, - <1 RK_PD3 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>, - <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD6 2 &pcfg_pull_none>, - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC5 2 &pcfg_pull_none>, - <2 RK_PC4 2 &pcfg_pull_none>, - <2 RK_PB3 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - phy_pins: phy-pins { - rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, - <2 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; - }; - - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, - <0 RK_PA7 2 &pcfg_pull_none>; - }; - - hdmi_cec: hdmi-cec { - rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, - <0 RK_PB1 1 &pcfg_pull_none>, - <0 RK_PB3 1 &pcfg_pull_none>, - <0 RK_PB4 1 &pcfg_pull_none>, - <0 RK_PB5 1 &pcfg_pull_none>, - <0 RK_PB6 1 &pcfg_pull_none>, - <1 RK_PA2 2 &pcfg_pull_none>, - <1 RK_PA4 2 &pcfg_pull_none>, - <1 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, - <2 RK_PD3 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - - uart21_xfer: uart21-xfer { - rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 02737c62df0..d92fcae2bb5 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -109,6 +109,7 @@ config ROCKCHIP_RK322X select TPL_OF_LIBFDT select TPL_HAVE_INIT_STACK if TPL select SPL_DRIVERS_MISC + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD imply SPL_SERIAL imply SPL_ROCKCHIP_COMMON_BOARD diff --git a/board/rockchip/evb_rk3229/MAINTAINERS b/board/rockchip/evb_rk3229/MAINTAINERS index 4de97dbb0a4..7758ee9b930 100644 --- a/board/rockchip/evb_rk3229/MAINTAINERS +++ b/board/rockchip/evb_rk3229/MAINTAINERS @@ -1,7 +1,6 @@ EVB-RK3229 M: Kever Yang S: Maintained -F: arch/arm/dts/rk3229-evb.dts F: arch/arm/dts/rk3229-evb-u-boot.dtsi F: board/rockchip/evb_rk3229 F: include/configs/evb_rk3229.h diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 251ff4a0b6d..577b6580b3b 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -9,7 +9,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x61100000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3229-evb" CONFIG_ROCKCHIP_RK322X=y CONFIG_TARGET_EVB_RK3229=y CONFIG_SPL_STACK_R_ADDR=0x60600000 @@ -24,7 +24,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3229-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x100000 diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h deleted file mode 100644 index de550ea56ee..00000000000 --- a/include/dt-bindings/clock/rk3228-cru.h +++ /dev/null @@ -1,287 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2015 Rockchip Electronics Co. Ltd. - * Author: Jeffy Chen - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define ARMCLK 5 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S0 80 -#define SCLK_I2S1 81 -#define SCLK_I2S2 82 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_SDIO_SRC 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_VOP 122 -#define SCLK_HDMI_HDCP 123 -#define SCLK_MAC_SRC 124 -#define SCLK_MAC_EXTCLK 125 -#define SCLK_MAC 126 -#define SCLK_MAC_REFOUT 127 -#define SCLK_MAC_REF 128 -#define SCLK_MAC_RX 129 -#define SCLK_MAC_TX 130 -#define SCLK_MAC_PHY 131 -#define SCLK_MAC_OUT 132 -#define SCLK_VDEC_CABAC 133 -#define SCLK_VDEC_CORE 134 -#define SCLK_RGA 135 -#define SCLK_HDCP 136 -#define SCLK_HDMI_CEC 137 -#define SCLK_CRYPTO 138 -#define SCLK_TSP 139 -#define SCLK_HSADC 140 -#define SCLK_WIFI 141 -#define SCLK_OTGPHY0 142 -#define SCLK_OTGPHY1 143 -#define SCLK_HDMI_PHY 144 - -/* dclk gates */ -#define DCLK_VOP 190 -#define DCLK_HDMI_PHY 191 - -/* aclk gates */ -#define ACLK_DMAC 194 -#define ACLK_CPU 195 -#define ACLK_VPU_PRE 196 -#define ACLK_RKVDEC_PRE 197 -#define ACLK_RGA_PRE 198 -#define ACLK_IEP_PRE 199 -#define ACLK_HDCP_PRE 200 -#define ACLK_VOP_PRE 201 -#define ACLK_VPU 202 -#define ACLK_RKVDEC 203 -#define ACLK_IEP 204 -#define ACLK_RGA 205 -#define ACLK_HDCP 206 -#define ACLK_PERI 210 -#define ACLK_VOP 211 -#define ACLK_GMAC 212 -#define ACLK_GPU 213 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_VIO_H2P 324 -#define PCLK_HDCP 325 -#define PCLK_EFUSE_1024 326 -#define PCLK_EFUSE_256 327 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_SPI0 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_TSADC 344 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_CPU 354 -#define PCLK_PERI 363 -#define PCLK_HDMI_CTRL 364 -#define PCLK_HDMI_PHY 365 -#define PCLK_GMAC 367 - -/* hclk gates */ -#define HCLK_I2S0_8CH 442 -#define HCLK_I2S1_8CH 443 -#define HCLK_I2S2_2CH 444 -#define HCLK_SPDIF_8CH 445 -#define HCLK_VOP 452 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_CPU 460 -#define HCLK_VPU_PRE 461 -#define HCLK_RKVDEC_PRE 462 -#define HCLK_VIO_PRE 463 -#define HCLK_VPU 464 -#define HCLK_RKVDEC 465 -#define HCLK_VIO 466 -#define HCLK_RGA 467 -#define HCLK_IEP 468 -#define HCLK_VIO_H2P 469 -#define HCLK_HDCP_MMU 470 -#define HCLK_HOST0 471 -#define HCLK_HOST1 472 -#define HCLK_HOST2 473 -#define HCLK_OTG 474 -#define HCLK_TSP 475 -#define HCLK_M_CRYPTO 476 -#define HCLK_S_CRYPTO 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_ACLK_CORE 13 -#define SRST_NOC 14 -#define SRST_L2C 15 - -#define SRST_CPUSYS_H 18 -#define SRST_BUSSYS_H 19 -#define SRST_SPDIF 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_OTG_ADP 23 -#define SRST_I2S0 24 -#define SRST_I2S1 25 -#define SRST_I2S2 26 -#define SRST_ACODEC_P 27 -#define SRST_DFIMON 28 -#define SRST_MSCH 29 -#define SRST_EFUSE1024 30 -#define SRST_EFUSE256 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_PERIPH_NOC_A 36 -#define SRST_PERIPH_NOC_BUS_H 37 -#define SRST_PERIPH_NOC_P 38 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_PHYNOC 42 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 - -#define SRST_PWM 48 -#define SRST_A53_GIC 49 -#define SRST_DAP 51 -#define SRST_DAP_NOC 52 -#define SRST_CRYPTO 53 -#define SRST_SGRF 54 -#define SRST_GRF 55 -#define SRST_GMAC 56 -#define SRST_PERIPH_NOC_H 58 -#define SRST_MACPHY 63 - -#define SRST_DMA 64 -#define SRST_NANDC 68 -#define SRST_USBOTG 69 -#define SRST_OTGC 70 -#define SRST_USBHOST0 71 -#define SRST_HOST_CTRL0 72 -#define SRST_USBHOST1 73 -#define SRST_HOST_CTRL1 74 -#define SRST_USBHOST2 75 -#define SRST_HOST_CTRL2 76 -#define SRST_USBPOR0 77 -#define SRST_USBPOR1 78 -#define SRST_DDRMSCH 79 - -#define SRST_SMART_CARD 80 -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI 84 -#define SRST_TSP_H 85 -#define SRST_TSP 86 -#define SRST_TSADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 -#define SRST_HOST0_ECHI 92 -#define SRST_HOST1_ECHI 93 -#define SRST_HOST2_ECHI 94 -#define SRST_VOP_NOC_A 95 - -#define SRST_HDMI_P 96 -#define SRST_VIO_ARBI_H 97 -#define SRST_IEP_NOC_A 98 -#define SRST_VIO_NOC_H 99 -#define SRST_VOP_A 100 -#define SRST_VOP_H 101 -#define SRST_VOP_D 102 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_UTMI2 105 -#define SRST_UTMI3 106 -#define SRST_RGA 107 -#define SRST_RGA_NOC_A 108 -#define SRST_RGA_A 109 -#define SRST_RGA_H 110 -#define SRST_HDCP_A 111 - -#define SRST_VPU_A 112 -#define SRST_VPU_H 113 -#define SRST_VPU_NOC_A 116 -#define SRST_VPU_NOC_H 117 -#define SRST_RKVDEC_A 118 -#define SRST_RKVDEC_NOC_A 119 -#define SRST_RKVDEC_H 120 -#define SRST_RKVDEC_NOC_H 121 -#define SRST_RKVDEC_CORE 122 -#define SRST_RKVDEC_CABAC 123 -#define SRST_IEP_A 124 -#define SRST_IEP_H 125 -#define SRST_GPU_A 126 -#define SRST_GPU_NOC_A 127 - -#define SRST_CORE_DBG 128 -#define SRST_DBG_P 129 -#define SRST_TIMER0 130 -#define SRST_TIMER1 131 -#define SRST_TIMER2 132 -#define SRST_TIMER3 133 -#define SRST_TIMER4 134 -#define SRST_TIMER5 135 -#define SRST_VIO_H2P 136 -#define SRST_HDMIPHY 139 -#define SRST_VDAC 140 -#define SRST_TIMER_6CH_P 141 - -#endif From a05adbb9b30115ef7d04668d35650f311458dd2d Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Mon, 18 May 2026 15:17:09 +0100 Subject: [PATCH 15/65] mailbox: mpfs-mbox: fix MMIO mapping calculation Correct the MMIO mapping size calculation, which previously relied on an invalid start/end subtraction. This change corrects a functional bug and cleans up the driver without altering its behavior. Fixes: 111e9bf6a5ac ("mailbox: add PolarFire SoC mailbox driver") Signed-off-by: Jamie Gibbons Reviewed-by: Conor Dooley --- drivers/mailbox/mpfs-mbox.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/mpfs-mbox.c b/drivers/mailbox/mpfs-mbox.c index 55238847ecd..4a9465c7a72 100644 --- a/drivers/mailbox/mpfs-mbox.c +++ b/drivers/mailbox/mpfs-mbox.c @@ -145,7 +145,7 @@ static int mpfs_mbox_probe(struct udevice *dev) return ret; }; - mbox->ctrl_base = devm_ioremap(dev, regs.start, regs.start - regs.end); + mbox->ctrl_base = devm_ioremap(dev, res.start, resource_size(&res)); ret = ofnode_read_resource(node, 2, ®s); if (ret) { @@ -153,7 +153,7 @@ static int mpfs_mbox_probe(struct udevice *dev) return ret; }; - mbox->mbox_base = devm_ioremap(dev, regs.start, regs.start - regs.end); + mbox->mbox_base = devm_ioremap(dev, res.start, resource_size(&res)); mbox->dev = dev; dev_set_priv(dev, mbox); From 1173e02c9880d9f7d1bf15308490493332b03a61 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Mon, 18 May 2026 15:17:10 +0100 Subject: [PATCH 16/65] mailbox: mpfs-mbox: fix Driver Model private data handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MPFS mailbox driver declares priv_auto but also allocates a second private data structure in the legacy probe path and overwrites the device’s private pointer using dev_set_priv(). This results in leaking the auto-allocated private data and replacing the driver’s private state mid-probe, which is incorrect usage of the U-Boot Driver Model and can lead to undefined behavior. Remove the redundant allocation and dev_set_priv() call so that the driver consistently uses the auto-allocated private data provided by U-Boot. Fixes: 111e9bf6a5ac ("mailbox: add PolarFire SoC mailbox driver") Signed-off-by: Jamie Gibbons Reviewed-by: Conor Dooley --- drivers/mailbox/mpfs-mbox.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/mailbox/mpfs-mbox.c b/drivers/mailbox/mpfs-mbox.c index 4a9465c7a72..2e20b08307c 100644 --- a/drivers/mailbox/mpfs-mbox.c +++ b/drivers/mailbox/mpfs-mbox.c @@ -135,10 +135,6 @@ static int mpfs_mbox_probe(struct udevice *dev) node = dev_ofnode(dev); - mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); - if (!mbox) - return -ENOMEM; - ret = ofnode_read_resource(node, 0, ®s); if (ret) { dev_err(dev, "No reg property for controller base\n"); @@ -156,7 +152,6 @@ static int mpfs_mbox_probe(struct udevice *dev) mbox->mbox_base = devm_ioremap(dev, res.start, resource_size(&res)); mbox->dev = dev; - dev_set_priv(dev, mbox); mbox->chan->con_priv = mbox; return 0; From 763435d0e3124539dc36c730c3832a1b4162d3f7 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Mon, 18 May 2026 15:17:11 +0100 Subject: [PATCH 17/65] mailbox: mpfs-mbox: fix driver bug and cleanup Remove an unused and invalid struct mbox_chan pointer from the private data and fix incorrect memory handling in the probe path, where the private data structure was allocated. This change corrects a functional bugs and cleans up the driver without altering its behavior. Fixes: 111e9bf6a5ac ("mailbox: add PolarFire SoC mailbox driver") Signed-off-by: Jamie Gibbons Reviewed-by: Conor Dooley --- drivers/mailbox/mpfs-mbox.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/mailbox/mpfs-mbox.c b/drivers/mailbox/mpfs-mbox.c index 2e20b08307c..08c51c96718 100644 --- a/drivers/mailbox/mpfs-mbox.c +++ b/drivers/mailbox/mpfs-mbox.c @@ -37,13 +37,12 @@ struct mpfs_mbox { struct udevice *dev; void __iomem *ctrl_base; void __iomem *mbox_base; - struct mbox_chan *chan; }; static bool mpfs_mbox_busy(struct mbox_chan *chan) { struct mpfs_mbox *mbox = dev_get_priv(chan->dev); - uint16_t status; + u32 status; status = readl(mbox->ctrl_base + SERVICES_SR_OFFSET); @@ -152,7 +151,6 @@ static int mpfs_mbox_probe(struct udevice *dev) mbox->mbox_base = devm_ioremap(dev, res.start, resource_size(&res)); mbox->dev = dev; - mbox->chan->con_priv = mbox; return 0; } From 6c128738240d7e3a6020676501ad382af3359f3e Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Mon, 18 May 2026 15:17:12 +0100 Subject: [PATCH 18/65] mailbox: mpfs-mbox: support new syscon based devicetree configuration The original PolarFire SoC mailbox devicetree bindings described the control/status and interrupt registers as standalone reg regions of the mailbox device. This was incorrect, as these registers are shared system control blocks and should instead be modeled as syscon devices. Linux has since corrected this by introducing syscon-based bindings for the MPFS mailbox and updating the mailbox driver to access the control and interrupt registers via syscon/regmap. U-Boot, however, continued to expect the legacy binding, causing mailbox access to fail when using Linux-aligned devicetrees. Update the U-Boot MPFS mailbox driver to support the new syscon-based bindings by resolving the control and sysreg syscon nodes and accessing the registers through regmap. Support for the legacy mailbox binding is retained for backwards compatibility with existing firmware-provided devicetrees. This brings the U-Boot mailbox driver in line with the corrected hardware description and matches the behavior of the Linux mailbox driver. Signed-off-by: Jamie Gibbons Reviewed-by: Conor Dooley --- drivers/mailbox/Kconfig | 2 + drivers/mailbox/mpfs-mbox.c | 99 +++++++++++++++++++++++++++---------- 2 files changed, 74 insertions(+), 27 deletions(-) diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index f45e611c966..1d9e284cfd1 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -32,6 +32,8 @@ config MPFS_MBOX bool "Enable MPFS system controller support" depends on DM_MAILBOX && ARCH_RV64I select DEVRES + depends on SYSCON + depends on REGMAP help Enable support for the mailboxes that provide a communication channel with the system controller integrated on PolarFire SoC. diff --git a/drivers/mailbox/mpfs-mbox.c b/drivers/mailbox/mpfs-mbox.c index 08c51c96718..b1ce377525e 100644 --- a/drivers/mailbox/mpfs-mbox.c +++ b/drivers/mailbox/mpfs-mbox.c @@ -13,19 +13,21 @@ #include #include #include -#include #include #include #include -#include -#include +#include +#include #include #include -#include #include +#include +#include #define SERVICES_CR_OFFSET 0x50u #define SERVICES_SR_OFFSET 0x54u +#define MESSAGE_INT_OFFSET 0x18cu +#define MAILBOX_REG_OFFSET 0x800u #define SERVICE_CR_REQ_MASK 0x1u #define SERVICE_SR_BUSY_MASK 0x2u @@ -35,8 +37,10 @@ struct mpfs_mbox { struct udevice *dev; - void __iomem *ctrl_base; void __iomem *mbox_base; + void __iomem *int_reg; + struct regmap *control_scb; + struct regmap *sysreg_scb; }; static bool mpfs_mbox_busy(struct mbox_chan *chan) @@ -44,7 +48,7 @@ static bool mpfs_mbox_busy(struct mbox_chan *chan) struct mpfs_mbox *mbox = dev_get_priv(chan->dev); u32 status; - status = readl(mbox->ctrl_base + SERVICES_SR_OFFSET); + regmap_read(mbox->control_scb, SERVICES_SR_OFFSET, &status); return status & SERVICE_SR_BUSY_MASK; } @@ -79,14 +83,15 @@ static int mpfs_mbox_send(struct mbox_chan *chan, const void *data) cmd_shifted = msg->cmd_opcode << SERVICE_CR_COMMAND_SHIFT; cmd_shifted |= SERVICE_CR_REQ_MASK; - writel(cmd_shifted, mbox->ctrl_base + SERVICES_CR_OFFSET); + + regmap_write(mbox->control_scb, SERVICES_CR_OFFSET, cmd_shifted); do { - value = readl(mbox->ctrl_base + SERVICES_CR_OFFSET); + regmap_read(mbox->control_scb, SERVICES_CR_OFFSET, &value); } while (SERVICE_CR_REQ_MASK == (value & SERVICE_CR_REQ_MASK)); do { - value = readl(mbox->ctrl_base + SERVICES_SR_OFFSET); + regmap_read(mbox->control_scb, SERVICES_SR_OFFSET, &value); } while (SERVICE_SR_BUSY_MASK == (value & SERVICE_SR_BUSY_MASK)); msg->response->resp_status = (value >> SERVICE_SR_STATUS_SHIFT); @@ -117,6 +122,11 @@ static int mpfs_mbox_recv(struct mbox_chan *chan, void *data) for (idx = 0; idx < response->resp_size; idx++) *((u8 *)(response->resp_msg) + idx) = readb(mbox->mbox_base + msg->resp_offset + idx); + if (mbox->sysreg_scb) + regmap_write(mbox->sysreg_scb, MESSAGE_INT_OFFSET, 0); + else + writel_relaxed(0, mbox->int_reg); + return 0; } @@ -125,34 +135,69 @@ static const struct mbox_ops mpfs_mbox_ops = { .recv = mpfs_mbox_recv, }; -static int mpfs_mbox_probe(struct udevice *dev) +/* + * Use global compatible lookup instead of phandles, as U-Boot may run + * with a reduced or firmware-provided device tree where mailbox syscon + * phandle properties are not guaranteed to be present. + */ +static int mpfs_mbox_syscon_probe(struct udevice *dev, struct mpfs_mbox *mbox) { - struct mpfs_mbox *mbox; - struct resource regs; ofnode node; + + node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-control-scb"); + if (!ofnode_valid(node)) + return -ENODEV; + + mbox->control_scb = syscon_node_to_regmap(node); + if (IS_ERR(mbox->control_scb)) + return PTR_ERR(mbox->control_scb); + + node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-sysreg-scb"); + if (!ofnode_valid(node)) + return -ENODEV; + + mbox->sysreg_scb = syscon_node_to_regmap(node); + if (IS_ERR(mbox->sysreg_scb)) + return PTR_ERR(mbox->sysreg_scb); + + mbox->mbox_base = dev_read_addr_ptr(dev); + if (!mbox->mbox_base) + return -EINVAL; + + return 0; +} + +static int mpfs_mbox_legacy_probe(struct udevice *dev, struct mpfs_mbox *mbox) +{ int ret; - node = dev_ofnode(dev); - - ret = ofnode_read_resource(node, 0, ®s); - if (ret) { - dev_err(dev, "No reg property for controller base\n"); + ret = regmap_init_mem_index(dev_ofnode(dev), &mbox->control_scb, 0); + if (ret) return ret; - }; - mbox->ctrl_base = devm_ioremap(dev, res.start, resource_size(&res)); + mbox->mbox_base = dev_read_addr_index_ptr(dev, 2); + if (!mbox->mbox_base) + mbox->mbox_base = dev_read_addr_index_ptr(dev, 0) + MAILBOX_REG_OFFSET; - ret = ofnode_read_resource(node, 2, ®s); - if (ret) { - dev_err(dev, "No reg property for mailbox base\n"); - return ret; - }; + mbox->int_reg = dev_read_addr_index_ptr(dev, 1); + if (!mbox->int_reg) + return -EINVAL; - mbox->mbox_base = devm_ioremap(dev, res.start, resource_size(&res)); + return 0; +} + +static int mpfs_mbox_probe(struct udevice *dev) +{ + struct mpfs_mbox *mbox = dev_get_priv(dev); + int ret; mbox->dev = dev; - return 0; + ret = mpfs_mbox_syscon_probe(dev, mbox); + if (!ret) + return 0; + + return mpfs_mbox_legacy_probe(dev, mbox); } static const struct udevice_id mpfs_mbox_ids[] = { @@ -167,4 +212,4 @@ U_BOOT_DRIVER(mpfs_mbox) = { .probe = mpfs_mbox_probe, .priv_auto = sizeof(struct mpfs_mbox), .ops = &mpfs_mbox_ops, -}; +}; \ No newline at end of file From 5e6f370c1e3dc5a97ed865a0c3e648f5100c349c Mon Sep 17 00:00:00 2001 From: Federico Amedeo Izzo Date: Sat, 23 May 2026 15:04:24 +0200 Subject: [PATCH 19/65] regulator: qcom-rpmh-regulator: fix regulator mode mismatch Initial regulator mode was read from dts but never applied. This caused a mismatch between saved mode and actual regulator mode. Apply the current mode from priv->mode during enable() and move rpmh_regulator_vrm_set_mode function before rpmh_regulator_set_enable_state(). Signed-off-by: Federico Amedeo Izzo Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260523-qcom-ufs-regulator-support-v4-1-45639533b06d@izzo.pro Signed-off-by: Casey Connolly --- drivers/power/regulator/qcom-rpmh-regulator.c | 108 +++++++++--------- 1 file changed, 57 insertions(+), 51 deletions(-) diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c index 4d65aae1690..f789b5b6f86 100644 --- a/drivers/power/regulator/qcom-rpmh-regulator.c +++ b/drivers/power/regulator/qcom-rpmh-regulator.c @@ -295,57 +295,6 @@ static int rpmh_regulator_vrm_get_value(struct udevice *rdev) return vreg->uv; } -static int rpmh_regulator_is_enabled(struct udevice *rdev) -{ - struct rpmh_vreg *vreg = dev_get_priv(rdev); - int ret; - - debug("%s: is_enabled %d\n", rdev->name, vreg->enabled); - - if (vreg->enabled < 0) { - struct tcs_cmd cmd = { - .addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE, - }; - ret = rpmh_regulator_read_data(vreg, &cmd); - /* - * Don't override if disabled since we will also vote the right voltage - * while enabling - */ - if (!ret && cmd.data) - vreg->enabled = cmd.data & RPMH_REGULATOR_ENABLE_MASK; - } - - return vreg->enabled > 0; -} - -static int rpmh_regulator_set_enable_state(struct udevice *rdev, - bool enable) -{ - struct rpmh_vreg *vreg = dev_get_priv(rdev); - struct tcs_cmd cmd = { - .addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE, - .data = enable, - }; - int ret; - - debug("%s: set_enable %d (current %d)\n", rdev->name, enable, - vreg->enabled); - - if (vreg->enabled == -EINVAL && - vreg->uv != -ENOTRECOVERABLE) { - ret = _rpmh_regulator_vrm_set_value(rdev, - vreg->uv, true); - if (ret < 0) - return ret; - } - - ret = rpmh_regulator_send_request(vreg, &cmd, enable); - if (!ret) - vreg->enabled = enable; - - return ret; -} - static int rpmh_regulator_vrm_set_mode_bypass(struct rpmh_vreg *vreg, unsigned int mode, bool bypassed) { @@ -396,6 +345,63 @@ static int rpmh_regulator_vrm_set_mode(struct udevice *rdev, return ret; } +static int rpmh_regulator_is_enabled(struct udevice *rdev) +{ + struct rpmh_vreg *vreg = dev_get_priv(rdev); + int ret; + + debug("%s: is_enabled %d\n", rdev->name, vreg->enabled); + + if (vreg->enabled < 0) { + struct tcs_cmd cmd = { + .addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE, + }; + ret = rpmh_regulator_read_data(vreg, &cmd); + /* + * Don't override if disabled since we will also vote the right voltage + * while enabling + */ + if (!ret && cmd.data) + vreg->enabled = cmd.data & RPMH_REGULATOR_ENABLE_MASK; + } + + return vreg->enabled > 0; +} + +static int rpmh_regulator_set_enable_state(struct udevice *rdev, + bool enable) +{ + struct rpmh_vreg *vreg = dev_get_priv(rdev); + struct tcs_cmd cmd = { + .addr = vreg->addr + RPMH_REGULATOR_REG_ENABLE, + .data = enable, + }; + int ret; + + debug("%s: set_enable %d (current %d)\n", rdev->name, enable, + vreg->enabled); + + if (vreg->mode != -EINVAL) { + ret = rpmh_regulator_vrm_set_mode_bypass(vreg, vreg->mode, vreg->bypassed); + if (ret < 0) + return ret; + } + + if (vreg->enabled == -EINVAL && + vreg->uv != -ENOTRECOVERABLE) { + ret = _rpmh_regulator_vrm_set_value(rdev, + vreg->uv, true); + if (ret < 0) + return ret; + } + + ret = rpmh_regulator_send_request(vreg, &cmd, enable); + if (!ret) + vreg->enabled = enable; + + return ret; +} + static int rpmh_regulator_vrm_get_pmic_mode(struct rpmh_vreg *vreg, int *pmic_mode) { struct tcs_cmd cmd = { From 957941943bdb7e48aa223737268c28a0ae2dcd6d Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 4 May 2026 17:45:08 +0400 Subject: [PATCH 20/65] rockchip: clk: clk_rk3576: Add support for RK3576 GMAC 25MHz clock output Rockchip RK3576 SoC has two built-in GMACs which connect to external PHYs via RGMII interface. The RGMII link can be clocked by either the PHY or the SoC. When the SoC is the master, as is the case on the RK3576 EVB1, the output clock needs to be configured in the CRU. Add the respective logic for getting and setting the RGMII reference clock output for both GMAC0 and GMAC1. Signed-off-by: Alexey Charkov Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/cru_rk3576.h | 14 ++++++ drivers/clk/rockchip/clk_rk3576.c | 50 +++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h index c51750beff2..fb77fbd7307 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h @@ -222,6 +222,20 @@ enum { REF_CLK0_OUT_PLL_DIV_SHIFT = 0, REF_CLK0_OUT_PLL_DIV_MASK = 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT, + /* CRU_CLK_SEL36_CON */ + CLK_REFCLKO25M_GMAC0_DIV_SHIFT = 0, + CLK_REFCLKO25M_GMAC0_DIV_MASK = 0x7f << CLK_REFCLKO25M_GMAC0_DIV_SHIFT, + CLK_REFCLKO25M_GMAC0_SEL_SHIFT = 7, + CLK_REFCLKO25M_GMAC0_SEL_MASK = 1 << CLK_REFCLKO25M_GMAC0_SEL_SHIFT, + CLK_REFCLKO25M_GMAC0_SEL_GPLL = 0, + CLK_REFCLKO25M_GMAC0_SEL_CPLL = 1, + CLK_REFCLKO25M_GMAC1_DIV_SHIFT = 8, + CLK_REFCLKO25M_GMAC1_DIV_MASK = 0x7f << CLK_REFCLKO25M_GMAC1_DIV_SHIFT, + CLK_REFCLKO25M_GMAC1_SEL_SHIFT = 15, + CLK_REFCLKO25M_GMAC1_SEL_MASK = 1 << CLK_REFCLKO25M_GMAC1_SEL_SHIFT, + CLK_REFCLKO25M_GMAC1_SEL_GPLL = 0, + CLK_REFCLKO25M_GMAC1_SEL_CPLL = 1, + /* CRU_CLK_SEL55_CON */ ACLK_BUS_ROOT_SEL_SHIFT = 9, ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT, diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index dd8b59356ef..db8ce25852f 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -1549,6 +1549,24 @@ static ulong rk3576_gmac_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) con = readl(&cru->clksel_con[31]); div = (con & CLK_GMAC1_125M_DIV_MASK) >> CLK_GMAC1_125M_DIV_SHIFT; return DIV_TO_RATE(priv->cpll_hz, div); + case REFCLKO25M_GMAC0_OUT: + con = readl(&cru->clksel_con[36]); + div = (con & CLK_REFCLKO25M_GMAC0_DIV_MASK) >> CLK_REFCLKO25M_GMAC0_DIV_SHIFT; + src = (con & CLK_REFCLKO25M_GMAC0_SEL_MASK) >> CLK_REFCLKO25M_GMAC0_SEL_SHIFT; + if (src == CLK_REFCLKO25M_GMAC0_SEL_CPLL) + p_rate = priv->cpll_hz; + else + p_rate = priv->gpll_hz; + return DIV_TO_RATE(p_rate, div); + case REFCLKO25M_GMAC1_OUT: + con = readl(&cru->clksel_con[36]); + div = (con & CLK_REFCLKO25M_GMAC1_DIV_MASK) >> CLK_REFCLKO25M_GMAC1_DIV_SHIFT; + src = (con & CLK_REFCLKO25M_GMAC1_SEL_MASK) >> CLK_REFCLKO25M_GMAC1_SEL_SHIFT; + if (src == CLK_REFCLKO25M_GMAC1_SEL_CPLL) + p_rate = priv->cpll_hz; + else + p_rate = priv->gpll_hz; + return DIV_TO_RATE(p_rate, div); default: return -ENOENT; } @@ -1608,6 +1626,34 @@ static ulong rk3576_gmac_set_clk(struct rk3576_clk_priv *priv, CLK_GMAC1_125M_DIV_MASK, (div - 1) << CLK_GMAC1_125M_DIV_SHIFT); break; + case REFCLKO25M_GMAC0_OUT: + if (!(priv->gpll_hz % rate)) { + src = CLK_REFCLKO25M_GMAC0_SEL_GPLL; + div = priv->gpll_hz / rate; + } else { + src = CLK_REFCLKO25M_GMAC0_SEL_CPLL; + div = priv->cpll_hz / rate; + } + rk_clrsetreg(&cru->clksel_con[36], + CLK_REFCLKO25M_GMAC0_SEL_MASK | + CLK_REFCLKO25M_GMAC0_DIV_MASK, + src << CLK_REFCLKO25M_GMAC0_SEL_SHIFT | + (div - 1) << CLK_REFCLKO25M_GMAC0_DIV_SHIFT); + break; + case REFCLKO25M_GMAC1_OUT: + if (!(priv->gpll_hz % rate)) { + src = CLK_REFCLKO25M_GMAC1_SEL_GPLL; + div = priv->gpll_hz / rate; + } else { + src = CLK_REFCLKO25M_GMAC1_SEL_CPLL; + div = priv->cpll_hz / rate; + } + rk_clrsetreg(&cru->clksel_con[36], + CLK_REFCLKO25M_GMAC1_SEL_MASK | + CLK_REFCLKO25M_GMAC1_DIV_MASK, + src << CLK_REFCLKO25M_GMAC1_SEL_SHIFT | + (div - 1) << CLK_REFCLKO25M_GMAC1_DIV_SHIFT); + break; default: return -ENOENT; } @@ -2016,6 +2062,8 @@ static ulong rk3576_clk_get_rate(struct clk *clk) case CLK_GMAC1_PTP_REF: case CLK_GMAC0_125M_SRC: case CLK_GMAC1_125M_SRC: + case REFCLKO25M_GMAC0_OUT: + case REFCLKO25M_GMAC1_OUT: rate = rk3576_gmac_get_clk(priv, clk->id); break; case CLK_UART_FRAC_0: @@ -2197,6 +2245,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate) case CLK_GMAC1_PTP_REF: case CLK_GMAC0_125M_SRC: case CLK_GMAC1_125M_SRC: + case REFCLKO25M_GMAC0_OUT: + case REFCLKO25M_GMAC1_OUT: ret = rk3576_gmac_set_clk(priv, clk->id, rate); break; case CLK_UART_FRAC_0: From 22fa81fd8cce908ecc7e93b55ec4e8df8507779b Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 18 May 2026 01:24:13 +0200 Subject: [PATCH 21/65] rockchip: MAINTAINERS: upstream devicetree update Most Rockchip boards are now using the upstream device tree. Some MAINTAINERS files still contain a reference to no longer available files. Update and where possible streamline with '*' ending. Signed-off-by: Johan Jonker Reviewed-by: Peter Robinson Acked-by: Matwey V. Kornilov Reviewed-by: Kever Yang --- .../neural-compute-module-6/MAINTAINERS | 8 +--- board/hardkernel/odroid_m1/MAINTAINERS | 3 +- board/khadas/khadas-edge2-rk3588s/MAINTAINERS | 2 +- board/pine64/quartz64_rk3566/MAINTAINERS | 21 ++-------- board/pine64/quartzpro64-rk3588/MAINTAINERS | 3 +- board/radxa/rock5a-rk3588s/MAINTAINERS | 3 +- board/rockchip/evb_rk3328/MAINTAINERS | 14 ++----- board/rockchip/evb_rk3399/MAINTAINERS | 7 +--- board/rockchip/evb_rk3568/MAINTAINERS | 38 +++++++------------ board/rockchip/evb_rk3588/MAINTAINERS | 21 ++++------ board/rockchip/toybrick_rk3588/MAINTAINERS | 3 +- board/turing/turing-rk1-rk3588/MAINTAINERS | 4 +- .../orangepi-5-ultra-rk3588/MAINTAINERS | 2 +- 13 files changed, 37 insertions(+), 92 deletions(-) diff --git a/board/edgeble/neural-compute-module-6/MAINTAINERS b/board/edgeble/neural-compute-module-6/MAINTAINERS index 42e5df506bf..97d8c96ae62 100644 --- a/board/edgeble/neural-compute-module-6/MAINTAINERS +++ b/board/edgeble/neural-compute-module-6/MAINTAINERS @@ -5,9 +5,5 @@ F: board/edgeble/neural-compute-module-6 F: include/configs/neural-compute-module-6.h F: configs/neu6a-io-rk3588_defconfig F: configs/neu6b-io-rk3588_defconfig -F: arch/arm/dts/rk3588-edgeble-neu6a.dtsi -F: arch/arm/dts/rk3588-edgeble-neu6a-io.dts -F: arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi -F: arch/arm/dts/rk3588-edgeble-neu6b.dtsi -F: arch/arm/dts/rk3588-edgeble-neu6b-io.dts -F: arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi +F: arch/arm/dts/rk3588-edgeble-neu6a-io* +F: arch/arm/dts/rk3588-edgeble-neu6b-io* diff --git a/board/hardkernel/odroid_m1/MAINTAINERS b/board/hardkernel/odroid_m1/MAINTAINERS index 165d2d96741..8686a552d1c 100644 --- a/board/hardkernel/odroid_m1/MAINTAINERS +++ b/board/hardkernel/odroid_m1/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/hardkernel/odroid_m1/ F: include/configs/odroid_m1.h F: configs/odroid-m1-rk3568_defconfig -F: arch/arm/dts/rk3568-odroid-m1.dts -F: arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi +F: arch/arm/dts/rk3568-odroid-m1* diff --git a/board/khadas/khadas-edge2-rk3588s/MAINTAINERS b/board/khadas/khadas-edge2-rk3588s/MAINTAINERS index 3f16923b0f2..c43f469589d 100644 --- a/board/khadas/khadas-edge2-rk3588s/MAINTAINERS +++ b/board/khadas/khadas-edge2-rk3588s/MAINTAINERS @@ -3,4 +3,4 @@ M: Jacobe Zang S: Maintained F: configs/khadas-edge2-rk3588s_defconfig F: include/configs/khadas-edge2-rk3588s.h -F: dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts \ No newline at end of file +F: arch/arm/dts/rk3588s-khadas-edge2* diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 37b8c1eb78b..955cb5de030 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -9,26 +9,11 @@ F: configs/quartz64-b-rk3566_defconfig F: configs/soquartz-blade-rk3566_defconfig F: configs/soquartz-cm4-rk3566_defconfig F: configs/soquartz-model-a-rk3566_defconfig -F: arch/arm/dts/rk3566-quartz64-a.dts -F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi -F: arch/arm/dts/rk3566-quartz64-b.dts -F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz.dtsi -F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz-blade.dts -F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz-cm4.dts -F: arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz-model-a.dts -F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi +F: arch/arm/dts/rk3566-quartz64* +F: arch/arm/dts/rk3566-soquartz* PINETAB2-RK3566 M: Jonas Karlman S: Maintained F: configs/pinetab2-rk3566_defconfig -F: arch/arm/dts/rk3566-pinetab2.dtsi -F: arch/arm/dts/rk3566-pinetab2-u-boot.dtsi -F: arch/arm/dts/rk3566-pinetab2-v0.1.dts -F: arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi -F: arch/arm/dts/rk3566-pinetab2-v2.0.dts -F: arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi +F: arch/arm/dts/rk3566-pinetab2* diff --git a/board/pine64/quartzpro64-rk3588/MAINTAINERS b/board/pine64/quartzpro64-rk3588/MAINTAINERS index a7e944b7478..ff3500a32fc 100644 --- a/board/pine64/quartzpro64-rk3588/MAINTAINERS +++ b/board/pine64/quartzpro64-rk3588/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/pine64/quartzpro64-rk3588 F: include/configs/quartzpro64-rk3588.h F: configs/quartzpro64-rk3588_defconfig -F: arch/arm/dts/rk3588-quartzpro64.dts -F: arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi +F: arch/arm/dts/rk3588-quartzpro64* diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/rock5a-rk3588s/MAINTAINERS index afc9bf5706c..d4cd82139d5 100644 --- a/board/radxa/rock5a-rk3588s/MAINTAINERS +++ b/board/radxa/rock5a-rk3588s/MAINTAINERS @@ -5,5 +5,4 @@ S: Maintained F: board/radxa/rock5a-rk3588s F: include/configs/rock5a-rk3588s.h F: configs/rock5a-rk3588s_defconfig -F: arch/arm/dts/rk3588s-rock-5a.dts -F: arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +F: arch/arm/dts/rk3588s-rock-5a* diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 8c9b42fe2bb..d8748c1c2a2 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,8 +4,7 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig -F: arch/arm/dts/rk3328-evb.dts -F: arch/arm/dts/rk3328-evb-u-boot.dtsi +F: arch/arm/dts/rk3328-evb* GENERIC-RK3328 M: Jonas Karlman @@ -17,14 +16,12 @@ NANOPI-R2C-RK3328 M: Tianling Shen S: Maintained F: configs/nanopi-r2c-rk3328_defconfig -F: arch/arm/dts/rk3328-nanopi-r2c.dts F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi NANOPI-R2C-PLUS-RK3328 M: Tianling Shen S: Maintained F: configs/nanopi-r2c-plus-rk3328_defconfig -F: arch/arm/dts/rk3328-nanopi-r2c-plus.dts F: arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi NANOPI-R2S-RK3328 @@ -32,7 +29,6 @@ M: David Bauer S: Maintained F: configs/nanopi-r2s-rk3328_defconfig F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi -F: arch/arm/dts/rk3328-nanopi-r2s.dts NANOPI-R2S-PLUS-RK3328 M: Jonas Karlman @@ -44,14 +40,12 @@ ORANGEPI-R1-PLUS-RK3328 M: Tianling Shen S: Maintained F: configs/orangepi-r1-plus-rk3328_defconfig -F: arch/arm/dts/rk3328-orangepi-r1-plus.dts F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi ORANGEPI-R1-PLUS-LTS-RK3328 M: Tianling Shen S: Maintained F: configs/orangepi-r1-plus-lts-rk3328_defconfig -F: arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi ROC-RK3328-CC @@ -60,16 +54,14 @@ M: Chen-Yu Tsai R: Jonas Karlman S: Maintained F: configs/roc-cc-rk3328_defconfig -F: arch/arm/dts/rk3328-roc-cc.dts -F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +F: arch/arm/dts/rk3328-roc-cc* ROCK64-RK3328 M: Matwey V. Kornilov R: Jonas Karlman S: Maintained F: configs/rock64-rk3328_defconfig -F: arch/arm/dts/rk3328-rock64.dts -F: arch/arm/dts/rk3328-rock64-u-boot.dtsi +F: arch/arm/dts/rk3328-rock64* ROCKPIE-RK3328 M: Banglang Huang diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 8319db2e976..860dd028759 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -24,9 +24,7 @@ KHADAS-EDGE M: Nick Xie S: Maintained F: configs/khadas-edge-rk3399_defconfig -F: arch/arm/dts/rk3399-khadas-edge.dts -F: arch/arm/dts/rk3399-khadas-edge.dtsi -F: arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi +F: arch/arm/dts/rk3399-khadas-edge* KHADAS-EDGE-CAPTAIN M: Nick Xie @@ -56,8 +54,7 @@ NANOPI-M4 M: Jagan Teki S: Maintained F: configs/nanopi-m4-rk3399_defconfig -F: arch/arm/dts/rk3399-nanopi-m4.dts -F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi +F: arch/arm/dts/rk3399-nanopi-m4* NANOPI-M4-2GB M: Jagan Teki diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 030cdbe6f3d..7e17a6a987a 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -2,8 +2,7 @@ BANANAPI-BPI-R2-PRO M: Frank Wunderlich S: Maintained F: configs/bpi-r2-pro-rk3568_defconfig -F: arch/arm/dts/rk3568-bpi-r2-pro.dts -F: arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi +F: arch/arm/dts/rk3568-bpi-r2-pro* EVB-RK3568 M: Joseph Chen @@ -11,78 +10,67 @@ S: Maintained F: board/rockchip/evb_rk3568 F: include/configs/evb_rk3568.h F: configs/evb-rk3568_defconfig -F: arch/arm/dts/rk3568-evb-u-boot.dtsi -F: arch/arm/dts/rk3568-evb.dts +F: arch/arm/dts/rk3568-evb* FASTRHINO-R66S-RK3568 M: Tianling Shen R: Jonas Karlman S: Maintained F: configs/fastrhino-r66s-rk3568_defconfig -F: arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi +F: arch/arm/dts/rk3568-fastrhino-r66s* GENERIC-RK3568 M: Jonas Karlman S: Maintained F: configs/generic-rk3568_defconfig -F: arch/arm/dts/rk3568-generic.dts -F: arch/arm/dts/rk3568-generic-u-boot.dtsi +F: arch/arm/dts/rk3568-generic* LUBANCAT-2 M: Andy Yan S: Maintained F: configs/lubancat-2-rk3568_defconfig -F: arch/arm/dts/rk3568-lubancat-2.dts -F: arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi +F: arch/arm/dts/rk3568-lubancat-2* NANOPI-R3S M: Tianling Shen R: Jonas Karlman S: Maintained F: configs/nanopi-r3s-rk3566_defconfig -F: arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi +F: arch/arm/dts/rk3566-nanopi-r3s* NANOPI-R5C M: Tianling Shen R: Jonas Karlman S: Maintained F: configs/nanopi-r5c-rk3568_defconfig -F: arch/arm/dts/rk3568-nanopi-r5c.dts -F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi +F: arch/arm/dts/rk3568-nanopi-r5c* NANOPI-R5S M: Tianling Shen R: Jonas Karlman S: Maintained F: configs/nanopi-r5s-rk3568_defconfig -F: arch/arm/dts/rk3568-nanopi-r5s.dts -F: arch/arm/dts/rk3568-nanopi-r5s.dtsi -F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +F: arch/arm/dts/rk3568-nanopi-r5s* RADXA-CM3-IO M: Jagan Teki R: Jonas Karlman S: Maintained F: configs/radxa-cm3-io-rk3566_defconfig -F: arch/arm/dts/rk3566-radxa-cm3.dtsi -F: arch/arm/dts/rk3566-radxa-cm3-io.dts -F: arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +F: arch/arm/dts/rk3566-radxa-cm3-io* RADXA-E25 M: Jonas Karlman S: Maintained F: configs/radxa-e25-rk3568_defconfig -F: arch/arm/dts/rk3568-radxa-cm3i.dtsi -F: arch/arm/dts/rk3568-radxa-e25.dts -F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi +F: arch/arm/dts/rk3568-radxa-e25* ROCK-3A M: Akash Gajjar R: Jonas Karlman S: Maintained F: configs/rock-3a-rk3568_defconfig -F: arch/arm/dts/rk3568-rock-3a.dts -F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +F: arch/arm/dts/rk3568-rock-3a* ROCK-3B M: Jonas Karlman @@ -94,11 +82,11 @@ ROCK-3C M: Jonas Karlman M: Maxim Moskalets S: Maintained -F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi +F: arch/arm/dts/rk3566-rock-3c* F: configs/rock-3c-rk3566_defconfig LCKFB-TaishanPi M: Jiehui He S: Maintained F: configs/lckfb-tspi-rk3566_defconfig -F: arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi +F: arch/arm/dts/rk3566-lckfb-tspi* diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 8b11db43f5f..b64dd4947ee 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -2,16 +2,13 @@ COOLPI-4B-RK3588S M: Andy Yan S: Maintained F: configs/coolpi-4b-rk3588s_defconfig -F: arch/arm/dts/rk3588s-coolpi-4b.dts -F: arch/arm/dts/rk3588s-coolpi-u-boot.dtsi +F: arch/arm/dts/rk3588s-coolpi-4b* COOLPI-CM5-EVB-RK3588 M: Andy Yan S: Maintained F: configs/coolpi-cm5-evb-rk3588_defconfig -F: arch/arm/dts/rk3588-coolpi-cm5.dtsi -F: arch/arm/dts/rk3588-coolpi-cm5-evb.dts -F: arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi +F: arch/arm/dts/rk3588-coolpi-cm5-evb* EVB-RK3588 M: Kever Yang @@ -19,15 +16,13 @@ S: Maintained F: board/rockchip/evb_rk3588 F: include/configs/evb_rk3588.h F: configs/evb-rk3588_defconfig -F: arch/arm/dts/rk3588-evb1-v10.dts -F: arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi +F: arch/arm/dts/rk3588-evb1-v10* GENERIC-RK3588 M: Jonas Karlman S: Maintained F: configs/generic-rk3588_defconfig -F: arch/arm/dts/rk3588-generic.dts -F: arch/arm/dts/rk3588-generic-u-boot.dtsi +F: arch/arm/dts/rk3588-generic* MNT-REFORM2-RK3588 M: Peter Robinson @@ -38,24 +33,22 @@ ORANGEPI-5-RK3588 M: Jonas Karlman S: Maintained F: configs/orangepi-5-rk3588s_defconfig -F: arch/arm/dts/rk3588s-orangepi-5.dts F: arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi ORANGEPI-5-MAX-RK3588 M: Ilya Katsnelson S: Maintained F: configs/orangepi-5-max-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi +F: arch/arm/dts/rk3588-orangepi-5-max* ORANGEPI-5-PLUS-RK3588 M: Jonas Karlman S: Maintained F: configs/orangepi-5-plus-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-plus.dts -F: arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi +F: arch/arm/dts/rk3588-orangepi-5-plus* ORANGEPI-5-RK3588-ULTRA M: Niu Zhihong S: Maintained F: configs/orangepi-5-ultra-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi +F: arch/arm/dts/rk3588-orangepi-5-ultra* diff --git a/board/rockchip/toybrick_rk3588/MAINTAINERS b/board/rockchip/toybrick_rk3588/MAINTAINERS index cd4401c24f3..e2c76f80e9b 100644 --- a/board/rockchip/toybrick_rk3588/MAINTAINERS +++ b/board/rockchip/toybrick_rk3588/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/rockchip/toybrick_rk3588 F: include/configs/toybrick_rk3588.h F: configs/toybrick-rk3588_defconfig -F: arch/arm/dts/rk3588-toybrick-x0.dts -F: arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi +F: arch/arm/dts/rk3588-toybrick-x0* diff --git a/board/turing/turing-rk1-rk3588/MAINTAINERS b/board/turing/turing-rk1-rk3588/MAINTAINERS index 4f313732fa1..973ac68836c 100644 --- a/board/turing/turing-rk1-rk3588/MAINTAINERS +++ b/board/turing/turing-rk1-rk3588/MAINTAINERS @@ -4,6 +4,4 @@ S: Maintained F: board/turing/turing-rk1-rk3588 F: include/configs/turing-rk1-rk3588.h F: configs/turing-rk1-rk3588_defconfig -F: arch/arm/dts/rk3588-turing-rk1.dts -F: arch/arm/dts/rk3588-turing-rk1.dtsi -F: arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi +F: arch/arm/dts/rk3588-turing-rk1* diff --git a/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS index be9c93f6b9d..79981aa43f1 100644 --- a/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS +++ b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS @@ -3,4 +3,4 @@ M: Niu Zhihong S: Maintained F: board/xunlong/orangepi-5-rk3588-ultra F: configs/orangepi-5-ultra-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-ultra.dts +F: arch/arm/dts/rk3588-orangepi-5-ultra* From e126a99992aa323fc9d570c879a60e75c039ea04 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 3 Nov 2025 12:40:29 +0530 Subject: [PATCH 22/65] arm: dts: k3-j7200: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for J7200 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar Signed-off-by: Neha Malcom Francis --- ...66.dtsi => k3-j7200-ddr-evm-lp4-3200.dtsi} | 563 +++++++++--------- .../arm/dts/k3-j7200-r5-common-proc-board.dts | 2 +- 2 files changed, 288 insertions(+), 277 deletions(-) rename arch/arm/dts/{k3-j7200-ddr-evm-lp4-2666.dtsi => k3-j7200-ddr-evm-lp4-3200.dtsi} (87%) diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi similarity index 87% rename from arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi rename to arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi index f0683088cf6..810415494ce 100644 --- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi +++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi @@ -1,14 +1,22 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0 - * This file was generated on 06/01/2021 + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 13:11:41 GMT+0530 (India Standard Time) */ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 -#define DDRSS_PLL_FREQUENCY_1 666500000 -#define DDRSS_PLL_FREQUENCY_2 666500000 +#define DDRSS_PLL_FREQUENCY_1 800000000 +#define DDRSS_PLL_FREQUENCY_2 800000000 + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000000 +#define DDR_REG1_SIZE_LSB 0x80000000 + #define DDRSS_CTL_00_DATA 0x00000B00 #define DDRSS_CTL_01_DATA 0x00000000 @@ -21,16 +29,16 @@ #define DDRSS_CTL_08_DATA 0x0001ADAF #define DDRSS_CTL_09_DATA 0x00000005 #define DDRSS_CTL_10_DATA 0x0000006E -#define DDRSS_CTL_11_DATA 0x000411AB -#define DDRSS_CTL_12_DATA 0x0028B0AB +#define DDRSS_CTL_11_DATA 0x0004E200 +#define DDRSS_CTL_12_DATA 0x0030D400 #define DDRSS_CTL_13_DATA 0x00000005 -#define DDRSS_CTL_14_DATA 0x00000A6B -#define DDRSS_CTL_15_DATA 0x000411AB -#define DDRSS_CTL_16_DATA 0x0028B0AB +#define DDRSS_CTL_14_DATA 0x00000C80 +#define DDRSS_CTL_15_DATA 0x0004E200 +#define DDRSS_CTL_16_DATA 0x0030D400 #define DDRSS_CTL_17_DATA 0x00000005 -#define DDRSS_CTL_18_DATA 0x00000A6B +#define DDRSS_CTL_18_DATA 0x00000C80 #define DDRSS_CTL_19_DATA 0x01010000 -#define DDRSS_CTL_20_DATA 0x02011001 +#define DDRSS_CTL_20_DATA 0x01011001 #define DDRSS_CTL_21_DATA 0x02010000 #define DDRSS_CTL_22_DATA 0x00020100 #define DDRSS_CTL_23_DATA 0x0000000B @@ -38,66 +46,66 @@ #define DDRSS_CTL_25_DATA 0x00000000 #define DDRSS_CTL_26_DATA 0x00000000 #define DDRSS_CTL_27_DATA 0x03020200 -#define DDRSS_CTL_28_DATA 0x00003636 +#define DDRSS_CTL_28_DATA 0x00004040 #define DDRSS_CTL_29_DATA 0x00100000 #define DDRSS_CTL_30_DATA 0x00000000 #define DDRSS_CTL_31_DATA 0x00000000 #define DDRSS_CTL_32_DATA 0x00000000 #define DDRSS_CTL_33_DATA 0x00000000 #define DDRSS_CTL_34_DATA 0x040C0000 -#define DDRSS_CTL_35_DATA 0x0C300C30 +#define DDRSS_CTL_35_DATA 0x0E400E40 #define DDRSS_CTL_36_DATA 0x00050804 #define DDRSS_CTL_37_DATA 0x09040008 -#define DDRSS_CTL_38_DATA 0x0D000204 -#define DDRSS_CTL_39_DATA 0x113C0057 -#define DDRSS_CTL_40_DATA 0x0D00291B -#define DDRSS_CTL_41_DATA 0x113C0057 -#define DDRSS_CTL_42_DATA 0x2000291B +#define DDRSS_CTL_38_DATA 0x14000304 +#define DDRSS_CTL_39_DATA 0x15480068 +#define DDRSS_CTL_40_DATA 0x14004220 +#define DDRSS_CTL_41_DATA 0x15480068 +#define DDRSS_CTL_42_DATA 0x20004220 #define DDRSS_CTL_43_DATA 0x000A0A09 -#define DDRSS_CTL_44_DATA 0x0400078A -#define DDRSS_CTL_45_DATA 0x130E0B04 -#define DDRSS_CTL_46_DATA 0x0A00B6D0 -#define DDRSS_CTL_47_DATA 0x130E0B0A -#define DDRSS_CTL_48_DATA 0x0A00B6D0 -#define DDRSS_CTL_49_DATA 0x0203040A -#define DDRSS_CTL_50_DATA 0x1C040500 -#define DDRSS_CTL_51_DATA 0x081D1C1D +#define DDRSS_CTL_44_DATA 0x040003C5 +#define DDRSS_CTL_45_DATA 0x17100D04 +#define DDRSS_CTL_46_DATA 0x0C006DB0 +#define DDRSS_CTL_47_DATA 0x17100D0C +#define DDRSS_CTL_48_DATA 0x0C006DB0 +#define DDRSS_CTL_49_DATA 0x0203040C +#define DDRSS_CTL_50_DATA 0x21060500 +#define DDRSS_CTL_51_DATA 0x08222122 #define DDRSS_CTL_52_DATA 0x14000E0A -#define DDRSS_CTL_53_DATA 0x02010A0A -#define DDRSS_CTL_54_DATA 0x01010002 -#define DDRSS_CTL_55_DATA 0x04383808 -#define DDRSS_CTL_56_DATA 0x041F1F04 -#define DDRSS_CTL_57_DATA 0x00001F1F +#define DDRSS_CTL_53_DATA 0x03010A0A +#define DDRSS_CTL_54_DATA 0x01010003 +#define DDRSS_CTL_55_DATA 0x0442420A +#define DDRSS_CTL_56_DATA 0x04252504 +#define DDRSS_CTL_57_DATA 0x00002525 #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 #define DDRSS_CTL_60_DATA 0x00001008 -#define DDRSS_CTL_61_DATA 0x000000CE -#define DDRSS_CTL_62_DATA 0x00000176 -#define DDRSS_CTL_63_DATA 0x00001448 -#define DDRSS_CTL_64_DATA 0x00000176 -#define DDRSS_CTL_65_DATA 0x00001448 +#define DDRSS_CTL_61_DATA 0x00000068 +#define DDRSS_CTL_62_DATA 0x000001C0 +#define DDRSS_CTL_63_DATA 0x00000C28 +#define DDRSS_CTL_64_DATA 0x000001C0 +#define DDRSS_CTL_65_DATA 0x00000C28 #define DDRSS_CTL_66_DATA 0x00000005 #define DDRSS_CTL_67_DATA 0x00040000 -#define DDRSS_CTL_68_DATA 0x005D0012 -#define DDRSS_CTL_69_DATA 0x005D0282 -#define DDRSS_CTL_70_DATA 0x00400282 +#define DDRSS_CTL_68_DATA 0x00700005 +#define DDRSS_CTL_69_DATA 0x0070017E +#define DDRSS_CTL_70_DATA 0x0040017E #define DDRSS_CTL_71_DATA 0x00120103 -#define DDRSS_CTL_72_DATA 0x000A0005 -#define DDRSS_CTL_73_DATA 0x1F08000A -#define DDRSS_CTL_74_DATA 0x0505011F +#define DDRSS_CTL_72_DATA 0x000C0005 +#define DDRSS_CTL_73_DATA 0x2408000C +#define DDRSS_CTL_74_DATA 0x05050124 #define DDRSS_CTL_75_DATA 0x0301030A -#define DDRSS_CTL_76_DATA 0x03130A07 -#define DDRSS_CTL_77_DATA 0x0A070301 -#define DDRSS_CTL_78_DATA 0x00010313 +#define DDRSS_CTL_76_DATA 0x03170C08 +#define DDRSS_CTL_77_DATA 0x0C080301 +#define DDRSS_CTL_78_DATA 0x00010317 #define DDRSS_CTL_79_DATA 0x00100010 -#define DDRSS_CTL_80_DATA 0x01800180 -#define DDRSS_CTL_81_DATA 0x01800180 +#define DDRSS_CTL_80_DATA 0x01CC01CC +#define DDRSS_CTL_81_DATA 0x01CC01CC #define DDRSS_CTL_82_DATA 0x03050505 #define DDRSS_CTL_83_DATA 0x03010303 -#define DDRSS_CTL_84_DATA 0x14070A07 -#define DDRSS_CTL_85_DATA 0x03030A03 -#define DDRSS_CTL_86_DATA 0x14070A07 -#define DDRSS_CTL_87_DATA 0x03030A03 +#define DDRSS_CTL_84_DATA 0x18080C08 +#define DDRSS_CTL_85_DATA 0x03030C03 +#define DDRSS_CTL_86_DATA 0x18080C08 +#define DDRSS_CTL_87_DATA 0x03030C03 #define DDRSS_CTL_88_DATA 0x03010000 #define DDRSS_CTL_89_DATA 0x00010000 #define DDRSS_CTL_90_DATA 0x00000000 @@ -112,27 +120,27 @@ #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x00040005 #define DDRSS_CTL_101_DATA 0x00000000 -#define DDRSS_CTL_102_DATA 0x00003380 -#define DDRSS_CTL_103_DATA 0x00003380 -#define DDRSS_CTL_104_DATA 0x00003380 -#define DDRSS_CTL_105_DATA 0x00003380 -#define DDRSS_CTL_106_DATA 0x00003380 +#define DDRSS_CTL_102_DATA 0x000018C0 +#define DDRSS_CTL_103_DATA 0x000018C0 +#define DDRSS_CTL_104_DATA 0x000018C0 +#define DDRSS_CTL_105_DATA 0x000018C0 +#define DDRSS_CTL_106_DATA 0x000018C0 #define DDRSS_CTL_107_DATA 0x00000000 -#define DDRSS_CTL_108_DATA 0x000005A2 -#define DDRSS_CTL_109_DATA 0x00051200 -#define DDRSS_CTL_110_DATA 0x00051200 -#define DDRSS_CTL_111_DATA 0x00051200 -#define DDRSS_CTL_112_DATA 0x00051200 -#define DDRSS_CTL_113_DATA 0x00051200 +#define DDRSS_CTL_108_DATA 0x000002B5 +#define DDRSS_CTL_109_DATA 0x00030A00 +#define DDRSS_CTL_110_DATA 0x00030A00 +#define DDRSS_CTL_111_DATA 0x00030A00 +#define DDRSS_CTL_112_DATA 0x00030A00 +#define DDRSS_CTL_113_DATA 0x00030A00 #define DDRSS_CTL_114_DATA 0x00000000 -#define DDRSS_CTL_115_DATA 0x00008DF8 -#define DDRSS_CTL_116_DATA 0x00051200 -#define DDRSS_CTL_117_DATA 0x00051200 -#define DDRSS_CTL_118_DATA 0x00051200 -#define DDRSS_CTL_119_DATA 0x00051200 -#define DDRSS_CTL_120_DATA 0x00051200 +#define DDRSS_CTL_115_DATA 0x00005518 +#define DDRSS_CTL_116_DATA 0x00030A00 +#define DDRSS_CTL_117_DATA 0x00030A00 +#define DDRSS_CTL_118_DATA 0x00030A00 +#define DDRSS_CTL_119_DATA 0x00030A00 +#define DDRSS_CTL_120_DATA 0x00030A00 #define DDRSS_CTL_121_DATA 0x00000000 -#define DDRSS_CTL_122_DATA 0x00008DF8 +#define DDRSS_CTL_122_DATA 0x00005518 #define DDRSS_CTL_123_DATA 0x00000000 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x00000000 @@ -141,8 +149,8 @@ #define DDRSS_CTL_128_DATA 0x00000000 #define DDRSS_CTL_129_DATA 0x00000000 #define DDRSS_CTL_130_DATA 0x00000000 -#define DDRSS_CTL_131_DATA 0x07030500 -#define DDRSS_CTL_132_DATA 0x00030703 +#define DDRSS_CTL_131_DATA 0x08030500 +#define DDRSS_CTL_132_DATA 0x00030803 #define DDRSS_CTL_133_DATA 0x0A090000 #define DDRSS_CTL_134_DATA 0x0A090701 #define DDRSS_CTL_135_DATA 0x0900000E @@ -177,31 +185,31 @@ #define DDRSS_CTL_164_DATA 0x000B0000 #define DDRSS_CTL_165_DATA 0x000E0006 #define DDRSS_CTL_166_DATA 0x000E0404 -#define DDRSS_CTL_167_DATA 0x0086010B -#define DDRSS_CTL_168_DATA 0x0A0A014E -#define DDRSS_CTL_169_DATA 0x010B014E -#define DDRSS_CTL_170_DATA 0x014E0086 -#define DDRSS_CTL_171_DATA 0x014E0A0A +#define DDRSS_CTL_167_DATA 0x00A00140 +#define DDRSS_CTL_168_DATA 0x0C0C0190 +#define DDRSS_CTL_169_DATA 0x01400190 +#define DDRSS_CTL_170_DATA 0x019000A0 +#define DDRSS_CTL_171_DATA 0x01900C0C #define DDRSS_CTL_172_DATA 0x00000000 #define DDRSS_CTL_173_DATA 0x00000000 #define DDRSS_CTL_174_DATA 0x00000000 -#define DDRSS_CTL_175_DATA 0x24C40084 -#define DDRSS_CTL_176_DATA 0x2B0024C4 -#define DDRSS_CTL_177_DATA 0x00002B2B +#define DDRSS_CTL_175_DATA 0x2DD40084 +#define DDRSS_CTL_176_DATA 0xEB002DD4 +#define DDRSS_CTL_177_DATA 0x0000EBEB #define DDRSS_CTL_178_DATA 0x36000000 #define DDRSS_CTL_179_DATA 0x27270036 #define DDRSS_CTL_180_DATA 0x0F0F0000 #define DDRSS_CTL_181_DATA 0x15000000 #define DDRSS_CTL_182_DATA 0x00841515 -#define DDRSS_CTL_183_DATA 0x24C424C4 -#define DDRSS_CTL_184_DATA 0x2B2B2B00 +#define DDRSS_CTL_183_DATA 0x2DD42DD4 +#define DDRSS_CTL_184_DATA 0xEBEBEB00 #define DDRSS_CTL_185_DATA 0x00000000 #define DDRSS_CTL_186_DATA 0x00363600 #define DDRSS_CTL_187_DATA 0x00002727 #define DDRSS_CTL_188_DATA 0x00000F0F #define DDRSS_CTL_189_DATA 0x15151500 #define DDRSS_CTL_190_DATA 0x00000020 -#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x01000000 #define DDRSS_CTL_192_DATA 0x00000001 #define DDRSS_CTL_193_DATA 0x00000000 #define DDRSS_CTL_194_DATA 0x01000000 @@ -239,17 +247,17 @@ #define DDRSS_CTL_226_DATA 0x00000000 #define DDRSS_CTL_227_DATA 0x15110000 #define DDRSS_CTL_228_DATA 0x00040C18 -#define DDRSS_CTL_229_DATA 0x00000000 -#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_229_DATA 0xF000C000 +#define DDRSS_CTL_230_DATA 0x0000F000 #define DDRSS_CTL_231_DATA 0x00000000 #define DDRSS_CTL_232_DATA 0x00000000 -#define DDRSS_CTL_233_DATA 0x00000000 -#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0xC0000000 +#define DDRSS_CTL_234_DATA 0xF000F000 #define DDRSS_CTL_235_DATA 0x00000000 #define DDRSS_CTL_236_DATA 0x00000000 #define DDRSS_CTL_237_DATA 0x00000000 -#define DDRSS_CTL_238_DATA 0x00000000 -#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0xF000C000 +#define DDRSS_CTL_239_DATA 0x0000F000 #define DDRSS_CTL_240_DATA 0x00000000 #define DDRSS_CTL_241_DATA 0x00000000 #define DDRSS_CTL_242_DATA 0x00030000 @@ -271,13 +279,13 @@ #define DDRSS_CTL_258_DATA 0x00370040 #define DDRSS_CTL_259_DATA 0x00020008 #define DDRSS_CTL_260_DATA 0x00400100 -#define DDRSS_CTL_261_DATA 0x00280536 +#define DDRSS_CTL_261_DATA 0x00300640 #define DDRSS_CTL_262_DATA 0x01000200 -#define DDRSS_CTL_263_DATA 0x05360040 -#define DDRSS_CTL_264_DATA 0x00000028 -#define DDRSS_CTL_265_DATA 0x00430003 -#define DDRSS_CTL_266_DATA 0x01000043 -#define DDRSS_CTL_267_DATA 0x00000000 +#define DDRSS_CTL_263_DATA 0x06400040 +#define DDRSS_CTL_264_DATA 0x00000030 +#define DDRSS_CTL_265_DATA 0x00500003 +#define DDRSS_CTL_266_DATA 0x01000050 +#define DDRSS_CTL_267_DATA 0x03030303 #define DDRSS_CTL_268_DATA 0x01010000 #define DDRSS_CTL_269_DATA 0x00000202 #define DDRSS_CTL_270_DATA 0x00000FFF @@ -301,14 +309,14 @@ #define DDRSS_CTL_288_DATA 0x00000000 #define DDRSS_CTL_289_DATA 0x00000000 #define DDRSS_CTL_290_DATA 0x03030300 -#define DDRSS_CTL_291_DATA 0x00000001 +#define DDRSS_CTL_291_DATA 0x00010101 #define DDRSS_CTL_292_DATA 0x00000000 #define DDRSS_CTL_293_DATA 0x00000000 #define DDRSS_CTL_294_DATA 0x00000000 #define DDRSS_CTL_295_DATA 0x00000000 #define DDRSS_CTL_296_DATA 0x00000000 -#define DDRSS_CTL_297_DATA 0x00000000 -#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0xFFFFFFFF +#define DDRSS_CTL_298_DATA 0x00000FFF #define DDRSS_CTL_299_DATA 0x00000000 #define DDRSS_CTL_300_DATA 0x00000000 #define DDRSS_CTL_301_DATA 0x00000000 @@ -328,15 +336,15 @@ #define DDRSS_CTL_315_DATA 0x01000101 #define DDRSS_CTL_316_DATA 0x01010001 #define DDRSS_CTL_317_DATA 0x00010101 -#define DDRSS_CTL_318_DATA 0x05070703 -#define DDRSS_CTL_319_DATA 0x0A081414 -#define DDRSS_CTL_320_DATA 0x0009030A -#define DDRSS_CTL_321_DATA 0x080C030F -#define DDRSS_CTL_322_DATA 0x080C0306 -#define DDRSS_CTL_323_DATA 0x0C090006 -#define DDRSS_CTL_324_DATA 0x0100000C -#define DDRSS_CTL_325_DATA 0x05020501 -#define DDRSS_CTL_326_DATA 0x00000002 +#define DDRSS_CTL_318_DATA 0x05080803 +#define DDRSS_CTL_319_DATA 0x0C081C1C +#define DDRSS_CTL_320_DATA 0x0009030C +#define DDRSS_CTL_321_DATA 0x090B030F +#define DDRSS_CTL_322_DATA 0x090B0306 +#define DDRSS_CTL_323_DATA 0x0B090006 +#define DDRSS_CTL_324_DATA 0x0100000B +#define DDRSS_CTL_325_DATA 0x06030601 +#define DDRSS_CTL_326_DATA 0x00000003 #define DDRSS_CTL_327_DATA 0x00000000 #define DDRSS_CTL_328_DATA 0x00010000 #define DDRSS_CTL_329_DATA 0x00280D00 @@ -397,32 +405,32 @@ #define DDRSS_CTL_384_DATA 0x00000000 #define DDRSS_CTL_385_DATA 0x00000000 #define DDRSS_CTL_386_DATA 0x00000000 -#define DDRSS_CTL_387_DATA 0x2E2E1B00 +#define DDRSS_CTL_387_DATA 0x33331B00 #define DDRSS_CTL_388_DATA 0x000A0000 -#define DDRSS_CTL_389_DATA 0x0000019C +#define DDRSS_CTL_389_DATA 0x000000C6 #define DDRSS_CTL_390_DATA 0x00000200 #define DDRSS_CTL_391_DATA 0x00000200 #define DDRSS_CTL_392_DATA 0x00000200 #define DDRSS_CTL_393_DATA 0x00000200 -#define DDRSS_CTL_394_DATA 0x000004D4 -#define DDRSS_CTL_395_DATA 0x00001018 +#define DDRSS_CTL_394_DATA 0x00000270 +#define DDRSS_CTL_395_DATA 0x000007BC #define DDRSS_CTL_396_DATA 0x00000204 -#define DDRSS_CTL_397_DATA 0x00002890 +#define DDRSS_CTL_397_DATA 0x00001850 #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x00000200 #define DDRSS_CTL_400_DATA 0x00000200 #define DDRSS_CTL_401_DATA 0x00000200 -#define DDRSS_CTL_402_DATA 0x000079B0 -#define DDRSS_CTL_403_DATA 0x000195A0 -#define DDRSS_CTL_404_DATA 0x0000080E -#define DDRSS_CTL_405_DATA 0x00002890 +#define DDRSS_CTL_402_DATA 0x000048F0 +#define DDRSS_CTL_403_DATA 0x0000F320 +#define DDRSS_CTL_404_DATA 0x00000A14 +#define DDRSS_CTL_405_DATA 0x00001850 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 #define DDRSS_CTL_409_DATA 0x00000200 -#define DDRSS_CTL_410_DATA 0x000079B0 -#define DDRSS_CTL_411_DATA 0x000195A0 -#define DDRSS_CTL_412_DATA 0x0202080E +#define DDRSS_CTL_410_DATA 0x000048F0 +#define DDRSS_CTL_411_DATA 0x0000F320 +#define DDRSS_CTL_412_DATA 0x02020A14 #define DDRSS_CTL_413_DATA 0x03030202 #define DDRSS_CTL_414_DATA 0x00000022 #define DDRSS_CTL_415_DATA 0x00000000 @@ -433,13 +441,13 @@ #define DDRSS_CTL_420_DATA 0x00000000 #define DDRSS_CTL_421_DATA 0x00030000 #define DDRSS_CTL_422_DATA 0x0007001F -#define DDRSS_CTL_423_DATA 0x0013002B -#define DDRSS_CTL_424_DATA 0x0013002B +#define DDRSS_CTL_423_DATA 0x0016002E +#define DDRSS_CTL_424_DATA 0x0016002E #define DDRSS_CTL_425_DATA 0x00000000 #define DDRSS_CTL_426_DATA 0x00000000 #define DDRSS_CTL_427_DATA 0x02000000 #define DDRSS_CTL_428_DATA 0x01000404 -#define DDRSS_CTL_429_DATA 0x05120512 +#define DDRSS_CTL_429_DATA 0x071A071A #define DDRSS_CTL_430_DATA 0x00000105 #define DDRSS_CTL_431_DATA 0x00010101 #define DDRSS_CTL_432_DATA 0x00010101 @@ -448,8 +456,8 @@ #define DDRSS_CTL_435_DATA 0x02000201 #define DDRSS_CTL_436_DATA 0x02010000 #define DDRSS_CTL_437_DATA 0x00000200 -#define DDRSS_CTL_438_DATA 0x18060000 -#define DDRSS_CTL_439_DATA 0x00000118 +#define DDRSS_CTL_438_DATA 0x1E060000 +#define DDRSS_CTL_439_DATA 0x0000011E #define DDRSS_CTL_440_DATA 0xFFFFFFFF #define DDRSS_CTL_441_DATA 0xFFFFFFFF #define DDRSS_CTL_442_DATA 0x00000000 @@ -482,8 +490,8 @@ #define DDRSS_PI_09_DATA 0x00000000 #define DDRSS_PI_10_DATA 0x00000000 #define DDRSS_PI_11_DATA 0x00000000 -#define DDRSS_PI_12_DATA 0x00000007 -#define DDRSS_PI_13_DATA 0x00010002 +#define DDRSS_PI_12_DATA 0x00000003 +#define DDRSS_PI_13_DATA 0x00010001 #define DDRSS_PI_14_DATA 0x0800000F #define DDRSS_PI_15_DATA 0x00000103 #define DDRSS_PI_16_DATA 0x00000005 @@ -516,7 +524,7 @@ #define DDRSS_PI_43_DATA 0x00000000 #define DDRSS_PI_44_DATA 0x00000000 #define DDRSS_PI_45_DATA 0x000F0F00 -#define DDRSS_PI_46_DATA 0x00000017 +#define DDRSS_PI_46_DATA 0x00000019 #define DDRSS_PI_47_DATA 0x000007D0 #define DDRSS_PI_48_DATA 0x00000300 #define DDRSS_PI_49_DATA 0x00000000 @@ -531,18 +539,18 @@ #define DDRSS_PI_58_DATA 0x00000000 #define DDRSS_PI_59_DATA 0x00000000 #define DDRSS_PI_60_DATA 0x0A0A140A -#define DDRSS_PI_61_DATA 0x10020101 +#define DDRSS_PI_61_DATA 0x10020201 #define DDRSS_PI_62_DATA 0x00020805 #define DDRSS_PI_63_DATA 0x01000404 #define DDRSS_PI_64_DATA 0x00000000 #define DDRSS_PI_65_DATA 0x00000000 -#define DDRSS_PI_66_DATA 0x00000100 -#define DDRSS_PI_67_DATA 0x0001010F +#define DDRSS_PI_66_DATA 0x01000100 +#define DDRSS_PI_67_DATA 0x0102020F #define DDRSS_PI_68_DATA 0x00340000 #define DDRSS_PI_69_DATA 0x00000000 #define DDRSS_PI_70_DATA 0x00000000 #define DDRSS_PI_71_DATA 0x0000FFFF -#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_72_DATA 0x01000000 #define DDRSS_PI_73_DATA 0x00080100 #define DDRSS_PI_74_DATA 0x02000200 #define DDRSS_PI_75_DATA 0x01000100 @@ -631,104 +639,104 @@ #define DDRSS_PI_158_DATA 0x00000000 #define DDRSS_PI_159_DATA 0x00000401 #define DDRSS_PI_160_DATA 0x00000000 -#define DDRSS_PI_161_DATA 0x00010000 -#define DDRSS_PI_162_DATA 0x00000000 -#define DDRSS_PI_163_DATA 0x1B1B0200 +#define DDRSS_PI_161_DATA 0x05010000 +#define DDRSS_PI_162_DATA 0x00000001 +#define DDRSS_PI_163_DATA 0x20200201 #define DDRSS_PI_164_DATA 0x00000034 -#define DDRSS_PI_165_DATA 0x00000051 -#define DDRSS_PI_166_DATA 0x00020051 +#define DDRSS_PI_165_DATA 0x0000005C +#define DDRSS_PI_166_DATA 0x0002005C #define DDRSS_PI_167_DATA 0x02000200 -#define DDRSS_PI_168_DATA 0x300C0C04 -#define DDRSS_PI_169_DATA 0x0010300C -#define DDRSS_PI_170_DATA 0x000000CE -#define DDRSS_PI_171_DATA 0x00000176 -#define DDRSS_PI_172_DATA 0x00001448 -#define DDRSS_PI_173_DATA 0x00000176 -#define DDRSS_PI_174_DATA 0x04001448 +#define DDRSS_PI_168_DATA 0x400E0C04 +#define DDRSS_PI_169_DATA 0x0010400E +#define DDRSS_PI_170_DATA 0x00000068 +#define DDRSS_PI_171_DATA 0x000001C0 +#define DDRSS_PI_172_DATA 0x00000C28 +#define DDRSS_PI_173_DATA 0x000001C0 +#define DDRSS_PI_174_DATA 0x04000C28 #define DDRSS_PI_175_DATA 0x01010404 -#define DDRSS_PI_176_DATA 0x00001501 +#define DDRSS_PI_176_DATA 0x00001500 #define DDRSS_PI_177_DATA 0x00150015 #define DDRSS_PI_178_DATA 0x01000100 #define DDRSS_PI_179_DATA 0x00000100 #define DDRSS_PI_180_DATA 0x00000000 #define DDRSS_PI_181_DATA 0x01010101 -#define DDRSS_PI_182_DATA 0x00000101 -#define DDRSS_PI_183_DATA 0x00000100 -#define DDRSS_PI_184_DATA 0x00000100 -#define DDRSS_PI_185_DATA 0x0E040100 -#define DDRSS_PI_186_DATA 0x0808020E +#define DDRSS_PI_182_DATA 0x00010000 +#define DDRSS_PI_183_DATA 0x00010100 +#define DDRSS_PI_184_DATA 0x00010100 +#define DDRSS_PI_185_DATA 0x14040100 +#define DDRSS_PI_186_DATA 0x0A0A0214 #define DDRSS_PI_187_DATA 0x00040402 #define DDRSS_PI_188_DATA 0x000D0035 -#define DDRSS_PI_189_DATA 0x00198041 -#define DDRSS_PI_190_DATA 0x00198041 -#define DDRSS_PI_191_DATA 0x01010101 -#define DDRSS_PI_192_DATA 0x0002000E -#define DDRSS_PI_193_DATA 0x0002014E -#define DDRSS_PI_194_DATA 0x0100014E +#define DDRSS_PI_189_DATA 0x001C0044 +#define DDRSS_PI_190_DATA 0x001C0044 +#define DDRSS_PI_191_DATA 0x01000101 +#define DDRSS_PI_192_DATA 0x0003000E +#define DDRSS_PI_193_DATA 0x00030190 +#define DDRSS_PI_194_DATA 0x01000190 #define DDRSS_PI_195_DATA 0x000F000F -#define DDRSS_PI_196_DATA 0x014F0100 -#define DDRSS_PI_197_DATA 0x0100014F -#define DDRSS_PI_198_DATA 0x014F014F -#define DDRSS_PI_199_DATA 0x32103200 -#define DDRSS_PI_200_DATA 0x01013210 +#define DDRSS_PI_196_DATA 0x01910100 +#define DDRSS_PI_197_DATA 0x01000191 +#define DDRSS_PI_198_DATA 0x01910191 +#define DDRSS_PI_199_DATA 0x2F1B3200 +#define DDRSS_PI_200_DATA 0x01012F1B #define DDRSS_PI_201_DATA 0x0A070601 -#define DDRSS_PI_202_DATA 0x140D080D -#define DDRSS_PI_203_DATA 0x140D0810 -#define DDRSS_PI_204_DATA 0x0000C010 +#define DDRSS_PI_202_DATA 0x180F090D +#define DDRSS_PI_203_DATA 0x180F0911 +#define DDRSS_PI_204_DATA 0x0000C011 #define DDRSS_PI_205_DATA 0x00C01000 #define DDRSS_PI_206_DATA 0x00C01000 #define DDRSS_PI_207_DATA 0x00021000 -#define DDRSS_PI_208_DATA 0x001C000E -#define DDRSS_PI_209_DATA 0x001C014E -#define DDRSS_PI_210_DATA 0x0011014E +#define DDRSS_PI_208_DATA 0x001E000E +#define DDRSS_PI_209_DATA 0x001E0190 +#define DDRSS_PI_210_DATA 0x00110190 #define DDRSS_PI_211_DATA 0x32000056 -#define DDRSS_PI_212_DATA 0x00000301 -#define DDRSS_PI_213_DATA 0x005A002A +#define DDRSS_PI_212_DATA 0x00000101 +#define DDRSS_PI_213_DATA 0x005E0030 #define DDRSS_PI_214_DATA 0x03013212 -#define DDRSS_PI_215_DATA 0x00002A00 -#define DDRSS_PI_216_DATA 0x3212005A -#define DDRSS_PI_217_DATA 0x09000301 -#define DDRSS_PI_218_DATA 0x04010504 -#define DDRSS_PI_219_DATA 0x040006C9 +#define DDRSS_PI_215_DATA 0x00003000 +#define DDRSS_PI_216_DATA 0x3212005E +#define DDRSS_PI_217_DATA 0x09000001 +#define DDRSS_PI_218_DATA 0x06010504 +#define DDRSS_PI_219_DATA 0x04000364 #define DDRSS_PI_220_DATA 0x0A032001 -#define DDRSS_PI_221_DATA 0x1C1F0B0A -#define DDRSS_PI_222_DATA 0x00001D12 -#define DDRSS_PI_223_DATA 0x3C00A488 -#define DDRSS_PI_224_DATA 0x13142005 -#define DDRSS_PI_225_DATA 0x1C1F0B0E -#define DDRSS_PI_226_DATA 0x00001D12 -#define DDRSS_PI_227_DATA 0x3C00A488 -#define DDRSS_PI_228_DATA 0x13142005 -#define DDRSS_PI_229_DATA 0x00019C0E -#define DDRSS_PI_230_DATA 0x00001018 -#define DDRSS_PI_231_DATA 0x00002890 -#define DDRSS_PI_232_DATA 0x000195A0 -#define DDRSS_PI_233_DATA 0x00002890 -#define DDRSS_PI_234_DATA 0x000195A0 -#define DDRSS_PI_235_DATA 0x01800010 -#define DDRSS_PI_236_DATA 0x03030180 +#define DDRSS_PI_221_DATA 0x21250D0A +#define DDRSS_PI_222_DATA 0x00002216 +#define DDRSS_PI_223_DATA 0x480062B8 +#define DDRSS_PI_224_DATA 0x17182006 +#define DDRSS_PI_225_DATA 0x21250D10 +#define DDRSS_PI_226_DATA 0x00002216 +#define DDRSS_PI_227_DATA 0x480062B8 +#define DDRSS_PI_228_DATA 0x17182006 +#define DDRSS_PI_229_DATA 0x0000C610 +#define DDRSS_PI_230_DATA 0x000007BC +#define DDRSS_PI_231_DATA 0x00001850 +#define DDRSS_PI_232_DATA 0x0000F320 +#define DDRSS_PI_233_DATA 0x00001850 +#define DDRSS_PI_234_DATA 0x0000F320 +#define DDRSS_PI_235_DATA 0x01CC0010 +#define DDRSS_PI_236_DATA 0x030301CC #define DDRSS_PI_237_DATA 0x002AF803 #define DDRSS_PI_238_DATA 0x0001ADAF #define DDRSS_PI_239_DATA 0x00000005 #define DDRSS_PI_240_DATA 0x0000006E #define DDRSS_PI_241_DATA 0x00000010 -#define DDRSS_PI_242_DATA 0x000411AB +#define DDRSS_PI_242_DATA 0x0004E200 #define DDRSS_PI_243_DATA 0x0001ADAF #define DDRSS_PI_244_DATA 0x00000005 -#define DDRSS_PI_245_DATA 0x00000A6B -#define DDRSS_PI_246_DATA 0x00000180 -#define DDRSS_PI_247_DATA 0x000411AB +#define DDRSS_PI_245_DATA 0x00000C80 +#define DDRSS_PI_246_DATA 0x000001CC +#define DDRSS_PI_247_DATA 0x0004E200 #define DDRSS_PI_248_DATA 0x0001ADAF #define DDRSS_PI_249_DATA 0x00000005 -#define DDRSS_PI_250_DATA 0x00000A6B -#define DDRSS_PI_251_DATA 0x01000180 +#define DDRSS_PI_250_DATA 0x00000C80 +#define DDRSS_PI_251_DATA 0x010001CC #define DDRSS_PI_252_DATA 0x00370040 #define DDRSS_PI_253_DATA 0x00010008 -#define DDRSS_PI_254_DATA 0x05360040 -#define DDRSS_PI_255_DATA 0x00010028 -#define DDRSS_PI_256_DATA 0x05360040 -#define DDRSS_PI_257_DATA 0x00000328 -#define DDRSS_PI_258_DATA 0x00430043 +#define DDRSS_PI_254_DATA 0x06400040 +#define DDRSS_PI_255_DATA 0x00010030 +#define DDRSS_PI_256_DATA 0x06400040 +#define DDRSS_PI_257_DATA 0x00000330 +#define DDRSS_PI_258_DATA 0x00500050 #define DDRSS_PI_259_DATA 0x08040404 #define DDRSS_PI_260_DATA 0x00000055 #define DDRSS_PI_261_DATA 0x55083C5A @@ -745,29 +753,29 @@ #define DDRSS_PI_272_DATA 0x00080804 #define DDRSS_PI_273_DATA 0x00000000 #define DDRSS_PI_274_DATA 0x00000000 -#define DDRSS_PI_275_DATA 0x002B0084 +#define DDRSS_PI_275_DATA 0x00EB0084 #define DDRSS_PI_276_DATA 0x00150000 -#define DDRSS_PI_277_DATA 0x362B24C4 +#define DDRSS_PI_277_DATA 0x36EB2DD4 #define DDRSS_PI_278_DATA 0x00150F27 -#define DDRSS_PI_279_DATA 0x362B24C4 +#define DDRSS_PI_279_DATA 0x36EB2DD4 #define DDRSS_PI_280_DATA 0x00150F27 -#define DDRSS_PI_281_DATA 0x002B0084 +#define DDRSS_PI_281_DATA 0x00EB0084 #define DDRSS_PI_282_DATA 0x00150000 -#define DDRSS_PI_283_DATA 0x362B24C4 +#define DDRSS_PI_283_DATA 0x36EB2DD4 #define DDRSS_PI_284_DATA 0x00150F27 -#define DDRSS_PI_285_DATA 0x362B24C4 +#define DDRSS_PI_285_DATA 0x36EB2DD4 #define DDRSS_PI_286_DATA 0x00150F27 -#define DDRSS_PI_287_DATA 0x002B0084 +#define DDRSS_PI_287_DATA 0x00EB0084 #define DDRSS_PI_288_DATA 0x00150000 -#define DDRSS_PI_289_DATA 0x362B24C4 +#define DDRSS_PI_289_DATA 0x36EB2DD4 #define DDRSS_PI_290_DATA 0x00150F27 -#define DDRSS_PI_291_DATA 0x362B24C4 +#define DDRSS_PI_291_DATA 0x36EB2DD4 #define DDRSS_PI_292_DATA 0x00150F27 -#define DDRSS_PI_293_DATA 0x002B0084 +#define DDRSS_PI_293_DATA 0x00EB0084 #define DDRSS_PI_294_DATA 0x00150000 -#define DDRSS_PI_295_DATA 0x362B24C4 +#define DDRSS_PI_295_DATA 0x36EB2DD4 #define DDRSS_PI_296_DATA 0x00150F27 -#define DDRSS_PI_297_DATA 0x362B24C4 +#define DDRSS_PI_297_DATA 0x36EB2DD4 #define DDRSS_PI_298_DATA 0x00150F27 #define DDRSS_PI_299_DATA 0x00000000 @@ -783,7 +791,7 @@ #define DDRSS_PHY_09_DATA 0x00000000 #define DDRSS_PHY_10_DATA 0x00000000 #define DDRSS_PHY_11_DATA 0x01000001 -#define DDRSS_PHY_12_DATA 0x00000100 +#define DDRSS_PHY_12_DATA 0x00000200 #define DDRSS_PHY_13_DATA 0x000800C0 #define DDRSS_PHY_14_DATA 0x060100CC #define DDRSS_PHY_15_DATA 0x00030066 @@ -802,9 +810,9 @@ #define DDRSS_PHY_28_DATA 0x2A000000 #define DDRSS_PHY_29_DATA 0x00000808 #define DDRSS_PHY_30_DATA 0x0F000000 -#define DDRSS_PHY_31_DATA 0x00000F0F -#define DDRSS_PHY_32_DATA 0x10200000 -#define DDRSS_PHY_33_DATA 0x0C002007 +#define DDRSS_PHY_31_DATA 0x00000F08 +#define DDRSS_PHY_32_DATA 0x10400000 +#define DDRSS_PHY_33_DATA 0x0C002006 #define DDRSS_PHY_34_DATA 0x00000000 #define DDRSS_PHY_35_DATA 0x00000000 #define DDRSS_PHY_36_DATA 0x55555555 @@ -871,20 +879,20 @@ #define DDRSS_PHY_97_DATA 0x00050010 #define DDRSS_PHY_98_DATA 0x51517041 #define DDRSS_PHY_99_DATA 0x31C06000 -#define DDRSS_PHY_100_DATA 0x07AB0340 +#define DDRSS_PHY_100_DATA 0x07AB01AB #define DDRSS_PHY_101_DATA 0x00C0C001 -#define DDRSS_PHY_102_DATA 0x09080001 +#define DDRSS_PHY_102_DATA 0x0B0A0101 #define DDRSS_PHY_103_DATA 0x10001000 -#define DDRSS_PHY_104_DATA 0x0C063E42 -#define DDRSS_PHY_105_DATA 0x0F0C2701 +#define DDRSS_PHY_104_DATA 0x0C073E42 +#define DDRSS_PHY_105_DATA 0x0F0C2D01 #define DDRSS_PHY_106_DATA 0x01000140 -#define DDRSS_PHY_107_DATA 0x04000420 +#define DDRSS_PHY_107_DATA 0x0C000420 #define DDRSS_PHY_108_DATA 0x00000198 #define DDRSS_PHY_109_DATA 0x0A0000D0 #define DDRSS_PHY_110_DATA 0x00030200 #define DDRSS_PHY_111_DATA 0x02800000 #define DDRSS_PHY_112_DATA 0x80800000 -#define DDRSS_PHY_113_DATA 0x00092010 +#define DDRSS_PHY_113_DATA 0x000B2010 #define DDRSS_PHY_114_DATA 0x76543210 #define DDRSS_PHY_115_DATA 0x00000008 #define DDRSS_PHY_116_DATA 0x02800280 @@ -901,8 +909,8 @@ #define DDRSS_PHY_127_DATA 0x00A000A0 #define DDRSS_PHY_128_DATA 0x00A000A0 #define DDRSS_PHY_129_DATA 0x00A000A0 -#define DDRSS_PHY_130_DATA 0x01C400A0 -#define DDRSS_PHY_131_DATA 0x01A00003 +#define DDRSS_PHY_130_DATA 0x011900A0 +#define DDRSS_PHY_131_DATA 0x01A00004 #define DDRSS_PHY_132_DATA 0x00000000 #define DDRSS_PHY_133_DATA 0x00000000 #define DDRSS_PHY_134_DATA 0x00080200 @@ -1039,7 +1047,7 @@ #define DDRSS_PHY_265_DATA 0x00000000 #define DDRSS_PHY_266_DATA 0x00000000 #define DDRSS_PHY_267_DATA 0x01000001 -#define DDRSS_PHY_268_DATA 0x00000100 +#define DDRSS_PHY_268_DATA 0x00000200 #define DDRSS_PHY_269_DATA 0x000800C0 #define DDRSS_PHY_270_DATA 0x060100CC #define DDRSS_PHY_271_DATA 0x00030066 @@ -1058,9 +1066,9 @@ #define DDRSS_PHY_284_DATA 0x2A000000 #define DDRSS_PHY_285_DATA 0x00000808 #define DDRSS_PHY_286_DATA 0x0F000000 -#define DDRSS_PHY_287_DATA 0x00000F0F -#define DDRSS_PHY_288_DATA 0x10200000 -#define DDRSS_PHY_289_DATA 0x0C002007 +#define DDRSS_PHY_287_DATA 0x00000F08 +#define DDRSS_PHY_288_DATA 0x10400000 +#define DDRSS_PHY_289_DATA 0x0C002006 #define DDRSS_PHY_290_DATA 0x00000000 #define DDRSS_PHY_291_DATA 0x00000000 #define DDRSS_PHY_292_DATA 0x55555555 @@ -1127,20 +1135,20 @@ #define DDRSS_PHY_353_DATA 0x00050010 #define DDRSS_PHY_354_DATA 0x51517041 #define DDRSS_PHY_355_DATA 0x31C06000 -#define DDRSS_PHY_356_DATA 0x07AB0340 +#define DDRSS_PHY_356_DATA 0x07AB01AB #define DDRSS_PHY_357_DATA 0x00C0C001 -#define DDRSS_PHY_358_DATA 0x09080001 +#define DDRSS_PHY_358_DATA 0x0B0A0101 #define DDRSS_PHY_359_DATA 0x10001000 -#define DDRSS_PHY_360_DATA 0x0C063E42 -#define DDRSS_PHY_361_DATA 0x0F0C2701 +#define DDRSS_PHY_360_DATA 0x0C073E42 +#define DDRSS_PHY_361_DATA 0x0F0C2D01 #define DDRSS_PHY_362_DATA 0x01000140 -#define DDRSS_PHY_363_DATA 0x04000420 +#define DDRSS_PHY_363_DATA 0x0C000420 #define DDRSS_PHY_364_DATA 0x00000198 #define DDRSS_PHY_365_DATA 0x0A0000D0 #define DDRSS_PHY_366_DATA 0x00030200 #define DDRSS_PHY_367_DATA 0x02800000 #define DDRSS_PHY_368_DATA 0x80800000 -#define DDRSS_PHY_369_DATA 0x00092010 +#define DDRSS_PHY_369_DATA 0x000B2010 #define DDRSS_PHY_370_DATA 0x76543210 #define DDRSS_PHY_371_DATA 0x00000008 #define DDRSS_PHY_372_DATA 0x02800280 @@ -1157,8 +1165,8 @@ #define DDRSS_PHY_383_DATA 0x00A000A0 #define DDRSS_PHY_384_DATA 0x00A000A0 #define DDRSS_PHY_385_DATA 0x00A000A0 -#define DDRSS_PHY_386_DATA 0x01C400A0 -#define DDRSS_PHY_387_DATA 0x01A00003 +#define DDRSS_PHY_386_DATA 0x011900A0 +#define DDRSS_PHY_387_DATA 0x01A00004 #define DDRSS_PHY_388_DATA 0x00000000 #define DDRSS_PHY_389_DATA 0x00000000 #define DDRSS_PHY_390_DATA 0x00080200 @@ -1295,7 +1303,7 @@ #define DDRSS_PHY_521_DATA 0x00000000 #define DDRSS_PHY_522_DATA 0x00000000 #define DDRSS_PHY_523_DATA 0x01000001 -#define DDRSS_PHY_524_DATA 0x00000100 +#define DDRSS_PHY_524_DATA 0x00000200 #define DDRSS_PHY_525_DATA 0x000800C0 #define DDRSS_PHY_526_DATA 0x060100CC #define DDRSS_PHY_527_DATA 0x00030066 @@ -1314,9 +1322,9 @@ #define DDRSS_PHY_540_DATA 0x2A000000 #define DDRSS_PHY_541_DATA 0x00000808 #define DDRSS_PHY_542_DATA 0x0F000000 -#define DDRSS_PHY_543_DATA 0x00000F0F -#define DDRSS_PHY_544_DATA 0x10200000 -#define DDRSS_PHY_545_DATA 0x0C002007 +#define DDRSS_PHY_543_DATA 0x00000F08 +#define DDRSS_PHY_544_DATA 0x10400000 +#define DDRSS_PHY_545_DATA 0x0C002006 #define DDRSS_PHY_546_DATA 0x00000000 #define DDRSS_PHY_547_DATA 0x00000000 #define DDRSS_PHY_548_DATA 0x55555555 @@ -1383,20 +1391,20 @@ #define DDRSS_PHY_609_DATA 0x00050010 #define DDRSS_PHY_610_DATA 0x51517041 #define DDRSS_PHY_611_DATA 0x31C06000 -#define DDRSS_PHY_612_DATA 0x07AB0340 +#define DDRSS_PHY_612_DATA 0x07AB01AB #define DDRSS_PHY_613_DATA 0x00C0C001 -#define DDRSS_PHY_614_DATA 0x09080001 +#define DDRSS_PHY_614_DATA 0x0B0A0101 #define DDRSS_PHY_615_DATA 0x10001000 -#define DDRSS_PHY_616_DATA 0x0C063E42 -#define DDRSS_PHY_617_DATA 0x0F0C2701 +#define DDRSS_PHY_616_DATA 0x0C073E42 +#define DDRSS_PHY_617_DATA 0x0F0C2D01 #define DDRSS_PHY_618_DATA 0x01000140 -#define DDRSS_PHY_619_DATA 0x04000420 +#define DDRSS_PHY_619_DATA 0x0C000420 #define DDRSS_PHY_620_DATA 0x00000198 #define DDRSS_PHY_621_DATA 0x0A0000D0 #define DDRSS_PHY_622_DATA 0x00030200 #define DDRSS_PHY_623_DATA 0x02800000 #define DDRSS_PHY_624_DATA 0x80800000 -#define DDRSS_PHY_625_DATA 0x00092010 +#define DDRSS_PHY_625_DATA 0x000B2010 #define DDRSS_PHY_626_DATA 0x76543210 #define DDRSS_PHY_627_DATA 0x00000008 #define DDRSS_PHY_628_DATA 0x02800280 @@ -1413,8 +1421,8 @@ #define DDRSS_PHY_639_DATA 0x00A000A0 #define DDRSS_PHY_640_DATA 0x00A000A0 #define DDRSS_PHY_641_DATA 0x00A000A0 -#define DDRSS_PHY_642_DATA 0x01C400A0 -#define DDRSS_PHY_643_DATA 0x01A00003 +#define DDRSS_PHY_642_DATA 0x011900A0 +#define DDRSS_PHY_643_DATA 0x01A00004 #define DDRSS_PHY_644_DATA 0x00000000 #define DDRSS_PHY_645_DATA 0x00000000 #define DDRSS_PHY_646_DATA 0x00080200 @@ -1551,7 +1559,7 @@ #define DDRSS_PHY_777_DATA 0x00000000 #define DDRSS_PHY_778_DATA 0x00000000 #define DDRSS_PHY_779_DATA 0x01000001 -#define DDRSS_PHY_780_DATA 0x00000100 +#define DDRSS_PHY_780_DATA 0x00000200 #define DDRSS_PHY_781_DATA 0x000800C0 #define DDRSS_PHY_782_DATA 0x060100CC #define DDRSS_PHY_783_DATA 0x00030066 @@ -1570,9 +1578,9 @@ #define DDRSS_PHY_796_DATA 0x2A000000 #define DDRSS_PHY_797_DATA 0x00000808 #define DDRSS_PHY_798_DATA 0x0F000000 -#define DDRSS_PHY_799_DATA 0x00000F0F -#define DDRSS_PHY_800_DATA 0x10200000 -#define DDRSS_PHY_801_DATA 0x0C002007 +#define DDRSS_PHY_799_DATA 0x00000F08 +#define DDRSS_PHY_800_DATA 0x10400000 +#define DDRSS_PHY_801_DATA 0x0C002006 #define DDRSS_PHY_802_DATA 0x00000000 #define DDRSS_PHY_803_DATA 0x00000000 #define DDRSS_PHY_804_DATA 0x55555555 @@ -1639,20 +1647,20 @@ #define DDRSS_PHY_865_DATA 0x00050010 #define DDRSS_PHY_866_DATA 0x51517041 #define DDRSS_PHY_867_DATA 0x31C06000 -#define DDRSS_PHY_868_DATA 0x07AB0340 +#define DDRSS_PHY_868_DATA 0x07AB01AB #define DDRSS_PHY_869_DATA 0x00C0C001 -#define DDRSS_PHY_870_DATA 0x09080001 +#define DDRSS_PHY_870_DATA 0x0B0A0101 #define DDRSS_PHY_871_DATA 0x10001000 -#define DDRSS_PHY_872_DATA 0x0C063E42 -#define DDRSS_PHY_873_DATA 0x0F0C2701 +#define DDRSS_PHY_872_DATA 0x0C073E42 +#define DDRSS_PHY_873_DATA 0x0F0C2D01 #define DDRSS_PHY_874_DATA 0x01000140 -#define DDRSS_PHY_875_DATA 0x04000420 +#define DDRSS_PHY_875_DATA 0x0C000420 #define DDRSS_PHY_876_DATA 0x00000198 #define DDRSS_PHY_877_DATA 0x0A0000D0 #define DDRSS_PHY_878_DATA 0x00030200 #define DDRSS_PHY_879_DATA 0x02800000 #define DDRSS_PHY_880_DATA 0x80800000 -#define DDRSS_PHY_881_DATA 0x00092010 +#define DDRSS_PHY_881_DATA 0x000B2010 #define DDRSS_PHY_882_DATA 0x76543210 #define DDRSS_PHY_883_DATA 0x00000008 #define DDRSS_PHY_884_DATA 0x02800280 @@ -1669,8 +1677,8 @@ #define DDRSS_PHY_895_DATA 0x00A000A0 #define DDRSS_PHY_896_DATA 0x00A000A0 #define DDRSS_PHY_897_DATA 0x00A000A0 -#define DDRSS_PHY_898_DATA 0x01C400A0 -#define DDRSS_PHY_899_DATA 0x01A00003 +#define DDRSS_PHY_898_DATA 0x011900A0 +#define DDRSS_PHY_899_DATA 0x01A00004 #define DDRSS_PHY_900_DATA 0x00000000 #define DDRSS_PHY_901_DATA 0x00000000 #define DDRSS_PHY_902_DATA 0x00080200 @@ -1810,7 +1818,7 @@ #define DDRSS_PHY_1036_DATA 0x00000080 #define DDRSS_PHY_1037_DATA 0x00DCBA98 #define DDRSS_PHY_1038_DATA 0x03000000 -#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1039_DATA 0x00200001 #define DDRSS_PHY_1040_DATA 0x00000000 #define DDRSS_PHY_1041_DATA 0x00000000 #define DDRSS_PHY_1042_DATA 0x00000000 @@ -1826,7 +1834,7 @@ #define DDRSS_PHY_1052_DATA 0x00000033 #define DDRSS_PHY_1053_DATA 0x00543210 #define DDRSS_PHY_1054_DATA 0x003F0000 -#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1055_DATA 0x000F3F3F #define DDRSS_PHY_1056_DATA 0x20202003 #define DDRSS_PHY_1057_DATA 0x00202020 #define DDRSS_PHY_1058_DATA 0x20008008 @@ -1835,7 +1843,7 @@ #define DDRSS_PHY_1061_DATA 0x00000000 #define DDRSS_PHY_1062_DATA 0x00000000 #define DDRSS_PHY_1063_DATA 0x00000000 -#define DDRSS_PHY_1064_DATA 0x000205BB +#define DDRSS_PHY_1064_DATA 0x000305CC #define DDRSS_PHY_1065_DATA 0x00030000 #define DDRSS_PHY_1066_DATA 0x00000300 #define DDRSS_PHY_1067_DATA 0x00000300 @@ -1844,8 +1852,8 @@ #define DDRSS_PHY_1070_DATA 0x00000300 #define DDRSS_PHY_1071_DATA 0x42080010 #define DDRSS_PHY_1072_DATA 0x0000803E -#define DDRSS_PHY_1073_DATA 0x00000001 -#define DDRSS_PHY_1074_DATA 0x01000102 +#define DDRSS_PHY_1073_DATA 0x00000004 +#define DDRSS_PHY_1074_DATA 0x01000002 #define DDRSS_PHY_1075_DATA 0x00008000 #define DDRSS_PHY_1076_DATA 0x00000000 #define DDRSS_PHY_1077_DATA 0x00000000 @@ -2074,14 +2082,14 @@ #define DDRSS_PHY_1300_DATA 0x00040101 #define DDRSS_PHY_1301_DATA 0x0000010F #define DDRSS_PHY_1302_DATA 0x00000000 -#define DDRSS_PHY_1303_DATA 0x0000FFFF +#define DDRSS_PHY_1303_DATA 0x00000064 #define DDRSS_PHY_1304_DATA 0x00000000 #define DDRSS_PHY_1305_DATA 0x01010000 #define DDRSS_PHY_1306_DATA 0x01080402 #define DDRSS_PHY_1307_DATA 0x01200F02 #define DDRSS_PHY_1308_DATA 0x00194280 #define DDRSS_PHY_1309_DATA 0x00000004 -#define DDRSS_PHY_1310_DATA 0x00052000 +#define DDRSS_PHY_1310_DATA 0x00042000 #define DDRSS_PHY_1311_DATA 0x00000000 #define DDRSS_PHY_1312_DATA 0x00000000 #define DDRSS_PHY_1313_DATA 0x00000000 @@ -2165,10 +2173,10 @@ #define DDRSS_PHY_1391_DATA 0x00000000 #define DDRSS_PHY_1392_DATA 0x00000000 #define DDRSS_PHY_1393_DATA 0x0001F7C0 -#define DDRSS_PHY_1394_DATA 0x00000002 +#define DDRSS_PHY_1394_DATA 0x00000003 #define DDRSS_PHY_1395_DATA 0x00000000 #define DDRSS_PHY_1396_DATA 0x00001142 -#define DDRSS_PHY_1397_DATA 0x010207AB +#define DDRSS_PHY_1397_DATA 0x040207AB #define DDRSS_PHY_1398_DATA 0x01000080 #define DDRSS_PHY_1399_DATA 0x03900390 #define DDRSS_PHY_1400_DATA 0x03900390 @@ -2177,20 +2185,23 @@ #define DDRSS_PHY_1403_DATA 0x00000390 #define DDRSS_PHY_1404_DATA 0x00000390 #define DDRSS_PHY_1405_DATA 0x00000005 -#define DDRSS_PHY_1406_DATA 0x01813FBB -#define DDRSS_PHY_1407_DATA 0x000000BB +#define DDRSS_PHY_1406_DATA 0x01813FCC +#define DDRSS_PHY_1407_DATA 0x000000CC #define DDRSS_PHY_1408_DATA 0x0C000DFF #define DDRSS_PHY_1409_DATA 0x30000DFF #define DDRSS_PHY_1410_DATA 0x3F0DFF11 #define DDRSS_PHY_1411_DATA 0x000100F0 -#define DDRSS_PHY_1412_DATA 0x780DFFBB +#define DDRSS_PHY_1412_DATA 0x780DFFCC #define DDRSS_PHY_1413_DATA 0x00007E31 #define DDRSS_PHY_1414_DATA 0x000CBF11 -#define DDRSS_PHY_1415_DATA 0x01770010 +#define DDRSS_PHY_1415_DATA 0x01990010 #define DDRSS_PHY_1416_DATA 0x000CBF11 -#define DDRSS_PHY_1417_DATA 0x01770010 +#define DDRSS_PHY_1417_DATA 0x01990010 #define DDRSS_PHY_1418_DATA 0x3F0DFF11 -#define DDRSS_PHY_1419_DATA 0x017700F0 +#define DDRSS_PHY_1419_DATA 0x00EF00F0 #define DDRSS_PHY_1420_DATA 0x3F0DFF11 #define DDRSS_PHY_1421_DATA 0x01FF00F0 #define DDRSS_PHY_1422_DATA 0x20040006 + + + diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index e35b767a7e3..3127ac83d7f 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-j7200-common-proc-board.dts" -#include "k3-j7200-ddr-evm-lp4-2666.dtsi" +#include "k3-j7200-ddr-evm-lp4-3200.dtsi" #include "k3-j721e-ddr.dtsi" #include "k3-j7200-common-proc-board-u-boot.dtsi" From 9627d70840ababb8d89dc73fb697edefb1732648 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 3 Nov 2025 12:40:30 +0530 Subject: [PATCH 23/65] arm: dts: k3-j721s2: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for J721S2 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi | 591 ++++++++++--------- 1 file changed, 307 insertions(+), 284 deletions(-) diff --git a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi index c91576bf093..ecd42b1cf4d 100644 --- a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi @@ -1,11 +1,23 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.7.0 - * This file was generated on 10/14/2021 - */ + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:46:29 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -16,6 +28,15 @@ #define MULTI_DDR_CFG_HYBRID_SELECT 0 #define MULTI_DDR_CFG_EMIFS_ACTIVE 3 +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000003 +#define DDR_REG1_SIZE_LSB 0x80000000 + + #define DDRSS0_CTL_00_DATA 0x00000B00 #define DDRSS0_CTL_01_DATA 0x00000000 #define DDRSS0_CTL_02_DATA 0x00000000 @@ -36,7 +57,7 @@ #define DDRSS0_CTL_17_DATA 0x00000005 #define DDRSS0_CTL_18_DATA 0x000010A9 #define DDRSS0_CTL_19_DATA 0x01010000 -#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_20_DATA 0x01011001 #define DDRSS0_CTL_21_DATA 0x02010000 #define DDRSS0_CTL_22_DATA 0x00020100 #define DDRSS0_CTL_23_DATA 0x0000000B @@ -51,7 +72,7 @@ #define DDRSS0_CTL_32_DATA 0x00000000 #define DDRSS0_CTL_33_DATA 0x00000000 #define DDRSS0_CTL_34_DATA 0x040C0000 -#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_35_DATA 0x12501250 #define DDRSS0_CTL_36_DATA 0x00050804 #define DDRSS0_CTL_37_DATA 0x09040008 #define DDRSS0_CTL_38_DATA 0x15000204 @@ -60,33 +81,33 @@ #define DDRSS0_CTL_41_DATA 0x1760008B #define DDRSS0_CTL_42_DATA 0x2000422B #define DDRSS0_CTL_43_DATA 0x000A0A09 -#define DDRSS0_CTL_44_DATA 0x0400078A +#define DDRSS0_CTL_44_DATA 0x040003C5 #define DDRSS0_CTL_45_DATA 0x1E161104 -#define DDRSS0_CTL_46_DATA 0x10012458 +#define DDRSS0_CTL_46_DATA 0x1000922C #define DDRSS0_CTL_47_DATA 0x1E161110 -#define DDRSS0_CTL_48_DATA 0x10012458 +#define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 -#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_50_DATA 0x2C060500 #define DDRSS0_CTL_51_DATA 0x08292C29 #define DDRSS0_CTL_52_DATA 0x14000E0A #define DDRSS0_CTL_53_DATA 0x04010A0A #define DDRSS0_CTL_54_DATA 0x01010004 -#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_55_DATA 0x0454540A #define DDRSS0_CTL_56_DATA 0x04313104 #define DDRSS0_CTL_57_DATA 0x00003131 #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x000000CE +#define DDRSS0_CTL_61_DATA 0x00000068 #define DDRSS0_CTL_62_DATA 0x0000032B -#define DDRSS0_CTL_63_DATA 0x00002073 +#define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B -#define DDRSS0_CTL_65_DATA 0x00002073 +#define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 -#define DDRSS0_CTL_68_DATA 0x00CB0012 -#define DDRSS0_CTL_69_DATA 0x00CB0408 -#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 #define DDRSS0_CTL_71_DATA 0x00120103 #define DDRSS0_CTL_72_DATA 0x00100005 #define DDRSS0_CTL_73_DATA 0x2F080010 @@ -118,27 +139,27 @@ #define DDRSS0_CTL_99_DATA 0x00000000 #define DDRSS0_CTL_100_DATA 0x00040005 #define DDRSS0_CTL_101_DATA 0x00000000 -#define DDRSS0_CTL_102_DATA 0x00003380 -#define DDRSS0_CTL_103_DATA 0x00003380 -#define DDRSS0_CTL_104_DATA 0x00003380 -#define DDRSS0_CTL_105_DATA 0x00003380 -#define DDRSS0_CTL_106_DATA 0x00003380 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 #define DDRSS0_CTL_107_DATA 0x00000000 -#define DDRSS0_CTL_108_DATA 0x000005A2 -#define DDRSS0_CTL_109_DATA 0x00081CC0 -#define DDRSS0_CTL_110_DATA 0x00081CC0 -#define DDRSS0_CTL_111_DATA 0x00081CC0 -#define DDRSS0_CTL_112_DATA 0x00081CC0 -#define DDRSS0_CTL_113_DATA 0x00081CC0 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 #define DDRSS0_CTL_114_DATA 0x00000000 -#define DDRSS0_CTL_115_DATA 0x0000E325 -#define DDRSS0_CTL_116_DATA 0x00081CC0 -#define DDRSS0_CTL_117_DATA 0x00081CC0 -#define DDRSS0_CTL_118_DATA 0x00081CC0 -#define DDRSS0_CTL_119_DATA 0x00081CC0 -#define DDRSS0_CTL_120_DATA 0x00081CC0 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 #define DDRSS0_CTL_121_DATA 0x00000000 -#define DDRSS0_CTL_122_DATA 0x0000E325 +#define DDRSS0_CTL_122_DATA 0x00007173 #define DDRSS0_CTL_123_DATA 0x00000000 #define DDRSS0_CTL_124_DATA 0x00000000 #define DDRSS0_CTL_125_DATA 0x00000000 @@ -192,22 +213,22 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 -#define DDRSS0_CTL_178_DATA 0x56000000 -#define DDRSS0_CTL_179_DATA 0x27270056 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 +#define DDRSS0_CTL_178_DATA 0x36000000 +#define DDRSS0_CTL_179_DATA 0x27270036 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 #define DDRSS0_CTL_185_DATA 0x00000000 -#define DDRSS0_CTL_186_DATA 0x00565600 +#define DDRSS0_CTL_186_DATA 0x00363600 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 #define DDRSS0_CTL_190_DATA 0x00000020 -#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_191_DATA 0x01000000 #define DDRSS0_CTL_192_DATA 0x00000001 #define DDRSS0_CTL_193_DATA 0x00000000 #define DDRSS0_CTL_194_DATA 0x01000000 @@ -245,17 +266,17 @@ #define DDRSS0_CTL_226_DATA 0x00000000 #define DDRSS0_CTL_227_DATA 0x15110000 #define DDRSS0_CTL_228_DATA 0x00040C18 -#define DDRSS0_CTL_229_DATA 0x00000000 -#define DDRSS0_CTL_230_DATA 0x00000000 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 #define DDRSS0_CTL_231_DATA 0x00000000 #define DDRSS0_CTL_232_DATA 0x00000000 -#define DDRSS0_CTL_233_DATA 0x00000000 -#define DDRSS0_CTL_234_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 #define DDRSS0_CTL_235_DATA 0x00000000 #define DDRSS0_CTL_236_DATA 0x00000000 #define DDRSS0_CTL_237_DATA 0x00000000 -#define DDRSS0_CTL_238_DATA 0x00000000 -#define DDRSS0_CTL_239_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 #define DDRSS0_CTL_240_DATA 0x00000000 #define DDRSS0_CTL_241_DATA 0x00000000 #define DDRSS0_CTL_242_DATA 0x00030000 @@ -283,7 +304,7 @@ #define DDRSS0_CTL_264_DATA 0x00000040 #define DDRSS0_CTL_265_DATA 0x006B0003 #define DDRSS0_CTL_266_DATA 0x0100006B -#define DDRSS0_CTL_267_DATA 0x00000000 +#define DDRSS0_CTL_267_DATA 0x03030303 #define DDRSS0_CTL_268_DATA 0x00000000 #define DDRSS0_CTL_269_DATA 0x00000202 #define DDRSS0_CTL_270_DATA 0x00001FFF @@ -307,14 +328,14 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00010101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 #define DDRSS0_CTL_295_DATA 0x00000000 #define DDRSS0_CTL_296_DATA 0x00000000 -#define DDRSS0_CTL_297_DATA 0x00000000 -#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF #define DDRSS0_CTL_299_DATA 0x00000000 #define DDRSS0_CTL_300_DATA 0x00000000 #define DDRSS0_CTL_301_DATA 0x00000000 @@ -335,7 +356,7 @@ #define DDRSS0_CTL_316_DATA 0x01010001 #define DDRSS0_CTL_317_DATA 0x00010101 #define DDRSS0_CTL_318_DATA 0x050A0A03 -#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_319_DATA 0x10082323 #define DDRSS0_CTL_320_DATA 0x00090310 #define DDRSS0_CTL_321_DATA 0x0B0C030F #define DDRSS0_CTL_322_DATA 0x0B0C0306 @@ -405,30 +426,30 @@ #define DDRSS0_CTL_386_DATA 0x00000000 #define DDRSS0_CTL_387_DATA 0x3A3A1B00 #define DDRSS0_CTL_388_DATA 0x000A0000 -#define DDRSS0_CTL_389_DATA 0x0000019C +#define DDRSS0_CTL_389_DATA 0x000000C6 #define DDRSS0_CTL_390_DATA 0x00000200 #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x000004D4 -#define DDRSS0_CTL_395_DATA 0x00001018 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 -#define DDRSS0_CTL_397_DATA 0x000040E6 +#define DDRSS0_CTL_397_DATA 0x0000206A #define DDRSS0_CTL_398_DATA 0x00000200 #define DDRSS0_CTL_399_DATA 0x00000200 #define DDRSS0_CTL_400_DATA 0x00000200 #define DDRSS0_CTL_401_DATA 0x00000200 -#define DDRSS0_CTL_402_DATA 0x0000C2B2 -#define DDRSS0_CTL_403_DATA 0x000288FC -#define DDRSS0_CTL_404_DATA 0x00000E15 -#define DDRSS0_CTL_405_DATA 0x000040E6 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 #define DDRSS0_CTL_408_DATA 0x00000200 #define DDRSS0_CTL_409_DATA 0x00000200 -#define DDRSS0_CTL_410_DATA 0x0000C2B2 -#define DDRSS0_CTL_411_DATA 0x000288FC -#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 #define DDRSS0_CTL_415_DATA 0x00000000 @@ -445,7 +466,7 @@ #define DDRSS0_CTL_426_DATA 0x00000000 #define DDRSS0_CTL_427_DATA 0x02000000 #define DDRSS0_CTL_428_DATA 0x01000404 -#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_429_DATA 0x0B220B22 #define DDRSS0_CTL_430_DATA 0x00000105 #define DDRSS0_CTL_431_DATA 0x00010101 #define DDRSS0_CTL_432_DATA 0x00010101 @@ -488,8 +509,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -537,18 +558,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 -#define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_66_DATA 0x01000100 +#define DDRSS0_PI_67_DATA 0x0102020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -637,37 +658,37 @@ #define DDRSS0_PI_158_DATA 0x00000000 #define DDRSS0_PI_159_DATA 0x00000401 #define DDRSS0_PI_160_DATA 0x00000000 -#define DDRSS0_PI_161_DATA 0x00010000 -#define DDRSS0_PI_162_DATA 0x00000000 -#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 #define DDRSS0_PI_164_DATA 0x00000034 -#define DDRSS0_PI_165_DATA 0x00000064 -#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 #define DDRSS0_PI_167_DATA 0x02000200 -#define DDRSS0_PI_168_DATA 0x48120C04 -#define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x000000CE +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 #define DDRSS0_PI_171_DATA 0x0000032B -#define DDRSS0_PI_172_DATA 0x00002073 +#define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B -#define DDRSS0_PI_174_DATA 0x04002073 +#define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 -#define DDRSS0_PI_185_DATA 0x15040000 -#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 #define DDRSS0_PI_187_DATA 0x00040402 #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -675,8 +696,8 @@ #define DDRSS0_PI_196_DATA 0x02170100 #define DDRSS0_PI_197_DATA 0x01000217 #define DDRSS0_PI_198_DATA 0x02170217 -#define DDRSS0_PI_199_DATA 0x32103200 -#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B #define DDRSS0_PI_201_DATA 0x0A070601 #define DDRSS0_PI_202_DATA 0x1F130A0D #define DDRSS0_PI_203_DATA 0x1F130A14 @@ -688,29 +709,29 @@ #define DDRSS0_PI_209_DATA 0x00240216 #define DDRSS0_PI_210_DATA 0x00110216 #define DDRSS0_PI_211_DATA 0x32000056 -#define DDRSS0_PI_212_DATA 0x00000301 -#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 -#define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 -#define DDRSS0_PI_218_DATA 0x04010504 -#define DDRSS0_PI_219_DATA 0x040006C9 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A #define DDRSS0_PI_222_DATA 0x00002918 -#define DDRSS0_PI_223_DATA 0x6001071C +#define DDRSS0_PI_223_DATA 0x6000838E #define DDRSS0_PI_224_DATA 0x1E202008 #define DDRSS0_PI_225_DATA 0x2C311116 #define DDRSS0_PI_226_DATA 0x00002918 -#define DDRSS0_PI_227_DATA 0x6001071C +#define DDRSS0_PI_227_DATA 0x6000838E #define DDRSS0_PI_228_DATA 0x1E202008 -#define DDRSS0_PI_229_DATA 0x00019C16 -#define DDRSS0_PI_230_DATA 0x00001018 -#define DDRSS0_PI_231_DATA 0x000040E6 -#define DDRSS0_PI_232_DATA 0x000288FC -#define DDRSS0_PI_233_DATA 0x000040E6 -#define DDRSS0_PI_234_DATA 0x000288FC +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 #define DDRSS0_PI_235_DATA 0x033B0016 #define DDRSS0_PI_236_DATA 0x0303033B #define DDRSS0_PI_237_DATA 0x002AF803 @@ -751,29 +772,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00F30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x56333FF4 +#define DDRSS0_PI_277_DATA 0x36F33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x56333FF4 +#define DDRSS0_PI_279_DATA 0x36F33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00F30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x56333FF4 +#define DDRSS0_PI_283_DATA 0x36F33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x56333FF4 +#define DDRSS0_PI_285_DATA 0x36F33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00F30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x56333FF4 +#define DDRSS0_PI_289_DATA 0x36F33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x56333FF4 +#define DDRSS0_PI_291_DATA 0x36F33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00F30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x56333FF4 +#define DDRSS0_PI_295_DATA 0x36F33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x56333FF4 +#define DDRSS0_PI_297_DATA 0x36F33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -789,7 +810,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -808,9 +829,9 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F -#define DDRSS0_PHY_32_DATA 0x10200000 -#define DDRSS0_PHY_33_DATA 0x0C002006 +#define DDRSS0_PHY_31_DATA 0x00000F08 +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002002 #define DDRSS0_PHY_34_DATA 0x00000000 #define DDRSS0_PHY_35_DATA 0x00000000 #define DDRSS0_PHY_36_DATA 0x55555555 @@ -877,9 +898,9 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 -#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 #define DDRSS0_PHY_103_DATA 0x10001000 #define DDRSS0_PHY_104_DATA 0x0C083E42 #define DDRSS0_PHY_105_DATA 0x0F0C3701 @@ -913,7 +934,7 @@ #define DDRSS0_PHY_133_DATA 0x00000000 #define DDRSS0_PHY_134_DATA 0x00080200 #define DDRSS0_PHY_135_DATA 0x00000000 -#define DDRSS0_PHY_136_DATA 0x20202000 +#define DDRSS0_PHY_136_DATA 0x20202020 #define DDRSS0_PHY_137_DATA 0x20202020 #define DDRSS0_PHY_138_DATA 0xF0F02020 #define DDRSS0_PHY_139_DATA 0x00000000 @@ -1045,7 +1066,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1064,9 +1085,9 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F -#define DDRSS0_PHY_288_DATA 0x10200000 -#define DDRSS0_PHY_289_DATA 0x0C002006 +#define DDRSS0_PHY_287_DATA 0x00000F08 +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002002 #define DDRSS0_PHY_290_DATA 0x00000000 #define DDRSS0_PHY_291_DATA 0x00000000 #define DDRSS0_PHY_292_DATA 0x55555555 @@ -1133,9 +1154,9 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 -#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 #define DDRSS0_PHY_359_DATA 0x10001000 #define DDRSS0_PHY_360_DATA 0x0C083E42 #define DDRSS0_PHY_361_DATA 0x0F0C3701 @@ -1169,7 +1190,7 @@ #define DDRSS0_PHY_389_DATA 0x00000000 #define DDRSS0_PHY_390_DATA 0x00080200 #define DDRSS0_PHY_391_DATA 0x00000000 -#define DDRSS0_PHY_392_DATA 0x20202000 +#define DDRSS0_PHY_392_DATA 0x20202020 #define DDRSS0_PHY_393_DATA 0x20202020 #define DDRSS0_PHY_394_DATA 0xF0F02020 #define DDRSS0_PHY_395_DATA 0x00000000 @@ -1301,7 +1322,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1320,9 +1341,9 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F -#define DDRSS0_PHY_544_DATA 0x10200000 -#define DDRSS0_PHY_545_DATA 0x0C002006 +#define DDRSS0_PHY_543_DATA 0x00000F08 +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002002 #define DDRSS0_PHY_546_DATA 0x00000000 #define DDRSS0_PHY_547_DATA 0x00000000 #define DDRSS0_PHY_548_DATA 0x55555555 @@ -1389,9 +1410,9 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 -#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 #define DDRSS0_PHY_615_DATA 0x10001000 #define DDRSS0_PHY_616_DATA 0x0C083E42 #define DDRSS0_PHY_617_DATA 0x0F0C3701 @@ -1425,7 +1446,7 @@ #define DDRSS0_PHY_645_DATA 0x00000000 #define DDRSS0_PHY_646_DATA 0x00080200 #define DDRSS0_PHY_647_DATA 0x00000000 -#define DDRSS0_PHY_648_DATA 0x20202000 +#define DDRSS0_PHY_648_DATA 0x20202020 #define DDRSS0_PHY_649_DATA 0x20202020 #define DDRSS0_PHY_650_DATA 0xF0F02020 #define DDRSS0_PHY_651_DATA 0x00000000 @@ -1557,7 +1578,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1576,9 +1597,9 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F -#define DDRSS0_PHY_800_DATA 0x10200000 -#define DDRSS0_PHY_801_DATA 0x0C002006 +#define DDRSS0_PHY_799_DATA 0x00000F08 +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002002 #define DDRSS0_PHY_802_DATA 0x00000000 #define DDRSS0_PHY_803_DATA 0x00000000 #define DDRSS0_PHY_804_DATA 0x55555555 @@ -1645,9 +1666,9 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 -#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 #define DDRSS0_PHY_871_DATA 0x10001000 #define DDRSS0_PHY_872_DATA 0x0C083E42 #define DDRSS0_PHY_873_DATA 0x0F0C3701 @@ -1681,7 +1702,7 @@ #define DDRSS0_PHY_901_DATA 0x00000000 #define DDRSS0_PHY_902_DATA 0x00080200 #define DDRSS0_PHY_903_DATA 0x00000000 -#define DDRSS0_PHY_904_DATA 0x20202000 +#define DDRSS0_PHY_904_DATA 0x20202020 #define DDRSS0_PHY_905_DATA 0x20202020 #define DDRSS0_PHY_906_DATA 0xF0F02020 #define DDRSS0_PHY_907_DATA 0x00000000 @@ -1832,7 +1853,7 @@ #define DDRSS0_PHY_1052_DATA 0x00000033 #define DDRSS0_PHY_1053_DATA 0x00543210 #define DDRSS0_PHY_1054_DATA 0x003F0000 -#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1055_DATA 0x000F3F3F #define DDRSS0_PHY_1056_DATA 0x20202003 #define DDRSS0_PHY_1057_DATA 0x00202020 #define DDRSS0_PHY_1058_DATA 0x20008008 @@ -2080,14 +2101,14 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 #define DDRSS0_PHY_1307_DATA 0x01200F02 #define DDRSS0_PHY_1308_DATA 0x00194280 #define DDRSS0_PHY_1309_DATA 0x00000004 -#define DDRSS0_PHY_1310_DATA 0x00052000 +#define DDRSS0_PHY_1310_DATA 0x00042000 #define DDRSS0_PHY_1311_DATA 0x00000000 #define DDRSS0_PHY_1312_DATA 0x00000000 #define DDRSS0_PHY_1313_DATA 0x00000000 @@ -2174,7 +2195,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2221,7 +2242,7 @@ #define DDRSS1_CTL_17_DATA 0x00000005 #define DDRSS1_CTL_18_DATA 0x000010A9 #define DDRSS1_CTL_19_DATA 0x01010000 -#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_20_DATA 0x01011001 #define DDRSS1_CTL_21_DATA 0x02010000 #define DDRSS1_CTL_22_DATA 0x00020100 #define DDRSS1_CTL_23_DATA 0x0000000B @@ -2236,7 +2257,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_35_DATA 0x12501250 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2245,33 +2266,33 @@ #define DDRSS1_CTL_41_DATA 0x1760008B #define DDRSS1_CTL_42_DATA 0x2000422B #define DDRSS1_CTL_43_DATA 0x000A0A09 -#define DDRSS1_CTL_44_DATA 0x0400078A +#define DDRSS1_CTL_44_DATA 0x040003C5 #define DDRSS1_CTL_45_DATA 0x1E161104 -#define DDRSS1_CTL_46_DATA 0x10012458 +#define DDRSS1_CTL_46_DATA 0x1000922C #define DDRSS1_CTL_47_DATA 0x1E161110 -#define DDRSS1_CTL_48_DATA 0x10012458 +#define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 -#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_50_DATA 0x2C060500 #define DDRSS1_CTL_51_DATA 0x08292C29 #define DDRSS1_CTL_52_DATA 0x14000E0A #define DDRSS1_CTL_53_DATA 0x04010A0A #define DDRSS1_CTL_54_DATA 0x01010004 -#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_55_DATA 0x0454540A #define DDRSS1_CTL_56_DATA 0x04313104 #define DDRSS1_CTL_57_DATA 0x00003131 #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x000000CE +#define DDRSS1_CTL_61_DATA 0x00000068 #define DDRSS1_CTL_62_DATA 0x0000032B -#define DDRSS1_CTL_63_DATA 0x00002073 +#define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B -#define DDRSS1_CTL_65_DATA 0x00002073 +#define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 -#define DDRSS1_CTL_68_DATA 0x00CB0012 -#define DDRSS1_CTL_69_DATA 0x00CB0408 -#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 #define DDRSS1_CTL_71_DATA 0x00120103 #define DDRSS1_CTL_72_DATA 0x00100005 #define DDRSS1_CTL_73_DATA 0x2F080010 @@ -2303,27 +2324,27 @@ #define DDRSS1_CTL_99_DATA 0x00000000 #define DDRSS1_CTL_100_DATA 0x00040005 #define DDRSS1_CTL_101_DATA 0x00000000 -#define DDRSS1_CTL_102_DATA 0x00003380 -#define DDRSS1_CTL_103_DATA 0x00003380 -#define DDRSS1_CTL_104_DATA 0x00003380 -#define DDRSS1_CTL_105_DATA 0x00003380 -#define DDRSS1_CTL_106_DATA 0x00003380 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 #define DDRSS1_CTL_107_DATA 0x00000000 -#define DDRSS1_CTL_108_DATA 0x000005A2 -#define DDRSS1_CTL_109_DATA 0x00081CC0 -#define DDRSS1_CTL_110_DATA 0x00081CC0 -#define DDRSS1_CTL_111_DATA 0x00081CC0 -#define DDRSS1_CTL_112_DATA 0x00081CC0 -#define DDRSS1_CTL_113_DATA 0x00081CC0 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 #define DDRSS1_CTL_114_DATA 0x00000000 -#define DDRSS1_CTL_115_DATA 0x0000E325 -#define DDRSS1_CTL_116_DATA 0x00081CC0 -#define DDRSS1_CTL_117_DATA 0x00081CC0 -#define DDRSS1_CTL_118_DATA 0x00081CC0 -#define DDRSS1_CTL_119_DATA 0x00081CC0 -#define DDRSS1_CTL_120_DATA 0x00081CC0 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 #define DDRSS1_CTL_121_DATA 0x00000000 -#define DDRSS1_CTL_122_DATA 0x0000E325 +#define DDRSS1_CTL_122_DATA 0x00007173 #define DDRSS1_CTL_123_DATA 0x00000000 #define DDRSS1_CTL_124_DATA 0x00000000 #define DDRSS1_CTL_125_DATA 0x00000000 @@ -2377,22 +2398,22 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 -#define DDRSS1_CTL_178_DATA 0x56000000 -#define DDRSS1_CTL_179_DATA 0x27270056 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 +#define DDRSS1_CTL_178_DATA 0x36000000 +#define DDRSS1_CTL_179_DATA 0x27270036 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 #define DDRSS1_CTL_185_DATA 0x00000000 -#define DDRSS1_CTL_186_DATA 0x00565600 +#define DDRSS1_CTL_186_DATA 0x00363600 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 #define DDRSS1_CTL_190_DATA 0x00000020 -#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_191_DATA 0x01000000 #define DDRSS1_CTL_192_DATA 0x00000001 #define DDRSS1_CTL_193_DATA 0x00000000 #define DDRSS1_CTL_194_DATA 0x01000000 @@ -2430,17 +2451,17 @@ #define DDRSS1_CTL_226_DATA 0x00000000 #define DDRSS1_CTL_227_DATA 0x15110000 #define DDRSS1_CTL_228_DATA 0x00040C18 -#define DDRSS1_CTL_229_DATA 0x00000000 -#define DDRSS1_CTL_230_DATA 0x00000000 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 #define DDRSS1_CTL_231_DATA 0x00000000 #define DDRSS1_CTL_232_DATA 0x00000000 -#define DDRSS1_CTL_233_DATA 0x00000000 -#define DDRSS1_CTL_234_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 #define DDRSS1_CTL_235_DATA 0x00000000 #define DDRSS1_CTL_236_DATA 0x00000000 #define DDRSS1_CTL_237_DATA 0x00000000 -#define DDRSS1_CTL_238_DATA 0x00000000 -#define DDRSS1_CTL_239_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 #define DDRSS1_CTL_240_DATA 0x00000000 #define DDRSS1_CTL_241_DATA 0x00000000 #define DDRSS1_CTL_242_DATA 0x00030000 @@ -2468,7 +2489,7 @@ #define DDRSS1_CTL_264_DATA 0x00000040 #define DDRSS1_CTL_265_DATA 0x006B0003 #define DDRSS1_CTL_266_DATA 0x0100006B -#define DDRSS1_CTL_267_DATA 0x00000000 +#define DDRSS1_CTL_267_DATA 0x03030303 #define DDRSS1_CTL_268_DATA 0x00000000 #define DDRSS1_CTL_269_DATA 0x00000202 #define DDRSS1_CTL_270_DATA 0x00001FFF @@ -2492,14 +2513,14 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00010101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 #define DDRSS1_CTL_295_DATA 0x00000000 #define DDRSS1_CTL_296_DATA 0x00000000 -#define DDRSS1_CTL_297_DATA 0x00000000 -#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF #define DDRSS1_CTL_299_DATA 0x00000000 #define DDRSS1_CTL_300_DATA 0x00000000 #define DDRSS1_CTL_301_DATA 0x00000000 @@ -2520,7 +2541,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_319_DATA 0x10082323 #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2590,30 +2611,30 @@ #define DDRSS1_CTL_386_DATA 0x00000000 #define DDRSS1_CTL_387_DATA 0x3A3A1B00 #define DDRSS1_CTL_388_DATA 0x000A0000 -#define DDRSS1_CTL_389_DATA 0x0000019C +#define DDRSS1_CTL_389_DATA 0x000000C6 #define DDRSS1_CTL_390_DATA 0x00000200 #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x000004D4 -#define DDRSS1_CTL_395_DATA 0x00001018 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 -#define DDRSS1_CTL_397_DATA 0x000040E6 +#define DDRSS1_CTL_397_DATA 0x0000206A #define DDRSS1_CTL_398_DATA 0x00000200 #define DDRSS1_CTL_399_DATA 0x00000200 #define DDRSS1_CTL_400_DATA 0x00000200 #define DDRSS1_CTL_401_DATA 0x00000200 -#define DDRSS1_CTL_402_DATA 0x0000C2B2 -#define DDRSS1_CTL_403_DATA 0x000288FC -#define DDRSS1_CTL_404_DATA 0x00000E15 -#define DDRSS1_CTL_405_DATA 0x000040E6 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 #define DDRSS1_CTL_408_DATA 0x00000200 #define DDRSS1_CTL_409_DATA 0x00000200 -#define DDRSS1_CTL_410_DATA 0x0000C2B2 -#define DDRSS1_CTL_411_DATA 0x000288FC -#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2630,7 +2651,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_429_DATA 0x0B220B22 #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2673,8 +2694,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2722,18 +2743,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2822,37 +2843,37 @@ #define DDRSS1_PI_158_DATA 0x00000000 #define DDRSS1_PI_159_DATA 0x00000401 #define DDRSS1_PI_160_DATA 0x00000000 -#define DDRSS1_PI_161_DATA 0x00010000 -#define DDRSS1_PI_162_DATA 0x00000000 -#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000064 -#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x48120C04 -#define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x000000CE +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 #define DDRSS1_PI_171_DATA 0x0000032B -#define DDRSS1_PI_172_DATA 0x00002073 +#define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B -#define DDRSS1_PI_174_DATA 0x04002073 +#define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x15040000 -#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2860,8 +2881,8 @@ #define DDRSS1_PI_196_DATA 0x02170100 #define DDRSS1_PI_197_DATA 0x01000217 #define DDRSS1_PI_198_DATA 0x02170217 -#define DDRSS1_PI_199_DATA 0x32103200 -#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B #define DDRSS1_PI_201_DATA 0x0A070601 #define DDRSS1_PI_202_DATA 0x1F130A0D #define DDRSS1_PI_203_DATA 0x1F130A14 @@ -2873,29 +2894,29 @@ #define DDRSS1_PI_209_DATA 0x00240216 #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 -#define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 -#define DDRSS1_PI_218_DATA 0x04010504 -#define DDRSS1_PI_219_DATA 0x040006C9 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A #define DDRSS1_PI_222_DATA 0x00002918 -#define DDRSS1_PI_223_DATA 0x6001071C +#define DDRSS1_PI_223_DATA 0x6000838E #define DDRSS1_PI_224_DATA 0x1E202008 #define DDRSS1_PI_225_DATA 0x2C311116 #define DDRSS1_PI_226_DATA 0x00002918 -#define DDRSS1_PI_227_DATA 0x6001071C +#define DDRSS1_PI_227_DATA 0x6000838E #define DDRSS1_PI_228_DATA 0x1E202008 -#define DDRSS1_PI_229_DATA 0x00019C16 -#define DDRSS1_PI_230_DATA 0x00001018 -#define DDRSS1_PI_231_DATA 0x000040E6 -#define DDRSS1_PI_232_DATA 0x000288FC -#define DDRSS1_PI_233_DATA 0x000040E6 -#define DDRSS1_PI_234_DATA 0x000288FC +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 #define DDRSS1_PI_235_DATA 0x033B0016 #define DDRSS1_PI_236_DATA 0x0303033B #define DDRSS1_PI_237_DATA 0x002AF803 @@ -2936,29 +2957,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00F30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x56333FF4 +#define DDRSS1_PI_277_DATA 0x36F33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x56333FF4 +#define DDRSS1_PI_279_DATA 0x36F33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00F30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x56333FF4 +#define DDRSS1_PI_283_DATA 0x36F33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x56333FF4 +#define DDRSS1_PI_285_DATA 0x36F33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00F30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x56333FF4 +#define DDRSS1_PI_289_DATA 0x36F33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x56333FF4 +#define DDRSS1_PI_291_DATA 0x36F33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00F30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x56333FF4 +#define DDRSS1_PI_295_DATA 0x36F33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x56333FF4 +#define DDRSS1_PI_297_DATA 0x36F33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2974,7 +2995,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2993,8 +3014,8 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F -#define DDRSS1_PHY_32_DATA 0x10200000 +#define DDRSS1_PHY_31_DATA 0x00000F08 +#define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 #define DDRSS1_PHY_35_DATA 0x00000000 @@ -3062,9 +3083,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3098,7 +3119,7 @@ #define DDRSS1_PHY_133_DATA 0x00000000 #define DDRSS1_PHY_134_DATA 0x00080200 #define DDRSS1_PHY_135_DATA 0x00000000 -#define DDRSS1_PHY_136_DATA 0x20202000 +#define DDRSS1_PHY_136_DATA 0x20202020 #define DDRSS1_PHY_137_DATA 0x20202020 #define DDRSS1_PHY_138_DATA 0xF0F02020 #define DDRSS1_PHY_139_DATA 0x00000000 @@ -3230,7 +3251,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3249,8 +3270,8 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F -#define DDRSS1_PHY_288_DATA 0x10200000 +#define DDRSS1_PHY_287_DATA 0x00000F08 +#define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 #define DDRSS1_PHY_291_DATA 0x00000000 @@ -3318,9 +3339,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3354,7 +3375,7 @@ #define DDRSS1_PHY_389_DATA 0x00000000 #define DDRSS1_PHY_390_DATA 0x00080200 #define DDRSS1_PHY_391_DATA 0x00000000 -#define DDRSS1_PHY_392_DATA 0x20202000 +#define DDRSS1_PHY_392_DATA 0x20202020 #define DDRSS1_PHY_393_DATA 0x20202020 #define DDRSS1_PHY_394_DATA 0xF0F02020 #define DDRSS1_PHY_395_DATA 0x00000000 @@ -3486,7 +3507,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3505,8 +3526,8 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F -#define DDRSS1_PHY_544_DATA 0x10200000 +#define DDRSS1_PHY_543_DATA 0x00000F08 +#define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 #define DDRSS1_PHY_547_DATA 0x00000000 @@ -3574,9 +3595,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3610,7 +3631,7 @@ #define DDRSS1_PHY_645_DATA 0x00000000 #define DDRSS1_PHY_646_DATA 0x00080200 #define DDRSS1_PHY_647_DATA 0x00000000 -#define DDRSS1_PHY_648_DATA 0x20202000 +#define DDRSS1_PHY_648_DATA 0x20202020 #define DDRSS1_PHY_649_DATA 0x20202020 #define DDRSS1_PHY_650_DATA 0xF0F02020 #define DDRSS1_PHY_651_DATA 0x00000000 @@ -3742,7 +3763,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3761,8 +3782,8 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F -#define DDRSS1_PHY_800_DATA 0x10200000 +#define DDRSS1_PHY_799_DATA 0x00000F08 +#define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 #define DDRSS1_PHY_803_DATA 0x00000000 @@ -3830,9 +3851,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -3866,7 +3887,7 @@ #define DDRSS1_PHY_901_DATA 0x00000000 #define DDRSS1_PHY_902_DATA 0x00080200 #define DDRSS1_PHY_903_DATA 0x00000000 -#define DDRSS1_PHY_904_DATA 0x20202000 +#define DDRSS1_PHY_904_DATA 0x20202020 #define DDRSS1_PHY_905_DATA 0x20202020 #define DDRSS1_PHY_906_DATA 0xF0F02020 #define DDRSS1_PHY_907_DATA 0x00000000 @@ -4017,7 +4038,7 @@ #define DDRSS1_PHY_1052_DATA 0x00000033 #define DDRSS1_PHY_1053_DATA 0x00543210 #define DDRSS1_PHY_1054_DATA 0x003F0000 -#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1055_DATA 0x000F3F3F #define DDRSS1_PHY_1056_DATA 0x20202003 #define DDRSS1_PHY_1057_DATA 0x00202020 #define DDRSS1_PHY_1058_DATA 0x20008008 @@ -4265,14 +4286,14 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 #define DDRSS1_PHY_1307_DATA 0x01200F02 #define DDRSS1_PHY_1308_DATA 0x00194280 #define DDRSS1_PHY_1309_DATA 0x00000004 -#define DDRSS1_PHY_1310_DATA 0x00052000 +#define DDRSS1_PHY_1310_DATA 0x00042000 #define DDRSS1_PHY_1311_DATA 0x00000000 #define DDRSS1_PHY_1312_DATA 0x00000000 #define DDRSS1_PHY_1313_DATA 0x00000000 @@ -4359,7 +4380,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 @@ -4385,3 +4406,5 @@ #define DDRSS1_PHY_1420_DATA 0x3F0DFF11 #define DDRSS1_PHY_1421_DATA 0x01FF00F0 #define DDRSS1_PHY_1422_DATA 0x20040006 + + From 168681795981a07d0ff301ffb61d9a596127decf Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 3 Nov 2025 12:40:31 +0530 Subject: [PATCH 24/65] arm: dts: k3-am68: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for AM68 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar Signed-off-by: Neha Malcom Francis Reviewed-by: Udit Kumar --- arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi | 4410 +++++++++++++++++++++ arch/arm/dts/k3-am68-sk-r5-base-board.dts | 2 +- 2 files changed, 4411 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi diff --git a/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi b/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi new file mode 100644 index 00000000000..ea773a2ca4f --- /dev/null +++ b/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi @@ -0,0 +1,4410 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:50:37 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_0 27500000 +#define DDRSS_PLL_FREQUENCY_1 1066500000 +#define DDRSS_PLL_FREQUENCY_2 1066500000 + +#define MULTI_DDR_CFG_INTRLV_GRAN 0 +#define MULTI_DDR_CFG_INTRLV_SIZE 11 +#define MULTI_DDR_CFG_ECC_ENABLE 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 0 +#define MULTI_DDR_CFG_EMIFS_ACTIVE 3 + +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000003 +#define DDR_REG1_SIZE_LSB 0x80000000 + + +#define DDRSS0_CTL_00_DATA 0x00000B00 +#define DDRSS0_CTL_01_DATA 0x00000000 +#define DDRSS0_CTL_02_DATA 0x00000000 +#define DDRSS0_CTL_03_DATA 0x00000000 +#define DDRSS0_CTL_04_DATA 0x00000000 +#define DDRSS0_CTL_05_DATA 0x00000000 +#define DDRSS0_CTL_06_DATA 0x00000000 +#define DDRSS0_CTL_07_DATA 0x00002AF8 +#define DDRSS0_CTL_08_DATA 0x0001ADAF +#define DDRSS0_CTL_09_DATA 0x00000005 +#define DDRSS0_CTL_10_DATA 0x0000006E +#define DDRSS0_CTL_11_DATA 0x000681C8 +#define DDRSS0_CTL_12_DATA 0x004111C9 +#define DDRSS0_CTL_13_DATA 0x00000005 +#define DDRSS0_CTL_14_DATA 0x000010A9 +#define DDRSS0_CTL_15_DATA 0x000681C8 +#define DDRSS0_CTL_16_DATA 0x004111C9 +#define DDRSS0_CTL_17_DATA 0x00000005 +#define DDRSS0_CTL_18_DATA 0x000010A9 +#define DDRSS0_CTL_19_DATA 0x01010000 +#define DDRSS0_CTL_20_DATA 0x01011001 +#define DDRSS0_CTL_21_DATA 0x02010000 +#define DDRSS0_CTL_22_DATA 0x00020100 +#define DDRSS0_CTL_23_DATA 0x0000000B +#define DDRSS0_CTL_24_DATA 0x0000001C +#define DDRSS0_CTL_25_DATA 0x00000000 +#define DDRSS0_CTL_26_DATA 0x00000000 +#define DDRSS0_CTL_27_DATA 0x03020200 +#define DDRSS0_CTL_28_DATA 0x00005656 +#define DDRSS0_CTL_29_DATA 0x00100000 +#define DDRSS0_CTL_30_DATA 0x00000000 +#define DDRSS0_CTL_31_DATA 0x00000000 +#define DDRSS0_CTL_32_DATA 0x00000000 +#define DDRSS0_CTL_33_DATA 0x00000000 +#define DDRSS0_CTL_34_DATA 0x040C0000 +#define DDRSS0_CTL_35_DATA 0x12501250 +#define DDRSS0_CTL_36_DATA 0x00050804 +#define DDRSS0_CTL_37_DATA 0x09040008 +#define DDRSS0_CTL_38_DATA 0x15000204 +#define DDRSS0_CTL_39_DATA 0x1760008B +#define DDRSS0_CTL_40_DATA 0x1500422B +#define DDRSS0_CTL_41_DATA 0x1760008B +#define DDRSS0_CTL_42_DATA 0x2000422B +#define DDRSS0_CTL_43_DATA 0x000A0A09 +#define DDRSS0_CTL_44_DATA 0x040003C5 +#define DDRSS0_CTL_45_DATA 0x1E161104 +#define DDRSS0_CTL_46_DATA 0x1000922C +#define DDRSS0_CTL_47_DATA 0x1E161110 +#define DDRSS0_CTL_48_DATA 0x1000922C +#define DDRSS0_CTL_49_DATA 0x02030410 +#define DDRSS0_CTL_50_DATA 0x2C060500 +#define DDRSS0_CTL_51_DATA 0x08292C29 +#define DDRSS0_CTL_52_DATA 0x14000E0A +#define DDRSS0_CTL_53_DATA 0x04010A0A +#define DDRSS0_CTL_54_DATA 0x01010004 +#define DDRSS0_CTL_55_DATA 0x0454540A +#define DDRSS0_CTL_56_DATA 0x04313104 +#define DDRSS0_CTL_57_DATA 0x00003131 +#define DDRSS0_CTL_58_DATA 0x00010100 +#define DDRSS0_CTL_59_DATA 0x03010000 +#define DDRSS0_CTL_60_DATA 0x00001508 +#define DDRSS0_CTL_61_DATA 0x00000068 +#define DDRSS0_CTL_62_DATA 0x0000032B +#define DDRSS0_CTL_63_DATA 0x00001035 +#define DDRSS0_CTL_64_DATA 0x0000032B +#define DDRSS0_CTL_65_DATA 0x00001035 +#define DDRSS0_CTL_66_DATA 0x00000005 +#define DDRSS0_CTL_67_DATA 0x00050000 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 +#define DDRSS0_CTL_71_DATA 0x00120103 +#define DDRSS0_CTL_72_DATA 0x00100005 +#define DDRSS0_CTL_73_DATA 0x2F080010 +#define DDRSS0_CTL_74_DATA 0x0505012F +#define DDRSS0_CTL_75_DATA 0x0401030A +#define DDRSS0_CTL_76_DATA 0x041E100B +#define DDRSS0_CTL_77_DATA 0x100B0401 +#define DDRSS0_CTL_78_DATA 0x0001041E +#define DDRSS0_CTL_79_DATA 0x00160016 +#define DDRSS0_CTL_80_DATA 0x033B033B +#define DDRSS0_CTL_81_DATA 0x033B033B +#define DDRSS0_CTL_82_DATA 0x03050505 +#define DDRSS0_CTL_83_DATA 0x03010303 +#define DDRSS0_CTL_84_DATA 0x200B100B +#define DDRSS0_CTL_85_DATA 0x04041004 +#define DDRSS0_CTL_86_DATA 0x200B100B +#define DDRSS0_CTL_87_DATA 0x04041004 +#define DDRSS0_CTL_88_DATA 0x03010000 +#define DDRSS0_CTL_89_DATA 0x00010000 +#define DDRSS0_CTL_90_DATA 0x00000000 +#define DDRSS0_CTL_91_DATA 0x00000000 +#define DDRSS0_CTL_92_DATA 0x01000000 +#define DDRSS0_CTL_93_DATA 0x80104002 +#define DDRSS0_CTL_94_DATA 0x00000000 +#define DDRSS0_CTL_95_DATA 0x00040005 +#define DDRSS0_CTL_96_DATA 0x00000000 +#define DDRSS0_CTL_97_DATA 0x00050000 +#define DDRSS0_CTL_98_DATA 0x00000004 +#define DDRSS0_CTL_99_DATA 0x00000000 +#define DDRSS0_CTL_100_DATA 0x00040005 +#define DDRSS0_CTL_101_DATA 0x00000000 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 +#define DDRSS0_CTL_107_DATA 0x00000000 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 +#define DDRSS0_CTL_114_DATA 0x00000000 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 +#define DDRSS0_CTL_121_DATA 0x00000000 +#define DDRSS0_CTL_122_DATA 0x00007173 +#define DDRSS0_CTL_123_DATA 0x00000000 +#define DDRSS0_CTL_124_DATA 0x00000000 +#define DDRSS0_CTL_125_DATA 0x00000000 +#define DDRSS0_CTL_126_DATA 0x00000000 +#define DDRSS0_CTL_127_DATA 0x00000000 +#define DDRSS0_CTL_128_DATA 0x00000000 +#define DDRSS0_CTL_129_DATA 0x00000000 +#define DDRSS0_CTL_130_DATA 0x00000000 +#define DDRSS0_CTL_131_DATA 0x0B030500 +#define DDRSS0_CTL_132_DATA 0x00040B04 +#define DDRSS0_CTL_133_DATA 0x0A090000 +#define DDRSS0_CTL_134_DATA 0x0A090701 +#define DDRSS0_CTL_135_DATA 0x0900000E +#define DDRSS0_CTL_136_DATA 0x0907010A +#define DDRSS0_CTL_137_DATA 0x00000E0A +#define DDRSS0_CTL_138_DATA 0x07010A09 +#define DDRSS0_CTL_139_DATA 0x000E0A09 +#define DDRSS0_CTL_140_DATA 0x07000401 +#define DDRSS0_CTL_141_DATA 0x00000000 +#define DDRSS0_CTL_142_DATA 0x00000000 +#define DDRSS0_CTL_143_DATA 0x00000000 +#define DDRSS0_CTL_144_DATA 0x00000000 +#define DDRSS0_CTL_145_DATA 0x00000000 +#define DDRSS0_CTL_146_DATA 0x00000000 +#define DDRSS0_CTL_147_DATA 0x00000000 +#define DDRSS0_CTL_148_DATA 0x08080000 +#define DDRSS0_CTL_149_DATA 0x01000000 +#define DDRSS0_CTL_150_DATA 0x800000C0 +#define DDRSS0_CTL_151_DATA 0x800000C0 +#define DDRSS0_CTL_152_DATA 0x800000C0 +#define DDRSS0_CTL_153_DATA 0x00000000 +#define DDRSS0_CTL_154_DATA 0x00001500 +#define DDRSS0_CTL_155_DATA 0x00000000 +#define DDRSS0_CTL_156_DATA 0x00000001 +#define DDRSS0_CTL_157_DATA 0x00000002 +#define DDRSS0_CTL_158_DATA 0x0000100E +#define DDRSS0_CTL_159_DATA 0x00000000 +#define DDRSS0_CTL_160_DATA 0x00000000 +#define DDRSS0_CTL_161_DATA 0x00000000 +#define DDRSS0_CTL_162_DATA 0x00000000 +#define DDRSS0_CTL_163_DATA 0x00000000 +#define DDRSS0_CTL_164_DATA 0x000B0000 +#define DDRSS0_CTL_165_DATA 0x000E0006 +#define DDRSS0_CTL_166_DATA 0x000E0404 +#define DDRSS0_CTL_167_DATA 0x00D601AB +#define DDRSS0_CTL_168_DATA 0x10100216 +#define DDRSS0_CTL_169_DATA 0x01AB0216 +#define DDRSS0_CTL_170_DATA 0x021600D6 +#define DDRSS0_CTL_171_DATA 0x02161010 +#define DDRSS0_CTL_172_DATA 0x00000000 +#define DDRSS0_CTL_173_DATA 0x00000000 +#define DDRSS0_CTL_174_DATA 0x00000000 +#define DDRSS0_CTL_175_DATA 0x3FF40084 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 +#define DDRSS0_CTL_178_DATA 0x36000000 +#define DDRSS0_CTL_179_DATA 0x27270036 +#define DDRSS0_CTL_180_DATA 0x0F0F0000 +#define DDRSS0_CTL_181_DATA 0x16000000 +#define DDRSS0_CTL_182_DATA 0x00841616 +#define DDRSS0_CTL_183_DATA 0x3FF43FF4 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 +#define DDRSS0_CTL_185_DATA 0x00000000 +#define DDRSS0_CTL_186_DATA 0x00363600 +#define DDRSS0_CTL_187_DATA 0x00002727 +#define DDRSS0_CTL_188_DATA 0x00000F0F +#define DDRSS0_CTL_189_DATA 0x16161600 +#define DDRSS0_CTL_190_DATA 0x00000020 +#define DDRSS0_CTL_191_DATA 0x01000000 +#define DDRSS0_CTL_192_DATA 0x00000001 +#define DDRSS0_CTL_193_DATA 0x00000000 +#define DDRSS0_CTL_194_DATA 0x01000000 +#define DDRSS0_CTL_195_DATA 0x00000001 +#define DDRSS0_CTL_196_DATA 0x00000000 +#define DDRSS0_CTL_197_DATA 0x00000000 +#define DDRSS0_CTL_198_DATA 0x00000000 +#define DDRSS0_CTL_199_DATA 0x00000000 +#define DDRSS0_CTL_200_DATA 0x00000000 +#define DDRSS0_CTL_201_DATA 0x00000000 +#define DDRSS0_CTL_202_DATA 0x00000000 +#define DDRSS0_CTL_203_DATA 0x00000000 +#define DDRSS0_CTL_204_DATA 0x00000000 +#define DDRSS0_CTL_205_DATA 0x00000000 +#define DDRSS0_CTL_206_DATA 0x02000000 +#define DDRSS0_CTL_207_DATA 0x01080101 +#define DDRSS0_CTL_208_DATA 0x00000000 +#define DDRSS0_CTL_209_DATA 0x00000000 +#define DDRSS0_CTL_210_DATA 0x00000000 +#define DDRSS0_CTL_211_DATA 0x00000000 +#define DDRSS0_CTL_212_DATA 0x00000000 +#define DDRSS0_CTL_213_DATA 0x00000000 +#define DDRSS0_CTL_214_DATA 0x00000000 +#define DDRSS0_CTL_215_DATA 0x00000000 +#define DDRSS0_CTL_216_DATA 0x00000000 +#define DDRSS0_CTL_217_DATA 0x00000000 +#define DDRSS0_CTL_218_DATA 0x00000000 +#define DDRSS0_CTL_219_DATA 0x00000000 +#define DDRSS0_CTL_220_DATA 0x00000000 +#define DDRSS0_CTL_221_DATA 0x00000000 +#define DDRSS0_CTL_222_DATA 0x00001000 +#define DDRSS0_CTL_223_DATA 0x006403E8 +#define DDRSS0_CTL_224_DATA 0x00000000 +#define DDRSS0_CTL_225_DATA 0x00000000 +#define DDRSS0_CTL_226_DATA 0x00000000 +#define DDRSS0_CTL_227_DATA 0x15110000 +#define DDRSS0_CTL_228_DATA 0x00040C18 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 +#define DDRSS0_CTL_231_DATA 0x00000000 +#define DDRSS0_CTL_232_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 +#define DDRSS0_CTL_235_DATA 0x00000000 +#define DDRSS0_CTL_236_DATA 0x00000000 +#define DDRSS0_CTL_237_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 +#define DDRSS0_CTL_240_DATA 0x00000000 +#define DDRSS0_CTL_241_DATA 0x00000000 +#define DDRSS0_CTL_242_DATA 0x00030000 +#define DDRSS0_CTL_243_DATA 0x00000000 +#define DDRSS0_CTL_244_DATA 0x00000000 +#define DDRSS0_CTL_245_DATA 0x00000000 +#define DDRSS0_CTL_246_DATA 0x00000000 +#define DDRSS0_CTL_247_DATA 0x00000000 +#define DDRSS0_CTL_248_DATA 0x00000000 +#define DDRSS0_CTL_249_DATA 0x00000000 +#define DDRSS0_CTL_250_DATA 0x00000000 +#define DDRSS0_CTL_251_DATA 0x00000000 +#define DDRSS0_CTL_252_DATA 0x00000000 +#define DDRSS0_CTL_253_DATA 0x00000000 +#define DDRSS0_CTL_254_DATA 0x00000000 +#define DDRSS0_CTL_255_DATA 0x00000000 +#define DDRSS0_CTL_256_DATA 0x00000000 +#define DDRSS0_CTL_257_DATA 0x01000200 +#define DDRSS0_CTL_258_DATA 0x00370040 +#define DDRSS0_CTL_259_DATA 0x00020008 +#define DDRSS0_CTL_260_DATA 0x00400100 +#define DDRSS0_CTL_261_DATA 0x00400855 +#define DDRSS0_CTL_262_DATA 0x01000200 +#define DDRSS0_CTL_263_DATA 0x08550040 +#define DDRSS0_CTL_264_DATA 0x00000040 +#define DDRSS0_CTL_265_DATA 0x006B0003 +#define DDRSS0_CTL_266_DATA 0x0100006B +#define DDRSS0_CTL_267_DATA 0x03030303 +#define DDRSS0_CTL_268_DATA 0x00000000 +#define DDRSS0_CTL_269_DATA 0x00000202 +#define DDRSS0_CTL_270_DATA 0x00001FFF +#define DDRSS0_CTL_271_DATA 0x3FFF2000 +#define DDRSS0_CTL_272_DATA 0x03FF0000 +#define DDRSS0_CTL_273_DATA 0x000103FF +#define DDRSS0_CTL_274_DATA 0x0FFF0B00 +#define DDRSS0_CTL_275_DATA 0x01010001 +#define DDRSS0_CTL_276_DATA 0x01010101 +#define DDRSS0_CTL_277_DATA 0x01180101 +#define DDRSS0_CTL_278_DATA 0x00030000 +#define DDRSS0_CTL_279_DATA 0x00000000 +#define DDRSS0_CTL_280_DATA 0x00000000 +#define DDRSS0_CTL_281_DATA 0x00000000 +#define DDRSS0_CTL_282_DATA 0x00000000 +#define DDRSS0_CTL_283_DATA 0x00000000 +#define DDRSS0_CTL_284_DATA 0x00000000 +#define DDRSS0_CTL_285_DATA 0x00000000 +#define DDRSS0_CTL_286_DATA 0x00040101 +#define DDRSS0_CTL_287_DATA 0x04010100 +#define DDRSS0_CTL_288_DATA 0x00000000 +#define DDRSS0_CTL_289_DATA 0x00000000 +#define DDRSS0_CTL_290_DATA 0x03030300 +#define DDRSS0_CTL_291_DATA 0x00010101 +#define DDRSS0_CTL_292_DATA 0x00000000 +#define DDRSS0_CTL_293_DATA 0x00000000 +#define DDRSS0_CTL_294_DATA 0x00000000 +#define DDRSS0_CTL_295_DATA 0x00000000 +#define DDRSS0_CTL_296_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF +#define DDRSS0_CTL_299_DATA 0x00000000 +#define DDRSS0_CTL_300_DATA 0x00000000 +#define DDRSS0_CTL_301_DATA 0x00000000 +#define DDRSS0_CTL_302_DATA 0x00000000 +#define DDRSS0_CTL_303_DATA 0x00000000 +#define DDRSS0_CTL_304_DATA 0x00000000 +#define DDRSS0_CTL_305_DATA 0x00000000 +#define DDRSS0_CTL_306_DATA 0x00000000 +#define DDRSS0_CTL_307_DATA 0x00000000 +#define DDRSS0_CTL_308_DATA 0x00000000 +#define DDRSS0_CTL_309_DATA 0x00000000 +#define DDRSS0_CTL_310_DATA 0x00000000 +#define DDRSS0_CTL_311_DATA 0x00000000 +#define DDRSS0_CTL_312_DATA 0x00000000 +#define DDRSS0_CTL_313_DATA 0x01000000 +#define DDRSS0_CTL_314_DATA 0x00020201 +#define DDRSS0_CTL_315_DATA 0x01000101 +#define DDRSS0_CTL_316_DATA 0x01010001 +#define DDRSS0_CTL_317_DATA 0x00010101 +#define DDRSS0_CTL_318_DATA 0x050A0A03 +#define DDRSS0_CTL_319_DATA 0x10082323 +#define DDRSS0_CTL_320_DATA 0x00090310 +#define DDRSS0_CTL_321_DATA 0x0B0C030F +#define DDRSS0_CTL_322_DATA 0x0B0C0306 +#define DDRSS0_CTL_323_DATA 0x0C090006 +#define DDRSS0_CTL_324_DATA 0x0100000C +#define DDRSS0_CTL_325_DATA 0x08040801 +#define DDRSS0_CTL_326_DATA 0x00000004 +#define DDRSS0_CTL_327_DATA 0x00000000 +#define DDRSS0_CTL_328_DATA 0x00010000 +#define DDRSS0_CTL_329_DATA 0x00280D00 +#define DDRSS0_CTL_330_DATA 0x00000001 +#define DDRSS0_CTL_331_DATA 0x00030001 +#define DDRSS0_CTL_332_DATA 0x00000000 +#define DDRSS0_CTL_333_DATA 0x00000000 +#define DDRSS0_CTL_334_DATA 0x00000000 +#define DDRSS0_CTL_335_DATA 0x00000000 +#define DDRSS0_CTL_336_DATA 0x00000000 +#define DDRSS0_CTL_337_DATA 0x00000000 +#define DDRSS0_CTL_338_DATA 0x00000000 +#define DDRSS0_CTL_339_DATA 0x00000000 +#define DDRSS0_CTL_340_DATA 0x01000000 +#define DDRSS0_CTL_341_DATA 0x00000001 +#define DDRSS0_CTL_342_DATA 0x00010100 +#define DDRSS0_CTL_343_DATA 0x03030000 +#define DDRSS0_CTL_344_DATA 0x00000000 +#define DDRSS0_CTL_345_DATA 0x00000000 +#define DDRSS0_CTL_346_DATA 0x00000000 +#define DDRSS0_CTL_347_DATA 0x00000000 +#define DDRSS0_CTL_348_DATA 0x00000000 +#define DDRSS0_CTL_349_DATA 0x00000000 +#define DDRSS0_CTL_350_DATA 0x00000000 +#define DDRSS0_CTL_351_DATA 0x00000000 +#define DDRSS0_CTL_352_DATA 0x00000000 +#define DDRSS0_CTL_353_DATA 0x00000000 +#define DDRSS0_CTL_354_DATA 0x00000000 +#define DDRSS0_CTL_355_DATA 0x00000000 +#define DDRSS0_CTL_356_DATA 0x00000000 +#define DDRSS0_CTL_357_DATA 0x00000000 +#define DDRSS0_CTL_358_DATA 0x00000000 +#define DDRSS0_CTL_359_DATA 0x00000000 +#define DDRSS0_CTL_360_DATA 0x000556AA +#define DDRSS0_CTL_361_DATA 0x000AAAAA +#define DDRSS0_CTL_362_DATA 0x000AA955 +#define DDRSS0_CTL_363_DATA 0x00055555 +#define DDRSS0_CTL_364_DATA 0x000B3133 +#define DDRSS0_CTL_365_DATA 0x0004CD33 +#define DDRSS0_CTL_366_DATA 0x0004CECC +#define DDRSS0_CTL_367_DATA 0x000B32CC +#define DDRSS0_CTL_368_DATA 0x00010300 +#define DDRSS0_CTL_369_DATA 0x03000100 +#define DDRSS0_CTL_370_DATA 0x00000000 +#define DDRSS0_CTL_371_DATA 0x00000000 +#define DDRSS0_CTL_372_DATA 0x00000000 +#define DDRSS0_CTL_373_DATA 0x00000000 +#define DDRSS0_CTL_374_DATA 0x00000000 +#define DDRSS0_CTL_375_DATA 0x00000000 +#define DDRSS0_CTL_376_DATA 0x00000000 +#define DDRSS0_CTL_377_DATA 0x00010000 +#define DDRSS0_CTL_378_DATA 0x00000404 +#define DDRSS0_CTL_379_DATA 0x00000000 +#define DDRSS0_CTL_380_DATA 0x00000000 +#define DDRSS0_CTL_381_DATA 0x00000000 +#define DDRSS0_CTL_382_DATA 0x00000000 +#define DDRSS0_CTL_383_DATA 0x00000000 +#define DDRSS0_CTL_384_DATA 0x00000000 +#define DDRSS0_CTL_385_DATA 0x00000000 +#define DDRSS0_CTL_386_DATA 0x00000000 +#define DDRSS0_CTL_387_DATA 0x3A3A1B00 +#define DDRSS0_CTL_388_DATA 0x000A0000 +#define DDRSS0_CTL_389_DATA 0x000000C6 +#define DDRSS0_CTL_390_DATA 0x00000200 +#define DDRSS0_CTL_391_DATA 0x00000200 +#define DDRSS0_CTL_392_DATA 0x00000200 +#define DDRSS0_CTL_393_DATA 0x00000200 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC +#define DDRSS0_CTL_396_DATA 0x00000204 +#define DDRSS0_CTL_397_DATA 0x0000206A +#define DDRSS0_CTL_398_DATA 0x00000200 +#define DDRSS0_CTL_399_DATA 0x00000200 +#define DDRSS0_CTL_400_DATA 0x00000200 +#define DDRSS0_CTL_401_DATA 0x00000200 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A +#define DDRSS0_CTL_406_DATA 0x00000200 +#define DDRSS0_CTL_407_DATA 0x00000200 +#define DDRSS0_CTL_408_DATA 0x00000200 +#define DDRSS0_CTL_409_DATA 0x00000200 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 +#define DDRSS0_CTL_413_DATA 0x03030202 +#define DDRSS0_CTL_414_DATA 0x00000022 +#define DDRSS0_CTL_415_DATA 0x00000000 +#define DDRSS0_CTL_416_DATA 0x00000000 +#define DDRSS0_CTL_417_DATA 0x00001403 +#define DDRSS0_CTL_418_DATA 0x000007D0 +#define DDRSS0_CTL_419_DATA 0x00000000 +#define DDRSS0_CTL_420_DATA 0x00000000 +#define DDRSS0_CTL_421_DATA 0x00030000 +#define DDRSS0_CTL_422_DATA 0x0007001F +#define DDRSS0_CTL_423_DATA 0x001B0033 +#define DDRSS0_CTL_424_DATA 0x001B0033 +#define DDRSS0_CTL_425_DATA 0x00000000 +#define DDRSS0_CTL_426_DATA 0x00000000 +#define DDRSS0_CTL_427_DATA 0x02000000 +#define DDRSS0_CTL_428_DATA 0x01000404 +#define DDRSS0_CTL_429_DATA 0x0B220B22 +#define DDRSS0_CTL_430_DATA 0x00000105 +#define DDRSS0_CTL_431_DATA 0x00010101 +#define DDRSS0_CTL_432_DATA 0x00010101 +#define DDRSS0_CTL_433_DATA 0x00010001 +#define DDRSS0_CTL_434_DATA 0x00000101 +#define DDRSS0_CTL_435_DATA 0x02000201 +#define DDRSS0_CTL_436_DATA 0x02010000 +#define DDRSS0_CTL_437_DATA 0x00000200 +#define DDRSS0_CTL_438_DATA 0x28060000 +#define DDRSS0_CTL_439_DATA 0x00000128 +#define DDRSS0_CTL_440_DATA 0xFFFFFFFF +#define DDRSS0_CTL_441_DATA 0xFFFFFFFF +#define DDRSS0_CTL_442_DATA 0x00000000 +#define DDRSS0_CTL_443_DATA 0x00000000 +#define DDRSS0_CTL_444_DATA 0x00000000 +#define DDRSS0_CTL_445_DATA 0x00000000 +#define DDRSS0_CTL_446_DATA 0x00000000 +#define DDRSS0_CTL_447_DATA 0x00000000 +#define DDRSS0_CTL_448_DATA 0x00000000 +#define DDRSS0_CTL_449_DATA 0x00000000 +#define DDRSS0_CTL_450_DATA 0x00000000 +#define DDRSS0_CTL_451_DATA 0x00000000 +#define DDRSS0_CTL_452_DATA 0x00000000 +#define DDRSS0_CTL_453_DATA 0x00000000 +#define DDRSS0_CTL_454_DATA 0x00000000 +#define DDRSS0_CTL_455_DATA 0x00000000 +#define DDRSS0_CTL_456_DATA 0x00000000 +#define DDRSS0_CTL_457_DATA 0x00000000 +#define DDRSS0_CTL_458_DATA 0x00000000 + +#define DDRSS0_PI_00_DATA 0x00000B00 +#define DDRSS0_PI_01_DATA 0x00000000 +#define DDRSS0_PI_02_DATA 0x00000000 +#define DDRSS0_PI_03_DATA 0x00000000 +#define DDRSS0_PI_04_DATA 0x00000000 +#define DDRSS0_PI_05_DATA 0x00000101 +#define DDRSS0_PI_06_DATA 0x00640000 +#define DDRSS0_PI_07_DATA 0x00000001 +#define DDRSS0_PI_08_DATA 0x00000000 +#define DDRSS0_PI_09_DATA 0x00000000 +#define DDRSS0_PI_10_DATA 0x00000000 +#define DDRSS0_PI_11_DATA 0x00000000 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 +#define DDRSS0_PI_14_DATA 0x0800000F +#define DDRSS0_PI_15_DATA 0x00000103 +#define DDRSS0_PI_16_DATA 0x00000005 +#define DDRSS0_PI_17_DATA 0x00000000 +#define DDRSS0_PI_18_DATA 0x00000000 +#define DDRSS0_PI_19_DATA 0x00000000 +#define DDRSS0_PI_20_DATA 0x00000000 +#define DDRSS0_PI_21_DATA 0x00000000 +#define DDRSS0_PI_22_DATA 0x00000000 +#define DDRSS0_PI_23_DATA 0x00000000 +#define DDRSS0_PI_24_DATA 0x00000000 +#define DDRSS0_PI_25_DATA 0x00000000 +#define DDRSS0_PI_26_DATA 0x00010100 +#define DDRSS0_PI_27_DATA 0x00280A00 +#define DDRSS0_PI_28_DATA 0x00000000 +#define DDRSS0_PI_29_DATA 0x0F000000 +#define DDRSS0_PI_30_DATA 0x00003200 +#define DDRSS0_PI_31_DATA 0x00000000 +#define DDRSS0_PI_32_DATA 0x00000000 +#define DDRSS0_PI_33_DATA 0x01010102 +#define DDRSS0_PI_34_DATA 0x00000000 +#define DDRSS0_PI_35_DATA 0x000000AA +#define DDRSS0_PI_36_DATA 0x00000055 +#define DDRSS0_PI_37_DATA 0x000000B5 +#define DDRSS0_PI_38_DATA 0x0000004A +#define DDRSS0_PI_39_DATA 0x00000056 +#define DDRSS0_PI_40_DATA 0x000000A9 +#define DDRSS0_PI_41_DATA 0x000000A9 +#define DDRSS0_PI_42_DATA 0x000000B5 +#define DDRSS0_PI_43_DATA 0x00000000 +#define DDRSS0_PI_44_DATA 0x00000000 +#define DDRSS0_PI_45_DATA 0x000F0F00 +#define DDRSS0_PI_46_DATA 0x0000001B +#define DDRSS0_PI_47_DATA 0x000007D0 +#define DDRSS0_PI_48_DATA 0x00000300 +#define DDRSS0_PI_49_DATA 0x00000000 +#define DDRSS0_PI_50_DATA 0x00000000 +#define DDRSS0_PI_51_DATA 0x01000000 +#define DDRSS0_PI_52_DATA 0x00010101 +#define DDRSS0_PI_53_DATA 0x00000000 +#define DDRSS0_PI_54_DATA 0x00030000 +#define DDRSS0_PI_55_DATA 0x0F000000 +#define DDRSS0_PI_56_DATA 0x00000017 +#define DDRSS0_PI_57_DATA 0x00000000 +#define DDRSS0_PI_58_DATA 0x00000000 +#define DDRSS0_PI_59_DATA 0x00000000 +#define DDRSS0_PI_60_DATA 0x0A0A140A +#define DDRSS0_PI_61_DATA 0x10020201 +#define DDRSS0_PI_62_DATA 0x00020805 +#define DDRSS0_PI_63_DATA 0x01000404 +#define DDRSS0_PI_64_DATA 0x00000000 +#define DDRSS0_PI_65_DATA 0x00000000 +#define DDRSS0_PI_66_DATA 0x01000100 +#define DDRSS0_PI_67_DATA 0x0102020F +#define DDRSS0_PI_68_DATA 0x00340000 +#define DDRSS0_PI_69_DATA 0x00000000 +#define DDRSS0_PI_70_DATA 0x00000000 +#define DDRSS0_PI_71_DATA 0x0000FFFF +#define DDRSS0_PI_72_DATA 0x01000000 +#define DDRSS0_PI_73_DATA 0x00080000 +#define DDRSS0_PI_74_DATA 0x02000200 +#define DDRSS0_PI_75_DATA 0x01000100 +#define DDRSS0_PI_76_DATA 0x01000000 +#define DDRSS0_PI_77_DATA 0x02000200 +#define DDRSS0_PI_78_DATA 0x00000200 +#define DDRSS0_PI_79_DATA 0x00000000 +#define DDRSS0_PI_80_DATA 0x00000000 +#define DDRSS0_PI_81_DATA 0x00000000 +#define DDRSS0_PI_82_DATA 0x00000000 +#define DDRSS0_PI_83_DATA 0x00000000 +#define DDRSS0_PI_84_DATA 0x00000000 +#define DDRSS0_PI_85_DATA 0x00000000 +#define DDRSS0_PI_86_DATA 0x00000000 +#define DDRSS0_PI_87_DATA 0x00000000 +#define DDRSS0_PI_88_DATA 0x00000000 +#define DDRSS0_PI_89_DATA 0x00000000 +#define DDRSS0_PI_90_DATA 0x00000000 +#define DDRSS0_PI_91_DATA 0x00000400 +#define DDRSS0_PI_92_DATA 0x02010000 +#define DDRSS0_PI_93_DATA 0x00080003 +#define DDRSS0_PI_94_DATA 0x00080000 +#define DDRSS0_PI_95_DATA 0x00000001 +#define DDRSS0_PI_96_DATA 0x00000000 +#define DDRSS0_PI_97_DATA 0x0000AA00 +#define DDRSS0_PI_98_DATA 0x00000000 +#define DDRSS0_PI_99_DATA 0x00000000 +#define DDRSS0_PI_100_DATA 0x00010000 +#define DDRSS0_PI_101_DATA 0x00000000 +#define DDRSS0_PI_102_DATA 0x00000000 +#define DDRSS0_PI_103_DATA 0x00000000 +#define DDRSS0_PI_104_DATA 0x00000000 +#define DDRSS0_PI_105_DATA 0x00000000 +#define DDRSS0_PI_106_DATA 0x00000000 +#define DDRSS0_PI_107_DATA 0x00000000 +#define DDRSS0_PI_108_DATA 0x00000000 +#define DDRSS0_PI_109_DATA 0x00000000 +#define DDRSS0_PI_110_DATA 0x00000000 +#define DDRSS0_PI_111_DATA 0x00000000 +#define DDRSS0_PI_112_DATA 0x00000000 +#define DDRSS0_PI_113_DATA 0x00000000 +#define DDRSS0_PI_114_DATA 0x00000000 +#define DDRSS0_PI_115_DATA 0x00000000 +#define DDRSS0_PI_116_DATA 0x00000000 +#define DDRSS0_PI_117_DATA 0x00000000 +#define DDRSS0_PI_118_DATA 0x00000000 +#define DDRSS0_PI_119_DATA 0x00000000 +#define DDRSS0_PI_120_DATA 0x00000000 +#define DDRSS0_PI_121_DATA 0x00000000 +#define DDRSS0_PI_122_DATA 0x00000000 +#define DDRSS0_PI_123_DATA 0x00000000 +#define DDRSS0_PI_124_DATA 0x00000000 +#define DDRSS0_PI_125_DATA 0x00000008 +#define DDRSS0_PI_126_DATA 0x00000000 +#define DDRSS0_PI_127_DATA 0x00000000 +#define DDRSS0_PI_128_DATA 0x00000000 +#define DDRSS0_PI_129_DATA 0x00000000 +#define DDRSS0_PI_130_DATA 0x00000000 +#define DDRSS0_PI_131_DATA 0x00000000 +#define DDRSS0_PI_132_DATA 0x00000000 +#define DDRSS0_PI_133_DATA 0x00000000 +#define DDRSS0_PI_134_DATA 0x00000002 +#define DDRSS0_PI_135_DATA 0x00000000 +#define DDRSS0_PI_136_DATA 0x00000000 +#define DDRSS0_PI_137_DATA 0x0000000A +#define DDRSS0_PI_138_DATA 0x00000019 +#define DDRSS0_PI_139_DATA 0x00000100 +#define DDRSS0_PI_140_DATA 0x00000000 +#define DDRSS0_PI_141_DATA 0x00000000 +#define DDRSS0_PI_142_DATA 0x00000000 +#define DDRSS0_PI_143_DATA 0x00000000 +#define DDRSS0_PI_144_DATA 0x01000000 +#define DDRSS0_PI_145_DATA 0x00010003 +#define DDRSS0_PI_146_DATA 0x02000101 +#define DDRSS0_PI_147_DATA 0x01030001 +#define DDRSS0_PI_148_DATA 0x00010400 +#define DDRSS0_PI_149_DATA 0x06000105 +#define DDRSS0_PI_150_DATA 0x01070001 +#define DDRSS0_PI_151_DATA 0x00000000 +#define DDRSS0_PI_152_DATA 0x00000000 +#define DDRSS0_PI_153_DATA 0x00000000 +#define DDRSS0_PI_154_DATA 0x00010001 +#define DDRSS0_PI_155_DATA 0x00000000 +#define DDRSS0_PI_156_DATA 0x00000000 +#define DDRSS0_PI_157_DATA 0x00000000 +#define DDRSS0_PI_158_DATA 0x00000000 +#define DDRSS0_PI_159_DATA 0x00000401 +#define DDRSS0_PI_160_DATA 0x00000000 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 +#define DDRSS0_PI_164_DATA 0x00000034 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 +#define DDRSS0_PI_167_DATA 0x02000200 +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 +#define DDRSS0_PI_171_DATA 0x0000032B +#define DDRSS0_PI_172_DATA 0x00001035 +#define DDRSS0_PI_173_DATA 0x0000032B +#define DDRSS0_PI_174_DATA 0x04001035 +#define DDRSS0_PI_175_DATA 0x01010404 +#define DDRSS0_PI_176_DATA 0x00001500 +#define DDRSS0_PI_177_DATA 0x00150015 +#define DDRSS0_PI_178_DATA 0x01000100 +#define DDRSS0_PI_179_DATA 0x00000100 +#define DDRSS0_PI_180_DATA 0x00000000 +#define DDRSS0_PI_181_DATA 0x01010101 +#define DDRSS0_PI_182_DATA 0x00000000 +#define DDRSS0_PI_183_DATA 0x00000000 +#define DDRSS0_PI_184_DATA 0x00000000 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 +#define DDRSS0_PI_187_DATA 0x00040402 +#define DDRSS0_PI_188_DATA 0x000D0035 +#define DDRSS0_PI_189_DATA 0x00218049 +#define DDRSS0_PI_190_DATA 0x00218049 +#define DDRSS0_PI_191_DATA 0x01000101 +#define DDRSS0_PI_192_DATA 0x0004000E +#define DDRSS0_PI_193_DATA 0x00040216 +#define DDRSS0_PI_194_DATA 0x01000216 +#define DDRSS0_PI_195_DATA 0x000F000F +#define DDRSS0_PI_196_DATA 0x02170100 +#define DDRSS0_PI_197_DATA 0x01000217 +#define DDRSS0_PI_198_DATA 0x02170217 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B +#define DDRSS0_PI_201_DATA 0x0A070601 +#define DDRSS0_PI_202_DATA 0x1F130A0D +#define DDRSS0_PI_203_DATA 0x1F130A14 +#define DDRSS0_PI_204_DATA 0x0000C014 +#define DDRSS0_PI_205_DATA 0x00C01000 +#define DDRSS0_PI_206_DATA 0x00C01000 +#define DDRSS0_PI_207_DATA 0x00021000 +#define DDRSS0_PI_208_DATA 0x0024000E +#define DDRSS0_PI_209_DATA 0x00240216 +#define DDRSS0_PI_210_DATA 0x00110216 +#define DDRSS0_PI_211_DATA 0x32000056 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 +#define DDRSS0_PI_214_DATA 0x03013212 +#define DDRSS0_PI_215_DATA 0x00003600 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 +#define DDRSS0_PI_220_DATA 0x0A032001 +#define DDRSS0_PI_221_DATA 0x2C31110A +#define DDRSS0_PI_222_DATA 0x00002918 +#define DDRSS0_PI_223_DATA 0x6000838E +#define DDRSS0_PI_224_DATA 0x1E202008 +#define DDRSS0_PI_225_DATA 0x2C311116 +#define DDRSS0_PI_226_DATA 0x00002918 +#define DDRSS0_PI_227_DATA 0x6000838E +#define DDRSS0_PI_228_DATA 0x1E202008 +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 +#define DDRSS0_PI_235_DATA 0x033B0016 +#define DDRSS0_PI_236_DATA 0x0303033B +#define DDRSS0_PI_237_DATA 0x002AF803 +#define DDRSS0_PI_238_DATA 0x0001ADAF +#define DDRSS0_PI_239_DATA 0x00000005 +#define DDRSS0_PI_240_DATA 0x0000006E +#define DDRSS0_PI_241_DATA 0x00000016 +#define DDRSS0_PI_242_DATA 0x000681C8 +#define DDRSS0_PI_243_DATA 0x0001ADAF +#define DDRSS0_PI_244_DATA 0x00000005 +#define DDRSS0_PI_245_DATA 0x000010A9 +#define DDRSS0_PI_246_DATA 0x0000033B +#define DDRSS0_PI_247_DATA 0x000681C8 +#define DDRSS0_PI_248_DATA 0x0001ADAF +#define DDRSS0_PI_249_DATA 0x00000005 +#define DDRSS0_PI_250_DATA 0x000010A9 +#define DDRSS0_PI_251_DATA 0x0100033B +#define DDRSS0_PI_252_DATA 0x00370040 +#define DDRSS0_PI_253_DATA 0x00010008 +#define DDRSS0_PI_254_DATA 0x08550040 +#define DDRSS0_PI_255_DATA 0x00010040 +#define DDRSS0_PI_256_DATA 0x08550040 +#define DDRSS0_PI_257_DATA 0x00000340 +#define DDRSS0_PI_258_DATA 0x006B006B +#define DDRSS0_PI_259_DATA 0x08040404 +#define DDRSS0_PI_260_DATA 0x00000055 +#define DDRSS0_PI_261_DATA 0x55083C5A +#define DDRSS0_PI_262_DATA 0x5A000000 +#define DDRSS0_PI_263_DATA 0x0055083C +#define DDRSS0_PI_264_DATA 0x3C5A0000 +#define DDRSS0_PI_265_DATA 0x00005508 +#define DDRSS0_PI_266_DATA 0x0C3C5A00 +#define DDRSS0_PI_267_DATA 0x080F0E0D +#define DDRSS0_PI_268_DATA 0x000B0A09 +#define DDRSS0_PI_269_DATA 0x00030201 +#define DDRSS0_PI_270_DATA 0x01000000 +#define DDRSS0_PI_271_DATA 0x04020201 +#define DDRSS0_PI_272_DATA 0x00080804 +#define DDRSS0_PI_273_DATA 0x00000000 +#define DDRSS0_PI_274_DATA 0x00000000 +#define DDRSS0_PI_275_DATA 0x00F30084 +#define DDRSS0_PI_276_DATA 0x00160000 +#define DDRSS0_PI_277_DATA 0x36F33FF4 +#define DDRSS0_PI_278_DATA 0x00160F27 +#define DDRSS0_PI_279_DATA 0x36F33FF4 +#define DDRSS0_PI_280_DATA 0x00160F27 +#define DDRSS0_PI_281_DATA 0x00F30084 +#define DDRSS0_PI_282_DATA 0x00160000 +#define DDRSS0_PI_283_DATA 0x36F33FF4 +#define DDRSS0_PI_284_DATA 0x00160F27 +#define DDRSS0_PI_285_DATA 0x36F33FF4 +#define DDRSS0_PI_286_DATA 0x00160F27 +#define DDRSS0_PI_287_DATA 0x00F30084 +#define DDRSS0_PI_288_DATA 0x00160000 +#define DDRSS0_PI_289_DATA 0x36F33FF4 +#define DDRSS0_PI_290_DATA 0x00160F27 +#define DDRSS0_PI_291_DATA 0x36F33FF4 +#define DDRSS0_PI_292_DATA 0x00160F27 +#define DDRSS0_PI_293_DATA 0x00F30084 +#define DDRSS0_PI_294_DATA 0x00160000 +#define DDRSS0_PI_295_DATA 0x36F33FF4 +#define DDRSS0_PI_296_DATA 0x00160F27 +#define DDRSS0_PI_297_DATA 0x36F33FF4 +#define DDRSS0_PI_298_DATA 0x00160F27 +#define DDRSS0_PI_299_DATA 0x00000000 + +#define DDRSS0_PHY_00_DATA 0x000004F0 +#define DDRSS0_PHY_01_DATA 0x00000000 +#define DDRSS0_PHY_02_DATA 0x00030200 +#define DDRSS0_PHY_03_DATA 0x00000000 +#define DDRSS0_PHY_04_DATA 0x00000000 +#define DDRSS0_PHY_05_DATA 0x01030000 +#define DDRSS0_PHY_06_DATA 0x00010000 +#define DDRSS0_PHY_07_DATA 0x01030004 +#define DDRSS0_PHY_08_DATA 0x01000000 +#define DDRSS0_PHY_09_DATA 0x00000000 +#define DDRSS0_PHY_10_DATA 0x00000000 +#define DDRSS0_PHY_11_DATA 0x01000001 +#define DDRSS0_PHY_12_DATA 0x00000200 +#define DDRSS0_PHY_13_DATA 0x000800C0 +#define DDRSS0_PHY_14_DATA 0x060100CC +#define DDRSS0_PHY_15_DATA 0x00030066 +#define DDRSS0_PHY_16_DATA 0x00000000 +#define DDRSS0_PHY_17_DATA 0x00000301 +#define DDRSS0_PHY_18_DATA 0x0000AAAA +#define DDRSS0_PHY_19_DATA 0x00005555 +#define DDRSS0_PHY_20_DATA 0x0000B5B5 +#define DDRSS0_PHY_21_DATA 0x00004A4A +#define DDRSS0_PHY_22_DATA 0x00005656 +#define DDRSS0_PHY_23_DATA 0x0000A9A9 +#define DDRSS0_PHY_24_DATA 0x0000A9A9 +#define DDRSS0_PHY_25_DATA 0x0000B5B5 +#define DDRSS0_PHY_26_DATA 0x00000000 +#define DDRSS0_PHY_27_DATA 0x00000000 +#define DDRSS0_PHY_28_DATA 0x2A000000 +#define DDRSS0_PHY_29_DATA 0x00000808 +#define DDRSS0_PHY_30_DATA 0x0F000000 +#define DDRSS0_PHY_31_DATA 0x00000F08 +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002002 +#define DDRSS0_PHY_34_DATA 0x00000000 +#define DDRSS0_PHY_35_DATA 0x00000000 +#define DDRSS0_PHY_36_DATA 0x55555555 +#define DDRSS0_PHY_37_DATA 0xAAAAAAAA +#define DDRSS0_PHY_38_DATA 0x55555555 +#define DDRSS0_PHY_39_DATA 0xAAAAAAAA +#define DDRSS0_PHY_40_DATA 0x00005555 +#define DDRSS0_PHY_41_DATA 0x01000100 +#define DDRSS0_PHY_42_DATA 0x00800180 +#define DDRSS0_PHY_43_DATA 0x00000001 +#define DDRSS0_PHY_44_DATA 0x00000000 +#define DDRSS0_PHY_45_DATA 0x00000000 +#define DDRSS0_PHY_46_DATA 0x00000000 +#define DDRSS0_PHY_47_DATA 0x00000000 +#define DDRSS0_PHY_48_DATA 0x00000000 +#define DDRSS0_PHY_49_DATA 0x00000000 +#define DDRSS0_PHY_50_DATA 0x00000000 +#define DDRSS0_PHY_51_DATA 0x00000000 +#define DDRSS0_PHY_52_DATA 0x00000000 +#define DDRSS0_PHY_53_DATA 0x00000000 +#define DDRSS0_PHY_54_DATA 0x00000000 +#define DDRSS0_PHY_55_DATA 0x00000000 +#define DDRSS0_PHY_56_DATA 0x00000000 +#define DDRSS0_PHY_57_DATA 0x00000000 +#define DDRSS0_PHY_58_DATA 0x00000000 +#define DDRSS0_PHY_59_DATA 0x00000000 +#define DDRSS0_PHY_60_DATA 0x00000000 +#define DDRSS0_PHY_61_DATA 0x00000000 +#define DDRSS0_PHY_62_DATA 0x00000000 +#define DDRSS0_PHY_63_DATA 0x00000000 +#define DDRSS0_PHY_64_DATA 0x00000000 +#define DDRSS0_PHY_65_DATA 0x00000000 +#define DDRSS0_PHY_66_DATA 0x00000104 +#define DDRSS0_PHY_67_DATA 0x00000120 +#define DDRSS0_PHY_68_DATA 0x00000000 +#define DDRSS0_PHY_69_DATA 0x00000000 +#define DDRSS0_PHY_70_DATA 0x00000000 +#define DDRSS0_PHY_71_DATA 0x00000000 +#define DDRSS0_PHY_72_DATA 0x00000000 +#define DDRSS0_PHY_73_DATA 0x00000000 +#define DDRSS0_PHY_74_DATA 0x00000000 +#define DDRSS0_PHY_75_DATA 0x00000001 +#define DDRSS0_PHY_76_DATA 0x07FF0000 +#define DDRSS0_PHY_77_DATA 0x0080081F +#define DDRSS0_PHY_78_DATA 0x00081020 +#define DDRSS0_PHY_79_DATA 0x04010000 +#define DDRSS0_PHY_80_DATA 0x00000000 +#define DDRSS0_PHY_81_DATA 0x00000000 +#define DDRSS0_PHY_82_DATA 0x00000000 +#define DDRSS0_PHY_83_DATA 0x00000100 +#define DDRSS0_PHY_84_DATA 0x01CC0C01 +#define DDRSS0_PHY_85_DATA 0x1003CC0C +#define DDRSS0_PHY_86_DATA 0x20000140 +#define DDRSS0_PHY_87_DATA 0x07FF0200 +#define DDRSS0_PHY_88_DATA 0x0000DD01 +#define DDRSS0_PHY_89_DATA 0x10100303 +#define DDRSS0_PHY_90_DATA 0x10101010 +#define DDRSS0_PHY_91_DATA 0x10101010 +#define DDRSS0_PHY_92_DATA 0x00021010 +#define DDRSS0_PHY_93_DATA 0x00100010 +#define DDRSS0_PHY_94_DATA 0x00100010 +#define DDRSS0_PHY_95_DATA 0x00100010 +#define DDRSS0_PHY_96_DATA 0x00100010 +#define DDRSS0_PHY_97_DATA 0x00050010 +#define DDRSS0_PHY_98_DATA 0x51517041 +#define DDRSS0_PHY_99_DATA 0x31C06001 +#define DDRSS0_PHY_100_DATA 0x07AB01AB +#define DDRSS0_PHY_101_DATA 0x00C0C001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 +#define DDRSS0_PHY_103_DATA 0x10001000 +#define DDRSS0_PHY_104_DATA 0x0C083E42 +#define DDRSS0_PHY_105_DATA 0x0F0C3701 +#define DDRSS0_PHY_106_DATA 0x01000140 +#define DDRSS0_PHY_107_DATA 0x0C000420 +#define DDRSS0_PHY_108_DATA 0x00000198 +#define DDRSS0_PHY_109_DATA 0x0A0000D0 +#define DDRSS0_PHY_110_DATA 0x00030200 +#define DDRSS0_PHY_111_DATA 0x02800000 +#define DDRSS0_PHY_112_DATA 0x80800000 +#define DDRSS0_PHY_113_DATA 0x000E2010 +#define DDRSS0_PHY_114_DATA 0x76543210 +#define DDRSS0_PHY_115_DATA 0x00000008 +#define DDRSS0_PHY_116_DATA 0x02800280 +#define DDRSS0_PHY_117_DATA 0x02800280 +#define DDRSS0_PHY_118_DATA 0x02800280 +#define DDRSS0_PHY_119_DATA 0x02800280 +#define DDRSS0_PHY_120_DATA 0x00000280 +#define DDRSS0_PHY_121_DATA 0x0000A000 +#define DDRSS0_PHY_122_DATA 0x00A000A0 +#define DDRSS0_PHY_123_DATA 0x00A000A0 +#define DDRSS0_PHY_124_DATA 0x00A000A0 +#define DDRSS0_PHY_125_DATA 0x00A000A0 +#define DDRSS0_PHY_126_DATA 0x00A000A0 +#define DDRSS0_PHY_127_DATA 0x00A000A0 +#define DDRSS0_PHY_128_DATA 0x00A000A0 +#define DDRSS0_PHY_129_DATA 0x00A000A0 +#define DDRSS0_PHY_130_DATA 0x01C200A0 +#define DDRSS0_PHY_131_DATA 0x01A00005 +#define DDRSS0_PHY_132_DATA 0x00000000 +#define DDRSS0_PHY_133_DATA 0x00000000 +#define DDRSS0_PHY_134_DATA 0x00080200 +#define DDRSS0_PHY_135_DATA 0x00000000 +#define DDRSS0_PHY_136_DATA 0x20202020 +#define DDRSS0_PHY_137_DATA 0x20202020 +#define DDRSS0_PHY_138_DATA 0xF0F02020 +#define DDRSS0_PHY_139_DATA 0x00000000 +#define DDRSS0_PHY_140_DATA 0x00000000 +#define DDRSS0_PHY_141_DATA 0x00000000 +#define DDRSS0_PHY_142_DATA 0x00000000 +#define DDRSS0_PHY_143_DATA 0x00000000 +#define DDRSS0_PHY_144_DATA 0x00000000 +#define DDRSS0_PHY_145_DATA 0x00000000 +#define DDRSS0_PHY_146_DATA 0x00000000 +#define DDRSS0_PHY_147_DATA 0x00000000 +#define DDRSS0_PHY_148_DATA 0x00000000 +#define DDRSS0_PHY_149_DATA 0x00000000 +#define DDRSS0_PHY_150_DATA 0x00000000 +#define DDRSS0_PHY_151_DATA 0x00000000 +#define DDRSS0_PHY_152_DATA 0x00000000 +#define DDRSS0_PHY_153_DATA 0x00000000 +#define DDRSS0_PHY_154_DATA 0x00000000 +#define DDRSS0_PHY_155_DATA 0x00000000 +#define DDRSS0_PHY_156_DATA 0x00000000 +#define DDRSS0_PHY_157_DATA 0x00000000 +#define DDRSS0_PHY_158_DATA 0x00000000 +#define DDRSS0_PHY_159_DATA 0x00000000 +#define DDRSS0_PHY_160_DATA 0x00000000 +#define DDRSS0_PHY_161_DATA 0x00000000 +#define DDRSS0_PHY_162_DATA 0x00000000 +#define DDRSS0_PHY_163_DATA 0x00000000 +#define DDRSS0_PHY_164_DATA 0x00000000 +#define DDRSS0_PHY_165_DATA 0x00000000 +#define DDRSS0_PHY_166_DATA 0x00000000 +#define DDRSS0_PHY_167_DATA 0x00000000 +#define DDRSS0_PHY_168_DATA 0x00000000 +#define DDRSS0_PHY_169_DATA 0x00000000 +#define DDRSS0_PHY_170_DATA 0x00000000 +#define DDRSS0_PHY_171_DATA 0x00000000 +#define DDRSS0_PHY_172_DATA 0x00000000 +#define DDRSS0_PHY_173_DATA 0x00000000 +#define DDRSS0_PHY_174_DATA 0x00000000 +#define DDRSS0_PHY_175_DATA 0x00000000 +#define DDRSS0_PHY_176_DATA 0x00000000 +#define DDRSS0_PHY_177_DATA 0x00000000 +#define DDRSS0_PHY_178_DATA 0x00000000 +#define DDRSS0_PHY_179_DATA 0x00000000 +#define DDRSS0_PHY_180_DATA 0x00000000 +#define DDRSS0_PHY_181_DATA 0x00000000 +#define DDRSS0_PHY_182_DATA 0x00000000 +#define DDRSS0_PHY_183_DATA 0x00000000 +#define DDRSS0_PHY_184_DATA 0x00000000 +#define DDRSS0_PHY_185_DATA 0x00000000 +#define DDRSS0_PHY_186_DATA 0x00000000 +#define DDRSS0_PHY_187_DATA 0x00000000 +#define DDRSS0_PHY_188_DATA 0x00000000 +#define DDRSS0_PHY_189_DATA 0x00000000 +#define DDRSS0_PHY_190_DATA 0x00000000 +#define DDRSS0_PHY_191_DATA 0x00000000 +#define DDRSS0_PHY_192_DATA 0x00000000 +#define DDRSS0_PHY_193_DATA 0x00000000 +#define DDRSS0_PHY_194_DATA 0x00000000 +#define DDRSS0_PHY_195_DATA 0x00000000 +#define DDRSS0_PHY_196_DATA 0x00000000 +#define DDRSS0_PHY_197_DATA 0x00000000 +#define DDRSS0_PHY_198_DATA 0x00000000 +#define DDRSS0_PHY_199_DATA 0x00000000 +#define DDRSS0_PHY_200_DATA 0x00000000 +#define DDRSS0_PHY_201_DATA 0x00000000 +#define DDRSS0_PHY_202_DATA 0x00000000 +#define DDRSS0_PHY_203_DATA 0x00000000 +#define DDRSS0_PHY_204_DATA 0x00000000 +#define DDRSS0_PHY_205_DATA 0x00000000 +#define DDRSS0_PHY_206_DATA 0x00000000 +#define DDRSS0_PHY_207_DATA 0x00000000 +#define DDRSS0_PHY_208_DATA 0x00000000 +#define DDRSS0_PHY_209_DATA 0x00000000 +#define DDRSS0_PHY_210_DATA 0x00000000 +#define DDRSS0_PHY_211_DATA 0x00000000 +#define DDRSS0_PHY_212_DATA 0x00000000 +#define DDRSS0_PHY_213_DATA 0x00000000 +#define DDRSS0_PHY_214_DATA 0x00000000 +#define DDRSS0_PHY_215_DATA 0x00000000 +#define DDRSS0_PHY_216_DATA 0x00000000 +#define DDRSS0_PHY_217_DATA 0x00000000 +#define DDRSS0_PHY_218_DATA 0x00000000 +#define DDRSS0_PHY_219_DATA 0x00000000 +#define DDRSS0_PHY_220_DATA 0x00000000 +#define DDRSS0_PHY_221_DATA 0x00000000 +#define DDRSS0_PHY_222_DATA 0x00000000 +#define DDRSS0_PHY_223_DATA 0x00000000 +#define DDRSS0_PHY_224_DATA 0x00000000 +#define DDRSS0_PHY_225_DATA 0x00000000 +#define DDRSS0_PHY_226_DATA 0x00000000 +#define DDRSS0_PHY_227_DATA 0x00000000 +#define DDRSS0_PHY_228_DATA 0x00000000 +#define DDRSS0_PHY_229_DATA 0x00000000 +#define DDRSS0_PHY_230_DATA 0x00000000 +#define DDRSS0_PHY_231_DATA 0x00000000 +#define DDRSS0_PHY_232_DATA 0x00000000 +#define DDRSS0_PHY_233_DATA 0x00000000 +#define DDRSS0_PHY_234_DATA 0x00000000 +#define DDRSS0_PHY_235_DATA 0x00000000 +#define DDRSS0_PHY_236_DATA 0x00000000 +#define DDRSS0_PHY_237_DATA 0x00000000 +#define DDRSS0_PHY_238_DATA 0x00000000 +#define DDRSS0_PHY_239_DATA 0x00000000 +#define DDRSS0_PHY_240_DATA 0x00000000 +#define DDRSS0_PHY_241_DATA 0x00000000 +#define DDRSS0_PHY_242_DATA 0x00000000 +#define DDRSS0_PHY_243_DATA 0x00000000 +#define DDRSS0_PHY_244_DATA 0x00000000 +#define DDRSS0_PHY_245_DATA 0x00000000 +#define DDRSS0_PHY_246_DATA 0x00000000 +#define DDRSS0_PHY_247_DATA 0x00000000 +#define DDRSS0_PHY_248_DATA 0x00000000 +#define DDRSS0_PHY_249_DATA 0x00000000 +#define DDRSS0_PHY_250_DATA 0x00000000 +#define DDRSS0_PHY_251_DATA 0x00000000 +#define DDRSS0_PHY_252_DATA 0x00000000 +#define DDRSS0_PHY_253_DATA 0x00000000 +#define DDRSS0_PHY_254_DATA 0x00000000 +#define DDRSS0_PHY_255_DATA 0x00000000 +#define DDRSS0_PHY_256_DATA 0x000004F0 +#define DDRSS0_PHY_257_DATA 0x00000000 +#define DDRSS0_PHY_258_DATA 0x00030200 +#define DDRSS0_PHY_259_DATA 0x00000000 +#define DDRSS0_PHY_260_DATA 0x00000000 +#define DDRSS0_PHY_261_DATA 0x01030000 +#define DDRSS0_PHY_262_DATA 0x00010000 +#define DDRSS0_PHY_263_DATA 0x01030004 +#define DDRSS0_PHY_264_DATA 0x01000000 +#define DDRSS0_PHY_265_DATA 0x00000000 +#define DDRSS0_PHY_266_DATA 0x00000000 +#define DDRSS0_PHY_267_DATA 0x01000001 +#define DDRSS0_PHY_268_DATA 0x00000200 +#define DDRSS0_PHY_269_DATA 0x000800C0 +#define DDRSS0_PHY_270_DATA 0x060100CC +#define DDRSS0_PHY_271_DATA 0x00030066 +#define DDRSS0_PHY_272_DATA 0x00000000 +#define DDRSS0_PHY_273_DATA 0x00000301 +#define DDRSS0_PHY_274_DATA 0x0000AAAA +#define DDRSS0_PHY_275_DATA 0x00005555 +#define DDRSS0_PHY_276_DATA 0x0000B5B5 +#define DDRSS0_PHY_277_DATA 0x00004A4A +#define DDRSS0_PHY_278_DATA 0x00005656 +#define DDRSS0_PHY_279_DATA 0x0000A9A9 +#define DDRSS0_PHY_280_DATA 0x0000A9A9 +#define DDRSS0_PHY_281_DATA 0x0000B5B5 +#define DDRSS0_PHY_282_DATA 0x00000000 +#define DDRSS0_PHY_283_DATA 0x00000000 +#define DDRSS0_PHY_284_DATA 0x2A000000 +#define DDRSS0_PHY_285_DATA 0x00000808 +#define DDRSS0_PHY_286_DATA 0x0F000000 +#define DDRSS0_PHY_287_DATA 0x00000F08 +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002002 +#define DDRSS0_PHY_290_DATA 0x00000000 +#define DDRSS0_PHY_291_DATA 0x00000000 +#define DDRSS0_PHY_292_DATA 0x55555555 +#define DDRSS0_PHY_293_DATA 0xAAAAAAAA +#define DDRSS0_PHY_294_DATA 0x55555555 +#define DDRSS0_PHY_295_DATA 0xAAAAAAAA +#define DDRSS0_PHY_296_DATA 0x00005555 +#define DDRSS0_PHY_297_DATA 0x01000100 +#define DDRSS0_PHY_298_DATA 0x00800180 +#define DDRSS0_PHY_299_DATA 0x00000000 +#define DDRSS0_PHY_300_DATA 0x00000000 +#define DDRSS0_PHY_301_DATA 0x00000000 +#define DDRSS0_PHY_302_DATA 0x00000000 +#define DDRSS0_PHY_303_DATA 0x00000000 +#define DDRSS0_PHY_304_DATA 0x00000000 +#define DDRSS0_PHY_305_DATA 0x00000000 +#define DDRSS0_PHY_306_DATA 0x00000000 +#define DDRSS0_PHY_307_DATA 0x00000000 +#define DDRSS0_PHY_308_DATA 0x00000000 +#define DDRSS0_PHY_309_DATA 0x00000000 +#define DDRSS0_PHY_310_DATA 0x00000000 +#define DDRSS0_PHY_311_DATA 0x00000000 +#define DDRSS0_PHY_312_DATA 0x00000000 +#define DDRSS0_PHY_313_DATA 0x00000000 +#define DDRSS0_PHY_314_DATA 0x00000000 +#define DDRSS0_PHY_315_DATA 0x00000000 +#define DDRSS0_PHY_316_DATA 0x00000000 +#define DDRSS0_PHY_317_DATA 0x00000000 +#define DDRSS0_PHY_318_DATA 0x00000000 +#define DDRSS0_PHY_319_DATA 0x00000000 +#define DDRSS0_PHY_320_DATA 0x00000000 +#define DDRSS0_PHY_321_DATA 0x00000000 +#define DDRSS0_PHY_322_DATA 0x00000104 +#define DDRSS0_PHY_323_DATA 0x00000120 +#define DDRSS0_PHY_324_DATA 0x00000000 +#define DDRSS0_PHY_325_DATA 0x00000000 +#define DDRSS0_PHY_326_DATA 0x00000000 +#define DDRSS0_PHY_327_DATA 0x00000000 +#define DDRSS0_PHY_328_DATA 0x00000000 +#define DDRSS0_PHY_329_DATA 0x00000000 +#define DDRSS0_PHY_330_DATA 0x00000000 +#define DDRSS0_PHY_331_DATA 0x00000001 +#define DDRSS0_PHY_332_DATA 0x07FF0000 +#define DDRSS0_PHY_333_DATA 0x0080081F +#define DDRSS0_PHY_334_DATA 0x00081020 +#define DDRSS0_PHY_335_DATA 0x04010000 +#define DDRSS0_PHY_336_DATA 0x00000000 +#define DDRSS0_PHY_337_DATA 0x00000000 +#define DDRSS0_PHY_338_DATA 0x00000000 +#define DDRSS0_PHY_339_DATA 0x00000100 +#define DDRSS0_PHY_340_DATA 0x01CC0C01 +#define DDRSS0_PHY_341_DATA 0x1003CC0C +#define DDRSS0_PHY_342_DATA 0x20000140 +#define DDRSS0_PHY_343_DATA 0x07FF0200 +#define DDRSS0_PHY_344_DATA 0x0000DD01 +#define DDRSS0_PHY_345_DATA 0x10100303 +#define DDRSS0_PHY_346_DATA 0x10101010 +#define DDRSS0_PHY_347_DATA 0x10101010 +#define DDRSS0_PHY_348_DATA 0x00021010 +#define DDRSS0_PHY_349_DATA 0x00100010 +#define DDRSS0_PHY_350_DATA 0x00100010 +#define DDRSS0_PHY_351_DATA 0x00100010 +#define DDRSS0_PHY_352_DATA 0x00100010 +#define DDRSS0_PHY_353_DATA 0x00050010 +#define DDRSS0_PHY_354_DATA 0x51517041 +#define DDRSS0_PHY_355_DATA 0x31C06001 +#define DDRSS0_PHY_356_DATA 0x07AB01AB +#define DDRSS0_PHY_357_DATA 0x00C0C001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 +#define DDRSS0_PHY_359_DATA 0x10001000 +#define DDRSS0_PHY_360_DATA 0x0C083E42 +#define DDRSS0_PHY_361_DATA 0x0F0C3701 +#define DDRSS0_PHY_362_DATA 0x01000140 +#define DDRSS0_PHY_363_DATA 0x0C000420 +#define DDRSS0_PHY_364_DATA 0x00000198 +#define DDRSS0_PHY_365_DATA 0x0A0000D0 +#define DDRSS0_PHY_366_DATA 0x00030200 +#define DDRSS0_PHY_367_DATA 0x02800000 +#define DDRSS0_PHY_368_DATA 0x80800000 +#define DDRSS0_PHY_369_DATA 0x000E2010 +#define DDRSS0_PHY_370_DATA 0x76543210 +#define DDRSS0_PHY_371_DATA 0x00000008 +#define DDRSS0_PHY_372_DATA 0x02800280 +#define DDRSS0_PHY_373_DATA 0x02800280 +#define DDRSS0_PHY_374_DATA 0x02800280 +#define DDRSS0_PHY_375_DATA 0x02800280 +#define DDRSS0_PHY_376_DATA 0x00000280 +#define DDRSS0_PHY_377_DATA 0x0000A000 +#define DDRSS0_PHY_378_DATA 0x00A000A0 +#define DDRSS0_PHY_379_DATA 0x00A000A0 +#define DDRSS0_PHY_380_DATA 0x00A000A0 +#define DDRSS0_PHY_381_DATA 0x00A000A0 +#define DDRSS0_PHY_382_DATA 0x00A000A0 +#define DDRSS0_PHY_383_DATA 0x00A000A0 +#define DDRSS0_PHY_384_DATA 0x00A000A0 +#define DDRSS0_PHY_385_DATA 0x00A000A0 +#define DDRSS0_PHY_386_DATA 0x01C200A0 +#define DDRSS0_PHY_387_DATA 0x01A00005 +#define DDRSS0_PHY_388_DATA 0x00000000 +#define DDRSS0_PHY_389_DATA 0x00000000 +#define DDRSS0_PHY_390_DATA 0x00080200 +#define DDRSS0_PHY_391_DATA 0x00000000 +#define DDRSS0_PHY_392_DATA 0x20202020 +#define DDRSS0_PHY_393_DATA 0x20202020 +#define DDRSS0_PHY_394_DATA 0xF0F02020 +#define DDRSS0_PHY_395_DATA 0x00000000 +#define DDRSS0_PHY_396_DATA 0x00000000 +#define DDRSS0_PHY_397_DATA 0x00000000 +#define DDRSS0_PHY_398_DATA 0x00000000 +#define DDRSS0_PHY_399_DATA 0x00000000 +#define DDRSS0_PHY_400_DATA 0x00000000 +#define DDRSS0_PHY_401_DATA 0x00000000 +#define DDRSS0_PHY_402_DATA 0x00000000 +#define DDRSS0_PHY_403_DATA 0x00000000 +#define DDRSS0_PHY_404_DATA 0x00000000 +#define DDRSS0_PHY_405_DATA 0x00000000 +#define DDRSS0_PHY_406_DATA 0x00000000 +#define DDRSS0_PHY_407_DATA 0x00000000 +#define DDRSS0_PHY_408_DATA 0x00000000 +#define DDRSS0_PHY_409_DATA 0x00000000 +#define DDRSS0_PHY_410_DATA 0x00000000 +#define DDRSS0_PHY_411_DATA 0x00000000 +#define DDRSS0_PHY_412_DATA 0x00000000 +#define DDRSS0_PHY_413_DATA 0x00000000 +#define DDRSS0_PHY_414_DATA 0x00000000 +#define DDRSS0_PHY_415_DATA 0x00000000 +#define DDRSS0_PHY_416_DATA 0x00000000 +#define DDRSS0_PHY_417_DATA 0x00000000 +#define DDRSS0_PHY_418_DATA 0x00000000 +#define DDRSS0_PHY_419_DATA 0x00000000 +#define DDRSS0_PHY_420_DATA 0x00000000 +#define DDRSS0_PHY_421_DATA 0x00000000 +#define DDRSS0_PHY_422_DATA 0x00000000 +#define DDRSS0_PHY_423_DATA 0x00000000 +#define DDRSS0_PHY_424_DATA 0x00000000 +#define DDRSS0_PHY_425_DATA 0x00000000 +#define DDRSS0_PHY_426_DATA 0x00000000 +#define DDRSS0_PHY_427_DATA 0x00000000 +#define DDRSS0_PHY_428_DATA 0x00000000 +#define DDRSS0_PHY_429_DATA 0x00000000 +#define DDRSS0_PHY_430_DATA 0x00000000 +#define DDRSS0_PHY_431_DATA 0x00000000 +#define DDRSS0_PHY_432_DATA 0x00000000 +#define DDRSS0_PHY_433_DATA 0x00000000 +#define DDRSS0_PHY_434_DATA 0x00000000 +#define DDRSS0_PHY_435_DATA 0x00000000 +#define DDRSS0_PHY_436_DATA 0x00000000 +#define DDRSS0_PHY_437_DATA 0x00000000 +#define DDRSS0_PHY_438_DATA 0x00000000 +#define DDRSS0_PHY_439_DATA 0x00000000 +#define DDRSS0_PHY_440_DATA 0x00000000 +#define DDRSS0_PHY_441_DATA 0x00000000 +#define DDRSS0_PHY_442_DATA 0x00000000 +#define DDRSS0_PHY_443_DATA 0x00000000 +#define DDRSS0_PHY_444_DATA 0x00000000 +#define DDRSS0_PHY_445_DATA 0x00000000 +#define DDRSS0_PHY_446_DATA 0x00000000 +#define DDRSS0_PHY_447_DATA 0x00000000 +#define DDRSS0_PHY_448_DATA 0x00000000 +#define DDRSS0_PHY_449_DATA 0x00000000 +#define DDRSS0_PHY_450_DATA 0x00000000 +#define DDRSS0_PHY_451_DATA 0x00000000 +#define DDRSS0_PHY_452_DATA 0x00000000 +#define DDRSS0_PHY_453_DATA 0x00000000 +#define DDRSS0_PHY_454_DATA 0x00000000 +#define DDRSS0_PHY_455_DATA 0x00000000 +#define DDRSS0_PHY_456_DATA 0x00000000 +#define DDRSS0_PHY_457_DATA 0x00000000 +#define DDRSS0_PHY_458_DATA 0x00000000 +#define DDRSS0_PHY_459_DATA 0x00000000 +#define DDRSS0_PHY_460_DATA 0x00000000 +#define DDRSS0_PHY_461_DATA 0x00000000 +#define DDRSS0_PHY_462_DATA 0x00000000 +#define DDRSS0_PHY_463_DATA 0x00000000 +#define DDRSS0_PHY_464_DATA 0x00000000 +#define DDRSS0_PHY_465_DATA 0x00000000 +#define DDRSS0_PHY_466_DATA 0x00000000 +#define DDRSS0_PHY_467_DATA 0x00000000 +#define DDRSS0_PHY_468_DATA 0x00000000 +#define DDRSS0_PHY_469_DATA 0x00000000 +#define DDRSS0_PHY_470_DATA 0x00000000 +#define DDRSS0_PHY_471_DATA 0x00000000 +#define DDRSS0_PHY_472_DATA 0x00000000 +#define DDRSS0_PHY_473_DATA 0x00000000 +#define DDRSS0_PHY_474_DATA 0x00000000 +#define DDRSS0_PHY_475_DATA 0x00000000 +#define DDRSS0_PHY_476_DATA 0x00000000 +#define DDRSS0_PHY_477_DATA 0x00000000 +#define DDRSS0_PHY_478_DATA 0x00000000 +#define DDRSS0_PHY_479_DATA 0x00000000 +#define DDRSS0_PHY_480_DATA 0x00000000 +#define DDRSS0_PHY_481_DATA 0x00000000 +#define DDRSS0_PHY_482_DATA 0x00000000 +#define DDRSS0_PHY_483_DATA 0x00000000 +#define DDRSS0_PHY_484_DATA 0x00000000 +#define DDRSS0_PHY_485_DATA 0x00000000 +#define DDRSS0_PHY_486_DATA 0x00000000 +#define DDRSS0_PHY_487_DATA 0x00000000 +#define DDRSS0_PHY_488_DATA 0x00000000 +#define DDRSS0_PHY_489_DATA 0x00000000 +#define DDRSS0_PHY_490_DATA 0x00000000 +#define DDRSS0_PHY_491_DATA 0x00000000 +#define DDRSS0_PHY_492_DATA 0x00000000 +#define DDRSS0_PHY_493_DATA 0x00000000 +#define DDRSS0_PHY_494_DATA 0x00000000 +#define DDRSS0_PHY_495_DATA 0x00000000 +#define DDRSS0_PHY_496_DATA 0x00000000 +#define DDRSS0_PHY_497_DATA 0x00000000 +#define DDRSS0_PHY_498_DATA 0x00000000 +#define DDRSS0_PHY_499_DATA 0x00000000 +#define DDRSS0_PHY_500_DATA 0x00000000 +#define DDRSS0_PHY_501_DATA 0x00000000 +#define DDRSS0_PHY_502_DATA 0x00000000 +#define DDRSS0_PHY_503_DATA 0x00000000 +#define DDRSS0_PHY_504_DATA 0x00000000 +#define DDRSS0_PHY_505_DATA 0x00000000 +#define DDRSS0_PHY_506_DATA 0x00000000 +#define DDRSS0_PHY_507_DATA 0x00000000 +#define DDRSS0_PHY_508_DATA 0x00000000 +#define DDRSS0_PHY_509_DATA 0x00000000 +#define DDRSS0_PHY_510_DATA 0x00000000 +#define DDRSS0_PHY_511_DATA 0x00000000 +#define DDRSS0_PHY_512_DATA 0x000004F0 +#define DDRSS0_PHY_513_DATA 0x00000000 +#define DDRSS0_PHY_514_DATA 0x00030200 +#define DDRSS0_PHY_515_DATA 0x00000000 +#define DDRSS0_PHY_516_DATA 0x00000000 +#define DDRSS0_PHY_517_DATA 0x01030000 +#define DDRSS0_PHY_518_DATA 0x00010000 +#define DDRSS0_PHY_519_DATA 0x01030004 +#define DDRSS0_PHY_520_DATA 0x01000000 +#define DDRSS0_PHY_521_DATA 0x00000000 +#define DDRSS0_PHY_522_DATA 0x00000000 +#define DDRSS0_PHY_523_DATA 0x01000001 +#define DDRSS0_PHY_524_DATA 0x00000200 +#define DDRSS0_PHY_525_DATA 0x000800C0 +#define DDRSS0_PHY_526_DATA 0x060100CC +#define DDRSS0_PHY_527_DATA 0x00030066 +#define DDRSS0_PHY_528_DATA 0x00000000 +#define DDRSS0_PHY_529_DATA 0x00000301 +#define DDRSS0_PHY_530_DATA 0x0000AAAA +#define DDRSS0_PHY_531_DATA 0x00005555 +#define DDRSS0_PHY_532_DATA 0x0000B5B5 +#define DDRSS0_PHY_533_DATA 0x00004A4A +#define DDRSS0_PHY_534_DATA 0x00005656 +#define DDRSS0_PHY_535_DATA 0x0000A9A9 +#define DDRSS0_PHY_536_DATA 0x0000A9A9 +#define DDRSS0_PHY_537_DATA 0x0000B5B5 +#define DDRSS0_PHY_538_DATA 0x00000000 +#define DDRSS0_PHY_539_DATA 0x00000000 +#define DDRSS0_PHY_540_DATA 0x2A000000 +#define DDRSS0_PHY_541_DATA 0x00000808 +#define DDRSS0_PHY_542_DATA 0x0F000000 +#define DDRSS0_PHY_543_DATA 0x00000F08 +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002002 +#define DDRSS0_PHY_546_DATA 0x00000000 +#define DDRSS0_PHY_547_DATA 0x00000000 +#define DDRSS0_PHY_548_DATA 0x55555555 +#define DDRSS0_PHY_549_DATA 0xAAAAAAAA +#define DDRSS0_PHY_550_DATA 0x55555555 +#define DDRSS0_PHY_551_DATA 0xAAAAAAAA +#define DDRSS0_PHY_552_DATA 0x00005555 +#define DDRSS0_PHY_553_DATA 0x01000100 +#define DDRSS0_PHY_554_DATA 0x00800180 +#define DDRSS0_PHY_555_DATA 0x00000001 +#define DDRSS0_PHY_556_DATA 0x00000000 +#define DDRSS0_PHY_557_DATA 0x00000000 +#define DDRSS0_PHY_558_DATA 0x00000000 +#define DDRSS0_PHY_559_DATA 0x00000000 +#define DDRSS0_PHY_560_DATA 0x00000000 +#define DDRSS0_PHY_561_DATA 0x00000000 +#define DDRSS0_PHY_562_DATA 0x00000000 +#define DDRSS0_PHY_563_DATA 0x00000000 +#define DDRSS0_PHY_564_DATA 0x00000000 +#define DDRSS0_PHY_565_DATA 0x00000000 +#define DDRSS0_PHY_566_DATA 0x00000000 +#define DDRSS0_PHY_567_DATA 0x00000000 +#define DDRSS0_PHY_568_DATA 0x00000000 +#define DDRSS0_PHY_569_DATA 0x00000000 +#define DDRSS0_PHY_570_DATA 0x00000000 +#define DDRSS0_PHY_571_DATA 0x00000000 +#define DDRSS0_PHY_572_DATA 0x00000000 +#define DDRSS0_PHY_573_DATA 0x00000000 +#define DDRSS0_PHY_574_DATA 0x00000000 +#define DDRSS0_PHY_575_DATA 0x00000000 +#define DDRSS0_PHY_576_DATA 0x00000000 +#define DDRSS0_PHY_577_DATA 0x00000000 +#define DDRSS0_PHY_578_DATA 0x00000104 +#define DDRSS0_PHY_579_DATA 0x00000120 +#define DDRSS0_PHY_580_DATA 0x00000000 +#define DDRSS0_PHY_581_DATA 0x00000000 +#define DDRSS0_PHY_582_DATA 0x00000000 +#define DDRSS0_PHY_583_DATA 0x00000000 +#define DDRSS0_PHY_584_DATA 0x00000000 +#define DDRSS0_PHY_585_DATA 0x00000000 +#define DDRSS0_PHY_586_DATA 0x00000000 +#define DDRSS0_PHY_587_DATA 0x00000001 +#define DDRSS0_PHY_588_DATA 0x07FF0000 +#define DDRSS0_PHY_589_DATA 0x0080081F +#define DDRSS0_PHY_590_DATA 0x00081020 +#define DDRSS0_PHY_591_DATA 0x04010000 +#define DDRSS0_PHY_592_DATA 0x00000000 +#define DDRSS0_PHY_593_DATA 0x00000000 +#define DDRSS0_PHY_594_DATA 0x00000000 +#define DDRSS0_PHY_595_DATA 0x00000100 +#define DDRSS0_PHY_596_DATA 0x01CC0C01 +#define DDRSS0_PHY_597_DATA 0x1003CC0C +#define DDRSS0_PHY_598_DATA 0x20000140 +#define DDRSS0_PHY_599_DATA 0x07FF0200 +#define DDRSS0_PHY_600_DATA 0x0000DD01 +#define DDRSS0_PHY_601_DATA 0x10100303 +#define DDRSS0_PHY_602_DATA 0x10101010 +#define DDRSS0_PHY_603_DATA 0x10101010 +#define DDRSS0_PHY_604_DATA 0x00021010 +#define DDRSS0_PHY_605_DATA 0x00100010 +#define DDRSS0_PHY_606_DATA 0x00100010 +#define DDRSS0_PHY_607_DATA 0x00100010 +#define DDRSS0_PHY_608_DATA 0x00100010 +#define DDRSS0_PHY_609_DATA 0x00050010 +#define DDRSS0_PHY_610_DATA 0x51517041 +#define DDRSS0_PHY_611_DATA 0x31C06001 +#define DDRSS0_PHY_612_DATA 0x07AB01AB +#define DDRSS0_PHY_613_DATA 0x00C0C001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 +#define DDRSS0_PHY_615_DATA 0x10001000 +#define DDRSS0_PHY_616_DATA 0x0C083E42 +#define DDRSS0_PHY_617_DATA 0x0F0C3701 +#define DDRSS0_PHY_618_DATA 0x01000140 +#define DDRSS0_PHY_619_DATA 0x0C000420 +#define DDRSS0_PHY_620_DATA 0x00000198 +#define DDRSS0_PHY_621_DATA 0x0A0000D0 +#define DDRSS0_PHY_622_DATA 0x00030200 +#define DDRSS0_PHY_623_DATA 0x02800000 +#define DDRSS0_PHY_624_DATA 0x80800000 +#define DDRSS0_PHY_625_DATA 0x000E2010 +#define DDRSS0_PHY_626_DATA 0x76543210 +#define DDRSS0_PHY_627_DATA 0x00000008 +#define DDRSS0_PHY_628_DATA 0x02800280 +#define DDRSS0_PHY_629_DATA 0x02800280 +#define DDRSS0_PHY_630_DATA 0x02800280 +#define DDRSS0_PHY_631_DATA 0x02800280 +#define DDRSS0_PHY_632_DATA 0x00000280 +#define DDRSS0_PHY_633_DATA 0x0000A000 +#define DDRSS0_PHY_634_DATA 0x00A000A0 +#define DDRSS0_PHY_635_DATA 0x00A000A0 +#define DDRSS0_PHY_636_DATA 0x00A000A0 +#define DDRSS0_PHY_637_DATA 0x00A000A0 +#define DDRSS0_PHY_638_DATA 0x00A000A0 +#define DDRSS0_PHY_639_DATA 0x00A000A0 +#define DDRSS0_PHY_640_DATA 0x00A000A0 +#define DDRSS0_PHY_641_DATA 0x00A000A0 +#define DDRSS0_PHY_642_DATA 0x01C200A0 +#define DDRSS0_PHY_643_DATA 0x01A00005 +#define DDRSS0_PHY_644_DATA 0x00000000 +#define DDRSS0_PHY_645_DATA 0x00000000 +#define DDRSS0_PHY_646_DATA 0x00080200 +#define DDRSS0_PHY_647_DATA 0x00000000 +#define DDRSS0_PHY_648_DATA 0x20202020 +#define DDRSS0_PHY_649_DATA 0x20202020 +#define DDRSS0_PHY_650_DATA 0xF0F02020 +#define DDRSS0_PHY_651_DATA 0x00000000 +#define DDRSS0_PHY_652_DATA 0x00000000 +#define DDRSS0_PHY_653_DATA 0x00000000 +#define DDRSS0_PHY_654_DATA 0x00000000 +#define DDRSS0_PHY_655_DATA 0x00000000 +#define DDRSS0_PHY_656_DATA 0x00000000 +#define DDRSS0_PHY_657_DATA 0x00000000 +#define DDRSS0_PHY_658_DATA 0x00000000 +#define DDRSS0_PHY_659_DATA 0x00000000 +#define DDRSS0_PHY_660_DATA 0x00000000 +#define DDRSS0_PHY_661_DATA 0x00000000 +#define DDRSS0_PHY_662_DATA 0x00000000 +#define DDRSS0_PHY_663_DATA 0x00000000 +#define DDRSS0_PHY_664_DATA 0x00000000 +#define DDRSS0_PHY_665_DATA 0x00000000 +#define DDRSS0_PHY_666_DATA 0x00000000 +#define DDRSS0_PHY_667_DATA 0x00000000 +#define DDRSS0_PHY_668_DATA 0x00000000 +#define DDRSS0_PHY_669_DATA 0x00000000 +#define DDRSS0_PHY_670_DATA 0x00000000 +#define DDRSS0_PHY_671_DATA 0x00000000 +#define DDRSS0_PHY_672_DATA 0x00000000 +#define DDRSS0_PHY_673_DATA 0x00000000 +#define DDRSS0_PHY_674_DATA 0x00000000 +#define DDRSS0_PHY_675_DATA 0x00000000 +#define DDRSS0_PHY_676_DATA 0x00000000 +#define DDRSS0_PHY_677_DATA 0x00000000 +#define DDRSS0_PHY_678_DATA 0x00000000 +#define DDRSS0_PHY_679_DATA 0x00000000 +#define DDRSS0_PHY_680_DATA 0x00000000 +#define DDRSS0_PHY_681_DATA 0x00000000 +#define DDRSS0_PHY_682_DATA 0x00000000 +#define DDRSS0_PHY_683_DATA 0x00000000 +#define DDRSS0_PHY_684_DATA 0x00000000 +#define DDRSS0_PHY_685_DATA 0x00000000 +#define DDRSS0_PHY_686_DATA 0x00000000 +#define DDRSS0_PHY_687_DATA 0x00000000 +#define DDRSS0_PHY_688_DATA 0x00000000 +#define DDRSS0_PHY_689_DATA 0x00000000 +#define DDRSS0_PHY_690_DATA 0x00000000 +#define DDRSS0_PHY_691_DATA 0x00000000 +#define DDRSS0_PHY_692_DATA 0x00000000 +#define DDRSS0_PHY_693_DATA 0x00000000 +#define DDRSS0_PHY_694_DATA 0x00000000 +#define DDRSS0_PHY_695_DATA 0x00000000 +#define DDRSS0_PHY_696_DATA 0x00000000 +#define DDRSS0_PHY_697_DATA 0x00000000 +#define DDRSS0_PHY_698_DATA 0x00000000 +#define DDRSS0_PHY_699_DATA 0x00000000 +#define DDRSS0_PHY_700_DATA 0x00000000 +#define DDRSS0_PHY_701_DATA 0x00000000 +#define DDRSS0_PHY_702_DATA 0x00000000 +#define DDRSS0_PHY_703_DATA 0x00000000 +#define DDRSS0_PHY_704_DATA 0x00000000 +#define DDRSS0_PHY_705_DATA 0x00000000 +#define DDRSS0_PHY_706_DATA 0x00000000 +#define DDRSS0_PHY_707_DATA 0x00000000 +#define DDRSS0_PHY_708_DATA 0x00000000 +#define DDRSS0_PHY_709_DATA 0x00000000 +#define DDRSS0_PHY_710_DATA 0x00000000 +#define DDRSS0_PHY_711_DATA 0x00000000 +#define DDRSS0_PHY_712_DATA 0x00000000 +#define DDRSS0_PHY_713_DATA 0x00000000 +#define DDRSS0_PHY_714_DATA 0x00000000 +#define DDRSS0_PHY_715_DATA 0x00000000 +#define DDRSS0_PHY_716_DATA 0x00000000 +#define DDRSS0_PHY_717_DATA 0x00000000 +#define DDRSS0_PHY_718_DATA 0x00000000 +#define DDRSS0_PHY_719_DATA 0x00000000 +#define DDRSS0_PHY_720_DATA 0x00000000 +#define DDRSS0_PHY_721_DATA 0x00000000 +#define DDRSS0_PHY_722_DATA 0x00000000 +#define DDRSS0_PHY_723_DATA 0x00000000 +#define DDRSS0_PHY_724_DATA 0x00000000 +#define DDRSS0_PHY_725_DATA 0x00000000 +#define DDRSS0_PHY_726_DATA 0x00000000 +#define DDRSS0_PHY_727_DATA 0x00000000 +#define DDRSS0_PHY_728_DATA 0x00000000 +#define DDRSS0_PHY_729_DATA 0x00000000 +#define DDRSS0_PHY_730_DATA 0x00000000 +#define DDRSS0_PHY_731_DATA 0x00000000 +#define DDRSS0_PHY_732_DATA 0x00000000 +#define DDRSS0_PHY_733_DATA 0x00000000 +#define DDRSS0_PHY_734_DATA 0x00000000 +#define DDRSS0_PHY_735_DATA 0x00000000 +#define DDRSS0_PHY_736_DATA 0x00000000 +#define DDRSS0_PHY_737_DATA 0x00000000 +#define DDRSS0_PHY_738_DATA 0x00000000 +#define DDRSS0_PHY_739_DATA 0x00000000 +#define DDRSS0_PHY_740_DATA 0x00000000 +#define DDRSS0_PHY_741_DATA 0x00000000 +#define DDRSS0_PHY_742_DATA 0x00000000 +#define DDRSS0_PHY_743_DATA 0x00000000 +#define DDRSS0_PHY_744_DATA 0x00000000 +#define DDRSS0_PHY_745_DATA 0x00000000 +#define DDRSS0_PHY_746_DATA 0x00000000 +#define DDRSS0_PHY_747_DATA 0x00000000 +#define DDRSS0_PHY_748_DATA 0x00000000 +#define DDRSS0_PHY_749_DATA 0x00000000 +#define DDRSS0_PHY_750_DATA 0x00000000 +#define DDRSS0_PHY_751_DATA 0x00000000 +#define DDRSS0_PHY_752_DATA 0x00000000 +#define DDRSS0_PHY_753_DATA 0x00000000 +#define DDRSS0_PHY_754_DATA 0x00000000 +#define DDRSS0_PHY_755_DATA 0x00000000 +#define DDRSS0_PHY_756_DATA 0x00000000 +#define DDRSS0_PHY_757_DATA 0x00000000 +#define DDRSS0_PHY_758_DATA 0x00000000 +#define DDRSS0_PHY_759_DATA 0x00000000 +#define DDRSS0_PHY_760_DATA 0x00000000 +#define DDRSS0_PHY_761_DATA 0x00000000 +#define DDRSS0_PHY_762_DATA 0x00000000 +#define DDRSS0_PHY_763_DATA 0x00000000 +#define DDRSS0_PHY_764_DATA 0x00000000 +#define DDRSS0_PHY_765_DATA 0x00000000 +#define DDRSS0_PHY_766_DATA 0x00000000 +#define DDRSS0_PHY_767_DATA 0x00000000 +#define DDRSS0_PHY_768_DATA 0x000004F0 +#define DDRSS0_PHY_769_DATA 0x00000000 +#define DDRSS0_PHY_770_DATA 0x00030200 +#define DDRSS0_PHY_771_DATA 0x00000000 +#define DDRSS0_PHY_772_DATA 0x00000000 +#define DDRSS0_PHY_773_DATA 0x01030000 +#define DDRSS0_PHY_774_DATA 0x00010000 +#define DDRSS0_PHY_775_DATA 0x01030004 +#define DDRSS0_PHY_776_DATA 0x01000000 +#define DDRSS0_PHY_777_DATA 0x00000000 +#define DDRSS0_PHY_778_DATA 0x00000000 +#define DDRSS0_PHY_779_DATA 0x01000001 +#define DDRSS0_PHY_780_DATA 0x00000200 +#define DDRSS0_PHY_781_DATA 0x000800C0 +#define DDRSS0_PHY_782_DATA 0x060100CC +#define DDRSS0_PHY_783_DATA 0x00030066 +#define DDRSS0_PHY_784_DATA 0x00000000 +#define DDRSS0_PHY_785_DATA 0x00000301 +#define DDRSS0_PHY_786_DATA 0x0000AAAA +#define DDRSS0_PHY_787_DATA 0x00005555 +#define DDRSS0_PHY_788_DATA 0x0000B5B5 +#define DDRSS0_PHY_789_DATA 0x00004A4A +#define DDRSS0_PHY_790_DATA 0x00005656 +#define DDRSS0_PHY_791_DATA 0x0000A9A9 +#define DDRSS0_PHY_792_DATA 0x0000A9A9 +#define DDRSS0_PHY_793_DATA 0x0000B5B5 +#define DDRSS0_PHY_794_DATA 0x00000000 +#define DDRSS0_PHY_795_DATA 0x00000000 +#define DDRSS0_PHY_796_DATA 0x2A000000 +#define DDRSS0_PHY_797_DATA 0x00000808 +#define DDRSS0_PHY_798_DATA 0x0F000000 +#define DDRSS0_PHY_799_DATA 0x00000F08 +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002002 +#define DDRSS0_PHY_802_DATA 0x00000000 +#define DDRSS0_PHY_803_DATA 0x00000000 +#define DDRSS0_PHY_804_DATA 0x55555555 +#define DDRSS0_PHY_805_DATA 0xAAAAAAAA +#define DDRSS0_PHY_806_DATA 0x55555555 +#define DDRSS0_PHY_807_DATA 0xAAAAAAAA +#define DDRSS0_PHY_808_DATA 0x00005555 +#define DDRSS0_PHY_809_DATA 0x01000100 +#define DDRSS0_PHY_810_DATA 0x00800180 +#define DDRSS0_PHY_811_DATA 0x00000000 +#define DDRSS0_PHY_812_DATA 0x00000000 +#define DDRSS0_PHY_813_DATA 0x00000000 +#define DDRSS0_PHY_814_DATA 0x00000000 +#define DDRSS0_PHY_815_DATA 0x00000000 +#define DDRSS0_PHY_816_DATA 0x00000000 +#define DDRSS0_PHY_817_DATA 0x00000000 +#define DDRSS0_PHY_818_DATA 0x00000000 +#define DDRSS0_PHY_819_DATA 0x00000000 +#define DDRSS0_PHY_820_DATA 0x00000000 +#define DDRSS0_PHY_821_DATA 0x00000000 +#define DDRSS0_PHY_822_DATA 0x00000000 +#define DDRSS0_PHY_823_DATA 0x00000000 +#define DDRSS0_PHY_824_DATA 0x00000000 +#define DDRSS0_PHY_825_DATA 0x00000000 +#define DDRSS0_PHY_826_DATA 0x00000000 +#define DDRSS0_PHY_827_DATA 0x00000000 +#define DDRSS0_PHY_828_DATA 0x00000000 +#define DDRSS0_PHY_829_DATA 0x00000000 +#define DDRSS0_PHY_830_DATA 0x00000000 +#define DDRSS0_PHY_831_DATA 0x00000000 +#define DDRSS0_PHY_832_DATA 0x00000000 +#define DDRSS0_PHY_833_DATA 0x00000000 +#define DDRSS0_PHY_834_DATA 0x00000104 +#define DDRSS0_PHY_835_DATA 0x00000120 +#define DDRSS0_PHY_836_DATA 0x00000000 +#define DDRSS0_PHY_837_DATA 0x00000000 +#define DDRSS0_PHY_838_DATA 0x00000000 +#define DDRSS0_PHY_839_DATA 0x00000000 +#define DDRSS0_PHY_840_DATA 0x00000000 +#define DDRSS0_PHY_841_DATA 0x00000000 +#define DDRSS0_PHY_842_DATA 0x00000000 +#define DDRSS0_PHY_843_DATA 0x00000001 +#define DDRSS0_PHY_844_DATA 0x07FF0000 +#define DDRSS0_PHY_845_DATA 0x0080081F +#define DDRSS0_PHY_846_DATA 0x00081020 +#define DDRSS0_PHY_847_DATA 0x04010000 +#define DDRSS0_PHY_848_DATA 0x00000000 +#define DDRSS0_PHY_849_DATA 0x00000000 +#define DDRSS0_PHY_850_DATA 0x00000000 +#define DDRSS0_PHY_851_DATA 0x00000100 +#define DDRSS0_PHY_852_DATA 0x01CC0C01 +#define DDRSS0_PHY_853_DATA 0x1003CC0C +#define DDRSS0_PHY_854_DATA 0x20000140 +#define DDRSS0_PHY_855_DATA 0x07FF0200 +#define DDRSS0_PHY_856_DATA 0x0000DD01 +#define DDRSS0_PHY_857_DATA 0x10100303 +#define DDRSS0_PHY_858_DATA 0x10101010 +#define DDRSS0_PHY_859_DATA 0x10101010 +#define DDRSS0_PHY_860_DATA 0x00021010 +#define DDRSS0_PHY_861_DATA 0x00100010 +#define DDRSS0_PHY_862_DATA 0x00100010 +#define DDRSS0_PHY_863_DATA 0x00100010 +#define DDRSS0_PHY_864_DATA 0x00100010 +#define DDRSS0_PHY_865_DATA 0x00050010 +#define DDRSS0_PHY_866_DATA 0x51517041 +#define DDRSS0_PHY_867_DATA 0x31C06001 +#define DDRSS0_PHY_868_DATA 0x07AB01AB +#define DDRSS0_PHY_869_DATA 0x00C0C001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 +#define DDRSS0_PHY_871_DATA 0x10001000 +#define DDRSS0_PHY_872_DATA 0x0C083E42 +#define DDRSS0_PHY_873_DATA 0x0F0C3701 +#define DDRSS0_PHY_874_DATA 0x01000140 +#define DDRSS0_PHY_875_DATA 0x0C000420 +#define DDRSS0_PHY_876_DATA 0x00000198 +#define DDRSS0_PHY_877_DATA 0x0A0000D0 +#define DDRSS0_PHY_878_DATA 0x00030200 +#define DDRSS0_PHY_879_DATA 0x02800000 +#define DDRSS0_PHY_880_DATA 0x80800000 +#define DDRSS0_PHY_881_DATA 0x000E2010 +#define DDRSS0_PHY_882_DATA 0x76543210 +#define DDRSS0_PHY_883_DATA 0x00000008 +#define DDRSS0_PHY_884_DATA 0x02800280 +#define DDRSS0_PHY_885_DATA 0x02800280 +#define DDRSS0_PHY_886_DATA 0x02800280 +#define DDRSS0_PHY_887_DATA 0x02800280 +#define DDRSS0_PHY_888_DATA 0x00000280 +#define DDRSS0_PHY_889_DATA 0x0000A000 +#define DDRSS0_PHY_890_DATA 0x00A000A0 +#define DDRSS0_PHY_891_DATA 0x00A000A0 +#define DDRSS0_PHY_892_DATA 0x00A000A0 +#define DDRSS0_PHY_893_DATA 0x00A000A0 +#define DDRSS0_PHY_894_DATA 0x00A000A0 +#define DDRSS0_PHY_895_DATA 0x00A000A0 +#define DDRSS0_PHY_896_DATA 0x00A000A0 +#define DDRSS0_PHY_897_DATA 0x00A000A0 +#define DDRSS0_PHY_898_DATA 0x01C200A0 +#define DDRSS0_PHY_899_DATA 0x01A00005 +#define DDRSS0_PHY_900_DATA 0x00000000 +#define DDRSS0_PHY_901_DATA 0x00000000 +#define DDRSS0_PHY_902_DATA 0x00080200 +#define DDRSS0_PHY_903_DATA 0x00000000 +#define DDRSS0_PHY_904_DATA 0x20202020 +#define DDRSS0_PHY_905_DATA 0x20202020 +#define DDRSS0_PHY_906_DATA 0xF0F02020 +#define DDRSS0_PHY_907_DATA 0x00000000 +#define DDRSS0_PHY_908_DATA 0x00000000 +#define DDRSS0_PHY_909_DATA 0x00000000 +#define DDRSS0_PHY_910_DATA 0x00000000 +#define DDRSS0_PHY_911_DATA 0x00000000 +#define DDRSS0_PHY_912_DATA 0x00000000 +#define DDRSS0_PHY_913_DATA 0x00000000 +#define DDRSS0_PHY_914_DATA 0x00000000 +#define DDRSS0_PHY_915_DATA 0x00000000 +#define DDRSS0_PHY_916_DATA 0x00000000 +#define DDRSS0_PHY_917_DATA 0x00000000 +#define DDRSS0_PHY_918_DATA 0x00000000 +#define DDRSS0_PHY_919_DATA 0x00000000 +#define DDRSS0_PHY_920_DATA 0x00000000 +#define DDRSS0_PHY_921_DATA 0x00000000 +#define DDRSS0_PHY_922_DATA 0x00000000 +#define DDRSS0_PHY_923_DATA 0x00000000 +#define DDRSS0_PHY_924_DATA 0x00000000 +#define DDRSS0_PHY_925_DATA 0x00000000 +#define DDRSS0_PHY_926_DATA 0x00000000 +#define DDRSS0_PHY_927_DATA 0x00000000 +#define DDRSS0_PHY_928_DATA 0x00000000 +#define DDRSS0_PHY_929_DATA 0x00000000 +#define DDRSS0_PHY_930_DATA 0x00000000 +#define DDRSS0_PHY_931_DATA 0x00000000 +#define DDRSS0_PHY_932_DATA 0x00000000 +#define DDRSS0_PHY_933_DATA 0x00000000 +#define DDRSS0_PHY_934_DATA 0x00000000 +#define DDRSS0_PHY_935_DATA 0x00000000 +#define DDRSS0_PHY_936_DATA 0x00000000 +#define DDRSS0_PHY_937_DATA 0x00000000 +#define DDRSS0_PHY_938_DATA 0x00000000 +#define DDRSS0_PHY_939_DATA 0x00000000 +#define DDRSS0_PHY_940_DATA 0x00000000 +#define DDRSS0_PHY_941_DATA 0x00000000 +#define DDRSS0_PHY_942_DATA 0x00000000 +#define DDRSS0_PHY_943_DATA 0x00000000 +#define DDRSS0_PHY_944_DATA 0x00000000 +#define DDRSS0_PHY_945_DATA 0x00000000 +#define DDRSS0_PHY_946_DATA 0x00000000 +#define DDRSS0_PHY_947_DATA 0x00000000 +#define DDRSS0_PHY_948_DATA 0x00000000 +#define DDRSS0_PHY_949_DATA 0x00000000 +#define DDRSS0_PHY_950_DATA 0x00000000 +#define DDRSS0_PHY_951_DATA 0x00000000 +#define DDRSS0_PHY_952_DATA 0x00000000 +#define DDRSS0_PHY_953_DATA 0x00000000 +#define DDRSS0_PHY_954_DATA 0x00000000 +#define DDRSS0_PHY_955_DATA 0x00000000 +#define DDRSS0_PHY_956_DATA 0x00000000 +#define DDRSS0_PHY_957_DATA 0x00000000 +#define DDRSS0_PHY_958_DATA 0x00000000 +#define DDRSS0_PHY_959_DATA 0x00000000 +#define DDRSS0_PHY_960_DATA 0x00000000 +#define DDRSS0_PHY_961_DATA 0x00000000 +#define DDRSS0_PHY_962_DATA 0x00000000 +#define DDRSS0_PHY_963_DATA 0x00000000 +#define DDRSS0_PHY_964_DATA 0x00000000 +#define DDRSS0_PHY_965_DATA 0x00000000 +#define DDRSS0_PHY_966_DATA 0x00000000 +#define DDRSS0_PHY_967_DATA 0x00000000 +#define DDRSS0_PHY_968_DATA 0x00000000 +#define DDRSS0_PHY_969_DATA 0x00000000 +#define DDRSS0_PHY_970_DATA 0x00000000 +#define DDRSS0_PHY_971_DATA 0x00000000 +#define DDRSS0_PHY_972_DATA 0x00000000 +#define DDRSS0_PHY_973_DATA 0x00000000 +#define DDRSS0_PHY_974_DATA 0x00000000 +#define DDRSS0_PHY_975_DATA 0x00000000 +#define DDRSS0_PHY_976_DATA 0x00000000 +#define DDRSS0_PHY_977_DATA 0x00000000 +#define DDRSS0_PHY_978_DATA 0x00000000 +#define DDRSS0_PHY_979_DATA 0x00000000 +#define DDRSS0_PHY_980_DATA 0x00000000 +#define DDRSS0_PHY_981_DATA 0x00000000 +#define DDRSS0_PHY_982_DATA 0x00000000 +#define DDRSS0_PHY_983_DATA 0x00000000 +#define DDRSS0_PHY_984_DATA 0x00000000 +#define DDRSS0_PHY_985_DATA 0x00000000 +#define DDRSS0_PHY_986_DATA 0x00000000 +#define DDRSS0_PHY_987_DATA 0x00000000 +#define DDRSS0_PHY_988_DATA 0x00000000 +#define DDRSS0_PHY_989_DATA 0x00000000 +#define DDRSS0_PHY_990_DATA 0x00000000 +#define DDRSS0_PHY_991_DATA 0x00000000 +#define DDRSS0_PHY_992_DATA 0x00000000 +#define DDRSS0_PHY_993_DATA 0x00000000 +#define DDRSS0_PHY_994_DATA 0x00000000 +#define DDRSS0_PHY_995_DATA 0x00000000 +#define DDRSS0_PHY_996_DATA 0x00000000 +#define DDRSS0_PHY_997_DATA 0x00000000 +#define DDRSS0_PHY_998_DATA 0x00000000 +#define DDRSS0_PHY_999_DATA 0x00000000 +#define DDRSS0_PHY_1000_DATA 0x00000000 +#define DDRSS0_PHY_1001_DATA 0x00000000 +#define DDRSS0_PHY_1002_DATA 0x00000000 +#define DDRSS0_PHY_1003_DATA 0x00000000 +#define DDRSS0_PHY_1004_DATA 0x00000000 +#define DDRSS0_PHY_1005_DATA 0x00000000 +#define DDRSS0_PHY_1006_DATA 0x00000000 +#define DDRSS0_PHY_1007_DATA 0x00000000 +#define DDRSS0_PHY_1008_DATA 0x00000000 +#define DDRSS0_PHY_1009_DATA 0x00000000 +#define DDRSS0_PHY_1010_DATA 0x00000000 +#define DDRSS0_PHY_1011_DATA 0x00000000 +#define DDRSS0_PHY_1012_DATA 0x00000000 +#define DDRSS0_PHY_1013_DATA 0x00000000 +#define DDRSS0_PHY_1014_DATA 0x00000000 +#define DDRSS0_PHY_1015_DATA 0x00000000 +#define DDRSS0_PHY_1016_DATA 0x00000000 +#define DDRSS0_PHY_1017_DATA 0x00000000 +#define DDRSS0_PHY_1018_DATA 0x00000000 +#define DDRSS0_PHY_1019_DATA 0x00000000 +#define DDRSS0_PHY_1020_DATA 0x00000000 +#define DDRSS0_PHY_1021_DATA 0x00000000 +#define DDRSS0_PHY_1022_DATA 0x00000000 +#define DDRSS0_PHY_1023_DATA 0x00000000 +#define DDRSS0_PHY_1024_DATA 0x00000000 +#define DDRSS0_PHY_1025_DATA 0x00000000 +#define DDRSS0_PHY_1026_DATA 0x00000000 +#define DDRSS0_PHY_1027_DATA 0x00000000 +#define DDRSS0_PHY_1028_DATA 0x00000000 +#define DDRSS0_PHY_1029_DATA 0x00000100 +#define DDRSS0_PHY_1030_DATA 0x00000200 +#define DDRSS0_PHY_1031_DATA 0x00000000 +#define DDRSS0_PHY_1032_DATA 0x00000000 +#define DDRSS0_PHY_1033_DATA 0x00000000 +#define DDRSS0_PHY_1034_DATA 0x00000000 +#define DDRSS0_PHY_1035_DATA 0x00400000 +#define DDRSS0_PHY_1036_DATA 0x00000080 +#define DDRSS0_PHY_1037_DATA 0x00DCBA98 +#define DDRSS0_PHY_1038_DATA 0x03000000 +#define DDRSS0_PHY_1039_DATA 0x00200000 +#define DDRSS0_PHY_1040_DATA 0x00000000 +#define DDRSS0_PHY_1041_DATA 0x00000000 +#define DDRSS0_PHY_1042_DATA 0x00000000 +#define DDRSS0_PHY_1043_DATA 0x00000000 +#define DDRSS0_PHY_1044_DATA 0x00000000 +#define DDRSS0_PHY_1045_DATA 0x0000002A +#define DDRSS0_PHY_1046_DATA 0x00000015 +#define DDRSS0_PHY_1047_DATA 0x00000015 +#define DDRSS0_PHY_1048_DATA 0x0000002A +#define DDRSS0_PHY_1049_DATA 0x00000033 +#define DDRSS0_PHY_1050_DATA 0x0000000C +#define DDRSS0_PHY_1051_DATA 0x0000000C +#define DDRSS0_PHY_1052_DATA 0x00000033 +#define DDRSS0_PHY_1053_DATA 0x00543210 +#define DDRSS0_PHY_1054_DATA 0x003F0000 +#define DDRSS0_PHY_1055_DATA 0x000F3F3F +#define DDRSS0_PHY_1056_DATA 0x20202003 +#define DDRSS0_PHY_1057_DATA 0x00202020 +#define DDRSS0_PHY_1058_DATA 0x20008008 +#define DDRSS0_PHY_1059_DATA 0x00000810 +#define DDRSS0_PHY_1060_DATA 0x00000F00 +#define DDRSS0_PHY_1061_DATA 0x00000000 +#define DDRSS0_PHY_1062_DATA 0x00000000 +#define DDRSS0_PHY_1063_DATA 0x00000000 +#define DDRSS0_PHY_1064_DATA 0x000305CC +#define DDRSS0_PHY_1065_DATA 0x00030000 +#define DDRSS0_PHY_1066_DATA 0x00000300 +#define DDRSS0_PHY_1067_DATA 0x00000300 +#define DDRSS0_PHY_1068_DATA 0x00000300 +#define DDRSS0_PHY_1069_DATA 0x00000300 +#define DDRSS0_PHY_1070_DATA 0x00000300 +#define DDRSS0_PHY_1071_DATA 0x42080010 +#define DDRSS0_PHY_1072_DATA 0x0000803E +#define DDRSS0_PHY_1073_DATA 0x00000001 +#define DDRSS0_PHY_1074_DATA 0x01000102 +#define DDRSS0_PHY_1075_DATA 0x00008000 +#define DDRSS0_PHY_1076_DATA 0x00000000 +#define DDRSS0_PHY_1077_DATA 0x00000000 +#define DDRSS0_PHY_1078_DATA 0x00000000 +#define DDRSS0_PHY_1079_DATA 0x00000000 +#define DDRSS0_PHY_1080_DATA 0x00000000 +#define DDRSS0_PHY_1081_DATA 0x00000000 +#define DDRSS0_PHY_1082_DATA 0x00000000 +#define DDRSS0_PHY_1083_DATA 0x00000000 +#define DDRSS0_PHY_1084_DATA 0x00000000 +#define DDRSS0_PHY_1085_DATA 0x00000000 +#define DDRSS0_PHY_1086_DATA 0x00000000 +#define DDRSS0_PHY_1087_DATA 0x00000000 +#define DDRSS0_PHY_1088_DATA 0x00000000 +#define DDRSS0_PHY_1089_DATA 0x00000000 +#define DDRSS0_PHY_1090_DATA 0x00000000 +#define DDRSS0_PHY_1091_DATA 0x00000000 +#define DDRSS0_PHY_1092_DATA 0x00000000 +#define DDRSS0_PHY_1093_DATA 0x00000000 +#define DDRSS0_PHY_1094_DATA 0x00000000 +#define DDRSS0_PHY_1095_DATA 0x00000000 +#define DDRSS0_PHY_1096_DATA 0x00000000 +#define DDRSS0_PHY_1097_DATA 0x00000000 +#define DDRSS0_PHY_1098_DATA 0x00000000 +#define DDRSS0_PHY_1099_DATA 0x00000000 +#define DDRSS0_PHY_1100_DATA 0x00000000 +#define DDRSS0_PHY_1101_DATA 0x00000000 +#define DDRSS0_PHY_1102_DATA 0x00000000 +#define DDRSS0_PHY_1103_DATA 0x00000000 +#define DDRSS0_PHY_1104_DATA 0x00000000 +#define DDRSS0_PHY_1105_DATA 0x00000000 +#define DDRSS0_PHY_1106_DATA 0x00000000 +#define DDRSS0_PHY_1107_DATA 0x00000000 +#define DDRSS0_PHY_1108_DATA 0x00000000 +#define DDRSS0_PHY_1109_DATA 0x00000000 +#define DDRSS0_PHY_1110_DATA 0x00000000 +#define DDRSS0_PHY_1111_DATA 0x00000000 +#define DDRSS0_PHY_1112_DATA 0x00000000 +#define DDRSS0_PHY_1113_DATA 0x00000000 +#define DDRSS0_PHY_1114_DATA 0x00000000 +#define DDRSS0_PHY_1115_DATA 0x00000000 +#define DDRSS0_PHY_1116_DATA 0x00000000 +#define DDRSS0_PHY_1117_DATA 0x00000000 +#define DDRSS0_PHY_1118_DATA 0x00000000 +#define DDRSS0_PHY_1119_DATA 0x00000000 +#define DDRSS0_PHY_1120_DATA 0x00000000 +#define DDRSS0_PHY_1121_DATA 0x00000000 +#define DDRSS0_PHY_1122_DATA 0x00000000 +#define DDRSS0_PHY_1123_DATA 0x00000000 +#define DDRSS0_PHY_1124_DATA 0x00000000 +#define DDRSS0_PHY_1125_DATA 0x00000000 +#define DDRSS0_PHY_1126_DATA 0x00000000 +#define DDRSS0_PHY_1127_DATA 0x00000000 +#define DDRSS0_PHY_1128_DATA 0x00000000 +#define DDRSS0_PHY_1129_DATA 0x00000000 +#define DDRSS0_PHY_1130_DATA 0x00000000 +#define DDRSS0_PHY_1131_DATA 0x00000000 +#define DDRSS0_PHY_1132_DATA 0x00000000 +#define DDRSS0_PHY_1133_DATA 0x00000000 +#define DDRSS0_PHY_1134_DATA 0x00000000 +#define DDRSS0_PHY_1135_DATA 0x00000000 +#define DDRSS0_PHY_1136_DATA 0x00000000 +#define DDRSS0_PHY_1137_DATA 0x00000000 +#define DDRSS0_PHY_1138_DATA 0x00000000 +#define DDRSS0_PHY_1139_DATA 0x00000000 +#define DDRSS0_PHY_1140_DATA 0x00000000 +#define DDRSS0_PHY_1141_DATA 0x00000000 +#define DDRSS0_PHY_1142_DATA 0x00000000 +#define DDRSS0_PHY_1143_DATA 0x00000000 +#define DDRSS0_PHY_1144_DATA 0x00000000 +#define DDRSS0_PHY_1145_DATA 0x00000000 +#define DDRSS0_PHY_1146_DATA 0x00000000 +#define DDRSS0_PHY_1147_DATA 0x00000000 +#define DDRSS0_PHY_1148_DATA 0x00000000 +#define DDRSS0_PHY_1149_DATA 0x00000000 +#define DDRSS0_PHY_1150_DATA 0x00000000 +#define DDRSS0_PHY_1151_DATA 0x00000000 +#define DDRSS0_PHY_1152_DATA 0x00000000 +#define DDRSS0_PHY_1153_DATA 0x00000000 +#define DDRSS0_PHY_1154_DATA 0x00000000 +#define DDRSS0_PHY_1155_DATA 0x00000000 +#define DDRSS0_PHY_1156_DATA 0x00000000 +#define DDRSS0_PHY_1157_DATA 0x00000000 +#define DDRSS0_PHY_1158_DATA 0x00000000 +#define DDRSS0_PHY_1159_DATA 0x00000000 +#define DDRSS0_PHY_1160_DATA 0x00000000 +#define DDRSS0_PHY_1161_DATA 0x00000000 +#define DDRSS0_PHY_1162_DATA 0x00000000 +#define DDRSS0_PHY_1163_DATA 0x00000000 +#define DDRSS0_PHY_1164_DATA 0x00000000 +#define DDRSS0_PHY_1165_DATA 0x00000000 +#define DDRSS0_PHY_1166_DATA 0x00000000 +#define DDRSS0_PHY_1167_DATA 0x00000000 +#define DDRSS0_PHY_1168_DATA 0x00000000 +#define DDRSS0_PHY_1169_DATA 0x00000000 +#define DDRSS0_PHY_1170_DATA 0x00000000 +#define DDRSS0_PHY_1171_DATA 0x00000000 +#define DDRSS0_PHY_1172_DATA 0x00000000 +#define DDRSS0_PHY_1173_DATA 0x00000000 +#define DDRSS0_PHY_1174_DATA 0x00000000 +#define DDRSS0_PHY_1175_DATA 0x00000000 +#define DDRSS0_PHY_1176_DATA 0x00000000 +#define DDRSS0_PHY_1177_DATA 0x00000000 +#define DDRSS0_PHY_1178_DATA 0x00000000 +#define DDRSS0_PHY_1179_DATA 0x00000000 +#define DDRSS0_PHY_1180_DATA 0x00000000 +#define DDRSS0_PHY_1181_DATA 0x00000000 +#define DDRSS0_PHY_1182_DATA 0x00000000 +#define DDRSS0_PHY_1183_DATA 0x00000000 +#define DDRSS0_PHY_1184_DATA 0x00000000 +#define DDRSS0_PHY_1185_DATA 0x00000000 +#define DDRSS0_PHY_1186_DATA 0x00000000 +#define DDRSS0_PHY_1187_DATA 0x00000000 +#define DDRSS0_PHY_1188_DATA 0x00000000 +#define DDRSS0_PHY_1189_DATA 0x00000000 +#define DDRSS0_PHY_1190_DATA 0x00000000 +#define DDRSS0_PHY_1191_DATA 0x00000000 +#define DDRSS0_PHY_1192_DATA 0x00000000 +#define DDRSS0_PHY_1193_DATA 0x00000000 +#define DDRSS0_PHY_1194_DATA 0x00000000 +#define DDRSS0_PHY_1195_DATA 0x00000000 +#define DDRSS0_PHY_1196_DATA 0x00000000 +#define DDRSS0_PHY_1197_DATA 0x00000000 +#define DDRSS0_PHY_1198_DATA 0x00000000 +#define DDRSS0_PHY_1199_DATA 0x00000000 +#define DDRSS0_PHY_1200_DATA 0x00000000 +#define DDRSS0_PHY_1201_DATA 0x00000000 +#define DDRSS0_PHY_1202_DATA 0x00000000 +#define DDRSS0_PHY_1203_DATA 0x00000000 +#define DDRSS0_PHY_1204_DATA 0x00000000 +#define DDRSS0_PHY_1205_DATA 0x00000000 +#define DDRSS0_PHY_1206_DATA 0x00000000 +#define DDRSS0_PHY_1207_DATA 0x00000000 +#define DDRSS0_PHY_1208_DATA 0x00000000 +#define DDRSS0_PHY_1209_DATA 0x00000000 +#define DDRSS0_PHY_1210_DATA 0x00000000 +#define DDRSS0_PHY_1211_DATA 0x00000000 +#define DDRSS0_PHY_1212_DATA 0x00000000 +#define DDRSS0_PHY_1213_DATA 0x00000000 +#define DDRSS0_PHY_1214_DATA 0x00000000 +#define DDRSS0_PHY_1215_DATA 0x00000000 +#define DDRSS0_PHY_1216_DATA 0x00000000 +#define DDRSS0_PHY_1217_DATA 0x00000000 +#define DDRSS0_PHY_1218_DATA 0x00000000 +#define DDRSS0_PHY_1219_DATA 0x00000000 +#define DDRSS0_PHY_1220_DATA 0x00000000 +#define DDRSS0_PHY_1221_DATA 0x00000000 +#define DDRSS0_PHY_1222_DATA 0x00000000 +#define DDRSS0_PHY_1223_DATA 0x00000000 +#define DDRSS0_PHY_1224_DATA 0x00000000 +#define DDRSS0_PHY_1225_DATA 0x00000000 +#define DDRSS0_PHY_1226_DATA 0x00000000 +#define DDRSS0_PHY_1227_DATA 0x00000000 +#define DDRSS0_PHY_1228_DATA 0x00000000 +#define DDRSS0_PHY_1229_DATA 0x00000000 +#define DDRSS0_PHY_1230_DATA 0x00000000 +#define DDRSS0_PHY_1231_DATA 0x00000000 +#define DDRSS0_PHY_1232_DATA 0x00000000 +#define DDRSS0_PHY_1233_DATA 0x00000000 +#define DDRSS0_PHY_1234_DATA 0x00000000 +#define DDRSS0_PHY_1235_DATA 0x00000000 +#define DDRSS0_PHY_1236_DATA 0x00000000 +#define DDRSS0_PHY_1237_DATA 0x00000000 +#define DDRSS0_PHY_1238_DATA 0x00000000 +#define DDRSS0_PHY_1239_DATA 0x00000000 +#define DDRSS0_PHY_1240_DATA 0x00000000 +#define DDRSS0_PHY_1241_DATA 0x00000000 +#define DDRSS0_PHY_1242_DATA 0x00000000 +#define DDRSS0_PHY_1243_DATA 0x00000000 +#define DDRSS0_PHY_1244_DATA 0x00000000 +#define DDRSS0_PHY_1245_DATA 0x00000000 +#define DDRSS0_PHY_1246_DATA 0x00000000 +#define DDRSS0_PHY_1247_DATA 0x00000000 +#define DDRSS0_PHY_1248_DATA 0x00000000 +#define DDRSS0_PHY_1249_DATA 0x00000000 +#define DDRSS0_PHY_1250_DATA 0x00000000 +#define DDRSS0_PHY_1251_DATA 0x00000000 +#define DDRSS0_PHY_1252_DATA 0x00000000 +#define DDRSS0_PHY_1253_DATA 0x00000000 +#define DDRSS0_PHY_1254_DATA 0x00000000 +#define DDRSS0_PHY_1255_DATA 0x00000000 +#define DDRSS0_PHY_1256_DATA 0x00000000 +#define DDRSS0_PHY_1257_DATA 0x00000000 +#define DDRSS0_PHY_1258_DATA 0x00000000 +#define DDRSS0_PHY_1259_DATA 0x00000000 +#define DDRSS0_PHY_1260_DATA 0x00000000 +#define DDRSS0_PHY_1261_DATA 0x00000000 +#define DDRSS0_PHY_1262_DATA 0x00000000 +#define DDRSS0_PHY_1263_DATA 0x00000000 +#define DDRSS0_PHY_1264_DATA 0x00000000 +#define DDRSS0_PHY_1265_DATA 0x00000000 +#define DDRSS0_PHY_1266_DATA 0x00000000 +#define DDRSS0_PHY_1267_DATA 0x00000000 +#define DDRSS0_PHY_1268_DATA 0x00000000 +#define DDRSS0_PHY_1269_DATA 0x00000000 +#define DDRSS0_PHY_1270_DATA 0x00000000 +#define DDRSS0_PHY_1271_DATA 0x00000000 +#define DDRSS0_PHY_1272_DATA 0x00000000 +#define DDRSS0_PHY_1273_DATA 0x00000000 +#define DDRSS0_PHY_1274_DATA 0x00000000 +#define DDRSS0_PHY_1275_DATA 0x00000000 +#define DDRSS0_PHY_1276_DATA 0x00000000 +#define DDRSS0_PHY_1277_DATA 0x00000000 +#define DDRSS0_PHY_1278_DATA 0x00000000 +#define DDRSS0_PHY_1279_DATA 0x00000000 +#define DDRSS0_PHY_1280_DATA 0x00000000 +#define DDRSS0_PHY_1281_DATA 0x00010100 +#define DDRSS0_PHY_1282_DATA 0x00000000 +#define DDRSS0_PHY_1283_DATA 0x00000000 +#define DDRSS0_PHY_1284_DATA 0x00050000 +#define DDRSS0_PHY_1285_DATA 0x04000000 +#define DDRSS0_PHY_1286_DATA 0x00000055 +#define DDRSS0_PHY_1287_DATA 0x00000000 +#define DDRSS0_PHY_1288_DATA 0x00000000 +#define DDRSS0_PHY_1289_DATA 0x00000000 +#define DDRSS0_PHY_1290_DATA 0x00000000 +#define DDRSS0_PHY_1291_DATA 0x00002001 +#define DDRSS0_PHY_1292_DATA 0x0000400F +#define DDRSS0_PHY_1293_DATA 0x50020028 +#define DDRSS0_PHY_1294_DATA 0x01010000 +#define DDRSS0_PHY_1295_DATA 0x80080001 +#define DDRSS0_PHY_1296_DATA 0x10200000 +#define DDRSS0_PHY_1297_DATA 0x00000008 +#define DDRSS0_PHY_1298_DATA 0x00000000 +#define DDRSS0_PHY_1299_DATA 0x01090E00 +#define DDRSS0_PHY_1300_DATA 0x00040101 +#define DDRSS0_PHY_1301_DATA 0x0000010F +#define DDRSS0_PHY_1302_DATA 0x00000000 +#define DDRSS0_PHY_1303_DATA 0x00000064 +#define DDRSS0_PHY_1304_DATA 0x00000000 +#define DDRSS0_PHY_1305_DATA 0x01010000 +#define DDRSS0_PHY_1306_DATA 0x01080402 +#define DDRSS0_PHY_1307_DATA 0x01200F02 +#define DDRSS0_PHY_1308_DATA 0x00194280 +#define DDRSS0_PHY_1309_DATA 0x00000004 +#define DDRSS0_PHY_1310_DATA 0x00042000 +#define DDRSS0_PHY_1311_DATA 0x00000000 +#define DDRSS0_PHY_1312_DATA 0x00000000 +#define DDRSS0_PHY_1313_DATA 0x00000000 +#define DDRSS0_PHY_1314_DATA 0x00000000 +#define DDRSS0_PHY_1315_DATA 0x00000000 +#define DDRSS0_PHY_1316_DATA 0x00000000 +#define DDRSS0_PHY_1317_DATA 0x01000000 +#define DDRSS0_PHY_1318_DATA 0x00000705 +#define DDRSS0_PHY_1319_DATA 0x00000054 +#define DDRSS0_PHY_1320_DATA 0x00030820 +#define DDRSS0_PHY_1321_DATA 0x00010820 +#define DDRSS0_PHY_1322_DATA 0x00010820 +#define DDRSS0_PHY_1323_DATA 0x00010820 +#define DDRSS0_PHY_1324_DATA 0x00010820 +#define DDRSS0_PHY_1325_DATA 0x00010820 +#define DDRSS0_PHY_1326_DATA 0x00010820 +#define DDRSS0_PHY_1327_DATA 0x00010820 +#define DDRSS0_PHY_1328_DATA 0x00010820 +#define DDRSS0_PHY_1329_DATA 0x00000000 +#define DDRSS0_PHY_1330_DATA 0x00000074 +#define DDRSS0_PHY_1331_DATA 0x00000400 +#define DDRSS0_PHY_1332_DATA 0x00000108 +#define DDRSS0_PHY_1333_DATA 0x00000000 +#define DDRSS0_PHY_1334_DATA 0x00000000 +#define DDRSS0_PHY_1335_DATA 0x00000000 +#define DDRSS0_PHY_1336_DATA 0x00000000 +#define DDRSS0_PHY_1337_DATA 0x00000000 +#define DDRSS0_PHY_1338_DATA 0x03000000 +#define DDRSS0_PHY_1339_DATA 0x00000000 +#define DDRSS0_PHY_1340_DATA 0x00000000 +#define DDRSS0_PHY_1341_DATA 0x00000000 +#define DDRSS0_PHY_1342_DATA 0x04102006 +#define DDRSS0_PHY_1343_DATA 0x00041020 +#define DDRSS0_PHY_1344_DATA 0x01C98C98 +#define DDRSS0_PHY_1345_DATA 0x3F400000 +#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS0_PHY_1347_DATA 0x0000001F +#define DDRSS0_PHY_1348_DATA 0x00000000 +#define DDRSS0_PHY_1349_DATA 0x00000000 +#define DDRSS0_PHY_1350_DATA 0x00000000 +#define DDRSS0_PHY_1351_DATA 0x00010000 +#define DDRSS0_PHY_1352_DATA 0x00000000 +#define DDRSS0_PHY_1353_DATA 0x00000000 +#define DDRSS0_PHY_1354_DATA 0x00000000 +#define DDRSS0_PHY_1355_DATA 0x00000000 +#define DDRSS0_PHY_1356_DATA 0x76543210 +#define DDRSS0_PHY_1357_DATA 0x00010198 +#define DDRSS0_PHY_1358_DATA 0x00000000 +#define DDRSS0_PHY_1359_DATA 0x00000000 +#define DDRSS0_PHY_1360_DATA 0x00000000 +#define DDRSS0_PHY_1361_DATA 0x00040700 +#define DDRSS0_PHY_1362_DATA 0x00000000 +#define DDRSS0_PHY_1363_DATA 0x00000000 +#define DDRSS0_PHY_1364_DATA 0x00000000 +#define DDRSS0_PHY_1365_DATA 0x00000000 +#define DDRSS0_PHY_1366_DATA 0x00000000 +#define DDRSS0_PHY_1367_DATA 0x00000002 +#define DDRSS0_PHY_1368_DATA 0x00000000 +#define DDRSS0_PHY_1369_DATA 0x00000000 +#define DDRSS0_PHY_1370_DATA 0x00000000 +#define DDRSS0_PHY_1371_DATA 0x00000000 +#define DDRSS0_PHY_1372_DATA 0x00000000 +#define DDRSS0_PHY_1373_DATA 0x00000000 +#define DDRSS0_PHY_1374_DATA 0x00080000 +#define DDRSS0_PHY_1375_DATA 0x000007FF +#define DDRSS0_PHY_1376_DATA 0x00000000 +#define DDRSS0_PHY_1377_DATA 0x00000000 +#define DDRSS0_PHY_1378_DATA 0x00000000 +#define DDRSS0_PHY_1379_DATA 0x00000000 +#define DDRSS0_PHY_1380_DATA 0x00000000 +#define DDRSS0_PHY_1381_DATA 0x00000000 +#define DDRSS0_PHY_1382_DATA 0x000FFFFF +#define DDRSS0_PHY_1383_DATA 0x000FFFFF +#define DDRSS0_PHY_1384_DATA 0x0000FFFF +#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS0_PHY_1386_DATA 0x030FFFFF +#define DDRSS0_PHY_1387_DATA 0x01FFFFFF +#define DDRSS0_PHY_1388_DATA 0x0000FFFF +#define DDRSS0_PHY_1389_DATA 0x00000000 +#define DDRSS0_PHY_1390_DATA 0x00000000 +#define DDRSS0_PHY_1391_DATA 0x00000000 +#define DDRSS0_PHY_1392_DATA 0x00000000 +#define DDRSS0_PHY_1393_DATA 0x0001F7C0 +#define DDRSS0_PHY_1394_DATA 0x00000003 +#define DDRSS0_PHY_1395_DATA 0x00000000 +#define DDRSS0_PHY_1396_DATA 0x00001142 +#define DDRSS0_PHY_1397_DATA 0x040207AB +#define DDRSS0_PHY_1398_DATA 0x01000080 +#define DDRSS0_PHY_1399_DATA 0x03900390 +#define DDRSS0_PHY_1400_DATA 0x03900390 +#define DDRSS0_PHY_1401_DATA 0x00000390 +#define DDRSS0_PHY_1402_DATA 0x00000390 +#define DDRSS0_PHY_1403_DATA 0x00000390 +#define DDRSS0_PHY_1404_DATA 0x00000390 +#define DDRSS0_PHY_1405_DATA 0x00000005 +#define DDRSS0_PHY_1406_DATA 0x01813FCC +#define DDRSS0_PHY_1407_DATA 0x000000CC +#define DDRSS0_PHY_1408_DATA 0x0C000DFF +#define DDRSS0_PHY_1409_DATA 0x30000DFF +#define DDRSS0_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1411_DATA 0x000100F0 +#define DDRSS0_PHY_1412_DATA 0x780DFFCC +#define DDRSS0_PHY_1413_DATA 0x00007E31 +#define DDRSS0_PHY_1414_DATA 0x000CBF11 +#define DDRSS0_PHY_1415_DATA 0x01990010 +#define DDRSS0_PHY_1416_DATA 0x000CBF11 +#define DDRSS0_PHY_1417_DATA 0x01990010 +#define DDRSS0_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1419_DATA 0x00EF00F0 +#define DDRSS0_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1421_DATA 0x01FF00F0 +#define DDRSS0_PHY_1422_DATA 0x20040006 + +#define DDRSS1_CTL_00_DATA 0x00000B00 +#define DDRSS1_CTL_01_DATA 0x00000000 +#define DDRSS1_CTL_02_DATA 0x00000000 +#define DDRSS1_CTL_03_DATA 0x00000000 +#define DDRSS1_CTL_04_DATA 0x00000000 +#define DDRSS1_CTL_05_DATA 0x00000000 +#define DDRSS1_CTL_06_DATA 0x00000000 +#define DDRSS1_CTL_07_DATA 0x00002AF8 +#define DDRSS1_CTL_08_DATA 0x0001ADAF +#define DDRSS1_CTL_09_DATA 0x00000005 +#define DDRSS1_CTL_10_DATA 0x0000006E +#define DDRSS1_CTL_11_DATA 0x000681C8 +#define DDRSS1_CTL_12_DATA 0x004111C9 +#define DDRSS1_CTL_13_DATA 0x00000005 +#define DDRSS1_CTL_14_DATA 0x000010A9 +#define DDRSS1_CTL_15_DATA 0x000681C8 +#define DDRSS1_CTL_16_DATA 0x004111C9 +#define DDRSS1_CTL_17_DATA 0x00000005 +#define DDRSS1_CTL_18_DATA 0x000010A9 +#define DDRSS1_CTL_19_DATA 0x01010000 +#define DDRSS1_CTL_20_DATA 0x01011001 +#define DDRSS1_CTL_21_DATA 0x02010000 +#define DDRSS1_CTL_22_DATA 0x00020100 +#define DDRSS1_CTL_23_DATA 0x0000000B +#define DDRSS1_CTL_24_DATA 0x0000001C +#define DDRSS1_CTL_25_DATA 0x00000000 +#define DDRSS1_CTL_26_DATA 0x00000000 +#define DDRSS1_CTL_27_DATA 0x03020200 +#define DDRSS1_CTL_28_DATA 0x00005656 +#define DDRSS1_CTL_29_DATA 0x00100000 +#define DDRSS1_CTL_30_DATA 0x00000000 +#define DDRSS1_CTL_31_DATA 0x00000000 +#define DDRSS1_CTL_32_DATA 0x00000000 +#define DDRSS1_CTL_33_DATA 0x00000000 +#define DDRSS1_CTL_34_DATA 0x040C0000 +#define DDRSS1_CTL_35_DATA 0x12501250 +#define DDRSS1_CTL_36_DATA 0x00050804 +#define DDRSS1_CTL_37_DATA 0x09040008 +#define DDRSS1_CTL_38_DATA 0x15000204 +#define DDRSS1_CTL_39_DATA 0x1760008B +#define DDRSS1_CTL_40_DATA 0x1500422B +#define DDRSS1_CTL_41_DATA 0x1760008B +#define DDRSS1_CTL_42_DATA 0x2000422B +#define DDRSS1_CTL_43_DATA 0x000A0A09 +#define DDRSS1_CTL_44_DATA 0x040003C5 +#define DDRSS1_CTL_45_DATA 0x1E161104 +#define DDRSS1_CTL_46_DATA 0x1000922C +#define DDRSS1_CTL_47_DATA 0x1E161110 +#define DDRSS1_CTL_48_DATA 0x1000922C +#define DDRSS1_CTL_49_DATA 0x02030410 +#define DDRSS1_CTL_50_DATA 0x2C060500 +#define DDRSS1_CTL_51_DATA 0x08292C29 +#define DDRSS1_CTL_52_DATA 0x14000E0A +#define DDRSS1_CTL_53_DATA 0x04010A0A +#define DDRSS1_CTL_54_DATA 0x01010004 +#define DDRSS1_CTL_55_DATA 0x0454540A +#define DDRSS1_CTL_56_DATA 0x04313104 +#define DDRSS1_CTL_57_DATA 0x00003131 +#define DDRSS1_CTL_58_DATA 0x00010100 +#define DDRSS1_CTL_59_DATA 0x03010000 +#define DDRSS1_CTL_60_DATA 0x00001508 +#define DDRSS1_CTL_61_DATA 0x00000068 +#define DDRSS1_CTL_62_DATA 0x0000032B +#define DDRSS1_CTL_63_DATA 0x00001035 +#define DDRSS1_CTL_64_DATA 0x0000032B +#define DDRSS1_CTL_65_DATA 0x00001035 +#define DDRSS1_CTL_66_DATA 0x00000005 +#define DDRSS1_CTL_67_DATA 0x00050000 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 +#define DDRSS1_CTL_71_DATA 0x00120103 +#define DDRSS1_CTL_72_DATA 0x00100005 +#define DDRSS1_CTL_73_DATA 0x2F080010 +#define DDRSS1_CTL_74_DATA 0x0505012F +#define DDRSS1_CTL_75_DATA 0x0401030A +#define DDRSS1_CTL_76_DATA 0x041E100B +#define DDRSS1_CTL_77_DATA 0x100B0401 +#define DDRSS1_CTL_78_DATA 0x0001041E +#define DDRSS1_CTL_79_DATA 0x00160016 +#define DDRSS1_CTL_80_DATA 0x033B033B +#define DDRSS1_CTL_81_DATA 0x033B033B +#define DDRSS1_CTL_82_DATA 0x03050505 +#define DDRSS1_CTL_83_DATA 0x03010303 +#define DDRSS1_CTL_84_DATA 0x200B100B +#define DDRSS1_CTL_85_DATA 0x04041004 +#define DDRSS1_CTL_86_DATA 0x200B100B +#define DDRSS1_CTL_87_DATA 0x04041004 +#define DDRSS1_CTL_88_DATA 0x03010000 +#define DDRSS1_CTL_89_DATA 0x00010000 +#define DDRSS1_CTL_90_DATA 0x00000000 +#define DDRSS1_CTL_91_DATA 0x00000000 +#define DDRSS1_CTL_92_DATA 0x01000000 +#define DDRSS1_CTL_93_DATA 0x80104002 +#define DDRSS1_CTL_94_DATA 0x00000000 +#define DDRSS1_CTL_95_DATA 0x00040005 +#define DDRSS1_CTL_96_DATA 0x00000000 +#define DDRSS1_CTL_97_DATA 0x00050000 +#define DDRSS1_CTL_98_DATA 0x00000004 +#define DDRSS1_CTL_99_DATA 0x00000000 +#define DDRSS1_CTL_100_DATA 0x00040005 +#define DDRSS1_CTL_101_DATA 0x00000000 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 +#define DDRSS1_CTL_107_DATA 0x00000000 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 +#define DDRSS1_CTL_114_DATA 0x00000000 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 +#define DDRSS1_CTL_121_DATA 0x00000000 +#define DDRSS1_CTL_122_DATA 0x00007173 +#define DDRSS1_CTL_123_DATA 0x00000000 +#define DDRSS1_CTL_124_DATA 0x00000000 +#define DDRSS1_CTL_125_DATA 0x00000000 +#define DDRSS1_CTL_126_DATA 0x00000000 +#define DDRSS1_CTL_127_DATA 0x00000000 +#define DDRSS1_CTL_128_DATA 0x00000000 +#define DDRSS1_CTL_129_DATA 0x00000000 +#define DDRSS1_CTL_130_DATA 0x00000000 +#define DDRSS1_CTL_131_DATA 0x0B030500 +#define DDRSS1_CTL_132_DATA 0x00040B04 +#define DDRSS1_CTL_133_DATA 0x0A090000 +#define DDRSS1_CTL_134_DATA 0x0A090701 +#define DDRSS1_CTL_135_DATA 0x0900000E +#define DDRSS1_CTL_136_DATA 0x0907010A +#define DDRSS1_CTL_137_DATA 0x00000E0A +#define DDRSS1_CTL_138_DATA 0x07010A09 +#define DDRSS1_CTL_139_DATA 0x000E0A09 +#define DDRSS1_CTL_140_DATA 0x07000401 +#define DDRSS1_CTL_141_DATA 0x00000000 +#define DDRSS1_CTL_142_DATA 0x00000000 +#define DDRSS1_CTL_143_DATA 0x00000000 +#define DDRSS1_CTL_144_DATA 0x00000000 +#define DDRSS1_CTL_145_DATA 0x00000000 +#define DDRSS1_CTL_146_DATA 0x00000000 +#define DDRSS1_CTL_147_DATA 0x00000000 +#define DDRSS1_CTL_148_DATA 0x08080000 +#define DDRSS1_CTL_149_DATA 0x01000000 +#define DDRSS1_CTL_150_DATA 0x800000C0 +#define DDRSS1_CTL_151_DATA 0x800000C0 +#define DDRSS1_CTL_152_DATA 0x800000C0 +#define DDRSS1_CTL_153_DATA 0x00000000 +#define DDRSS1_CTL_154_DATA 0x00001500 +#define DDRSS1_CTL_155_DATA 0x00000000 +#define DDRSS1_CTL_156_DATA 0x00000001 +#define DDRSS1_CTL_157_DATA 0x00000002 +#define DDRSS1_CTL_158_DATA 0x0000100E +#define DDRSS1_CTL_159_DATA 0x00000000 +#define DDRSS1_CTL_160_DATA 0x00000000 +#define DDRSS1_CTL_161_DATA 0x00000000 +#define DDRSS1_CTL_162_DATA 0x00000000 +#define DDRSS1_CTL_163_DATA 0x00000000 +#define DDRSS1_CTL_164_DATA 0x000B0000 +#define DDRSS1_CTL_165_DATA 0x000E0006 +#define DDRSS1_CTL_166_DATA 0x000E0404 +#define DDRSS1_CTL_167_DATA 0x00D601AB +#define DDRSS1_CTL_168_DATA 0x10100216 +#define DDRSS1_CTL_169_DATA 0x01AB0216 +#define DDRSS1_CTL_170_DATA 0x021600D6 +#define DDRSS1_CTL_171_DATA 0x02161010 +#define DDRSS1_CTL_172_DATA 0x00000000 +#define DDRSS1_CTL_173_DATA 0x00000000 +#define DDRSS1_CTL_174_DATA 0x00000000 +#define DDRSS1_CTL_175_DATA 0x3FF40084 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 +#define DDRSS1_CTL_178_DATA 0x36000000 +#define DDRSS1_CTL_179_DATA 0x27270036 +#define DDRSS1_CTL_180_DATA 0x0F0F0000 +#define DDRSS1_CTL_181_DATA 0x16000000 +#define DDRSS1_CTL_182_DATA 0x00841616 +#define DDRSS1_CTL_183_DATA 0x3FF43FF4 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 +#define DDRSS1_CTL_185_DATA 0x00000000 +#define DDRSS1_CTL_186_DATA 0x00363600 +#define DDRSS1_CTL_187_DATA 0x00002727 +#define DDRSS1_CTL_188_DATA 0x00000F0F +#define DDRSS1_CTL_189_DATA 0x16161600 +#define DDRSS1_CTL_190_DATA 0x00000020 +#define DDRSS1_CTL_191_DATA 0x01000000 +#define DDRSS1_CTL_192_DATA 0x00000001 +#define DDRSS1_CTL_193_DATA 0x00000000 +#define DDRSS1_CTL_194_DATA 0x01000000 +#define DDRSS1_CTL_195_DATA 0x00000001 +#define DDRSS1_CTL_196_DATA 0x00000000 +#define DDRSS1_CTL_197_DATA 0x00000000 +#define DDRSS1_CTL_198_DATA 0x00000000 +#define DDRSS1_CTL_199_DATA 0x00000000 +#define DDRSS1_CTL_200_DATA 0x00000000 +#define DDRSS1_CTL_201_DATA 0x00000000 +#define DDRSS1_CTL_202_DATA 0x00000000 +#define DDRSS1_CTL_203_DATA 0x00000000 +#define DDRSS1_CTL_204_DATA 0x00000000 +#define DDRSS1_CTL_205_DATA 0x00000000 +#define DDRSS1_CTL_206_DATA 0x02000000 +#define DDRSS1_CTL_207_DATA 0x01080101 +#define DDRSS1_CTL_208_DATA 0x00000000 +#define DDRSS1_CTL_209_DATA 0x00000000 +#define DDRSS1_CTL_210_DATA 0x00000000 +#define DDRSS1_CTL_211_DATA 0x00000000 +#define DDRSS1_CTL_212_DATA 0x00000000 +#define DDRSS1_CTL_213_DATA 0x00000000 +#define DDRSS1_CTL_214_DATA 0x00000000 +#define DDRSS1_CTL_215_DATA 0x00000000 +#define DDRSS1_CTL_216_DATA 0x00000000 +#define DDRSS1_CTL_217_DATA 0x00000000 +#define DDRSS1_CTL_218_DATA 0x00000000 +#define DDRSS1_CTL_219_DATA 0x00000000 +#define DDRSS1_CTL_220_DATA 0x00000000 +#define DDRSS1_CTL_221_DATA 0x00000000 +#define DDRSS1_CTL_222_DATA 0x00001000 +#define DDRSS1_CTL_223_DATA 0x006403E8 +#define DDRSS1_CTL_224_DATA 0x00000000 +#define DDRSS1_CTL_225_DATA 0x00000000 +#define DDRSS1_CTL_226_DATA 0x00000000 +#define DDRSS1_CTL_227_DATA 0x15110000 +#define DDRSS1_CTL_228_DATA 0x00040C18 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 +#define DDRSS1_CTL_231_DATA 0x00000000 +#define DDRSS1_CTL_232_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 +#define DDRSS1_CTL_235_DATA 0x00000000 +#define DDRSS1_CTL_236_DATA 0x00000000 +#define DDRSS1_CTL_237_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 +#define DDRSS1_CTL_240_DATA 0x00000000 +#define DDRSS1_CTL_241_DATA 0x00000000 +#define DDRSS1_CTL_242_DATA 0x00030000 +#define DDRSS1_CTL_243_DATA 0x00000000 +#define DDRSS1_CTL_244_DATA 0x00000000 +#define DDRSS1_CTL_245_DATA 0x00000000 +#define DDRSS1_CTL_246_DATA 0x00000000 +#define DDRSS1_CTL_247_DATA 0x00000000 +#define DDRSS1_CTL_248_DATA 0x00000000 +#define DDRSS1_CTL_249_DATA 0x00000000 +#define DDRSS1_CTL_250_DATA 0x00000000 +#define DDRSS1_CTL_251_DATA 0x00000000 +#define DDRSS1_CTL_252_DATA 0x00000000 +#define DDRSS1_CTL_253_DATA 0x00000000 +#define DDRSS1_CTL_254_DATA 0x00000000 +#define DDRSS1_CTL_255_DATA 0x00000000 +#define DDRSS1_CTL_256_DATA 0x00000000 +#define DDRSS1_CTL_257_DATA 0x01000200 +#define DDRSS1_CTL_258_DATA 0x00370040 +#define DDRSS1_CTL_259_DATA 0x00020008 +#define DDRSS1_CTL_260_DATA 0x00400100 +#define DDRSS1_CTL_261_DATA 0x00400855 +#define DDRSS1_CTL_262_DATA 0x01000200 +#define DDRSS1_CTL_263_DATA 0x08550040 +#define DDRSS1_CTL_264_DATA 0x00000040 +#define DDRSS1_CTL_265_DATA 0x006B0003 +#define DDRSS1_CTL_266_DATA 0x0100006B +#define DDRSS1_CTL_267_DATA 0x03030303 +#define DDRSS1_CTL_268_DATA 0x00000000 +#define DDRSS1_CTL_269_DATA 0x00000202 +#define DDRSS1_CTL_270_DATA 0x00001FFF +#define DDRSS1_CTL_271_DATA 0x3FFF2000 +#define DDRSS1_CTL_272_DATA 0x03FF0000 +#define DDRSS1_CTL_273_DATA 0x000103FF +#define DDRSS1_CTL_274_DATA 0x0FFF0B00 +#define DDRSS1_CTL_275_DATA 0x01010001 +#define DDRSS1_CTL_276_DATA 0x01010101 +#define DDRSS1_CTL_277_DATA 0x01180101 +#define DDRSS1_CTL_278_DATA 0x00030000 +#define DDRSS1_CTL_279_DATA 0x00000000 +#define DDRSS1_CTL_280_DATA 0x00000000 +#define DDRSS1_CTL_281_DATA 0x00000000 +#define DDRSS1_CTL_282_DATA 0x00000000 +#define DDRSS1_CTL_283_DATA 0x00000000 +#define DDRSS1_CTL_284_DATA 0x00000000 +#define DDRSS1_CTL_285_DATA 0x00000000 +#define DDRSS1_CTL_286_DATA 0x00040101 +#define DDRSS1_CTL_287_DATA 0x04010100 +#define DDRSS1_CTL_288_DATA 0x00000000 +#define DDRSS1_CTL_289_DATA 0x00000000 +#define DDRSS1_CTL_290_DATA 0x03030300 +#define DDRSS1_CTL_291_DATA 0x00010101 +#define DDRSS1_CTL_292_DATA 0x00000000 +#define DDRSS1_CTL_293_DATA 0x00000000 +#define DDRSS1_CTL_294_DATA 0x00000000 +#define DDRSS1_CTL_295_DATA 0x00000000 +#define DDRSS1_CTL_296_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF +#define DDRSS1_CTL_299_DATA 0x00000000 +#define DDRSS1_CTL_300_DATA 0x00000000 +#define DDRSS1_CTL_301_DATA 0x00000000 +#define DDRSS1_CTL_302_DATA 0x00000000 +#define DDRSS1_CTL_303_DATA 0x00000000 +#define DDRSS1_CTL_304_DATA 0x00000000 +#define DDRSS1_CTL_305_DATA 0x00000000 +#define DDRSS1_CTL_306_DATA 0x00000000 +#define DDRSS1_CTL_307_DATA 0x00000000 +#define DDRSS1_CTL_308_DATA 0x00000000 +#define DDRSS1_CTL_309_DATA 0x00000000 +#define DDRSS1_CTL_310_DATA 0x00000000 +#define DDRSS1_CTL_311_DATA 0x00000000 +#define DDRSS1_CTL_312_DATA 0x00000000 +#define DDRSS1_CTL_313_DATA 0x01000000 +#define DDRSS1_CTL_314_DATA 0x00020201 +#define DDRSS1_CTL_315_DATA 0x01000101 +#define DDRSS1_CTL_316_DATA 0x01010001 +#define DDRSS1_CTL_317_DATA 0x00010101 +#define DDRSS1_CTL_318_DATA 0x050A0A03 +#define DDRSS1_CTL_319_DATA 0x10082323 +#define DDRSS1_CTL_320_DATA 0x00090310 +#define DDRSS1_CTL_321_DATA 0x0B0C030F +#define DDRSS1_CTL_322_DATA 0x0B0C0306 +#define DDRSS1_CTL_323_DATA 0x0C090006 +#define DDRSS1_CTL_324_DATA 0x0100000C +#define DDRSS1_CTL_325_DATA 0x08040801 +#define DDRSS1_CTL_326_DATA 0x00000004 +#define DDRSS1_CTL_327_DATA 0x00000000 +#define DDRSS1_CTL_328_DATA 0x00010000 +#define DDRSS1_CTL_329_DATA 0x00280D00 +#define DDRSS1_CTL_330_DATA 0x00000001 +#define DDRSS1_CTL_331_DATA 0x00030001 +#define DDRSS1_CTL_332_DATA 0x00000000 +#define DDRSS1_CTL_333_DATA 0x00000000 +#define DDRSS1_CTL_334_DATA 0x00000000 +#define DDRSS1_CTL_335_DATA 0x00000000 +#define DDRSS1_CTL_336_DATA 0x00000000 +#define DDRSS1_CTL_337_DATA 0x00000000 +#define DDRSS1_CTL_338_DATA 0x00000000 +#define DDRSS1_CTL_339_DATA 0x00000000 +#define DDRSS1_CTL_340_DATA 0x01000000 +#define DDRSS1_CTL_341_DATA 0x00000001 +#define DDRSS1_CTL_342_DATA 0x00010100 +#define DDRSS1_CTL_343_DATA 0x03030000 +#define DDRSS1_CTL_344_DATA 0x00000000 +#define DDRSS1_CTL_345_DATA 0x00000000 +#define DDRSS1_CTL_346_DATA 0x00000000 +#define DDRSS1_CTL_347_DATA 0x00000000 +#define DDRSS1_CTL_348_DATA 0x00000000 +#define DDRSS1_CTL_349_DATA 0x00000000 +#define DDRSS1_CTL_350_DATA 0x00000000 +#define DDRSS1_CTL_351_DATA 0x00000000 +#define DDRSS1_CTL_352_DATA 0x00000000 +#define DDRSS1_CTL_353_DATA 0x00000000 +#define DDRSS1_CTL_354_DATA 0x00000000 +#define DDRSS1_CTL_355_DATA 0x00000000 +#define DDRSS1_CTL_356_DATA 0x00000000 +#define DDRSS1_CTL_357_DATA 0x00000000 +#define DDRSS1_CTL_358_DATA 0x00000000 +#define DDRSS1_CTL_359_DATA 0x00000000 +#define DDRSS1_CTL_360_DATA 0x000556AA +#define DDRSS1_CTL_361_DATA 0x000AAAAA +#define DDRSS1_CTL_362_DATA 0x000AA955 +#define DDRSS1_CTL_363_DATA 0x00055555 +#define DDRSS1_CTL_364_DATA 0x000B3133 +#define DDRSS1_CTL_365_DATA 0x0004CD33 +#define DDRSS1_CTL_366_DATA 0x0004CECC +#define DDRSS1_CTL_367_DATA 0x000B32CC +#define DDRSS1_CTL_368_DATA 0x00010300 +#define DDRSS1_CTL_369_DATA 0x03000100 +#define DDRSS1_CTL_370_DATA 0x00000000 +#define DDRSS1_CTL_371_DATA 0x00000000 +#define DDRSS1_CTL_372_DATA 0x00000000 +#define DDRSS1_CTL_373_DATA 0x00000000 +#define DDRSS1_CTL_374_DATA 0x00000000 +#define DDRSS1_CTL_375_DATA 0x00000000 +#define DDRSS1_CTL_376_DATA 0x00000000 +#define DDRSS1_CTL_377_DATA 0x00010000 +#define DDRSS1_CTL_378_DATA 0x00000404 +#define DDRSS1_CTL_379_DATA 0x00000000 +#define DDRSS1_CTL_380_DATA 0x00000000 +#define DDRSS1_CTL_381_DATA 0x00000000 +#define DDRSS1_CTL_382_DATA 0x00000000 +#define DDRSS1_CTL_383_DATA 0x00000000 +#define DDRSS1_CTL_384_DATA 0x00000000 +#define DDRSS1_CTL_385_DATA 0x00000000 +#define DDRSS1_CTL_386_DATA 0x00000000 +#define DDRSS1_CTL_387_DATA 0x3A3A1B00 +#define DDRSS1_CTL_388_DATA 0x000A0000 +#define DDRSS1_CTL_389_DATA 0x000000C6 +#define DDRSS1_CTL_390_DATA 0x00000200 +#define DDRSS1_CTL_391_DATA 0x00000200 +#define DDRSS1_CTL_392_DATA 0x00000200 +#define DDRSS1_CTL_393_DATA 0x00000200 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC +#define DDRSS1_CTL_396_DATA 0x00000204 +#define DDRSS1_CTL_397_DATA 0x0000206A +#define DDRSS1_CTL_398_DATA 0x00000200 +#define DDRSS1_CTL_399_DATA 0x00000200 +#define DDRSS1_CTL_400_DATA 0x00000200 +#define DDRSS1_CTL_401_DATA 0x00000200 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A +#define DDRSS1_CTL_406_DATA 0x00000200 +#define DDRSS1_CTL_407_DATA 0x00000200 +#define DDRSS1_CTL_408_DATA 0x00000200 +#define DDRSS1_CTL_409_DATA 0x00000200 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 +#define DDRSS1_CTL_413_DATA 0x03030202 +#define DDRSS1_CTL_414_DATA 0x00000022 +#define DDRSS1_CTL_415_DATA 0x00000000 +#define DDRSS1_CTL_416_DATA 0x00000000 +#define DDRSS1_CTL_417_DATA 0x00001403 +#define DDRSS1_CTL_418_DATA 0x000007D0 +#define DDRSS1_CTL_419_DATA 0x00000000 +#define DDRSS1_CTL_420_DATA 0x00000000 +#define DDRSS1_CTL_421_DATA 0x00030000 +#define DDRSS1_CTL_422_DATA 0x0007001F +#define DDRSS1_CTL_423_DATA 0x001B0033 +#define DDRSS1_CTL_424_DATA 0x001B0033 +#define DDRSS1_CTL_425_DATA 0x00000000 +#define DDRSS1_CTL_426_DATA 0x00000000 +#define DDRSS1_CTL_427_DATA 0x02000000 +#define DDRSS1_CTL_428_DATA 0x01000404 +#define DDRSS1_CTL_429_DATA 0x0B220B22 +#define DDRSS1_CTL_430_DATA 0x00000105 +#define DDRSS1_CTL_431_DATA 0x00010101 +#define DDRSS1_CTL_432_DATA 0x00010101 +#define DDRSS1_CTL_433_DATA 0x00010001 +#define DDRSS1_CTL_434_DATA 0x00000101 +#define DDRSS1_CTL_435_DATA 0x02000201 +#define DDRSS1_CTL_436_DATA 0x02010000 +#define DDRSS1_CTL_437_DATA 0x00000200 +#define DDRSS1_CTL_438_DATA 0x28060000 +#define DDRSS1_CTL_439_DATA 0x00000128 +#define DDRSS1_CTL_440_DATA 0xFFFFFFFF +#define DDRSS1_CTL_441_DATA 0xFFFFFFFF +#define DDRSS1_CTL_442_DATA 0x00000000 +#define DDRSS1_CTL_443_DATA 0x00000000 +#define DDRSS1_CTL_444_DATA 0x00000000 +#define DDRSS1_CTL_445_DATA 0x00000000 +#define DDRSS1_CTL_446_DATA 0x00000000 +#define DDRSS1_CTL_447_DATA 0x00000000 +#define DDRSS1_CTL_448_DATA 0x00000000 +#define DDRSS1_CTL_449_DATA 0x00000000 +#define DDRSS1_CTL_450_DATA 0x00000000 +#define DDRSS1_CTL_451_DATA 0x00000000 +#define DDRSS1_CTL_452_DATA 0x00000000 +#define DDRSS1_CTL_453_DATA 0x00000000 +#define DDRSS1_CTL_454_DATA 0x00000000 +#define DDRSS1_CTL_455_DATA 0x00000000 +#define DDRSS1_CTL_456_DATA 0x00000000 +#define DDRSS1_CTL_457_DATA 0x00000000 +#define DDRSS1_CTL_458_DATA 0x00000000 + +#define DDRSS1_PI_00_DATA 0x00000B00 +#define DDRSS1_PI_01_DATA 0x00000000 +#define DDRSS1_PI_02_DATA 0x00000000 +#define DDRSS1_PI_03_DATA 0x00000000 +#define DDRSS1_PI_04_DATA 0x00000000 +#define DDRSS1_PI_05_DATA 0x00000101 +#define DDRSS1_PI_06_DATA 0x00640000 +#define DDRSS1_PI_07_DATA 0x00000001 +#define DDRSS1_PI_08_DATA 0x00000000 +#define DDRSS1_PI_09_DATA 0x00000000 +#define DDRSS1_PI_10_DATA 0x00000000 +#define DDRSS1_PI_11_DATA 0x00000000 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 +#define DDRSS1_PI_14_DATA 0x0800000F +#define DDRSS1_PI_15_DATA 0x00000103 +#define DDRSS1_PI_16_DATA 0x00000005 +#define DDRSS1_PI_17_DATA 0x00000000 +#define DDRSS1_PI_18_DATA 0x00000000 +#define DDRSS1_PI_19_DATA 0x00000000 +#define DDRSS1_PI_20_DATA 0x00000000 +#define DDRSS1_PI_21_DATA 0x00000000 +#define DDRSS1_PI_22_DATA 0x00000000 +#define DDRSS1_PI_23_DATA 0x00000000 +#define DDRSS1_PI_24_DATA 0x00000000 +#define DDRSS1_PI_25_DATA 0x00000000 +#define DDRSS1_PI_26_DATA 0x00010100 +#define DDRSS1_PI_27_DATA 0x00280A00 +#define DDRSS1_PI_28_DATA 0x00000000 +#define DDRSS1_PI_29_DATA 0x0F000000 +#define DDRSS1_PI_30_DATA 0x00003200 +#define DDRSS1_PI_31_DATA 0x00000000 +#define DDRSS1_PI_32_DATA 0x00000000 +#define DDRSS1_PI_33_DATA 0x01010102 +#define DDRSS1_PI_34_DATA 0x00000000 +#define DDRSS1_PI_35_DATA 0x000000AA +#define DDRSS1_PI_36_DATA 0x00000055 +#define DDRSS1_PI_37_DATA 0x000000B5 +#define DDRSS1_PI_38_DATA 0x0000004A +#define DDRSS1_PI_39_DATA 0x00000056 +#define DDRSS1_PI_40_DATA 0x000000A9 +#define DDRSS1_PI_41_DATA 0x000000A9 +#define DDRSS1_PI_42_DATA 0x000000B5 +#define DDRSS1_PI_43_DATA 0x00000000 +#define DDRSS1_PI_44_DATA 0x00000000 +#define DDRSS1_PI_45_DATA 0x000F0F00 +#define DDRSS1_PI_46_DATA 0x0000001B +#define DDRSS1_PI_47_DATA 0x000007D0 +#define DDRSS1_PI_48_DATA 0x00000300 +#define DDRSS1_PI_49_DATA 0x00000000 +#define DDRSS1_PI_50_DATA 0x00000000 +#define DDRSS1_PI_51_DATA 0x01000000 +#define DDRSS1_PI_52_DATA 0x00010101 +#define DDRSS1_PI_53_DATA 0x00000000 +#define DDRSS1_PI_54_DATA 0x00030000 +#define DDRSS1_PI_55_DATA 0x0F000000 +#define DDRSS1_PI_56_DATA 0x00000017 +#define DDRSS1_PI_57_DATA 0x00000000 +#define DDRSS1_PI_58_DATA 0x00000000 +#define DDRSS1_PI_59_DATA 0x00000000 +#define DDRSS1_PI_60_DATA 0x0A0A140A +#define DDRSS1_PI_61_DATA 0x10020201 +#define DDRSS1_PI_62_DATA 0x00020805 +#define DDRSS1_PI_63_DATA 0x01000404 +#define DDRSS1_PI_64_DATA 0x00000000 +#define DDRSS1_PI_65_DATA 0x00000000 +#define DDRSS1_PI_66_DATA 0x00000100 +#define DDRSS1_PI_67_DATA 0x0002020F +#define DDRSS1_PI_68_DATA 0x00340000 +#define DDRSS1_PI_69_DATA 0x00000000 +#define DDRSS1_PI_70_DATA 0x00000000 +#define DDRSS1_PI_71_DATA 0x0000FFFF +#define DDRSS1_PI_72_DATA 0x01000000 +#define DDRSS1_PI_73_DATA 0x00080000 +#define DDRSS1_PI_74_DATA 0x02000200 +#define DDRSS1_PI_75_DATA 0x01000100 +#define DDRSS1_PI_76_DATA 0x01000000 +#define DDRSS1_PI_77_DATA 0x02000200 +#define DDRSS1_PI_78_DATA 0x00000200 +#define DDRSS1_PI_79_DATA 0x00000000 +#define DDRSS1_PI_80_DATA 0x00000000 +#define DDRSS1_PI_81_DATA 0x00000000 +#define DDRSS1_PI_82_DATA 0x00000000 +#define DDRSS1_PI_83_DATA 0x00000000 +#define DDRSS1_PI_84_DATA 0x00000000 +#define DDRSS1_PI_85_DATA 0x00000000 +#define DDRSS1_PI_86_DATA 0x00000000 +#define DDRSS1_PI_87_DATA 0x00000000 +#define DDRSS1_PI_88_DATA 0x00000000 +#define DDRSS1_PI_89_DATA 0x00000000 +#define DDRSS1_PI_90_DATA 0x00000000 +#define DDRSS1_PI_91_DATA 0x00000400 +#define DDRSS1_PI_92_DATA 0x02010000 +#define DDRSS1_PI_93_DATA 0x00080003 +#define DDRSS1_PI_94_DATA 0x00080000 +#define DDRSS1_PI_95_DATA 0x00000001 +#define DDRSS1_PI_96_DATA 0x00000000 +#define DDRSS1_PI_97_DATA 0x0000AA00 +#define DDRSS1_PI_98_DATA 0x00000000 +#define DDRSS1_PI_99_DATA 0x00000000 +#define DDRSS1_PI_100_DATA 0x00010000 +#define DDRSS1_PI_101_DATA 0x00000000 +#define DDRSS1_PI_102_DATA 0x00000000 +#define DDRSS1_PI_103_DATA 0x00000000 +#define DDRSS1_PI_104_DATA 0x00000000 +#define DDRSS1_PI_105_DATA 0x00000000 +#define DDRSS1_PI_106_DATA 0x00000000 +#define DDRSS1_PI_107_DATA 0x00000000 +#define DDRSS1_PI_108_DATA 0x00000000 +#define DDRSS1_PI_109_DATA 0x00000000 +#define DDRSS1_PI_110_DATA 0x00000000 +#define DDRSS1_PI_111_DATA 0x00000000 +#define DDRSS1_PI_112_DATA 0x00000000 +#define DDRSS1_PI_113_DATA 0x00000000 +#define DDRSS1_PI_114_DATA 0x00000000 +#define DDRSS1_PI_115_DATA 0x00000000 +#define DDRSS1_PI_116_DATA 0x00000000 +#define DDRSS1_PI_117_DATA 0x00000000 +#define DDRSS1_PI_118_DATA 0x00000000 +#define DDRSS1_PI_119_DATA 0x00000000 +#define DDRSS1_PI_120_DATA 0x00000000 +#define DDRSS1_PI_121_DATA 0x00000000 +#define DDRSS1_PI_122_DATA 0x00000000 +#define DDRSS1_PI_123_DATA 0x00000000 +#define DDRSS1_PI_124_DATA 0x00000000 +#define DDRSS1_PI_125_DATA 0x00000008 +#define DDRSS1_PI_126_DATA 0x00000000 +#define DDRSS1_PI_127_DATA 0x00000000 +#define DDRSS1_PI_128_DATA 0x00000000 +#define DDRSS1_PI_129_DATA 0x00000000 +#define DDRSS1_PI_130_DATA 0x00000000 +#define DDRSS1_PI_131_DATA 0x00000000 +#define DDRSS1_PI_132_DATA 0x00000000 +#define DDRSS1_PI_133_DATA 0x00000000 +#define DDRSS1_PI_134_DATA 0x00000002 +#define DDRSS1_PI_135_DATA 0x00000000 +#define DDRSS1_PI_136_DATA 0x00000000 +#define DDRSS1_PI_137_DATA 0x0000000A +#define DDRSS1_PI_138_DATA 0x00000019 +#define DDRSS1_PI_139_DATA 0x00000100 +#define DDRSS1_PI_140_DATA 0x00000000 +#define DDRSS1_PI_141_DATA 0x00000000 +#define DDRSS1_PI_142_DATA 0x00000000 +#define DDRSS1_PI_143_DATA 0x00000000 +#define DDRSS1_PI_144_DATA 0x01000000 +#define DDRSS1_PI_145_DATA 0x00010003 +#define DDRSS1_PI_146_DATA 0x02000101 +#define DDRSS1_PI_147_DATA 0x01030001 +#define DDRSS1_PI_148_DATA 0x00010400 +#define DDRSS1_PI_149_DATA 0x06000105 +#define DDRSS1_PI_150_DATA 0x01070001 +#define DDRSS1_PI_151_DATA 0x00000000 +#define DDRSS1_PI_152_DATA 0x00000000 +#define DDRSS1_PI_153_DATA 0x00000000 +#define DDRSS1_PI_154_DATA 0x00010001 +#define DDRSS1_PI_155_DATA 0x00000000 +#define DDRSS1_PI_156_DATA 0x00000000 +#define DDRSS1_PI_157_DATA 0x00000000 +#define DDRSS1_PI_158_DATA 0x00000000 +#define DDRSS1_PI_159_DATA 0x00000401 +#define DDRSS1_PI_160_DATA 0x00000000 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 +#define DDRSS1_PI_164_DATA 0x00000034 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 +#define DDRSS1_PI_167_DATA 0x02000200 +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 +#define DDRSS1_PI_171_DATA 0x0000032B +#define DDRSS1_PI_172_DATA 0x00001035 +#define DDRSS1_PI_173_DATA 0x0000032B +#define DDRSS1_PI_174_DATA 0x04001035 +#define DDRSS1_PI_175_DATA 0x01010404 +#define DDRSS1_PI_176_DATA 0x00001500 +#define DDRSS1_PI_177_DATA 0x00150015 +#define DDRSS1_PI_178_DATA 0x01000100 +#define DDRSS1_PI_179_DATA 0x00000100 +#define DDRSS1_PI_180_DATA 0x00000000 +#define DDRSS1_PI_181_DATA 0x01010101 +#define DDRSS1_PI_182_DATA 0x00000000 +#define DDRSS1_PI_183_DATA 0x00000000 +#define DDRSS1_PI_184_DATA 0x00000000 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 +#define DDRSS1_PI_187_DATA 0x00040402 +#define DDRSS1_PI_188_DATA 0x000D0035 +#define DDRSS1_PI_189_DATA 0x00218049 +#define DDRSS1_PI_190_DATA 0x00218049 +#define DDRSS1_PI_191_DATA 0x01000101 +#define DDRSS1_PI_192_DATA 0x0004000E +#define DDRSS1_PI_193_DATA 0x00040216 +#define DDRSS1_PI_194_DATA 0x01000216 +#define DDRSS1_PI_195_DATA 0x000F000F +#define DDRSS1_PI_196_DATA 0x02170100 +#define DDRSS1_PI_197_DATA 0x01000217 +#define DDRSS1_PI_198_DATA 0x02170217 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B +#define DDRSS1_PI_201_DATA 0x0A070601 +#define DDRSS1_PI_202_DATA 0x1F130A0D +#define DDRSS1_PI_203_DATA 0x1F130A14 +#define DDRSS1_PI_204_DATA 0x0000C014 +#define DDRSS1_PI_205_DATA 0x00C01000 +#define DDRSS1_PI_206_DATA 0x00C01000 +#define DDRSS1_PI_207_DATA 0x00021000 +#define DDRSS1_PI_208_DATA 0x0024000E +#define DDRSS1_PI_209_DATA 0x00240216 +#define DDRSS1_PI_210_DATA 0x00110216 +#define DDRSS1_PI_211_DATA 0x32000056 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 +#define DDRSS1_PI_214_DATA 0x03013212 +#define DDRSS1_PI_215_DATA 0x00003600 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 +#define DDRSS1_PI_220_DATA 0x0A032001 +#define DDRSS1_PI_221_DATA 0x2C31110A +#define DDRSS1_PI_222_DATA 0x00002918 +#define DDRSS1_PI_223_DATA 0x6000838E +#define DDRSS1_PI_224_DATA 0x1E202008 +#define DDRSS1_PI_225_DATA 0x2C311116 +#define DDRSS1_PI_226_DATA 0x00002918 +#define DDRSS1_PI_227_DATA 0x6000838E +#define DDRSS1_PI_228_DATA 0x1E202008 +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 +#define DDRSS1_PI_235_DATA 0x033B0016 +#define DDRSS1_PI_236_DATA 0x0303033B +#define DDRSS1_PI_237_DATA 0x002AF803 +#define DDRSS1_PI_238_DATA 0x0001ADAF +#define DDRSS1_PI_239_DATA 0x00000005 +#define DDRSS1_PI_240_DATA 0x0000006E +#define DDRSS1_PI_241_DATA 0x00000016 +#define DDRSS1_PI_242_DATA 0x000681C8 +#define DDRSS1_PI_243_DATA 0x0001ADAF +#define DDRSS1_PI_244_DATA 0x00000005 +#define DDRSS1_PI_245_DATA 0x000010A9 +#define DDRSS1_PI_246_DATA 0x0000033B +#define DDRSS1_PI_247_DATA 0x000681C8 +#define DDRSS1_PI_248_DATA 0x0001ADAF +#define DDRSS1_PI_249_DATA 0x00000005 +#define DDRSS1_PI_250_DATA 0x000010A9 +#define DDRSS1_PI_251_DATA 0x0100033B +#define DDRSS1_PI_252_DATA 0x00370040 +#define DDRSS1_PI_253_DATA 0x00010008 +#define DDRSS1_PI_254_DATA 0x08550040 +#define DDRSS1_PI_255_DATA 0x00010040 +#define DDRSS1_PI_256_DATA 0x08550040 +#define DDRSS1_PI_257_DATA 0x00000340 +#define DDRSS1_PI_258_DATA 0x006B006B +#define DDRSS1_PI_259_DATA 0x08040404 +#define DDRSS1_PI_260_DATA 0x00000055 +#define DDRSS1_PI_261_DATA 0x55083C5A +#define DDRSS1_PI_262_DATA 0x5A000000 +#define DDRSS1_PI_263_DATA 0x0055083C +#define DDRSS1_PI_264_DATA 0x3C5A0000 +#define DDRSS1_PI_265_DATA 0x00005508 +#define DDRSS1_PI_266_DATA 0x0C3C5A00 +#define DDRSS1_PI_267_DATA 0x080F0E0D +#define DDRSS1_PI_268_DATA 0x000B0A09 +#define DDRSS1_PI_269_DATA 0x00030201 +#define DDRSS1_PI_270_DATA 0x01000000 +#define DDRSS1_PI_271_DATA 0x04020201 +#define DDRSS1_PI_272_DATA 0x00080804 +#define DDRSS1_PI_273_DATA 0x00000000 +#define DDRSS1_PI_274_DATA 0x00000000 +#define DDRSS1_PI_275_DATA 0x00F30084 +#define DDRSS1_PI_276_DATA 0x00160000 +#define DDRSS1_PI_277_DATA 0x36F33FF4 +#define DDRSS1_PI_278_DATA 0x00160F27 +#define DDRSS1_PI_279_DATA 0x36F33FF4 +#define DDRSS1_PI_280_DATA 0x00160F27 +#define DDRSS1_PI_281_DATA 0x00F30084 +#define DDRSS1_PI_282_DATA 0x00160000 +#define DDRSS1_PI_283_DATA 0x36F33FF4 +#define DDRSS1_PI_284_DATA 0x00160F27 +#define DDRSS1_PI_285_DATA 0x36F33FF4 +#define DDRSS1_PI_286_DATA 0x00160F27 +#define DDRSS1_PI_287_DATA 0x00F30084 +#define DDRSS1_PI_288_DATA 0x00160000 +#define DDRSS1_PI_289_DATA 0x36F33FF4 +#define DDRSS1_PI_290_DATA 0x00160F27 +#define DDRSS1_PI_291_DATA 0x36F33FF4 +#define DDRSS1_PI_292_DATA 0x00160F27 +#define DDRSS1_PI_293_DATA 0x00F30084 +#define DDRSS1_PI_294_DATA 0x00160000 +#define DDRSS1_PI_295_DATA 0x36F33FF4 +#define DDRSS1_PI_296_DATA 0x00160F27 +#define DDRSS1_PI_297_DATA 0x36F33FF4 +#define DDRSS1_PI_298_DATA 0x00160F27 +#define DDRSS1_PI_299_DATA 0x00000000 + +#define DDRSS1_PHY_00_DATA 0x000004F0 +#define DDRSS1_PHY_01_DATA 0x00000000 +#define DDRSS1_PHY_02_DATA 0x00030200 +#define DDRSS1_PHY_03_DATA 0x00000000 +#define DDRSS1_PHY_04_DATA 0x00000000 +#define DDRSS1_PHY_05_DATA 0x01030000 +#define DDRSS1_PHY_06_DATA 0x00010000 +#define DDRSS1_PHY_07_DATA 0x01030004 +#define DDRSS1_PHY_08_DATA 0x01000000 +#define DDRSS1_PHY_09_DATA 0x00000000 +#define DDRSS1_PHY_10_DATA 0x00000000 +#define DDRSS1_PHY_11_DATA 0x01000001 +#define DDRSS1_PHY_12_DATA 0x00000200 +#define DDRSS1_PHY_13_DATA 0x000800C0 +#define DDRSS1_PHY_14_DATA 0x060100CC +#define DDRSS1_PHY_15_DATA 0x00030066 +#define DDRSS1_PHY_16_DATA 0x00000000 +#define DDRSS1_PHY_17_DATA 0x00000301 +#define DDRSS1_PHY_18_DATA 0x0000AAAA +#define DDRSS1_PHY_19_DATA 0x00005555 +#define DDRSS1_PHY_20_DATA 0x0000B5B5 +#define DDRSS1_PHY_21_DATA 0x00004A4A +#define DDRSS1_PHY_22_DATA 0x00005656 +#define DDRSS1_PHY_23_DATA 0x0000A9A9 +#define DDRSS1_PHY_24_DATA 0x0000A9A9 +#define DDRSS1_PHY_25_DATA 0x0000B5B5 +#define DDRSS1_PHY_26_DATA 0x00000000 +#define DDRSS1_PHY_27_DATA 0x00000000 +#define DDRSS1_PHY_28_DATA 0x2A000000 +#define DDRSS1_PHY_29_DATA 0x00000808 +#define DDRSS1_PHY_30_DATA 0x0F000000 +#define DDRSS1_PHY_31_DATA 0x00000F08 +#define DDRSS1_PHY_32_DATA 0x10400000 +#define DDRSS1_PHY_33_DATA 0x0C002006 +#define DDRSS1_PHY_34_DATA 0x00000000 +#define DDRSS1_PHY_35_DATA 0x00000000 +#define DDRSS1_PHY_36_DATA 0x55555555 +#define DDRSS1_PHY_37_DATA 0xAAAAAAAA +#define DDRSS1_PHY_38_DATA 0x55555555 +#define DDRSS1_PHY_39_DATA 0xAAAAAAAA +#define DDRSS1_PHY_40_DATA 0x00005555 +#define DDRSS1_PHY_41_DATA 0x01000100 +#define DDRSS1_PHY_42_DATA 0x00800180 +#define DDRSS1_PHY_43_DATA 0x00000001 +#define DDRSS1_PHY_44_DATA 0x00000000 +#define DDRSS1_PHY_45_DATA 0x00000000 +#define DDRSS1_PHY_46_DATA 0x00000000 +#define DDRSS1_PHY_47_DATA 0x00000000 +#define DDRSS1_PHY_48_DATA 0x00000000 +#define DDRSS1_PHY_49_DATA 0x00000000 +#define DDRSS1_PHY_50_DATA 0x00000000 +#define DDRSS1_PHY_51_DATA 0x00000000 +#define DDRSS1_PHY_52_DATA 0x00000000 +#define DDRSS1_PHY_53_DATA 0x00000000 +#define DDRSS1_PHY_54_DATA 0x00000000 +#define DDRSS1_PHY_55_DATA 0x00000000 +#define DDRSS1_PHY_56_DATA 0x00000000 +#define DDRSS1_PHY_57_DATA 0x00000000 +#define DDRSS1_PHY_58_DATA 0x00000000 +#define DDRSS1_PHY_59_DATA 0x00000000 +#define DDRSS1_PHY_60_DATA 0x00000000 +#define DDRSS1_PHY_61_DATA 0x00000000 +#define DDRSS1_PHY_62_DATA 0x00000000 +#define DDRSS1_PHY_63_DATA 0x00000000 +#define DDRSS1_PHY_64_DATA 0x00000000 +#define DDRSS1_PHY_65_DATA 0x00000000 +#define DDRSS1_PHY_66_DATA 0x00000104 +#define DDRSS1_PHY_67_DATA 0x00000120 +#define DDRSS1_PHY_68_DATA 0x00000000 +#define DDRSS1_PHY_69_DATA 0x00000000 +#define DDRSS1_PHY_70_DATA 0x00000000 +#define DDRSS1_PHY_71_DATA 0x00000000 +#define DDRSS1_PHY_72_DATA 0x00000000 +#define DDRSS1_PHY_73_DATA 0x00000000 +#define DDRSS1_PHY_74_DATA 0x00000000 +#define DDRSS1_PHY_75_DATA 0x00000001 +#define DDRSS1_PHY_76_DATA 0x07FF0000 +#define DDRSS1_PHY_77_DATA 0x0080081F +#define DDRSS1_PHY_78_DATA 0x00081020 +#define DDRSS1_PHY_79_DATA 0x04010000 +#define DDRSS1_PHY_80_DATA 0x00000000 +#define DDRSS1_PHY_81_DATA 0x00000000 +#define DDRSS1_PHY_82_DATA 0x00000000 +#define DDRSS1_PHY_83_DATA 0x00000100 +#define DDRSS1_PHY_84_DATA 0x01CC0C01 +#define DDRSS1_PHY_85_DATA 0x1003CC0C +#define DDRSS1_PHY_86_DATA 0x20000140 +#define DDRSS1_PHY_87_DATA 0x07FF0200 +#define DDRSS1_PHY_88_DATA 0x0000DD01 +#define DDRSS1_PHY_89_DATA 0x10100303 +#define DDRSS1_PHY_90_DATA 0x10101010 +#define DDRSS1_PHY_91_DATA 0x10101010 +#define DDRSS1_PHY_92_DATA 0x00021010 +#define DDRSS1_PHY_93_DATA 0x00100010 +#define DDRSS1_PHY_94_DATA 0x00100010 +#define DDRSS1_PHY_95_DATA 0x00100010 +#define DDRSS1_PHY_96_DATA 0x00100010 +#define DDRSS1_PHY_97_DATA 0x00050010 +#define DDRSS1_PHY_98_DATA 0x51517041 +#define DDRSS1_PHY_99_DATA 0x31C06001 +#define DDRSS1_PHY_100_DATA 0x07AB01AB +#define DDRSS1_PHY_101_DATA 0x00C0C001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 +#define DDRSS1_PHY_103_DATA 0x10001000 +#define DDRSS1_PHY_104_DATA 0x0C083E42 +#define DDRSS1_PHY_105_DATA 0x0F0C3701 +#define DDRSS1_PHY_106_DATA 0x01000140 +#define DDRSS1_PHY_107_DATA 0x0C000420 +#define DDRSS1_PHY_108_DATA 0x00000198 +#define DDRSS1_PHY_109_DATA 0x0A0000D0 +#define DDRSS1_PHY_110_DATA 0x00030200 +#define DDRSS1_PHY_111_DATA 0x02800000 +#define DDRSS1_PHY_112_DATA 0x80800000 +#define DDRSS1_PHY_113_DATA 0x000E2010 +#define DDRSS1_PHY_114_DATA 0x76543210 +#define DDRSS1_PHY_115_DATA 0x00000008 +#define DDRSS1_PHY_116_DATA 0x02800280 +#define DDRSS1_PHY_117_DATA 0x02800280 +#define DDRSS1_PHY_118_DATA 0x02800280 +#define DDRSS1_PHY_119_DATA 0x02800280 +#define DDRSS1_PHY_120_DATA 0x00000280 +#define DDRSS1_PHY_121_DATA 0x0000A000 +#define DDRSS1_PHY_122_DATA 0x00A000A0 +#define DDRSS1_PHY_123_DATA 0x00A000A0 +#define DDRSS1_PHY_124_DATA 0x00A000A0 +#define DDRSS1_PHY_125_DATA 0x00A000A0 +#define DDRSS1_PHY_126_DATA 0x00A000A0 +#define DDRSS1_PHY_127_DATA 0x00A000A0 +#define DDRSS1_PHY_128_DATA 0x00A000A0 +#define DDRSS1_PHY_129_DATA 0x00A000A0 +#define DDRSS1_PHY_130_DATA 0x01C200A0 +#define DDRSS1_PHY_131_DATA 0x01A00005 +#define DDRSS1_PHY_132_DATA 0x00000000 +#define DDRSS1_PHY_133_DATA 0x00000000 +#define DDRSS1_PHY_134_DATA 0x00080200 +#define DDRSS1_PHY_135_DATA 0x00000000 +#define DDRSS1_PHY_136_DATA 0x20202020 +#define DDRSS1_PHY_137_DATA 0x20202020 +#define DDRSS1_PHY_138_DATA 0xF0F02020 +#define DDRSS1_PHY_139_DATA 0x00000000 +#define DDRSS1_PHY_140_DATA 0x00000000 +#define DDRSS1_PHY_141_DATA 0x00000000 +#define DDRSS1_PHY_142_DATA 0x00000000 +#define DDRSS1_PHY_143_DATA 0x00000000 +#define DDRSS1_PHY_144_DATA 0x00000000 +#define DDRSS1_PHY_145_DATA 0x00000000 +#define DDRSS1_PHY_146_DATA 0x00000000 +#define DDRSS1_PHY_147_DATA 0x00000000 +#define DDRSS1_PHY_148_DATA 0x00000000 +#define DDRSS1_PHY_149_DATA 0x00000000 +#define DDRSS1_PHY_150_DATA 0x00000000 +#define DDRSS1_PHY_151_DATA 0x00000000 +#define DDRSS1_PHY_152_DATA 0x00000000 +#define DDRSS1_PHY_153_DATA 0x00000000 +#define DDRSS1_PHY_154_DATA 0x00000000 +#define DDRSS1_PHY_155_DATA 0x00000000 +#define DDRSS1_PHY_156_DATA 0x00000000 +#define DDRSS1_PHY_157_DATA 0x00000000 +#define DDRSS1_PHY_158_DATA 0x00000000 +#define DDRSS1_PHY_159_DATA 0x00000000 +#define DDRSS1_PHY_160_DATA 0x00000000 +#define DDRSS1_PHY_161_DATA 0x00000000 +#define DDRSS1_PHY_162_DATA 0x00000000 +#define DDRSS1_PHY_163_DATA 0x00000000 +#define DDRSS1_PHY_164_DATA 0x00000000 +#define DDRSS1_PHY_165_DATA 0x00000000 +#define DDRSS1_PHY_166_DATA 0x00000000 +#define DDRSS1_PHY_167_DATA 0x00000000 +#define DDRSS1_PHY_168_DATA 0x00000000 +#define DDRSS1_PHY_169_DATA 0x00000000 +#define DDRSS1_PHY_170_DATA 0x00000000 +#define DDRSS1_PHY_171_DATA 0x00000000 +#define DDRSS1_PHY_172_DATA 0x00000000 +#define DDRSS1_PHY_173_DATA 0x00000000 +#define DDRSS1_PHY_174_DATA 0x00000000 +#define DDRSS1_PHY_175_DATA 0x00000000 +#define DDRSS1_PHY_176_DATA 0x00000000 +#define DDRSS1_PHY_177_DATA 0x00000000 +#define DDRSS1_PHY_178_DATA 0x00000000 +#define DDRSS1_PHY_179_DATA 0x00000000 +#define DDRSS1_PHY_180_DATA 0x00000000 +#define DDRSS1_PHY_181_DATA 0x00000000 +#define DDRSS1_PHY_182_DATA 0x00000000 +#define DDRSS1_PHY_183_DATA 0x00000000 +#define DDRSS1_PHY_184_DATA 0x00000000 +#define DDRSS1_PHY_185_DATA 0x00000000 +#define DDRSS1_PHY_186_DATA 0x00000000 +#define DDRSS1_PHY_187_DATA 0x00000000 +#define DDRSS1_PHY_188_DATA 0x00000000 +#define DDRSS1_PHY_189_DATA 0x00000000 +#define DDRSS1_PHY_190_DATA 0x00000000 +#define DDRSS1_PHY_191_DATA 0x00000000 +#define DDRSS1_PHY_192_DATA 0x00000000 +#define DDRSS1_PHY_193_DATA 0x00000000 +#define DDRSS1_PHY_194_DATA 0x00000000 +#define DDRSS1_PHY_195_DATA 0x00000000 +#define DDRSS1_PHY_196_DATA 0x00000000 +#define DDRSS1_PHY_197_DATA 0x00000000 +#define DDRSS1_PHY_198_DATA 0x00000000 +#define DDRSS1_PHY_199_DATA 0x00000000 +#define DDRSS1_PHY_200_DATA 0x00000000 +#define DDRSS1_PHY_201_DATA 0x00000000 +#define DDRSS1_PHY_202_DATA 0x00000000 +#define DDRSS1_PHY_203_DATA 0x00000000 +#define DDRSS1_PHY_204_DATA 0x00000000 +#define DDRSS1_PHY_205_DATA 0x00000000 +#define DDRSS1_PHY_206_DATA 0x00000000 +#define DDRSS1_PHY_207_DATA 0x00000000 +#define DDRSS1_PHY_208_DATA 0x00000000 +#define DDRSS1_PHY_209_DATA 0x00000000 +#define DDRSS1_PHY_210_DATA 0x00000000 +#define DDRSS1_PHY_211_DATA 0x00000000 +#define DDRSS1_PHY_212_DATA 0x00000000 +#define DDRSS1_PHY_213_DATA 0x00000000 +#define DDRSS1_PHY_214_DATA 0x00000000 +#define DDRSS1_PHY_215_DATA 0x00000000 +#define DDRSS1_PHY_216_DATA 0x00000000 +#define DDRSS1_PHY_217_DATA 0x00000000 +#define DDRSS1_PHY_218_DATA 0x00000000 +#define DDRSS1_PHY_219_DATA 0x00000000 +#define DDRSS1_PHY_220_DATA 0x00000000 +#define DDRSS1_PHY_221_DATA 0x00000000 +#define DDRSS1_PHY_222_DATA 0x00000000 +#define DDRSS1_PHY_223_DATA 0x00000000 +#define DDRSS1_PHY_224_DATA 0x00000000 +#define DDRSS1_PHY_225_DATA 0x00000000 +#define DDRSS1_PHY_226_DATA 0x00000000 +#define DDRSS1_PHY_227_DATA 0x00000000 +#define DDRSS1_PHY_228_DATA 0x00000000 +#define DDRSS1_PHY_229_DATA 0x00000000 +#define DDRSS1_PHY_230_DATA 0x00000000 +#define DDRSS1_PHY_231_DATA 0x00000000 +#define DDRSS1_PHY_232_DATA 0x00000000 +#define DDRSS1_PHY_233_DATA 0x00000000 +#define DDRSS1_PHY_234_DATA 0x00000000 +#define DDRSS1_PHY_235_DATA 0x00000000 +#define DDRSS1_PHY_236_DATA 0x00000000 +#define DDRSS1_PHY_237_DATA 0x00000000 +#define DDRSS1_PHY_238_DATA 0x00000000 +#define DDRSS1_PHY_239_DATA 0x00000000 +#define DDRSS1_PHY_240_DATA 0x00000000 +#define DDRSS1_PHY_241_DATA 0x00000000 +#define DDRSS1_PHY_242_DATA 0x00000000 +#define DDRSS1_PHY_243_DATA 0x00000000 +#define DDRSS1_PHY_244_DATA 0x00000000 +#define DDRSS1_PHY_245_DATA 0x00000000 +#define DDRSS1_PHY_246_DATA 0x00000000 +#define DDRSS1_PHY_247_DATA 0x00000000 +#define DDRSS1_PHY_248_DATA 0x00000000 +#define DDRSS1_PHY_249_DATA 0x00000000 +#define DDRSS1_PHY_250_DATA 0x00000000 +#define DDRSS1_PHY_251_DATA 0x00000000 +#define DDRSS1_PHY_252_DATA 0x00000000 +#define DDRSS1_PHY_253_DATA 0x00000000 +#define DDRSS1_PHY_254_DATA 0x00000000 +#define DDRSS1_PHY_255_DATA 0x00000000 +#define DDRSS1_PHY_256_DATA 0x000004F0 +#define DDRSS1_PHY_257_DATA 0x00000000 +#define DDRSS1_PHY_258_DATA 0x00030200 +#define DDRSS1_PHY_259_DATA 0x00000000 +#define DDRSS1_PHY_260_DATA 0x00000000 +#define DDRSS1_PHY_261_DATA 0x01030000 +#define DDRSS1_PHY_262_DATA 0x00010000 +#define DDRSS1_PHY_263_DATA 0x01030004 +#define DDRSS1_PHY_264_DATA 0x01000000 +#define DDRSS1_PHY_265_DATA 0x00000000 +#define DDRSS1_PHY_266_DATA 0x00000000 +#define DDRSS1_PHY_267_DATA 0x01000001 +#define DDRSS1_PHY_268_DATA 0x00000200 +#define DDRSS1_PHY_269_DATA 0x000800C0 +#define DDRSS1_PHY_270_DATA 0x060100CC +#define DDRSS1_PHY_271_DATA 0x00030066 +#define DDRSS1_PHY_272_DATA 0x00000000 +#define DDRSS1_PHY_273_DATA 0x00000301 +#define DDRSS1_PHY_274_DATA 0x0000AAAA +#define DDRSS1_PHY_275_DATA 0x00005555 +#define DDRSS1_PHY_276_DATA 0x0000B5B5 +#define DDRSS1_PHY_277_DATA 0x00004A4A +#define DDRSS1_PHY_278_DATA 0x00005656 +#define DDRSS1_PHY_279_DATA 0x0000A9A9 +#define DDRSS1_PHY_280_DATA 0x0000A9A9 +#define DDRSS1_PHY_281_DATA 0x0000B5B5 +#define DDRSS1_PHY_282_DATA 0x00000000 +#define DDRSS1_PHY_283_DATA 0x00000000 +#define DDRSS1_PHY_284_DATA 0x2A000000 +#define DDRSS1_PHY_285_DATA 0x00000808 +#define DDRSS1_PHY_286_DATA 0x0F000000 +#define DDRSS1_PHY_287_DATA 0x00000F08 +#define DDRSS1_PHY_288_DATA 0x10400000 +#define DDRSS1_PHY_289_DATA 0x0C002006 +#define DDRSS1_PHY_290_DATA 0x00000000 +#define DDRSS1_PHY_291_DATA 0x00000000 +#define DDRSS1_PHY_292_DATA 0x55555555 +#define DDRSS1_PHY_293_DATA 0xAAAAAAAA +#define DDRSS1_PHY_294_DATA 0x55555555 +#define DDRSS1_PHY_295_DATA 0xAAAAAAAA +#define DDRSS1_PHY_296_DATA 0x00005555 +#define DDRSS1_PHY_297_DATA 0x01000100 +#define DDRSS1_PHY_298_DATA 0x00800180 +#define DDRSS1_PHY_299_DATA 0x00000000 +#define DDRSS1_PHY_300_DATA 0x00000000 +#define DDRSS1_PHY_301_DATA 0x00000000 +#define DDRSS1_PHY_302_DATA 0x00000000 +#define DDRSS1_PHY_303_DATA 0x00000000 +#define DDRSS1_PHY_304_DATA 0x00000000 +#define DDRSS1_PHY_305_DATA 0x00000000 +#define DDRSS1_PHY_306_DATA 0x00000000 +#define DDRSS1_PHY_307_DATA 0x00000000 +#define DDRSS1_PHY_308_DATA 0x00000000 +#define DDRSS1_PHY_309_DATA 0x00000000 +#define DDRSS1_PHY_310_DATA 0x00000000 +#define DDRSS1_PHY_311_DATA 0x00000000 +#define DDRSS1_PHY_312_DATA 0x00000000 +#define DDRSS1_PHY_313_DATA 0x00000000 +#define DDRSS1_PHY_314_DATA 0x00000000 +#define DDRSS1_PHY_315_DATA 0x00000000 +#define DDRSS1_PHY_316_DATA 0x00000000 +#define DDRSS1_PHY_317_DATA 0x00000000 +#define DDRSS1_PHY_318_DATA 0x00000000 +#define DDRSS1_PHY_319_DATA 0x00000000 +#define DDRSS1_PHY_320_DATA 0x00000000 +#define DDRSS1_PHY_321_DATA 0x00000000 +#define DDRSS1_PHY_322_DATA 0x00000104 +#define DDRSS1_PHY_323_DATA 0x00000120 +#define DDRSS1_PHY_324_DATA 0x00000000 +#define DDRSS1_PHY_325_DATA 0x00000000 +#define DDRSS1_PHY_326_DATA 0x00000000 +#define DDRSS1_PHY_327_DATA 0x00000000 +#define DDRSS1_PHY_328_DATA 0x00000000 +#define DDRSS1_PHY_329_DATA 0x00000000 +#define DDRSS1_PHY_330_DATA 0x00000000 +#define DDRSS1_PHY_331_DATA 0x00000001 +#define DDRSS1_PHY_332_DATA 0x07FF0000 +#define DDRSS1_PHY_333_DATA 0x0080081F +#define DDRSS1_PHY_334_DATA 0x00081020 +#define DDRSS1_PHY_335_DATA 0x04010000 +#define DDRSS1_PHY_336_DATA 0x00000000 +#define DDRSS1_PHY_337_DATA 0x00000000 +#define DDRSS1_PHY_338_DATA 0x00000000 +#define DDRSS1_PHY_339_DATA 0x00000100 +#define DDRSS1_PHY_340_DATA 0x01CC0C01 +#define DDRSS1_PHY_341_DATA 0x1003CC0C +#define DDRSS1_PHY_342_DATA 0x20000140 +#define DDRSS1_PHY_343_DATA 0x07FF0200 +#define DDRSS1_PHY_344_DATA 0x0000DD01 +#define DDRSS1_PHY_345_DATA 0x10100303 +#define DDRSS1_PHY_346_DATA 0x10101010 +#define DDRSS1_PHY_347_DATA 0x10101010 +#define DDRSS1_PHY_348_DATA 0x00021010 +#define DDRSS1_PHY_349_DATA 0x00100010 +#define DDRSS1_PHY_350_DATA 0x00100010 +#define DDRSS1_PHY_351_DATA 0x00100010 +#define DDRSS1_PHY_352_DATA 0x00100010 +#define DDRSS1_PHY_353_DATA 0x00050010 +#define DDRSS1_PHY_354_DATA 0x51517041 +#define DDRSS1_PHY_355_DATA 0x31C06001 +#define DDRSS1_PHY_356_DATA 0x07AB01AB +#define DDRSS1_PHY_357_DATA 0x00C0C001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 +#define DDRSS1_PHY_359_DATA 0x10001000 +#define DDRSS1_PHY_360_DATA 0x0C083E42 +#define DDRSS1_PHY_361_DATA 0x0F0C3701 +#define DDRSS1_PHY_362_DATA 0x01000140 +#define DDRSS1_PHY_363_DATA 0x0C000420 +#define DDRSS1_PHY_364_DATA 0x00000198 +#define DDRSS1_PHY_365_DATA 0x0A0000D0 +#define DDRSS1_PHY_366_DATA 0x00030200 +#define DDRSS1_PHY_367_DATA 0x02800000 +#define DDRSS1_PHY_368_DATA 0x80800000 +#define DDRSS1_PHY_369_DATA 0x000E2010 +#define DDRSS1_PHY_370_DATA 0x76543210 +#define DDRSS1_PHY_371_DATA 0x00000008 +#define DDRSS1_PHY_372_DATA 0x02800280 +#define DDRSS1_PHY_373_DATA 0x02800280 +#define DDRSS1_PHY_374_DATA 0x02800280 +#define DDRSS1_PHY_375_DATA 0x02800280 +#define DDRSS1_PHY_376_DATA 0x00000280 +#define DDRSS1_PHY_377_DATA 0x0000A000 +#define DDRSS1_PHY_378_DATA 0x00A000A0 +#define DDRSS1_PHY_379_DATA 0x00A000A0 +#define DDRSS1_PHY_380_DATA 0x00A000A0 +#define DDRSS1_PHY_381_DATA 0x00A000A0 +#define DDRSS1_PHY_382_DATA 0x00A000A0 +#define DDRSS1_PHY_383_DATA 0x00A000A0 +#define DDRSS1_PHY_384_DATA 0x00A000A0 +#define DDRSS1_PHY_385_DATA 0x00A000A0 +#define DDRSS1_PHY_386_DATA 0x01C200A0 +#define DDRSS1_PHY_387_DATA 0x01A00005 +#define DDRSS1_PHY_388_DATA 0x00000000 +#define DDRSS1_PHY_389_DATA 0x00000000 +#define DDRSS1_PHY_390_DATA 0x00080200 +#define DDRSS1_PHY_391_DATA 0x00000000 +#define DDRSS1_PHY_392_DATA 0x20202020 +#define DDRSS1_PHY_393_DATA 0x20202020 +#define DDRSS1_PHY_394_DATA 0xF0F02020 +#define DDRSS1_PHY_395_DATA 0x00000000 +#define DDRSS1_PHY_396_DATA 0x00000000 +#define DDRSS1_PHY_397_DATA 0x00000000 +#define DDRSS1_PHY_398_DATA 0x00000000 +#define DDRSS1_PHY_399_DATA 0x00000000 +#define DDRSS1_PHY_400_DATA 0x00000000 +#define DDRSS1_PHY_401_DATA 0x00000000 +#define DDRSS1_PHY_402_DATA 0x00000000 +#define DDRSS1_PHY_403_DATA 0x00000000 +#define DDRSS1_PHY_404_DATA 0x00000000 +#define DDRSS1_PHY_405_DATA 0x00000000 +#define DDRSS1_PHY_406_DATA 0x00000000 +#define DDRSS1_PHY_407_DATA 0x00000000 +#define DDRSS1_PHY_408_DATA 0x00000000 +#define DDRSS1_PHY_409_DATA 0x00000000 +#define DDRSS1_PHY_410_DATA 0x00000000 +#define DDRSS1_PHY_411_DATA 0x00000000 +#define DDRSS1_PHY_412_DATA 0x00000000 +#define DDRSS1_PHY_413_DATA 0x00000000 +#define DDRSS1_PHY_414_DATA 0x00000000 +#define DDRSS1_PHY_415_DATA 0x00000000 +#define DDRSS1_PHY_416_DATA 0x00000000 +#define DDRSS1_PHY_417_DATA 0x00000000 +#define DDRSS1_PHY_418_DATA 0x00000000 +#define DDRSS1_PHY_419_DATA 0x00000000 +#define DDRSS1_PHY_420_DATA 0x00000000 +#define DDRSS1_PHY_421_DATA 0x00000000 +#define DDRSS1_PHY_422_DATA 0x00000000 +#define DDRSS1_PHY_423_DATA 0x00000000 +#define DDRSS1_PHY_424_DATA 0x00000000 +#define DDRSS1_PHY_425_DATA 0x00000000 +#define DDRSS1_PHY_426_DATA 0x00000000 +#define DDRSS1_PHY_427_DATA 0x00000000 +#define DDRSS1_PHY_428_DATA 0x00000000 +#define DDRSS1_PHY_429_DATA 0x00000000 +#define DDRSS1_PHY_430_DATA 0x00000000 +#define DDRSS1_PHY_431_DATA 0x00000000 +#define DDRSS1_PHY_432_DATA 0x00000000 +#define DDRSS1_PHY_433_DATA 0x00000000 +#define DDRSS1_PHY_434_DATA 0x00000000 +#define DDRSS1_PHY_435_DATA 0x00000000 +#define DDRSS1_PHY_436_DATA 0x00000000 +#define DDRSS1_PHY_437_DATA 0x00000000 +#define DDRSS1_PHY_438_DATA 0x00000000 +#define DDRSS1_PHY_439_DATA 0x00000000 +#define DDRSS1_PHY_440_DATA 0x00000000 +#define DDRSS1_PHY_441_DATA 0x00000000 +#define DDRSS1_PHY_442_DATA 0x00000000 +#define DDRSS1_PHY_443_DATA 0x00000000 +#define DDRSS1_PHY_444_DATA 0x00000000 +#define DDRSS1_PHY_445_DATA 0x00000000 +#define DDRSS1_PHY_446_DATA 0x00000000 +#define DDRSS1_PHY_447_DATA 0x00000000 +#define DDRSS1_PHY_448_DATA 0x00000000 +#define DDRSS1_PHY_449_DATA 0x00000000 +#define DDRSS1_PHY_450_DATA 0x00000000 +#define DDRSS1_PHY_451_DATA 0x00000000 +#define DDRSS1_PHY_452_DATA 0x00000000 +#define DDRSS1_PHY_453_DATA 0x00000000 +#define DDRSS1_PHY_454_DATA 0x00000000 +#define DDRSS1_PHY_455_DATA 0x00000000 +#define DDRSS1_PHY_456_DATA 0x00000000 +#define DDRSS1_PHY_457_DATA 0x00000000 +#define DDRSS1_PHY_458_DATA 0x00000000 +#define DDRSS1_PHY_459_DATA 0x00000000 +#define DDRSS1_PHY_460_DATA 0x00000000 +#define DDRSS1_PHY_461_DATA 0x00000000 +#define DDRSS1_PHY_462_DATA 0x00000000 +#define DDRSS1_PHY_463_DATA 0x00000000 +#define DDRSS1_PHY_464_DATA 0x00000000 +#define DDRSS1_PHY_465_DATA 0x00000000 +#define DDRSS1_PHY_466_DATA 0x00000000 +#define DDRSS1_PHY_467_DATA 0x00000000 +#define DDRSS1_PHY_468_DATA 0x00000000 +#define DDRSS1_PHY_469_DATA 0x00000000 +#define DDRSS1_PHY_470_DATA 0x00000000 +#define DDRSS1_PHY_471_DATA 0x00000000 +#define DDRSS1_PHY_472_DATA 0x00000000 +#define DDRSS1_PHY_473_DATA 0x00000000 +#define DDRSS1_PHY_474_DATA 0x00000000 +#define DDRSS1_PHY_475_DATA 0x00000000 +#define DDRSS1_PHY_476_DATA 0x00000000 +#define DDRSS1_PHY_477_DATA 0x00000000 +#define DDRSS1_PHY_478_DATA 0x00000000 +#define DDRSS1_PHY_479_DATA 0x00000000 +#define DDRSS1_PHY_480_DATA 0x00000000 +#define DDRSS1_PHY_481_DATA 0x00000000 +#define DDRSS1_PHY_482_DATA 0x00000000 +#define DDRSS1_PHY_483_DATA 0x00000000 +#define DDRSS1_PHY_484_DATA 0x00000000 +#define DDRSS1_PHY_485_DATA 0x00000000 +#define DDRSS1_PHY_486_DATA 0x00000000 +#define DDRSS1_PHY_487_DATA 0x00000000 +#define DDRSS1_PHY_488_DATA 0x00000000 +#define DDRSS1_PHY_489_DATA 0x00000000 +#define DDRSS1_PHY_490_DATA 0x00000000 +#define DDRSS1_PHY_491_DATA 0x00000000 +#define DDRSS1_PHY_492_DATA 0x00000000 +#define DDRSS1_PHY_493_DATA 0x00000000 +#define DDRSS1_PHY_494_DATA 0x00000000 +#define DDRSS1_PHY_495_DATA 0x00000000 +#define DDRSS1_PHY_496_DATA 0x00000000 +#define DDRSS1_PHY_497_DATA 0x00000000 +#define DDRSS1_PHY_498_DATA 0x00000000 +#define DDRSS1_PHY_499_DATA 0x00000000 +#define DDRSS1_PHY_500_DATA 0x00000000 +#define DDRSS1_PHY_501_DATA 0x00000000 +#define DDRSS1_PHY_502_DATA 0x00000000 +#define DDRSS1_PHY_503_DATA 0x00000000 +#define DDRSS1_PHY_504_DATA 0x00000000 +#define DDRSS1_PHY_505_DATA 0x00000000 +#define DDRSS1_PHY_506_DATA 0x00000000 +#define DDRSS1_PHY_507_DATA 0x00000000 +#define DDRSS1_PHY_508_DATA 0x00000000 +#define DDRSS1_PHY_509_DATA 0x00000000 +#define DDRSS1_PHY_510_DATA 0x00000000 +#define DDRSS1_PHY_511_DATA 0x00000000 +#define DDRSS1_PHY_512_DATA 0x000004F0 +#define DDRSS1_PHY_513_DATA 0x00000000 +#define DDRSS1_PHY_514_DATA 0x00030200 +#define DDRSS1_PHY_515_DATA 0x00000000 +#define DDRSS1_PHY_516_DATA 0x00000000 +#define DDRSS1_PHY_517_DATA 0x01030000 +#define DDRSS1_PHY_518_DATA 0x00010000 +#define DDRSS1_PHY_519_DATA 0x01030004 +#define DDRSS1_PHY_520_DATA 0x01000000 +#define DDRSS1_PHY_521_DATA 0x00000000 +#define DDRSS1_PHY_522_DATA 0x00000000 +#define DDRSS1_PHY_523_DATA 0x01000001 +#define DDRSS1_PHY_524_DATA 0x00000200 +#define DDRSS1_PHY_525_DATA 0x000800C0 +#define DDRSS1_PHY_526_DATA 0x060100CC +#define DDRSS1_PHY_527_DATA 0x00030066 +#define DDRSS1_PHY_528_DATA 0x00000000 +#define DDRSS1_PHY_529_DATA 0x00000301 +#define DDRSS1_PHY_530_DATA 0x0000AAAA +#define DDRSS1_PHY_531_DATA 0x00005555 +#define DDRSS1_PHY_532_DATA 0x0000B5B5 +#define DDRSS1_PHY_533_DATA 0x00004A4A +#define DDRSS1_PHY_534_DATA 0x00005656 +#define DDRSS1_PHY_535_DATA 0x0000A9A9 +#define DDRSS1_PHY_536_DATA 0x0000A9A9 +#define DDRSS1_PHY_537_DATA 0x0000B5B5 +#define DDRSS1_PHY_538_DATA 0x00000000 +#define DDRSS1_PHY_539_DATA 0x00000000 +#define DDRSS1_PHY_540_DATA 0x2A000000 +#define DDRSS1_PHY_541_DATA 0x00000808 +#define DDRSS1_PHY_542_DATA 0x0F000000 +#define DDRSS1_PHY_543_DATA 0x00000F08 +#define DDRSS1_PHY_544_DATA 0x10400000 +#define DDRSS1_PHY_545_DATA 0x0C002006 +#define DDRSS1_PHY_546_DATA 0x00000000 +#define DDRSS1_PHY_547_DATA 0x00000000 +#define DDRSS1_PHY_548_DATA 0x55555555 +#define DDRSS1_PHY_549_DATA 0xAAAAAAAA +#define DDRSS1_PHY_550_DATA 0x55555555 +#define DDRSS1_PHY_551_DATA 0xAAAAAAAA +#define DDRSS1_PHY_552_DATA 0x00005555 +#define DDRSS1_PHY_553_DATA 0x01000100 +#define DDRSS1_PHY_554_DATA 0x00800180 +#define DDRSS1_PHY_555_DATA 0x00000001 +#define DDRSS1_PHY_556_DATA 0x00000000 +#define DDRSS1_PHY_557_DATA 0x00000000 +#define DDRSS1_PHY_558_DATA 0x00000000 +#define DDRSS1_PHY_559_DATA 0x00000000 +#define DDRSS1_PHY_560_DATA 0x00000000 +#define DDRSS1_PHY_561_DATA 0x00000000 +#define DDRSS1_PHY_562_DATA 0x00000000 +#define DDRSS1_PHY_563_DATA 0x00000000 +#define DDRSS1_PHY_564_DATA 0x00000000 +#define DDRSS1_PHY_565_DATA 0x00000000 +#define DDRSS1_PHY_566_DATA 0x00000000 +#define DDRSS1_PHY_567_DATA 0x00000000 +#define DDRSS1_PHY_568_DATA 0x00000000 +#define DDRSS1_PHY_569_DATA 0x00000000 +#define DDRSS1_PHY_570_DATA 0x00000000 +#define DDRSS1_PHY_571_DATA 0x00000000 +#define DDRSS1_PHY_572_DATA 0x00000000 +#define DDRSS1_PHY_573_DATA 0x00000000 +#define DDRSS1_PHY_574_DATA 0x00000000 +#define DDRSS1_PHY_575_DATA 0x00000000 +#define DDRSS1_PHY_576_DATA 0x00000000 +#define DDRSS1_PHY_577_DATA 0x00000000 +#define DDRSS1_PHY_578_DATA 0x00000104 +#define DDRSS1_PHY_579_DATA 0x00000120 +#define DDRSS1_PHY_580_DATA 0x00000000 +#define DDRSS1_PHY_581_DATA 0x00000000 +#define DDRSS1_PHY_582_DATA 0x00000000 +#define DDRSS1_PHY_583_DATA 0x00000000 +#define DDRSS1_PHY_584_DATA 0x00000000 +#define DDRSS1_PHY_585_DATA 0x00000000 +#define DDRSS1_PHY_586_DATA 0x00000000 +#define DDRSS1_PHY_587_DATA 0x00000001 +#define DDRSS1_PHY_588_DATA 0x07FF0000 +#define DDRSS1_PHY_589_DATA 0x0080081F +#define DDRSS1_PHY_590_DATA 0x00081020 +#define DDRSS1_PHY_591_DATA 0x04010000 +#define DDRSS1_PHY_592_DATA 0x00000000 +#define DDRSS1_PHY_593_DATA 0x00000000 +#define DDRSS1_PHY_594_DATA 0x00000000 +#define DDRSS1_PHY_595_DATA 0x00000100 +#define DDRSS1_PHY_596_DATA 0x01CC0C01 +#define DDRSS1_PHY_597_DATA 0x1003CC0C +#define DDRSS1_PHY_598_DATA 0x20000140 +#define DDRSS1_PHY_599_DATA 0x07FF0200 +#define DDRSS1_PHY_600_DATA 0x0000DD01 +#define DDRSS1_PHY_601_DATA 0x10100303 +#define DDRSS1_PHY_602_DATA 0x10101010 +#define DDRSS1_PHY_603_DATA 0x10101010 +#define DDRSS1_PHY_604_DATA 0x00021010 +#define DDRSS1_PHY_605_DATA 0x00100010 +#define DDRSS1_PHY_606_DATA 0x00100010 +#define DDRSS1_PHY_607_DATA 0x00100010 +#define DDRSS1_PHY_608_DATA 0x00100010 +#define DDRSS1_PHY_609_DATA 0x00050010 +#define DDRSS1_PHY_610_DATA 0x51517041 +#define DDRSS1_PHY_611_DATA 0x31C06001 +#define DDRSS1_PHY_612_DATA 0x07AB01AB +#define DDRSS1_PHY_613_DATA 0x00C0C001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 +#define DDRSS1_PHY_615_DATA 0x10001000 +#define DDRSS1_PHY_616_DATA 0x0C083E42 +#define DDRSS1_PHY_617_DATA 0x0F0C3701 +#define DDRSS1_PHY_618_DATA 0x01000140 +#define DDRSS1_PHY_619_DATA 0x0C000420 +#define DDRSS1_PHY_620_DATA 0x00000198 +#define DDRSS1_PHY_621_DATA 0x0A0000D0 +#define DDRSS1_PHY_622_DATA 0x00030200 +#define DDRSS1_PHY_623_DATA 0x02800000 +#define DDRSS1_PHY_624_DATA 0x80800000 +#define DDRSS1_PHY_625_DATA 0x000E2010 +#define DDRSS1_PHY_626_DATA 0x76543210 +#define DDRSS1_PHY_627_DATA 0x00000008 +#define DDRSS1_PHY_628_DATA 0x02800280 +#define DDRSS1_PHY_629_DATA 0x02800280 +#define DDRSS1_PHY_630_DATA 0x02800280 +#define DDRSS1_PHY_631_DATA 0x02800280 +#define DDRSS1_PHY_632_DATA 0x00000280 +#define DDRSS1_PHY_633_DATA 0x0000A000 +#define DDRSS1_PHY_634_DATA 0x00A000A0 +#define DDRSS1_PHY_635_DATA 0x00A000A0 +#define DDRSS1_PHY_636_DATA 0x00A000A0 +#define DDRSS1_PHY_637_DATA 0x00A000A0 +#define DDRSS1_PHY_638_DATA 0x00A000A0 +#define DDRSS1_PHY_639_DATA 0x00A000A0 +#define DDRSS1_PHY_640_DATA 0x00A000A0 +#define DDRSS1_PHY_641_DATA 0x00A000A0 +#define DDRSS1_PHY_642_DATA 0x01C200A0 +#define DDRSS1_PHY_643_DATA 0x01A00005 +#define DDRSS1_PHY_644_DATA 0x00000000 +#define DDRSS1_PHY_645_DATA 0x00000000 +#define DDRSS1_PHY_646_DATA 0x00080200 +#define DDRSS1_PHY_647_DATA 0x00000000 +#define DDRSS1_PHY_648_DATA 0x20202020 +#define DDRSS1_PHY_649_DATA 0x20202020 +#define DDRSS1_PHY_650_DATA 0xF0F02020 +#define DDRSS1_PHY_651_DATA 0x00000000 +#define DDRSS1_PHY_652_DATA 0x00000000 +#define DDRSS1_PHY_653_DATA 0x00000000 +#define DDRSS1_PHY_654_DATA 0x00000000 +#define DDRSS1_PHY_655_DATA 0x00000000 +#define DDRSS1_PHY_656_DATA 0x00000000 +#define DDRSS1_PHY_657_DATA 0x00000000 +#define DDRSS1_PHY_658_DATA 0x00000000 +#define DDRSS1_PHY_659_DATA 0x00000000 +#define DDRSS1_PHY_660_DATA 0x00000000 +#define DDRSS1_PHY_661_DATA 0x00000000 +#define DDRSS1_PHY_662_DATA 0x00000000 +#define DDRSS1_PHY_663_DATA 0x00000000 +#define DDRSS1_PHY_664_DATA 0x00000000 +#define DDRSS1_PHY_665_DATA 0x00000000 +#define DDRSS1_PHY_666_DATA 0x00000000 +#define DDRSS1_PHY_667_DATA 0x00000000 +#define DDRSS1_PHY_668_DATA 0x00000000 +#define DDRSS1_PHY_669_DATA 0x00000000 +#define DDRSS1_PHY_670_DATA 0x00000000 +#define DDRSS1_PHY_671_DATA 0x00000000 +#define DDRSS1_PHY_672_DATA 0x00000000 +#define DDRSS1_PHY_673_DATA 0x00000000 +#define DDRSS1_PHY_674_DATA 0x00000000 +#define DDRSS1_PHY_675_DATA 0x00000000 +#define DDRSS1_PHY_676_DATA 0x00000000 +#define DDRSS1_PHY_677_DATA 0x00000000 +#define DDRSS1_PHY_678_DATA 0x00000000 +#define DDRSS1_PHY_679_DATA 0x00000000 +#define DDRSS1_PHY_680_DATA 0x00000000 +#define DDRSS1_PHY_681_DATA 0x00000000 +#define DDRSS1_PHY_682_DATA 0x00000000 +#define DDRSS1_PHY_683_DATA 0x00000000 +#define DDRSS1_PHY_684_DATA 0x00000000 +#define DDRSS1_PHY_685_DATA 0x00000000 +#define DDRSS1_PHY_686_DATA 0x00000000 +#define DDRSS1_PHY_687_DATA 0x00000000 +#define DDRSS1_PHY_688_DATA 0x00000000 +#define DDRSS1_PHY_689_DATA 0x00000000 +#define DDRSS1_PHY_690_DATA 0x00000000 +#define DDRSS1_PHY_691_DATA 0x00000000 +#define DDRSS1_PHY_692_DATA 0x00000000 +#define DDRSS1_PHY_693_DATA 0x00000000 +#define DDRSS1_PHY_694_DATA 0x00000000 +#define DDRSS1_PHY_695_DATA 0x00000000 +#define DDRSS1_PHY_696_DATA 0x00000000 +#define DDRSS1_PHY_697_DATA 0x00000000 +#define DDRSS1_PHY_698_DATA 0x00000000 +#define DDRSS1_PHY_699_DATA 0x00000000 +#define DDRSS1_PHY_700_DATA 0x00000000 +#define DDRSS1_PHY_701_DATA 0x00000000 +#define DDRSS1_PHY_702_DATA 0x00000000 +#define DDRSS1_PHY_703_DATA 0x00000000 +#define DDRSS1_PHY_704_DATA 0x00000000 +#define DDRSS1_PHY_705_DATA 0x00000000 +#define DDRSS1_PHY_706_DATA 0x00000000 +#define DDRSS1_PHY_707_DATA 0x00000000 +#define DDRSS1_PHY_708_DATA 0x00000000 +#define DDRSS1_PHY_709_DATA 0x00000000 +#define DDRSS1_PHY_710_DATA 0x00000000 +#define DDRSS1_PHY_711_DATA 0x00000000 +#define DDRSS1_PHY_712_DATA 0x00000000 +#define DDRSS1_PHY_713_DATA 0x00000000 +#define DDRSS1_PHY_714_DATA 0x00000000 +#define DDRSS1_PHY_715_DATA 0x00000000 +#define DDRSS1_PHY_716_DATA 0x00000000 +#define DDRSS1_PHY_717_DATA 0x00000000 +#define DDRSS1_PHY_718_DATA 0x00000000 +#define DDRSS1_PHY_719_DATA 0x00000000 +#define DDRSS1_PHY_720_DATA 0x00000000 +#define DDRSS1_PHY_721_DATA 0x00000000 +#define DDRSS1_PHY_722_DATA 0x00000000 +#define DDRSS1_PHY_723_DATA 0x00000000 +#define DDRSS1_PHY_724_DATA 0x00000000 +#define DDRSS1_PHY_725_DATA 0x00000000 +#define DDRSS1_PHY_726_DATA 0x00000000 +#define DDRSS1_PHY_727_DATA 0x00000000 +#define DDRSS1_PHY_728_DATA 0x00000000 +#define DDRSS1_PHY_729_DATA 0x00000000 +#define DDRSS1_PHY_730_DATA 0x00000000 +#define DDRSS1_PHY_731_DATA 0x00000000 +#define DDRSS1_PHY_732_DATA 0x00000000 +#define DDRSS1_PHY_733_DATA 0x00000000 +#define DDRSS1_PHY_734_DATA 0x00000000 +#define DDRSS1_PHY_735_DATA 0x00000000 +#define DDRSS1_PHY_736_DATA 0x00000000 +#define DDRSS1_PHY_737_DATA 0x00000000 +#define DDRSS1_PHY_738_DATA 0x00000000 +#define DDRSS1_PHY_739_DATA 0x00000000 +#define DDRSS1_PHY_740_DATA 0x00000000 +#define DDRSS1_PHY_741_DATA 0x00000000 +#define DDRSS1_PHY_742_DATA 0x00000000 +#define DDRSS1_PHY_743_DATA 0x00000000 +#define DDRSS1_PHY_744_DATA 0x00000000 +#define DDRSS1_PHY_745_DATA 0x00000000 +#define DDRSS1_PHY_746_DATA 0x00000000 +#define DDRSS1_PHY_747_DATA 0x00000000 +#define DDRSS1_PHY_748_DATA 0x00000000 +#define DDRSS1_PHY_749_DATA 0x00000000 +#define DDRSS1_PHY_750_DATA 0x00000000 +#define DDRSS1_PHY_751_DATA 0x00000000 +#define DDRSS1_PHY_752_DATA 0x00000000 +#define DDRSS1_PHY_753_DATA 0x00000000 +#define DDRSS1_PHY_754_DATA 0x00000000 +#define DDRSS1_PHY_755_DATA 0x00000000 +#define DDRSS1_PHY_756_DATA 0x00000000 +#define DDRSS1_PHY_757_DATA 0x00000000 +#define DDRSS1_PHY_758_DATA 0x00000000 +#define DDRSS1_PHY_759_DATA 0x00000000 +#define DDRSS1_PHY_760_DATA 0x00000000 +#define DDRSS1_PHY_761_DATA 0x00000000 +#define DDRSS1_PHY_762_DATA 0x00000000 +#define DDRSS1_PHY_763_DATA 0x00000000 +#define DDRSS1_PHY_764_DATA 0x00000000 +#define DDRSS1_PHY_765_DATA 0x00000000 +#define DDRSS1_PHY_766_DATA 0x00000000 +#define DDRSS1_PHY_767_DATA 0x00000000 +#define DDRSS1_PHY_768_DATA 0x000004F0 +#define DDRSS1_PHY_769_DATA 0x00000000 +#define DDRSS1_PHY_770_DATA 0x00030200 +#define DDRSS1_PHY_771_DATA 0x00000000 +#define DDRSS1_PHY_772_DATA 0x00000000 +#define DDRSS1_PHY_773_DATA 0x01030000 +#define DDRSS1_PHY_774_DATA 0x00010000 +#define DDRSS1_PHY_775_DATA 0x01030004 +#define DDRSS1_PHY_776_DATA 0x01000000 +#define DDRSS1_PHY_777_DATA 0x00000000 +#define DDRSS1_PHY_778_DATA 0x00000000 +#define DDRSS1_PHY_779_DATA 0x01000001 +#define DDRSS1_PHY_780_DATA 0x00000200 +#define DDRSS1_PHY_781_DATA 0x000800C0 +#define DDRSS1_PHY_782_DATA 0x060100CC +#define DDRSS1_PHY_783_DATA 0x00030066 +#define DDRSS1_PHY_784_DATA 0x00000000 +#define DDRSS1_PHY_785_DATA 0x00000301 +#define DDRSS1_PHY_786_DATA 0x0000AAAA +#define DDRSS1_PHY_787_DATA 0x00005555 +#define DDRSS1_PHY_788_DATA 0x0000B5B5 +#define DDRSS1_PHY_789_DATA 0x00004A4A +#define DDRSS1_PHY_790_DATA 0x00005656 +#define DDRSS1_PHY_791_DATA 0x0000A9A9 +#define DDRSS1_PHY_792_DATA 0x0000A9A9 +#define DDRSS1_PHY_793_DATA 0x0000B5B5 +#define DDRSS1_PHY_794_DATA 0x00000000 +#define DDRSS1_PHY_795_DATA 0x00000000 +#define DDRSS1_PHY_796_DATA 0x2A000000 +#define DDRSS1_PHY_797_DATA 0x00000808 +#define DDRSS1_PHY_798_DATA 0x0F000000 +#define DDRSS1_PHY_799_DATA 0x00000F08 +#define DDRSS1_PHY_800_DATA 0x10400000 +#define DDRSS1_PHY_801_DATA 0x0C002006 +#define DDRSS1_PHY_802_DATA 0x00000000 +#define DDRSS1_PHY_803_DATA 0x00000000 +#define DDRSS1_PHY_804_DATA 0x55555555 +#define DDRSS1_PHY_805_DATA 0xAAAAAAAA +#define DDRSS1_PHY_806_DATA 0x55555555 +#define DDRSS1_PHY_807_DATA 0xAAAAAAAA +#define DDRSS1_PHY_808_DATA 0x00005555 +#define DDRSS1_PHY_809_DATA 0x01000100 +#define DDRSS1_PHY_810_DATA 0x00800180 +#define DDRSS1_PHY_811_DATA 0x00000000 +#define DDRSS1_PHY_812_DATA 0x00000000 +#define DDRSS1_PHY_813_DATA 0x00000000 +#define DDRSS1_PHY_814_DATA 0x00000000 +#define DDRSS1_PHY_815_DATA 0x00000000 +#define DDRSS1_PHY_816_DATA 0x00000000 +#define DDRSS1_PHY_817_DATA 0x00000000 +#define DDRSS1_PHY_818_DATA 0x00000000 +#define DDRSS1_PHY_819_DATA 0x00000000 +#define DDRSS1_PHY_820_DATA 0x00000000 +#define DDRSS1_PHY_821_DATA 0x00000000 +#define DDRSS1_PHY_822_DATA 0x00000000 +#define DDRSS1_PHY_823_DATA 0x00000000 +#define DDRSS1_PHY_824_DATA 0x00000000 +#define DDRSS1_PHY_825_DATA 0x00000000 +#define DDRSS1_PHY_826_DATA 0x00000000 +#define DDRSS1_PHY_827_DATA 0x00000000 +#define DDRSS1_PHY_828_DATA 0x00000000 +#define DDRSS1_PHY_829_DATA 0x00000000 +#define DDRSS1_PHY_830_DATA 0x00000000 +#define DDRSS1_PHY_831_DATA 0x00000000 +#define DDRSS1_PHY_832_DATA 0x00000000 +#define DDRSS1_PHY_833_DATA 0x00000000 +#define DDRSS1_PHY_834_DATA 0x00000104 +#define DDRSS1_PHY_835_DATA 0x00000120 +#define DDRSS1_PHY_836_DATA 0x00000000 +#define DDRSS1_PHY_837_DATA 0x00000000 +#define DDRSS1_PHY_838_DATA 0x00000000 +#define DDRSS1_PHY_839_DATA 0x00000000 +#define DDRSS1_PHY_840_DATA 0x00000000 +#define DDRSS1_PHY_841_DATA 0x00000000 +#define DDRSS1_PHY_842_DATA 0x00000000 +#define DDRSS1_PHY_843_DATA 0x00000001 +#define DDRSS1_PHY_844_DATA 0x07FF0000 +#define DDRSS1_PHY_845_DATA 0x0080081F +#define DDRSS1_PHY_846_DATA 0x00081020 +#define DDRSS1_PHY_847_DATA 0x04010000 +#define DDRSS1_PHY_848_DATA 0x00000000 +#define DDRSS1_PHY_849_DATA 0x00000000 +#define DDRSS1_PHY_850_DATA 0x00000000 +#define DDRSS1_PHY_851_DATA 0x00000100 +#define DDRSS1_PHY_852_DATA 0x01CC0C01 +#define DDRSS1_PHY_853_DATA 0x1003CC0C +#define DDRSS1_PHY_854_DATA 0x20000140 +#define DDRSS1_PHY_855_DATA 0x07FF0200 +#define DDRSS1_PHY_856_DATA 0x0000DD01 +#define DDRSS1_PHY_857_DATA 0x10100303 +#define DDRSS1_PHY_858_DATA 0x10101010 +#define DDRSS1_PHY_859_DATA 0x10101010 +#define DDRSS1_PHY_860_DATA 0x00021010 +#define DDRSS1_PHY_861_DATA 0x00100010 +#define DDRSS1_PHY_862_DATA 0x00100010 +#define DDRSS1_PHY_863_DATA 0x00100010 +#define DDRSS1_PHY_864_DATA 0x00100010 +#define DDRSS1_PHY_865_DATA 0x00050010 +#define DDRSS1_PHY_866_DATA 0x51517041 +#define DDRSS1_PHY_867_DATA 0x31C06001 +#define DDRSS1_PHY_868_DATA 0x07AB01AB +#define DDRSS1_PHY_869_DATA 0x00C0C001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 +#define DDRSS1_PHY_871_DATA 0x10001000 +#define DDRSS1_PHY_872_DATA 0x0C083E42 +#define DDRSS1_PHY_873_DATA 0x0F0C3701 +#define DDRSS1_PHY_874_DATA 0x01000140 +#define DDRSS1_PHY_875_DATA 0x0C000420 +#define DDRSS1_PHY_876_DATA 0x00000198 +#define DDRSS1_PHY_877_DATA 0x0A0000D0 +#define DDRSS1_PHY_878_DATA 0x00030200 +#define DDRSS1_PHY_879_DATA 0x02800000 +#define DDRSS1_PHY_880_DATA 0x80800000 +#define DDRSS1_PHY_881_DATA 0x000E2010 +#define DDRSS1_PHY_882_DATA 0x76543210 +#define DDRSS1_PHY_883_DATA 0x00000008 +#define DDRSS1_PHY_884_DATA 0x02800280 +#define DDRSS1_PHY_885_DATA 0x02800280 +#define DDRSS1_PHY_886_DATA 0x02800280 +#define DDRSS1_PHY_887_DATA 0x02800280 +#define DDRSS1_PHY_888_DATA 0x00000280 +#define DDRSS1_PHY_889_DATA 0x0000A000 +#define DDRSS1_PHY_890_DATA 0x00A000A0 +#define DDRSS1_PHY_891_DATA 0x00A000A0 +#define DDRSS1_PHY_892_DATA 0x00A000A0 +#define DDRSS1_PHY_893_DATA 0x00A000A0 +#define DDRSS1_PHY_894_DATA 0x00A000A0 +#define DDRSS1_PHY_895_DATA 0x00A000A0 +#define DDRSS1_PHY_896_DATA 0x00A000A0 +#define DDRSS1_PHY_897_DATA 0x00A000A0 +#define DDRSS1_PHY_898_DATA 0x01C200A0 +#define DDRSS1_PHY_899_DATA 0x01A00005 +#define DDRSS1_PHY_900_DATA 0x00000000 +#define DDRSS1_PHY_901_DATA 0x00000000 +#define DDRSS1_PHY_902_DATA 0x00080200 +#define DDRSS1_PHY_903_DATA 0x00000000 +#define DDRSS1_PHY_904_DATA 0x20202020 +#define DDRSS1_PHY_905_DATA 0x20202020 +#define DDRSS1_PHY_906_DATA 0xF0F02020 +#define DDRSS1_PHY_907_DATA 0x00000000 +#define DDRSS1_PHY_908_DATA 0x00000000 +#define DDRSS1_PHY_909_DATA 0x00000000 +#define DDRSS1_PHY_910_DATA 0x00000000 +#define DDRSS1_PHY_911_DATA 0x00000000 +#define DDRSS1_PHY_912_DATA 0x00000000 +#define DDRSS1_PHY_913_DATA 0x00000000 +#define DDRSS1_PHY_914_DATA 0x00000000 +#define DDRSS1_PHY_915_DATA 0x00000000 +#define DDRSS1_PHY_916_DATA 0x00000000 +#define DDRSS1_PHY_917_DATA 0x00000000 +#define DDRSS1_PHY_918_DATA 0x00000000 +#define DDRSS1_PHY_919_DATA 0x00000000 +#define DDRSS1_PHY_920_DATA 0x00000000 +#define DDRSS1_PHY_921_DATA 0x00000000 +#define DDRSS1_PHY_922_DATA 0x00000000 +#define DDRSS1_PHY_923_DATA 0x00000000 +#define DDRSS1_PHY_924_DATA 0x00000000 +#define DDRSS1_PHY_925_DATA 0x00000000 +#define DDRSS1_PHY_926_DATA 0x00000000 +#define DDRSS1_PHY_927_DATA 0x00000000 +#define DDRSS1_PHY_928_DATA 0x00000000 +#define DDRSS1_PHY_929_DATA 0x00000000 +#define DDRSS1_PHY_930_DATA 0x00000000 +#define DDRSS1_PHY_931_DATA 0x00000000 +#define DDRSS1_PHY_932_DATA 0x00000000 +#define DDRSS1_PHY_933_DATA 0x00000000 +#define DDRSS1_PHY_934_DATA 0x00000000 +#define DDRSS1_PHY_935_DATA 0x00000000 +#define DDRSS1_PHY_936_DATA 0x00000000 +#define DDRSS1_PHY_937_DATA 0x00000000 +#define DDRSS1_PHY_938_DATA 0x00000000 +#define DDRSS1_PHY_939_DATA 0x00000000 +#define DDRSS1_PHY_940_DATA 0x00000000 +#define DDRSS1_PHY_941_DATA 0x00000000 +#define DDRSS1_PHY_942_DATA 0x00000000 +#define DDRSS1_PHY_943_DATA 0x00000000 +#define DDRSS1_PHY_944_DATA 0x00000000 +#define DDRSS1_PHY_945_DATA 0x00000000 +#define DDRSS1_PHY_946_DATA 0x00000000 +#define DDRSS1_PHY_947_DATA 0x00000000 +#define DDRSS1_PHY_948_DATA 0x00000000 +#define DDRSS1_PHY_949_DATA 0x00000000 +#define DDRSS1_PHY_950_DATA 0x00000000 +#define DDRSS1_PHY_951_DATA 0x00000000 +#define DDRSS1_PHY_952_DATA 0x00000000 +#define DDRSS1_PHY_953_DATA 0x00000000 +#define DDRSS1_PHY_954_DATA 0x00000000 +#define DDRSS1_PHY_955_DATA 0x00000000 +#define DDRSS1_PHY_956_DATA 0x00000000 +#define DDRSS1_PHY_957_DATA 0x00000000 +#define DDRSS1_PHY_958_DATA 0x00000000 +#define DDRSS1_PHY_959_DATA 0x00000000 +#define DDRSS1_PHY_960_DATA 0x00000000 +#define DDRSS1_PHY_961_DATA 0x00000000 +#define DDRSS1_PHY_962_DATA 0x00000000 +#define DDRSS1_PHY_963_DATA 0x00000000 +#define DDRSS1_PHY_964_DATA 0x00000000 +#define DDRSS1_PHY_965_DATA 0x00000000 +#define DDRSS1_PHY_966_DATA 0x00000000 +#define DDRSS1_PHY_967_DATA 0x00000000 +#define DDRSS1_PHY_968_DATA 0x00000000 +#define DDRSS1_PHY_969_DATA 0x00000000 +#define DDRSS1_PHY_970_DATA 0x00000000 +#define DDRSS1_PHY_971_DATA 0x00000000 +#define DDRSS1_PHY_972_DATA 0x00000000 +#define DDRSS1_PHY_973_DATA 0x00000000 +#define DDRSS1_PHY_974_DATA 0x00000000 +#define DDRSS1_PHY_975_DATA 0x00000000 +#define DDRSS1_PHY_976_DATA 0x00000000 +#define DDRSS1_PHY_977_DATA 0x00000000 +#define DDRSS1_PHY_978_DATA 0x00000000 +#define DDRSS1_PHY_979_DATA 0x00000000 +#define DDRSS1_PHY_980_DATA 0x00000000 +#define DDRSS1_PHY_981_DATA 0x00000000 +#define DDRSS1_PHY_982_DATA 0x00000000 +#define DDRSS1_PHY_983_DATA 0x00000000 +#define DDRSS1_PHY_984_DATA 0x00000000 +#define DDRSS1_PHY_985_DATA 0x00000000 +#define DDRSS1_PHY_986_DATA 0x00000000 +#define DDRSS1_PHY_987_DATA 0x00000000 +#define DDRSS1_PHY_988_DATA 0x00000000 +#define DDRSS1_PHY_989_DATA 0x00000000 +#define DDRSS1_PHY_990_DATA 0x00000000 +#define DDRSS1_PHY_991_DATA 0x00000000 +#define DDRSS1_PHY_992_DATA 0x00000000 +#define DDRSS1_PHY_993_DATA 0x00000000 +#define DDRSS1_PHY_994_DATA 0x00000000 +#define DDRSS1_PHY_995_DATA 0x00000000 +#define DDRSS1_PHY_996_DATA 0x00000000 +#define DDRSS1_PHY_997_DATA 0x00000000 +#define DDRSS1_PHY_998_DATA 0x00000000 +#define DDRSS1_PHY_999_DATA 0x00000000 +#define DDRSS1_PHY_1000_DATA 0x00000000 +#define DDRSS1_PHY_1001_DATA 0x00000000 +#define DDRSS1_PHY_1002_DATA 0x00000000 +#define DDRSS1_PHY_1003_DATA 0x00000000 +#define DDRSS1_PHY_1004_DATA 0x00000000 +#define DDRSS1_PHY_1005_DATA 0x00000000 +#define DDRSS1_PHY_1006_DATA 0x00000000 +#define DDRSS1_PHY_1007_DATA 0x00000000 +#define DDRSS1_PHY_1008_DATA 0x00000000 +#define DDRSS1_PHY_1009_DATA 0x00000000 +#define DDRSS1_PHY_1010_DATA 0x00000000 +#define DDRSS1_PHY_1011_DATA 0x00000000 +#define DDRSS1_PHY_1012_DATA 0x00000000 +#define DDRSS1_PHY_1013_DATA 0x00000000 +#define DDRSS1_PHY_1014_DATA 0x00000000 +#define DDRSS1_PHY_1015_DATA 0x00000000 +#define DDRSS1_PHY_1016_DATA 0x00000000 +#define DDRSS1_PHY_1017_DATA 0x00000000 +#define DDRSS1_PHY_1018_DATA 0x00000000 +#define DDRSS1_PHY_1019_DATA 0x00000000 +#define DDRSS1_PHY_1020_DATA 0x00000000 +#define DDRSS1_PHY_1021_DATA 0x00000000 +#define DDRSS1_PHY_1022_DATA 0x00000000 +#define DDRSS1_PHY_1023_DATA 0x00000000 +#define DDRSS1_PHY_1024_DATA 0x00000000 +#define DDRSS1_PHY_1025_DATA 0x00000000 +#define DDRSS1_PHY_1026_DATA 0x00000000 +#define DDRSS1_PHY_1027_DATA 0x00000000 +#define DDRSS1_PHY_1028_DATA 0x00000000 +#define DDRSS1_PHY_1029_DATA 0x00000100 +#define DDRSS1_PHY_1030_DATA 0x00000200 +#define DDRSS1_PHY_1031_DATA 0x00000000 +#define DDRSS1_PHY_1032_DATA 0x00000000 +#define DDRSS1_PHY_1033_DATA 0x00000000 +#define DDRSS1_PHY_1034_DATA 0x00000000 +#define DDRSS1_PHY_1035_DATA 0x00400000 +#define DDRSS1_PHY_1036_DATA 0x00000080 +#define DDRSS1_PHY_1037_DATA 0x00DCBA98 +#define DDRSS1_PHY_1038_DATA 0x03000000 +#define DDRSS1_PHY_1039_DATA 0x00200000 +#define DDRSS1_PHY_1040_DATA 0x00000000 +#define DDRSS1_PHY_1041_DATA 0x00000000 +#define DDRSS1_PHY_1042_DATA 0x00000000 +#define DDRSS1_PHY_1043_DATA 0x00000000 +#define DDRSS1_PHY_1044_DATA 0x00000000 +#define DDRSS1_PHY_1045_DATA 0x0000002A +#define DDRSS1_PHY_1046_DATA 0x00000015 +#define DDRSS1_PHY_1047_DATA 0x00000015 +#define DDRSS1_PHY_1048_DATA 0x0000002A +#define DDRSS1_PHY_1049_DATA 0x00000033 +#define DDRSS1_PHY_1050_DATA 0x0000000C +#define DDRSS1_PHY_1051_DATA 0x0000000C +#define DDRSS1_PHY_1052_DATA 0x00000033 +#define DDRSS1_PHY_1053_DATA 0x00543210 +#define DDRSS1_PHY_1054_DATA 0x003F0000 +#define DDRSS1_PHY_1055_DATA 0x000F3F3F +#define DDRSS1_PHY_1056_DATA 0x20202003 +#define DDRSS1_PHY_1057_DATA 0x00202020 +#define DDRSS1_PHY_1058_DATA 0x20008008 +#define DDRSS1_PHY_1059_DATA 0x00000810 +#define DDRSS1_PHY_1060_DATA 0x00000F00 +#define DDRSS1_PHY_1061_DATA 0x00000000 +#define DDRSS1_PHY_1062_DATA 0x00000000 +#define DDRSS1_PHY_1063_DATA 0x00000000 +#define DDRSS1_PHY_1064_DATA 0x000305CC +#define DDRSS1_PHY_1065_DATA 0x00030000 +#define DDRSS1_PHY_1066_DATA 0x00000300 +#define DDRSS1_PHY_1067_DATA 0x00000300 +#define DDRSS1_PHY_1068_DATA 0x00000300 +#define DDRSS1_PHY_1069_DATA 0x00000300 +#define DDRSS1_PHY_1070_DATA 0x00000300 +#define DDRSS1_PHY_1071_DATA 0x42080010 +#define DDRSS1_PHY_1072_DATA 0x0000803E +#define DDRSS1_PHY_1073_DATA 0x00000001 +#define DDRSS1_PHY_1074_DATA 0x01000102 +#define DDRSS1_PHY_1075_DATA 0x00008000 +#define DDRSS1_PHY_1076_DATA 0x00000000 +#define DDRSS1_PHY_1077_DATA 0x00000000 +#define DDRSS1_PHY_1078_DATA 0x00000000 +#define DDRSS1_PHY_1079_DATA 0x00000000 +#define DDRSS1_PHY_1080_DATA 0x00000000 +#define DDRSS1_PHY_1081_DATA 0x00000000 +#define DDRSS1_PHY_1082_DATA 0x00000000 +#define DDRSS1_PHY_1083_DATA 0x00000000 +#define DDRSS1_PHY_1084_DATA 0x00000000 +#define DDRSS1_PHY_1085_DATA 0x00000000 +#define DDRSS1_PHY_1086_DATA 0x00000000 +#define DDRSS1_PHY_1087_DATA 0x00000000 +#define DDRSS1_PHY_1088_DATA 0x00000000 +#define DDRSS1_PHY_1089_DATA 0x00000000 +#define DDRSS1_PHY_1090_DATA 0x00000000 +#define DDRSS1_PHY_1091_DATA 0x00000000 +#define DDRSS1_PHY_1092_DATA 0x00000000 +#define DDRSS1_PHY_1093_DATA 0x00000000 +#define DDRSS1_PHY_1094_DATA 0x00000000 +#define DDRSS1_PHY_1095_DATA 0x00000000 +#define DDRSS1_PHY_1096_DATA 0x00000000 +#define DDRSS1_PHY_1097_DATA 0x00000000 +#define DDRSS1_PHY_1098_DATA 0x00000000 +#define DDRSS1_PHY_1099_DATA 0x00000000 +#define DDRSS1_PHY_1100_DATA 0x00000000 +#define DDRSS1_PHY_1101_DATA 0x00000000 +#define DDRSS1_PHY_1102_DATA 0x00000000 +#define DDRSS1_PHY_1103_DATA 0x00000000 +#define DDRSS1_PHY_1104_DATA 0x00000000 +#define DDRSS1_PHY_1105_DATA 0x00000000 +#define DDRSS1_PHY_1106_DATA 0x00000000 +#define DDRSS1_PHY_1107_DATA 0x00000000 +#define DDRSS1_PHY_1108_DATA 0x00000000 +#define DDRSS1_PHY_1109_DATA 0x00000000 +#define DDRSS1_PHY_1110_DATA 0x00000000 +#define DDRSS1_PHY_1111_DATA 0x00000000 +#define DDRSS1_PHY_1112_DATA 0x00000000 +#define DDRSS1_PHY_1113_DATA 0x00000000 +#define DDRSS1_PHY_1114_DATA 0x00000000 +#define DDRSS1_PHY_1115_DATA 0x00000000 +#define DDRSS1_PHY_1116_DATA 0x00000000 +#define DDRSS1_PHY_1117_DATA 0x00000000 +#define DDRSS1_PHY_1118_DATA 0x00000000 +#define DDRSS1_PHY_1119_DATA 0x00000000 +#define DDRSS1_PHY_1120_DATA 0x00000000 +#define DDRSS1_PHY_1121_DATA 0x00000000 +#define DDRSS1_PHY_1122_DATA 0x00000000 +#define DDRSS1_PHY_1123_DATA 0x00000000 +#define DDRSS1_PHY_1124_DATA 0x00000000 +#define DDRSS1_PHY_1125_DATA 0x00000000 +#define DDRSS1_PHY_1126_DATA 0x00000000 +#define DDRSS1_PHY_1127_DATA 0x00000000 +#define DDRSS1_PHY_1128_DATA 0x00000000 +#define DDRSS1_PHY_1129_DATA 0x00000000 +#define DDRSS1_PHY_1130_DATA 0x00000000 +#define DDRSS1_PHY_1131_DATA 0x00000000 +#define DDRSS1_PHY_1132_DATA 0x00000000 +#define DDRSS1_PHY_1133_DATA 0x00000000 +#define DDRSS1_PHY_1134_DATA 0x00000000 +#define DDRSS1_PHY_1135_DATA 0x00000000 +#define DDRSS1_PHY_1136_DATA 0x00000000 +#define DDRSS1_PHY_1137_DATA 0x00000000 +#define DDRSS1_PHY_1138_DATA 0x00000000 +#define DDRSS1_PHY_1139_DATA 0x00000000 +#define DDRSS1_PHY_1140_DATA 0x00000000 +#define DDRSS1_PHY_1141_DATA 0x00000000 +#define DDRSS1_PHY_1142_DATA 0x00000000 +#define DDRSS1_PHY_1143_DATA 0x00000000 +#define DDRSS1_PHY_1144_DATA 0x00000000 +#define DDRSS1_PHY_1145_DATA 0x00000000 +#define DDRSS1_PHY_1146_DATA 0x00000000 +#define DDRSS1_PHY_1147_DATA 0x00000000 +#define DDRSS1_PHY_1148_DATA 0x00000000 +#define DDRSS1_PHY_1149_DATA 0x00000000 +#define DDRSS1_PHY_1150_DATA 0x00000000 +#define DDRSS1_PHY_1151_DATA 0x00000000 +#define DDRSS1_PHY_1152_DATA 0x00000000 +#define DDRSS1_PHY_1153_DATA 0x00000000 +#define DDRSS1_PHY_1154_DATA 0x00000000 +#define DDRSS1_PHY_1155_DATA 0x00000000 +#define DDRSS1_PHY_1156_DATA 0x00000000 +#define DDRSS1_PHY_1157_DATA 0x00000000 +#define DDRSS1_PHY_1158_DATA 0x00000000 +#define DDRSS1_PHY_1159_DATA 0x00000000 +#define DDRSS1_PHY_1160_DATA 0x00000000 +#define DDRSS1_PHY_1161_DATA 0x00000000 +#define DDRSS1_PHY_1162_DATA 0x00000000 +#define DDRSS1_PHY_1163_DATA 0x00000000 +#define DDRSS1_PHY_1164_DATA 0x00000000 +#define DDRSS1_PHY_1165_DATA 0x00000000 +#define DDRSS1_PHY_1166_DATA 0x00000000 +#define DDRSS1_PHY_1167_DATA 0x00000000 +#define DDRSS1_PHY_1168_DATA 0x00000000 +#define DDRSS1_PHY_1169_DATA 0x00000000 +#define DDRSS1_PHY_1170_DATA 0x00000000 +#define DDRSS1_PHY_1171_DATA 0x00000000 +#define DDRSS1_PHY_1172_DATA 0x00000000 +#define DDRSS1_PHY_1173_DATA 0x00000000 +#define DDRSS1_PHY_1174_DATA 0x00000000 +#define DDRSS1_PHY_1175_DATA 0x00000000 +#define DDRSS1_PHY_1176_DATA 0x00000000 +#define DDRSS1_PHY_1177_DATA 0x00000000 +#define DDRSS1_PHY_1178_DATA 0x00000000 +#define DDRSS1_PHY_1179_DATA 0x00000000 +#define DDRSS1_PHY_1180_DATA 0x00000000 +#define DDRSS1_PHY_1181_DATA 0x00000000 +#define DDRSS1_PHY_1182_DATA 0x00000000 +#define DDRSS1_PHY_1183_DATA 0x00000000 +#define DDRSS1_PHY_1184_DATA 0x00000000 +#define DDRSS1_PHY_1185_DATA 0x00000000 +#define DDRSS1_PHY_1186_DATA 0x00000000 +#define DDRSS1_PHY_1187_DATA 0x00000000 +#define DDRSS1_PHY_1188_DATA 0x00000000 +#define DDRSS1_PHY_1189_DATA 0x00000000 +#define DDRSS1_PHY_1190_DATA 0x00000000 +#define DDRSS1_PHY_1191_DATA 0x00000000 +#define DDRSS1_PHY_1192_DATA 0x00000000 +#define DDRSS1_PHY_1193_DATA 0x00000000 +#define DDRSS1_PHY_1194_DATA 0x00000000 +#define DDRSS1_PHY_1195_DATA 0x00000000 +#define DDRSS1_PHY_1196_DATA 0x00000000 +#define DDRSS1_PHY_1197_DATA 0x00000000 +#define DDRSS1_PHY_1198_DATA 0x00000000 +#define DDRSS1_PHY_1199_DATA 0x00000000 +#define DDRSS1_PHY_1200_DATA 0x00000000 +#define DDRSS1_PHY_1201_DATA 0x00000000 +#define DDRSS1_PHY_1202_DATA 0x00000000 +#define DDRSS1_PHY_1203_DATA 0x00000000 +#define DDRSS1_PHY_1204_DATA 0x00000000 +#define DDRSS1_PHY_1205_DATA 0x00000000 +#define DDRSS1_PHY_1206_DATA 0x00000000 +#define DDRSS1_PHY_1207_DATA 0x00000000 +#define DDRSS1_PHY_1208_DATA 0x00000000 +#define DDRSS1_PHY_1209_DATA 0x00000000 +#define DDRSS1_PHY_1210_DATA 0x00000000 +#define DDRSS1_PHY_1211_DATA 0x00000000 +#define DDRSS1_PHY_1212_DATA 0x00000000 +#define DDRSS1_PHY_1213_DATA 0x00000000 +#define DDRSS1_PHY_1214_DATA 0x00000000 +#define DDRSS1_PHY_1215_DATA 0x00000000 +#define DDRSS1_PHY_1216_DATA 0x00000000 +#define DDRSS1_PHY_1217_DATA 0x00000000 +#define DDRSS1_PHY_1218_DATA 0x00000000 +#define DDRSS1_PHY_1219_DATA 0x00000000 +#define DDRSS1_PHY_1220_DATA 0x00000000 +#define DDRSS1_PHY_1221_DATA 0x00000000 +#define DDRSS1_PHY_1222_DATA 0x00000000 +#define DDRSS1_PHY_1223_DATA 0x00000000 +#define DDRSS1_PHY_1224_DATA 0x00000000 +#define DDRSS1_PHY_1225_DATA 0x00000000 +#define DDRSS1_PHY_1226_DATA 0x00000000 +#define DDRSS1_PHY_1227_DATA 0x00000000 +#define DDRSS1_PHY_1228_DATA 0x00000000 +#define DDRSS1_PHY_1229_DATA 0x00000000 +#define DDRSS1_PHY_1230_DATA 0x00000000 +#define DDRSS1_PHY_1231_DATA 0x00000000 +#define DDRSS1_PHY_1232_DATA 0x00000000 +#define DDRSS1_PHY_1233_DATA 0x00000000 +#define DDRSS1_PHY_1234_DATA 0x00000000 +#define DDRSS1_PHY_1235_DATA 0x00000000 +#define DDRSS1_PHY_1236_DATA 0x00000000 +#define DDRSS1_PHY_1237_DATA 0x00000000 +#define DDRSS1_PHY_1238_DATA 0x00000000 +#define DDRSS1_PHY_1239_DATA 0x00000000 +#define DDRSS1_PHY_1240_DATA 0x00000000 +#define DDRSS1_PHY_1241_DATA 0x00000000 +#define DDRSS1_PHY_1242_DATA 0x00000000 +#define DDRSS1_PHY_1243_DATA 0x00000000 +#define DDRSS1_PHY_1244_DATA 0x00000000 +#define DDRSS1_PHY_1245_DATA 0x00000000 +#define DDRSS1_PHY_1246_DATA 0x00000000 +#define DDRSS1_PHY_1247_DATA 0x00000000 +#define DDRSS1_PHY_1248_DATA 0x00000000 +#define DDRSS1_PHY_1249_DATA 0x00000000 +#define DDRSS1_PHY_1250_DATA 0x00000000 +#define DDRSS1_PHY_1251_DATA 0x00000000 +#define DDRSS1_PHY_1252_DATA 0x00000000 +#define DDRSS1_PHY_1253_DATA 0x00000000 +#define DDRSS1_PHY_1254_DATA 0x00000000 +#define DDRSS1_PHY_1255_DATA 0x00000000 +#define DDRSS1_PHY_1256_DATA 0x00000000 +#define DDRSS1_PHY_1257_DATA 0x00000000 +#define DDRSS1_PHY_1258_DATA 0x00000000 +#define DDRSS1_PHY_1259_DATA 0x00000000 +#define DDRSS1_PHY_1260_DATA 0x00000000 +#define DDRSS1_PHY_1261_DATA 0x00000000 +#define DDRSS1_PHY_1262_DATA 0x00000000 +#define DDRSS1_PHY_1263_DATA 0x00000000 +#define DDRSS1_PHY_1264_DATA 0x00000000 +#define DDRSS1_PHY_1265_DATA 0x00000000 +#define DDRSS1_PHY_1266_DATA 0x00000000 +#define DDRSS1_PHY_1267_DATA 0x00000000 +#define DDRSS1_PHY_1268_DATA 0x00000000 +#define DDRSS1_PHY_1269_DATA 0x00000000 +#define DDRSS1_PHY_1270_DATA 0x00000000 +#define DDRSS1_PHY_1271_DATA 0x00000000 +#define DDRSS1_PHY_1272_DATA 0x00000000 +#define DDRSS1_PHY_1273_DATA 0x00000000 +#define DDRSS1_PHY_1274_DATA 0x00000000 +#define DDRSS1_PHY_1275_DATA 0x00000000 +#define DDRSS1_PHY_1276_DATA 0x00000000 +#define DDRSS1_PHY_1277_DATA 0x00000000 +#define DDRSS1_PHY_1278_DATA 0x00000000 +#define DDRSS1_PHY_1279_DATA 0x00000000 +#define DDRSS1_PHY_1280_DATA 0x00000000 +#define DDRSS1_PHY_1281_DATA 0x00010100 +#define DDRSS1_PHY_1282_DATA 0x00000000 +#define DDRSS1_PHY_1283_DATA 0x00000000 +#define DDRSS1_PHY_1284_DATA 0x00050000 +#define DDRSS1_PHY_1285_DATA 0x04000000 +#define DDRSS1_PHY_1286_DATA 0x00000055 +#define DDRSS1_PHY_1287_DATA 0x00000000 +#define DDRSS1_PHY_1288_DATA 0x00000000 +#define DDRSS1_PHY_1289_DATA 0x00000000 +#define DDRSS1_PHY_1290_DATA 0x00000000 +#define DDRSS1_PHY_1291_DATA 0x00002001 +#define DDRSS1_PHY_1292_DATA 0x0000400F +#define DDRSS1_PHY_1293_DATA 0x50020028 +#define DDRSS1_PHY_1294_DATA 0x01010000 +#define DDRSS1_PHY_1295_DATA 0x80080001 +#define DDRSS1_PHY_1296_DATA 0x10200000 +#define DDRSS1_PHY_1297_DATA 0x00000008 +#define DDRSS1_PHY_1298_DATA 0x00000000 +#define DDRSS1_PHY_1299_DATA 0x01090E00 +#define DDRSS1_PHY_1300_DATA 0x00040101 +#define DDRSS1_PHY_1301_DATA 0x0000010F +#define DDRSS1_PHY_1302_DATA 0x00000000 +#define DDRSS1_PHY_1303_DATA 0x00000064 +#define DDRSS1_PHY_1304_DATA 0x00000000 +#define DDRSS1_PHY_1305_DATA 0x01010000 +#define DDRSS1_PHY_1306_DATA 0x01080402 +#define DDRSS1_PHY_1307_DATA 0x01200F02 +#define DDRSS1_PHY_1308_DATA 0x00194280 +#define DDRSS1_PHY_1309_DATA 0x00000004 +#define DDRSS1_PHY_1310_DATA 0x00042000 +#define DDRSS1_PHY_1311_DATA 0x00000000 +#define DDRSS1_PHY_1312_DATA 0x00000000 +#define DDRSS1_PHY_1313_DATA 0x00000000 +#define DDRSS1_PHY_1314_DATA 0x00000000 +#define DDRSS1_PHY_1315_DATA 0x00000000 +#define DDRSS1_PHY_1316_DATA 0x00000000 +#define DDRSS1_PHY_1317_DATA 0x01000000 +#define DDRSS1_PHY_1318_DATA 0x00000705 +#define DDRSS1_PHY_1319_DATA 0x00000054 +#define DDRSS1_PHY_1320_DATA 0x00030820 +#define DDRSS1_PHY_1321_DATA 0x00010820 +#define DDRSS1_PHY_1322_DATA 0x00010820 +#define DDRSS1_PHY_1323_DATA 0x00010820 +#define DDRSS1_PHY_1324_DATA 0x00010820 +#define DDRSS1_PHY_1325_DATA 0x00010820 +#define DDRSS1_PHY_1326_DATA 0x00010820 +#define DDRSS1_PHY_1327_DATA 0x00010820 +#define DDRSS1_PHY_1328_DATA 0x00010820 +#define DDRSS1_PHY_1329_DATA 0x00000000 +#define DDRSS1_PHY_1330_DATA 0x00000074 +#define DDRSS1_PHY_1331_DATA 0x00000400 +#define DDRSS1_PHY_1332_DATA 0x00000108 +#define DDRSS1_PHY_1333_DATA 0x00000000 +#define DDRSS1_PHY_1334_DATA 0x00000000 +#define DDRSS1_PHY_1335_DATA 0x00000000 +#define DDRSS1_PHY_1336_DATA 0x00000000 +#define DDRSS1_PHY_1337_DATA 0x00000000 +#define DDRSS1_PHY_1338_DATA 0x03000000 +#define DDRSS1_PHY_1339_DATA 0x00000000 +#define DDRSS1_PHY_1340_DATA 0x00000000 +#define DDRSS1_PHY_1341_DATA 0x00000000 +#define DDRSS1_PHY_1342_DATA 0x04102006 +#define DDRSS1_PHY_1343_DATA 0x00041020 +#define DDRSS1_PHY_1344_DATA 0x01C98C98 +#define DDRSS1_PHY_1345_DATA 0x3F400000 +#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS1_PHY_1347_DATA 0x0000001F +#define DDRSS1_PHY_1348_DATA 0x00000000 +#define DDRSS1_PHY_1349_DATA 0x00000000 +#define DDRSS1_PHY_1350_DATA 0x00000000 +#define DDRSS1_PHY_1351_DATA 0x00010000 +#define DDRSS1_PHY_1352_DATA 0x00000000 +#define DDRSS1_PHY_1353_DATA 0x00000000 +#define DDRSS1_PHY_1354_DATA 0x00000000 +#define DDRSS1_PHY_1355_DATA 0x00000000 +#define DDRSS1_PHY_1356_DATA 0x76543210 +#define DDRSS1_PHY_1357_DATA 0x00010198 +#define DDRSS1_PHY_1358_DATA 0x00000000 +#define DDRSS1_PHY_1359_DATA 0x00000000 +#define DDRSS1_PHY_1360_DATA 0x00000000 +#define DDRSS1_PHY_1361_DATA 0x00040700 +#define DDRSS1_PHY_1362_DATA 0x00000000 +#define DDRSS1_PHY_1363_DATA 0x00000000 +#define DDRSS1_PHY_1364_DATA 0x00000000 +#define DDRSS1_PHY_1365_DATA 0x00000000 +#define DDRSS1_PHY_1366_DATA 0x00000000 +#define DDRSS1_PHY_1367_DATA 0x00000002 +#define DDRSS1_PHY_1368_DATA 0x00000000 +#define DDRSS1_PHY_1369_DATA 0x00000000 +#define DDRSS1_PHY_1370_DATA 0x00000000 +#define DDRSS1_PHY_1371_DATA 0x00000000 +#define DDRSS1_PHY_1372_DATA 0x00000000 +#define DDRSS1_PHY_1373_DATA 0x00000000 +#define DDRSS1_PHY_1374_DATA 0x00080000 +#define DDRSS1_PHY_1375_DATA 0x000007FF +#define DDRSS1_PHY_1376_DATA 0x00000000 +#define DDRSS1_PHY_1377_DATA 0x00000000 +#define DDRSS1_PHY_1378_DATA 0x00000000 +#define DDRSS1_PHY_1379_DATA 0x00000000 +#define DDRSS1_PHY_1380_DATA 0x00000000 +#define DDRSS1_PHY_1381_DATA 0x00000000 +#define DDRSS1_PHY_1382_DATA 0x000FFFFF +#define DDRSS1_PHY_1383_DATA 0x000FFFFF +#define DDRSS1_PHY_1384_DATA 0x0000FFFF +#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS1_PHY_1386_DATA 0x030FFFFF +#define DDRSS1_PHY_1387_DATA 0x01FFFFFF +#define DDRSS1_PHY_1388_DATA 0x0000FFFF +#define DDRSS1_PHY_1389_DATA 0x00000000 +#define DDRSS1_PHY_1390_DATA 0x00000000 +#define DDRSS1_PHY_1391_DATA 0x00000000 +#define DDRSS1_PHY_1392_DATA 0x00000000 +#define DDRSS1_PHY_1393_DATA 0x0001F7C0 +#define DDRSS1_PHY_1394_DATA 0x00000003 +#define DDRSS1_PHY_1395_DATA 0x00000000 +#define DDRSS1_PHY_1396_DATA 0x00001142 +#define DDRSS1_PHY_1397_DATA 0x040207AB +#define DDRSS1_PHY_1398_DATA 0x01000080 +#define DDRSS1_PHY_1399_DATA 0x03900390 +#define DDRSS1_PHY_1400_DATA 0x03900390 +#define DDRSS1_PHY_1401_DATA 0x00000390 +#define DDRSS1_PHY_1402_DATA 0x00000390 +#define DDRSS1_PHY_1403_DATA 0x00000390 +#define DDRSS1_PHY_1404_DATA 0x00000390 +#define DDRSS1_PHY_1405_DATA 0x00000005 +#define DDRSS1_PHY_1406_DATA 0x01813FCC +#define DDRSS1_PHY_1407_DATA 0x000000CC +#define DDRSS1_PHY_1408_DATA 0x0C000DFF +#define DDRSS1_PHY_1409_DATA 0x30000DFF +#define DDRSS1_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1411_DATA 0x000100F0 +#define DDRSS1_PHY_1412_DATA 0x780DFFCC +#define DDRSS1_PHY_1413_DATA 0x00007E31 +#define DDRSS1_PHY_1414_DATA 0x000CBF11 +#define DDRSS1_PHY_1415_DATA 0x01990010 +#define DDRSS1_PHY_1416_DATA 0x000CBF11 +#define DDRSS1_PHY_1417_DATA 0x01990010 +#define DDRSS1_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1419_DATA 0x00EF00F0 +#define DDRSS1_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1421_DATA 0x01FF00F0 +#define DDRSS1_PHY_1422_DATA 0x20040006 + + diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts index b61d22b3b4b..c43e7a1c46e 100644 --- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-am68-sk-base-board.dts" -#include "k3-j721s2-ddr-evm-lp4-4266.dtsi" +#include "k3-am68-ddr-sk-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" #include "k3-am68-sk-base-board-u-boot.dtsi" #include "k3-j721s2-r5.dtsi" From c70fd4e5a291147151da1162effe5e20f6aed413 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 3 Nov 2025 12:40:32 +0530 Subject: [PATCH 25/65] arm: dts: k3-j784s4: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for J784S4 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi | 653 ++++++++++--------- 1 file changed, 341 insertions(+), 312 deletions(-) diff --git a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi index 0e16d2f201d..521464e2264 100644 --- a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi @@ -1,11 +1,29 @@ -// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0 - * This file was generated on 04/12/2023 - */ + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:55:08 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 2 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 3 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 +#define DDRSS2_PLL_FHS_CNT 5 +#define DDRSS3_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -16,6 +34,17 @@ #define MULTI_DDR_CFG_HYBRID_SELECT 24 #define MULTI_DDR_CFG_EMIFS_ACTIVE 15 +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay +#define DDR2_CTL_NODE_STAT okay +#define DDR3_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000007 +#define DDR_REG1_SIZE_LSB 0x80000000 + + #define DDRSS0_CTL_00_DATA 0x00000B00 #define DDRSS0_CTL_01_DATA 0x00000000 #define DDRSS0_CTL_02_DATA 0x00000000 @@ -36,7 +65,7 @@ #define DDRSS0_CTL_17_DATA 0x00000005 #define DDRSS0_CTL_18_DATA 0x000010A9 #define DDRSS0_CTL_19_DATA 0x01010000 -#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_20_DATA 0x01011001 #define DDRSS0_CTL_21_DATA 0x02010000 #define DDRSS0_CTL_22_DATA 0x00020100 #define DDRSS0_CTL_23_DATA 0x0000000B @@ -51,7 +80,7 @@ #define DDRSS0_CTL_32_DATA 0x00000000 #define DDRSS0_CTL_33_DATA 0x00000000 #define DDRSS0_CTL_34_DATA 0x040C0000 -#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_35_DATA 0x12501250 #define DDRSS0_CTL_36_DATA 0x00050804 #define DDRSS0_CTL_37_DATA 0x09040008 #define DDRSS0_CTL_38_DATA 0x15000204 @@ -66,27 +95,27 @@ #define DDRSS0_CTL_47_DATA 0x1E161110 #define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 -#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_50_DATA 0x2C060500 #define DDRSS0_CTL_51_DATA 0x08292C29 #define DDRSS0_CTL_52_DATA 0x14000E0A #define DDRSS0_CTL_53_DATA 0x04010A0A #define DDRSS0_CTL_54_DATA 0x01010004 -#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_55_DATA 0x0454540A #define DDRSS0_CTL_56_DATA 0x04313104 #define DDRSS0_CTL_57_DATA 0x00003131 #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x00000063 +#define DDRSS0_CTL_61_DATA 0x00000068 #define DDRSS0_CTL_62_DATA 0x0000032B #define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B #define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 -#define DDRSS0_CTL_68_DATA 0x00CB0012 -#define DDRSS0_CTL_69_DATA 0x00CB0408 -#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 #define DDRSS0_CTL_71_DATA 0x00120103 #define DDRSS0_CTL_72_DATA 0x00100005 #define DDRSS0_CTL_73_DATA 0x2F080010 @@ -192,22 +221,22 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 #define DDRSS0_CTL_178_DATA 0x35000000 #define DDRSS0_CTL_179_DATA 0x27270035 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 #define DDRSS0_CTL_185_DATA 0x00000000 #define DDRSS0_CTL_186_DATA 0x00353500 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 #define DDRSS0_CTL_190_DATA 0x00000020 -#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_191_DATA 0x01000000 #define DDRSS0_CTL_192_DATA 0x00000001 #define DDRSS0_CTL_193_DATA 0x00000000 #define DDRSS0_CTL_194_DATA 0x01000000 @@ -307,14 +336,14 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00010101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 #define DDRSS0_CTL_295_DATA 0x00000000 #define DDRSS0_CTL_296_DATA 0x00000000 -#define DDRSS0_CTL_297_DATA 0x00000000 -#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF #define DDRSS0_CTL_299_DATA 0x00000000 #define DDRSS0_CTL_300_DATA 0x00000000 #define DDRSS0_CTL_301_DATA 0x00000000 @@ -335,7 +364,7 @@ #define DDRSS0_CTL_316_DATA 0x01010001 #define DDRSS0_CTL_317_DATA 0x00010101 #define DDRSS0_CTL_318_DATA 0x050A0A03 -#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_319_DATA 0x10082323 #define DDRSS0_CTL_320_DATA 0x00090310 #define DDRSS0_CTL_321_DATA 0x0B0C030F #define DDRSS0_CTL_322_DATA 0x0B0C0306 @@ -410,7 +439,7 @@ #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x00000252 +#define DDRSS0_CTL_394_DATA 0x00000270 #define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 #define DDRSS0_CTL_397_DATA 0x0000206A @@ -420,7 +449,7 @@ #define DDRSS0_CTL_401_DATA 0x00000200 #define DDRSS0_CTL_402_DATA 0x0000613E #define DDRSS0_CTL_403_DATA 0x00014424 -#define DDRSS0_CTL_404_DATA 0x00000E15 +#define DDRSS0_CTL_404_DATA 0x00000E19 #define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 @@ -428,7 +457,7 @@ #define DDRSS0_CTL_409_DATA 0x00000200 #define DDRSS0_CTL_410_DATA 0x0000613E #define DDRSS0_CTL_411_DATA 0x00014424 -#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_412_DATA 0x02020E19 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 #define DDRSS0_CTL_415_DATA 0x00000000 @@ -445,7 +474,7 @@ #define DDRSS0_CTL_426_DATA 0x00000000 #define DDRSS0_CTL_427_DATA 0x02000000 #define DDRSS0_CTL_428_DATA 0x01000404 -#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_429_DATA 0x0B220B22 #define DDRSS0_CTL_430_DATA 0x00000105 #define DDRSS0_CTL_431_DATA 0x00010101 #define DDRSS0_CTL_432_DATA 0x00010101 @@ -488,8 +517,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -537,18 +566,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 #define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_67_DATA 0x0002020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -637,37 +666,37 @@ #define DDRSS0_PI_158_DATA 0x00000000 #define DDRSS0_PI_159_DATA 0x00000401 #define DDRSS0_PI_160_DATA 0x00000000 -#define DDRSS0_PI_161_DATA 0x00010000 -#define DDRSS0_PI_162_DATA 0x00000000 -#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 #define DDRSS0_PI_164_DATA 0x00000034 -#define DDRSS0_PI_165_DATA 0x00000064 -#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 #define DDRSS0_PI_167_DATA 0x02000200 -#define DDRSS0_PI_168_DATA 0x48120C04 -#define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x00000063 +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 #define DDRSS0_PI_171_DATA 0x0000032B #define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B #define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 -#define DDRSS0_PI_185_DATA 0x15040000 -#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 #define DDRSS0_PI_187_DATA 0x00040402 #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -675,8 +704,8 @@ #define DDRSS0_PI_196_DATA 0x02170100 #define DDRSS0_PI_197_DATA 0x01000217 #define DDRSS0_PI_198_DATA 0x02170217 -#define DDRSS0_PI_199_DATA 0x32103200 -#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B #define DDRSS0_PI_201_DATA 0x0A070601 #define DDRSS0_PI_202_DATA 0x1F130A0D #define DDRSS0_PI_203_DATA 0x1F130A14 @@ -688,13 +717,13 @@ #define DDRSS0_PI_209_DATA 0x00240216 #define DDRSS0_PI_210_DATA 0x00110216 #define DDRSS0_PI_211_DATA 0x32000056 -#define DDRSS0_PI_212_DATA 0x00000301 -#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 -#define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 -#define DDRSS0_PI_218_DATA 0x04010504 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 #define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A @@ -751,29 +780,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00F30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x35333FF4 +#define DDRSS0_PI_277_DATA 0x35F33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x35333FF4 +#define DDRSS0_PI_279_DATA 0x35F33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00F30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x35333FF4 +#define DDRSS0_PI_283_DATA 0x35F33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x35333FF4 +#define DDRSS0_PI_285_DATA 0x35F33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00F30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x35333FF4 +#define DDRSS0_PI_289_DATA 0x35F33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x35333FF4 +#define DDRSS0_PI_291_DATA 0x35F33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00F30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x35333FF4 +#define DDRSS0_PI_295_DATA 0x35F33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x35333FF4 +#define DDRSS0_PI_297_DATA 0x35F33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -789,7 +818,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -808,7 +837,7 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F +#define DDRSS0_PHY_31_DATA 0x00000F08 #define DDRSS0_PHY_32_DATA 0x10400000 #define DDRSS0_PHY_33_DATA 0x0C002006 #define DDRSS0_PHY_34_DATA 0x00000000 @@ -877,9 +906,9 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 -#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 #define DDRSS0_PHY_103_DATA 0x10001000 #define DDRSS0_PHY_104_DATA 0x0C083E42 #define DDRSS0_PHY_105_DATA 0x0F0C3701 @@ -1045,7 +1074,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1064,7 +1093,7 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F +#define DDRSS0_PHY_287_DATA 0x00000F08 #define DDRSS0_PHY_288_DATA 0x10400000 #define DDRSS0_PHY_289_DATA 0x0C002006 #define DDRSS0_PHY_290_DATA 0x00000000 @@ -1133,9 +1162,9 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 -#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 #define DDRSS0_PHY_359_DATA 0x10001000 #define DDRSS0_PHY_360_DATA 0x0C083E42 #define DDRSS0_PHY_361_DATA 0x0F0C3701 @@ -1301,7 +1330,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1320,7 +1349,7 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F +#define DDRSS0_PHY_543_DATA 0x00000F08 #define DDRSS0_PHY_544_DATA 0x10400000 #define DDRSS0_PHY_545_DATA 0x0C002006 #define DDRSS0_PHY_546_DATA 0x00000000 @@ -1389,9 +1418,9 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 -#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 #define DDRSS0_PHY_615_DATA 0x10001000 #define DDRSS0_PHY_616_DATA 0x0C083E42 #define DDRSS0_PHY_617_DATA 0x0F0C3701 @@ -1557,7 +1586,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1576,7 +1605,7 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F +#define DDRSS0_PHY_799_DATA 0x00000F08 #define DDRSS0_PHY_800_DATA 0x10400000 #define DDRSS0_PHY_801_DATA 0x0C002006 #define DDRSS0_PHY_802_DATA 0x00000000 @@ -1645,9 +1674,9 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 -#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 #define DDRSS0_PHY_871_DATA 0x10001000 #define DDRSS0_PHY_872_DATA 0x0C083E42 #define DDRSS0_PHY_873_DATA 0x0F0C3701 @@ -1832,7 +1861,7 @@ #define DDRSS0_PHY_1052_DATA 0x00000033 #define DDRSS0_PHY_1053_DATA 0x00543210 #define DDRSS0_PHY_1054_DATA 0x003F0000 -#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1055_DATA 0x000F3F3F #define DDRSS0_PHY_1056_DATA 0x20202003 #define DDRSS0_PHY_1057_DATA 0x00202020 #define DDRSS0_PHY_1058_DATA 0x20008008 @@ -2080,7 +2109,7 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 @@ -2174,7 +2203,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2221,7 +2250,7 @@ #define DDRSS1_CTL_17_DATA 0x00000005 #define DDRSS1_CTL_18_DATA 0x000010A9 #define DDRSS1_CTL_19_DATA 0x01010000 -#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_20_DATA 0x01011001 #define DDRSS1_CTL_21_DATA 0x02010000 #define DDRSS1_CTL_22_DATA 0x00020100 #define DDRSS1_CTL_23_DATA 0x0000000B @@ -2236,7 +2265,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_35_DATA 0x12501250 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2251,27 +2280,27 @@ #define DDRSS1_CTL_47_DATA 0x1E161110 #define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 -#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_50_DATA 0x2C060500 #define DDRSS1_CTL_51_DATA 0x08292C29 #define DDRSS1_CTL_52_DATA 0x14000E0A #define DDRSS1_CTL_53_DATA 0x04010A0A #define DDRSS1_CTL_54_DATA 0x01010004 -#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_55_DATA 0x0454540A #define DDRSS1_CTL_56_DATA 0x04313104 #define DDRSS1_CTL_57_DATA 0x00003131 #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x00000063 +#define DDRSS1_CTL_61_DATA 0x00000068 #define DDRSS1_CTL_62_DATA 0x0000032B #define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B #define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 -#define DDRSS1_CTL_68_DATA 0x00CB0012 -#define DDRSS1_CTL_69_DATA 0x00CB0408 -#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 #define DDRSS1_CTL_71_DATA 0x00120103 #define DDRSS1_CTL_72_DATA 0x00100005 #define DDRSS1_CTL_73_DATA 0x2F080010 @@ -2377,22 +2406,22 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 #define DDRSS1_CTL_178_DATA 0x35000000 #define DDRSS1_CTL_179_DATA 0x27270035 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 #define DDRSS1_CTL_185_DATA 0x00000000 #define DDRSS1_CTL_186_DATA 0x00353500 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 #define DDRSS1_CTL_190_DATA 0x00000020 -#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_191_DATA 0x01000000 #define DDRSS1_CTL_192_DATA 0x00000001 #define DDRSS1_CTL_193_DATA 0x00000000 #define DDRSS1_CTL_194_DATA 0x01000000 @@ -2492,14 +2521,14 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00010101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 #define DDRSS1_CTL_295_DATA 0x00000000 #define DDRSS1_CTL_296_DATA 0x00000000 -#define DDRSS1_CTL_297_DATA 0x00000000 -#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF #define DDRSS1_CTL_299_DATA 0x00000000 #define DDRSS1_CTL_300_DATA 0x00000000 #define DDRSS1_CTL_301_DATA 0x00000000 @@ -2520,7 +2549,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_319_DATA 0x10082323 #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2595,7 +2624,7 @@ #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x00000252 +#define DDRSS1_CTL_394_DATA 0x00000270 #define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 #define DDRSS1_CTL_397_DATA 0x0000206A @@ -2605,7 +2634,7 @@ #define DDRSS1_CTL_401_DATA 0x00000200 #define DDRSS1_CTL_402_DATA 0x0000613E #define DDRSS1_CTL_403_DATA 0x00014424 -#define DDRSS1_CTL_404_DATA 0x00000E15 +#define DDRSS1_CTL_404_DATA 0x00000E19 #define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 @@ -2613,7 +2642,7 @@ #define DDRSS1_CTL_409_DATA 0x00000200 #define DDRSS1_CTL_410_DATA 0x0000613E #define DDRSS1_CTL_411_DATA 0x00014424 -#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_412_DATA 0x02020E19 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2630,7 +2659,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_429_DATA 0x0B220B22 #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2673,8 +2702,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2722,18 +2751,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2822,37 +2851,37 @@ #define DDRSS1_PI_158_DATA 0x00000000 #define DDRSS1_PI_159_DATA 0x00000401 #define DDRSS1_PI_160_DATA 0x00000000 -#define DDRSS1_PI_161_DATA 0x00010000 -#define DDRSS1_PI_162_DATA 0x00000000 -#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000064 -#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x48120C04 -#define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x00000063 +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 #define DDRSS1_PI_171_DATA 0x0000032B #define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B #define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x15040000 -#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2860,8 +2889,8 @@ #define DDRSS1_PI_196_DATA 0x02170100 #define DDRSS1_PI_197_DATA 0x01000217 #define DDRSS1_PI_198_DATA 0x02170217 -#define DDRSS1_PI_199_DATA 0x32103200 -#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B #define DDRSS1_PI_201_DATA 0x0A070601 #define DDRSS1_PI_202_DATA 0x1F130A0D #define DDRSS1_PI_203_DATA 0x1F130A14 @@ -2873,13 +2902,13 @@ #define DDRSS1_PI_209_DATA 0x00240216 #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 -#define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 -#define DDRSS1_PI_218_DATA 0x04010504 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 #define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A @@ -2936,29 +2965,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00F30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x35333FF4 +#define DDRSS1_PI_277_DATA 0x35F33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x35333FF4 +#define DDRSS1_PI_279_DATA 0x35F33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00F30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x35333FF4 +#define DDRSS1_PI_283_DATA 0x35F33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x35333FF4 +#define DDRSS1_PI_285_DATA 0x35F33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00F30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x35333FF4 +#define DDRSS1_PI_289_DATA 0x35F33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x35333FF4 +#define DDRSS1_PI_291_DATA 0x35F33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00F30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x35333FF4 +#define DDRSS1_PI_295_DATA 0x35F33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x35333FF4 +#define DDRSS1_PI_297_DATA 0x35F33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2974,7 +3003,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2993,7 +3022,7 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F +#define DDRSS1_PHY_31_DATA 0x00000F08 #define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 @@ -3062,9 +3091,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3230,7 +3259,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3249,7 +3278,7 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F +#define DDRSS1_PHY_287_DATA 0x00000F08 #define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 @@ -3318,9 +3347,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3486,7 +3515,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3505,7 +3534,7 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F +#define DDRSS1_PHY_543_DATA 0x00000F08 #define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 @@ -3574,9 +3603,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3742,7 +3771,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3761,7 +3790,7 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F +#define DDRSS1_PHY_799_DATA 0x00000F08 #define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 @@ -3830,9 +3859,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -4017,7 +4046,7 @@ #define DDRSS1_PHY_1052_DATA 0x00000033 #define DDRSS1_PHY_1053_DATA 0x00543210 #define DDRSS1_PHY_1054_DATA 0x003F0000 -#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1055_DATA 0x000F3F3F #define DDRSS1_PHY_1056_DATA 0x20202003 #define DDRSS1_PHY_1057_DATA 0x00202020 #define DDRSS1_PHY_1058_DATA 0x20008008 @@ -4265,7 +4294,7 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 @@ -4359,7 +4388,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 @@ -4406,7 +4435,7 @@ #define DDRSS2_CTL_17_DATA 0x00000005 #define DDRSS2_CTL_18_DATA 0x000010A9 #define DDRSS2_CTL_19_DATA 0x01010000 -#define DDRSS2_CTL_20_DATA 0x02011001 +#define DDRSS2_CTL_20_DATA 0x01011001 #define DDRSS2_CTL_21_DATA 0x02010000 #define DDRSS2_CTL_22_DATA 0x00020100 #define DDRSS2_CTL_23_DATA 0x0000000B @@ -4421,7 +4450,7 @@ #define DDRSS2_CTL_32_DATA 0x00000000 #define DDRSS2_CTL_33_DATA 0x00000000 #define DDRSS2_CTL_34_DATA 0x040C0000 -#define DDRSS2_CTL_35_DATA 0x12481248 +#define DDRSS2_CTL_35_DATA 0x12501250 #define DDRSS2_CTL_36_DATA 0x00050804 #define DDRSS2_CTL_37_DATA 0x09040008 #define DDRSS2_CTL_38_DATA 0x15000204 @@ -4436,27 +4465,27 @@ #define DDRSS2_CTL_47_DATA 0x1E161110 #define DDRSS2_CTL_48_DATA 0x1000922C #define DDRSS2_CTL_49_DATA 0x02030410 -#define DDRSS2_CTL_50_DATA 0x2C040500 +#define DDRSS2_CTL_50_DATA 0x2C060500 #define DDRSS2_CTL_51_DATA 0x08292C29 #define DDRSS2_CTL_52_DATA 0x14000E0A #define DDRSS2_CTL_53_DATA 0x04010A0A #define DDRSS2_CTL_54_DATA 0x01010004 -#define DDRSS2_CTL_55_DATA 0x04545408 +#define DDRSS2_CTL_55_DATA 0x0454540A #define DDRSS2_CTL_56_DATA 0x04313104 #define DDRSS2_CTL_57_DATA 0x00003131 #define DDRSS2_CTL_58_DATA 0x00010100 #define DDRSS2_CTL_59_DATA 0x03010000 #define DDRSS2_CTL_60_DATA 0x00001508 -#define DDRSS2_CTL_61_DATA 0x00000063 +#define DDRSS2_CTL_61_DATA 0x00000068 #define DDRSS2_CTL_62_DATA 0x0000032B #define DDRSS2_CTL_63_DATA 0x00001035 #define DDRSS2_CTL_64_DATA 0x0000032B #define DDRSS2_CTL_65_DATA 0x00001035 #define DDRSS2_CTL_66_DATA 0x00000005 #define DDRSS2_CTL_67_DATA 0x00050000 -#define DDRSS2_CTL_68_DATA 0x00CB0012 -#define DDRSS2_CTL_69_DATA 0x00CB0408 -#define DDRSS2_CTL_70_DATA 0x00400408 +#define DDRSS2_CTL_68_DATA 0x00CB0005 +#define DDRSS2_CTL_69_DATA 0x00CB0200 +#define DDRSS2_CTL_70_DATA 0x00400200 #define DDRSS2_CTL_71_DATA 0x00120103 #define DDRSS2_CTL_72_DATA 0x00100005 #define DDRSS2_CTL_73_DATA 0x2F080010 @@ -4562,22 +4591,22 @@ #define DDRSS2_CTL_173_DATA 0x00000000 #define DDRSS2_CTL_174_DATA 0x00000000 #define DDRSS2_CTL_175_DATA 0x3FF40084 -#define DDRSS2_CTL_176_DATA 0x33003FF4 -#define DDRSS2_CTL_177_DATA 0x00003333 +#define DDRSS2_CTL_176_DATA 0xF3003FF4 +#define DDRSS2_CTL_177_DATA 0x0000F3F3 #define DDRSS2_CTL_178_DATA 0x35000000 #define DDRSS2_CTL_179_DATA 0x27270035 #define DDRSS2_CTL_180_DATA 0x0F0F0000 #define DDRSS2_CTL_181_DATA 0x16000000 #define DDRSS2_CTL_182_DATA 0x00841616 #define DDRSS2_CTL_183_DATA 0x3FF43FF4 -#define DDRSS2_CTL_184_DATA 0x33333300 +#define DDRSS2_CTL_184_DATA 0xF3F3F300 #define DDRSS2_CTL_185_DATA 0x00000000 #define DDRSS2_CTL_186_DATA 0x00353500 #define DDRSS2_CTL_187_DATA 0x00002727 #define DDRSS2_CTL_188_DATA 0x00000F0F #define DDRSS2_CTL_189_DATA 0x16161600 #define DDRSS2_CTL_190_DATA 0x00000020 -#define DDRSS2_CTL_191_DATA 0x00000000 +#define DDRSS2_CTL_191_DATA 0x01000000 #define DDRSS2_CTL_192_DATA 0x00000001 #define DDRSS2_CTL_193_DATA 0x00000000 #define DDRSS2_CTL_194_DATA 0x01000000 @@ -4677,14 +4706,14 @@ #define DDRSS2_CTL_288_DATA 0x00000000 #define DDRSS2_CTL_289_DATA 0x00000000 #define DDRSS2_CTL_290_DATA 0x03030300 -#define DDRSS2_CTL_291_DATA 0x00000001 +#define DDRSS2_CTL_291_DATA 0x00010101 #define DDRSS2_CTL_292_DATA 0x00000000 #define DDRSS2_CTL_293_DATA 0x00000000 #define DDRSS2_CTL_294_DATA 0x00000000 #define DDRSS2_CTL_295_DATA 0x00000000 #define DDRSS2_CTL_296_DATA 0x00000000 -#define DDRSS2_CTL_297_DATA 0x00000000 -#define DDRSS2_CTL_298_DATA 0x00000000 +#define DDRSS2_CTL_297_DATA 0xFFFFFFFF +#define DDRSS2_CTL_298_DATA 0x00000FFF #define DDRSS2_CTL_299_DATA 0x00000000 #define DDRSS2_CTL_300_DATA 0x00000000 #define DDRSS2_CTL_301_DATA 0x00000000 @@ -4705,7 +4734,7 @@ #define DDRSS2_CTL_316_DATA 0x01010001 #define DDRSS2_CTL_317_DATA 0x00010101 #define DDRSS2_CTL_318_DATA 0x050A0A03 -#define DDRSS2_CTL_319_DATA 0x10081F1F +#define DDRSS2_CTL_319_DATA 0x10082323 #define DDRSS2_CTL_320_DATA 0x00090310 #define DDRSS2_CTL_321_DATA 0x0B0C030F #define DDRSS2_CTL_322_DATA 0x0B0C0306 @@ -4780,7 +4809,7 @@ #define DDRSS2_CTL_391_DATA 0x00000200 #define DDRSS2_CTL_392_DATA 0x00000200 #define DDRSS2_CTL_393_DATA 0x00000200 -#define DDRSS2_CTL_394_DATA 0x00000252 +#define DDRSS2_CTL_394_DATA 0x00000270 #define DDRSS2_CTL_395_DATA 0x000007BC #define DDRSS2_CTL_396_DATA 0x00000204 #define DDRSS2_CTL_397_DATA 0x0000206A @@ -4790,7 +4819,7 @@ #define DDRSS2_CTL_401_DATA 0x00000200 #define DDRSS2_CTL_402_DATA 0x0000613E #define DDRSS2_CTL_403_DATA 0x00014424 -#define DDRSS2_CTL_404_DATA 0x00000E15 +#define DDRSS2_CTL_404_DATA 0x00000E19 #define DDRSS2_CTL_405_DATA 0x0000206A #define DDRSS2_CTL_406_DATA 0x00000200 #define DDRSS2_CTL_407_DATA 0x00000200 @@ -4798,7 +4827,7 @@ #define DDRSS2_CTL_409_DATA 0x00000200 #define DDRSS2_CTL_410_DATA 0x0000613E #define DDRSS2_CTL_411_DATA 0x00014424 -#define DDRSS2_CTL_412_DATA 0x02020E15 +#define DDRSS2_CTL_412_DATA 0x02020E19 #define DDRSS2_CTL_413_DATA 0x03030202 #define DDRSS2_CTL_414_DATA 0x00000022 #define DDRSS2_CTL_415_DATA 0x00000000 @@ -4815,7 +4844,7 @@ #define DDRSS2_CTL_426_DATA 0x00000000 #define DDRSS2_CTL_427_DATA 0x02000000 #define DDRSS2_CTL_428_DATA 0x01000404 -#define DDRSS2_CTL_429_DATA 0x0B1E0B1E +#define DDRSS2_CTL_429_DATA 0x0B220B22 #define DDRSS2_CTL_430_DATA 0x00000105 #define DDRSS2_CTL_431_DATA 0x00010101 #define DDRSS2_CTL_432_DATA 0x00010101 @@ -4858,8 +4887,8 @@ #define DDRSS2_PI_09_DATA 0x00000000 #define DDRSS2_PI_10_DATA 0x00000000 #define DDRSS2_PI_11_DATA 0x00000000 -#define DDRSS2_PI_12_DATA 0x00000007 -#define DDRSS2_PI_13_DATA 0x00010002 +#define DDRSS2_PI_12_DATA 0x00000003 +#define DDRSS2_PI_13_DATA 0x00010001 #define DDRSS2_PI_14_DATA 0x0800000F #define DDRSS2_PI_15_DATA 0x00000103 #define DDRSS2_PI_16_DATA 0x00000005 @@ -4907,18 +4936,18 @@ #define DDRSS2_PI_58_DATA 0x00000000 #define DDRSS2_PI_59_DATA 0x00000000 #define DDRSS2_PI_60_DATA 0x0A0A140A -#define DDRSS2_PI_61_DATA 0x10020101 +#define DDRSS2_PI_61_DATA 0x10020201 #define DDRSS2_PI_62_DATA 0x00020805 #define DDRSS2_PI_63_DATA 0x01000404 #define DDRSS2_PI_64_DATA 0x00000000 #define DDRSS2_PI_65_DATA 0x00000000 #define DDRSS2_PI_66_DATA 0x00000100 -#define DDRSS2_PI_67_DATA 0x0001010F +#define DDRSS2_PI_67_DATA 0x0002020F #define DDRSS2_PI_68_DATA 0x00340000 #define DDRSS2_PI_69_DATA 0x00000000 #define DDRSS2_PI_70_DATA 0x00000000 #define DDRSS2_PI_71_DATA 0x0000FFFF -#define DDRSS2_PI_72_DATA 0x00000000 +#define DDRSS2_PI_72_DATA 0x01000000 #define DDRSS2_PI_73_DATA 0x00080000 #define DDRSS2_PI_74_DATA 0x02000200 #define DDRSS2_PI_75_DATA 0x01000100 @@ -5007,37 +5036,37 @@ #define DDRSS2_PI_158_DATA 0x00000000 #define DDRSS2_PI_159_DATA 0x00000401 #define DDRSS2_PI_160_DATA 0x00000000 -#define DDRSS2_PI_161_DATA 0x00010000 -#define DDRSS2_PI_162_DATA 0x00000000 -#define DDRSS2_PI_163_DATA 0x2B2B0200 +#define DDRSS2_PI_161_DATA 0x05010000 +#define DDRSS2_PI_162_DATA 0x00000001 +#define DDRSS2_PI_163_DATA 0x2B2B0201 #define DDRSS2_PI_164_DATA 0x00000034 -#define DDRSS2_PI_165_DATA 0x00000064 -#define DDRSS2_PI_166_DATA 0x00020064 +#define DDRSS2_PI_165_DATA 0x00000068 +#define DDRSS2_PI_166_DATA 0x00020068 #define DDRSS2_PI_167_DATA 0x02000200 -#define DDRSS2_PI_168_DATA 0x48120C04 -#define DDRSS2_PI_169_DATA 0x00154812 -#define DDRSS2_PI_170_DATA 0x00000063 +#define DDRSS2_PI_168_DATA 0x50120C04 +#define DDRSS2_PI_169_DATA 0x00155012 +#define DDRSS2_PI_170_DATA 0x00000068 #define DDRSS2_PI_171_DATA 0x0000032B #define DDRSS2_PI_172_DATA 0x00001035 #define DDRSS2_PI_173_DATA 0x0000032B #define DDRSS2_PI_174_DATA 0x04001035 #define DDRSS2_PI_175_DATA 0x01010404 -#define DDRSS2_PI_176_DATA 0x00001501 +#define DDRSS2_PI_176_DATA 0x00001500 #define DDRSS2_PI_177_DATA 0x00150015 #define DDRSS2_PI_178_DATA 0x01000100 #define DDRSS2_PI_179_DATA 0x00000100 #define DDRSS2_PI_180_DATA 0x00000000 #define DDRSS2_PI_181_DATA 0x01010101 -#define DDRSS2_PI_182_DATA 0x00000101 +#define DDRSS2_PI_182_DATA 0x00000000 #define DDRSS2_PI_183_DATA 0x00000000 #define DDRSS2_PI_184_DATA 0x00000000 -#define DDRSS2_PI_185_DATA 0x15040000 -#define DDRSS2_PI_186_DATA 0x0E0E0215 +#define DDRSS2_PI_185_DATA 0x19040000 +#define DDRSS2_PI_186_DATA 0x0E0E0219 #define DDRSS2_PI_187_DATA 0x00040402 #define DDRSS2_PI_188_DATA 0x000D0035 #define DDRSS2_PI_189_DATA 0x00218049 #define DDRSS2_PI_190_DATA 0x00218049 -#define DDRSS2_PI_191_DATA 0x01010101 +#define DDRSS2_PI_191_DATA 0x01000101 #define DDRSS2_PI_192_DATA 0x0004000E #define DDRSS2_PI_193_DATA 0x00040216 #define DDRSS2_PI_194_DATA 0x01000216 @@ -5045,8 +5074,8 @@ #define DDRSS2_PI_196_DATA 0x02170100 #define DDRSS2_PI_197_DATA 0x01000217 #define DDRSS2_PI_198_DATA 0x02170217 -#define DDRSS2_PI_199_DATA 0x32103200 -#define DDRSS2_PI_200_DATA 0x01013210 +#define DDRSS2_PI_199_DATA 0x2F1B3200 +#define DDRSS2_PI_200_DATA 0x01012F1B #define DDRSS2_PI_201_DATA 0x0A070601 #define DDRSS2_PI_202_DATA 0x1F130A0D #define DDRSS2_PI_203_DATA 0x1F130A14 @@ -5058,13 +5087,13 @@ #define DDRSS2_PI_209_DATA 0x00240216 #define DDRSS2_PI_210_DATA 0x00110216 #define DDRSS2_PI_211_DATA 0x32000056 -#define DDRSS2_PI_212_DATA 0x00000301 -#define DDRSS2_PI_213_DATA 0x005B0036 +#define DDRSS2_PI_212_DATA 0x00000101 +#define DDRSS2_PI_213_DATA 0x005F0036 #define DDRSS2_PI_214_DATA 0x03013212 #define DDRSS2_PI_215_DATA 0x00003600 -#define DDRSS2_PI_216_DATA 0x3212005B -#define DDRSS2_PI_217_DATA 0x09000301 -#define DDRSS2_PI_218_DATA 0x04010504 +#define DDRSS2_PI_216_DATA 0x3212005F +#define DDRSS2_PI_217_DATA 0x09000001 +#define DDRSS2_PI_218_DATA 0x06010504 #define DDRSS2_PI_219_DATA 0x04000364 #define DDRSS2_PI_220_DATA 0x0A032001 #define DDRSS2_PI_221_DATA 0x2C31110A @@ -5121,29 +5150,29 @@ #define DDRSS2_PI_272_DATA 0x00080804 #define DDRSS2_PI_273_DATA 0x00000000 #define DDRSS2_PI_274_DATA 0x00000000 -#define DDRSS2_PI_275_DATA 0x00330084 +#define DDRSS2_PI_275_DATA 0x00F30084 #define DDRSS2_PI_276_DATA 0x00160000 -#define DDRSS2_PI_277_DATA 0x35333FF4 +#define DDRSS2_PI_277_DATA 0x35F33FF4 #define DDRSS2_PI_278_DATA 0x00160F27 -#define DDRSS2_PI_279_DATA 0x35333FF4 +#define DDRSS2_PI_279_DATA 0x35F33FF4 #define DDRSS2_PI_280_DATA 0x00160F27 -#define DDRSS2_PI_281_DATA 0x00330084 +#define DDRSS2_PI_281_DATA 0x00F30084 #define DDRSS2_PI_282_DATA 0x00160000 -#define DDRSS2_PI_283_DATA 0x35333FF4 +#define DDRSS2_PI_283_DATA 0x35F33FF4 #define DDRSS2_PI_284_DATA 0x00160F27 -#define DDRSS2_PI_285_DATA 0x35333FF4 +#define DDRSS2_PI_285_DATA 0x35F33FF4 #define DDRSS2_PI_286_DATA 0x00160F27 -#define DDRSS2_PI_287_DATA 0x00330084 +#define DDRSS2_PI_287_DATA 0x00F30084 #define DDRSS2_PI_288_DATA 0x00160000 -#define DDRSS2_PI_289_DATA 0x35333FF4 +#define DDRSS2_PI_289_DATA 0x35F33FF4 #define DDRSS2_PI_290_DATA 0x00160F27 -#define DDRSS2_PI_291_DATA 0x35333FF4 +#define DDRSS2_PI_291_DATA 0x35F33FF4 #define DDRSS2_PI_292_DATA 0x00160F27 -#define DDRSS2_PI_293_DATA 0x00330084 +#define DDRSS2_PI_293_DATA 0x00F30084 #define DDRSS2_PI_294_DATA 0x00160000 -#define DDRSS2_PI_295_DATA 0x35333FF4 +#define DDRSS2_PI_295_DATA 0x35F33FF4 #define DDRSS2_PI_296_DATA 0x00160F27 -#define DDRSS2_PI_297_DATA 0x35333FF4 +#define DDRSS2_PI_297_DATA 0x35F33FF4 #define DDRSS2_PI_298_DATA 0x00160F27 #define DDRSS2_PI_299_DATA 0x00000000 @@ -5159,7 +5188,7 @@ #define DDRSS2_PHY_09_DATA 0x00000000 #define DDRSS2_PHY_10_DATA 0x00000000 #define DDRSS2_PHY_11_DATA 0x01000001 -#define DDRSS2_PHY_12_DATA 0x00000100 +#define DDRSS2_PHY_12_DATA 0x00000200 #define DDRSS2_PHY_13_DATA 0x000800C0 #define DDRSS2_PHY_14_DATA 0x060100CC #define DDRSS2_PHY_15_DATA 0x00030066 @@ -5178,7 +5207,7 @@ #define DDRSS2_PHY_28_DATA 0x2A000000 #define DDRSS2_PHY_29_DATA 0x00000808 #define DDRSS2_PHY_30_DATA 0x0F000000 -#define DDRSS2_PHY_31_DATA 0x00000F0F +#define DDRSS2_PHY_31_DATA 0x00000F08 #define DDRSS2_PHY_32_DATA 0x10400000 #define DDRSS2_PHY_33_DATA 0x0C002006 #define DDRSS2_PHY_34_DATA 0x00000000 @@ -5247,9 +5276,9 @@ #define DDRSS2_PHY_97_DATA 0x00050010 #define DDRSS2_PHY_98_DATA 0x51517041 #define DDRSS2_PHY_99_DATA 0x31C06001 -#define DDRSS2_PHY_100_DATA 0x07AB0340 +#define DDRSS2_PHY_100_DATA 0x07AB01AB #define DDRSS2_PHY_101_DATA 0x00C0C001 -#define DDRSS2_PHY_102_DATA 0x0E0D0001 +#define DDRSS2_PHY_102_DATA 0x0E0D0101 #define DDRSS2_PHY_103_DATA 0x10001000 #define DDRSS2_PHY_104_DATA 0x0C083E42 #define DDRSS2_PHY_105_DATA 0x0F0C3701 @@ -5415,7 +5444,7 @@ #define DDRSS2_PHY_265_DATA 0x00000000 #define DDRSS2_PHY_266_DATA 0x00000000 #define DDRSS2_PHY_267_DATA 0x01000001 -#define DDRSS2_PHY_268_DATA 0x00000100 +#define DDRSS2_PHY_268_DATA 0x00000200 #define DDRSS2_PHY_269_DATA 0x000800C0 #define DDRSS2_PHY_270_DATA 0x060100CC #define DDRSS2_PHY_271_DATA 0x00030066 @@ -5434,7 +5463,7 @@ #define DDRSS2_PHY_284_DATA 0x2A000000 #define DDRSS2_PHY_285_DATA 0x00000808 #define DDRSS2_PHY_286_DATA 0x0F000000 -#define DDRSS2_PHY_287_DATA 0x00000F0F +#define DDRSS2_PHY_287_DATA 0x00000F08 #define DDRSS2_PHY_288_DATA 0x10400000 #define DDRSS2_PHY_289_DATA 0x0C002006 #define DDRSS2_PHY_290_DATA 0x00000000 @@ -5503,9 +5532,9 @@ #define DDRSS2_PHY_353_DATA 0x00050010 #define DDRSS2_PHY_354_DATA 0x51517041 #define DDRSS2_PHY_355_DATA 0x31C06001 -#define DDRSS2_PHY_356_DATA 0x07AB0340 +#define DDRSS2_PHY_356_DATA 0x07AB01AB #define DDRSS2_PHY_357_DATA 0x00C0C001 -#define DDRSS2_PHY_358_DATA 0x0E0D0001 +#define DDRSS2_PHY_358_DATA 0x0E0D0101 #define DDRSS2_PHY_359_DATA 0x10001000 #define DDRSS2_PHY_360_DATA 0x0C083E42 #define DDRSS2_PHY_361_DATA 0x0F0C3701 @@ -5671,7 +5700,7 @@ #define DDRSS2_PHY_521_DATA 0x00000000 #define DDRSS2_PHY_522_DATA 0x00000000 #define DDRSS2_PHY_523_DATA 0x01000001 -#define DDRSS2_PHY_524_DATA 0x00000100 +#define DDRSS2_PHY_524_DATA 0x00000200 #define DDRSS2_PHY_525_DATA 0x000800C0 #define DDRSS2_PHY_526_DATA 0x060100CC #define DDRSS2_PHY_527_DATA 0x00030066 @@ -5690,7 +5719,7 @@ #define DDRSS2_PHY_540_DATA 0x2A000000 #define DDRSS2_PHY_541_DATA 0x00000808 #define DDRSS2_PHY_542_DATA 0x0F000000 -#define DDRSS2_PHY_543_DATA 0x00000F0F +#define DDRSS2_PHY_543_DATA 0x00000F08 #define DDRSS2_PHY_544_DATA 0x10400000 #define DDRSS2_PHY_545_DATA 0x0C002006 #define DDRSS2_PHY_546_DATA 0x00000000 @@ -5759,9 +5788,9 @@ #define DDRSS2_PHY_609_DATA 0x00050010 #define DDRSS2_PHY_610_DATA 0x51517041 #define DDRSS2_PHY_611_DATA 0x31C06001 -#define DDRSS2_PHY_612_DATA 0x07AB0340 +#define DDRSS2_PHY_612_DATA 0x07AB01AB #define DDRSS2_PHY_613_DATA 0x00C0C001 -#define DDRSS2_PHY_614_DATA 0x0E0D0001 +#define DDRSS2_PHY_614_DATA 0x0E0D0101 #define DDRSS2_PHY_615_DATA 0x10001000 #define DDRSS2_PHY_616_DATA 0x0C083E42 #define DDRSS2_PHY_617_DATA 0x0F0C3701 @@ -5927,7 +5956,7 @@ #define DDRSS2_PHY_777_DATA 0x00000000 #define DDRSS2_PHY_778_DATA 0x00000000 #define DDRSS2_PHY_779_DATA 0x01000001 -#define DDRSS2_PHY_780_DATA 0x00000100 +#define DDRSS2_PHY_780_DATA 0x00000200 #define DDRSS2_PHY_781_DATA 0x000800C0 #define DDRSS2_PHY_782_DATA 0x060100CC #define DDRSS2_PHY_783_DATA 0x00030066 @@ -5946,7 +5975,7 @@ #define DDRSS2_PHY_796_DATA 0x2A000000 #define DDRSS2_PHY_797_DATA 0x00000808 #define DDRSS2_PHY_798_DATA 0x0F000000 -#define DDRSS2_PHY_799_DATA 0x00000F0F +#define DDRSS2_PHY_799_DATA 0x00000F08 #define DDRSS2_PHY_800_DATA 0x10400000 #define DDRSS2_PHY_801_DATA 0x0C002006 #define DDRSS2_PHY_802_DATA 0x00000000 @@ -6015,9 +6044,9 @@ #define DDRSS2_PHY_865_DATA 0x00050010 #define DDRSS2_PHY_866_DATA 0x51517041 #define DDRSS2_PHY_867_DATA 0x31C06001 -#define DDRSS2_PHY_868_DATA 0x07AB0340 +#define DDRSS2_PHY_868_DATA 0x07AB01AB #define DDRSS2_PHY_869_DATA 0x00C0C001 -#define DDRSS2_PHY_870_DATA 0x0E0D0001 +#define DDRSS2_PHY_870_DATA 0x0E0D0101 #define DDRSS2_PHY_871_DATA 0x10001000 #define DDRSS2_PHY_872_DATA 0x0C083E42 #define DDRSS2_PHY_873_DATA 0x0F0C3701 @@ -6202,7 +6231,7 @@ #define DDRSS2_PHY_1052_DATA 0x00000033 #define DDRSS2_PHY_1053_DATA 0x00543210 #define DDRSS2_PHY_1054_DATA 0x003F0000 -#define DDRSS2_PHY_1055_DATA 0x000F013F +#define DDRSS2_PHY_1055_DATA 0x000F3F3F #define DDRSS2_PHY_1056_DATA 0x20202003 #define DDRSS2_PHY_1057_DATA 0x00202020 #define DDRSS2_PHY_1058_DATA 0x20008008 @@ -6450,7 +6479,7 @@ #define DDRSS2_PHY_1300_DATA 0x00040101 #define DDRSS2_PHY_1301_DATA 0x0000010F #define DDRSS2_PHY_1302_DATA 0x00000000 -#define DDRSS2_PHY_1303_DATA 0x0000FFFF +#define DDRSS2_PHY_1303_DATA 0x00000064 #define DDRSS2_PHY_1304_DATA 0x00000000 #define DDRSS2_PHY_1305_DATA 0x01010000 #define DDRSS2_PHY_1306_DATA 0x01080402 @@ -6544,7 +6573,7 @@ #define DDRSS2_PHY_1394_DATA 0x00000003 #define DDRSS2_PHY_1395_DATA 0x00000000 #define DDRSS2_PHY_1396_DATA 0x00001142 -#define DDRSS2_PHY_1397_DATA 0x010207AB +#define DDRSS2_PHY_1397_DATA 0x040207AB #define DDRSS2_PHY_1398_DATA 0x01000080 #define DDRSS2_PHY_1399_DATA 0x03900390 #define DDRSS2_PHY_1400_DATA 0x03900390 @@ -6591,7 +6620,7 @@ #define DDRSS3_CTL_17_DATA 0x00000005 #define DDRSS3_CTL_18_DATA 0x000010A9 #define DDRSS3_CTL_19_DATA 0x01010000 -#define DDRSS3_CTL_20_DATA 0x02011001 +#define DDRSS3_CTL_20_DATA 0x01011001 #define DDRSS3_CTL_21_DATA 0x02010000 #define DDRSS3_CTL_22_DATA 0x00020100 #define DDRSS3_CTL_23_DATA 0x0000000B @@ -6606,7 +6635,7 @@ #define DDRSS3_CTL_32_DATA 0x00000000 #define DDRSS3_CTL_33_DATA 0x00000000 #define DDRSS3_CTL_34_DATA 0x040C0000 -#define DDRSS3_CTL_35_DATA 0x12481248 +#define DDRSS3_CTL_35_DATA 0x12501250 #define DDRSS3_CTL_36_DATA 0x00050804 #define DDRSS3_CTL_37_DATA 0x09040008 #define DDRSS3_CTL_38_DATA 0x15000204 @@ -6621,27 +6650,27 @@ #define DDRSS3_CTL_47_DATA 0x1E161110 #define DDRSS3_CTL_48_DATA 0x1000922C #define DDRSS3_CTL_49_DATA 0x02030410 -#define DDRSS3_CTL_50_DATA 0x2C040500 +#define DDRSS3_CTL_50_DATA 0x2C060500 #define DDRSS3_CTL_51_DATA 0x08292C29 #define DDRSS3_CTL_52_DATA 0x14000E0A #define DDRSS3_CTL_53_DATA 0x04010A0A #define DDRSS3_CTL_54_DATA 0x01010004 -#define DDRSS3_CTL_55_DATA 0x04545408 +#define DDRSS3_CTL_55_DATA 0x0454540A #define DDRSS3_CTL_56_DATA 0x04313104 #define DDRSS3_CTL_57_DATA 0x00003131 #define DDRSS3_CTL_58_DATA 0x00010100 #define DDRSS3_CTL_59_DATA 0x03010000 #define DDRSS3_CTL_60_DATA 0x00001508 -#define DDRSS3_CTL_61_DATA 0x00000063 +#define DDRSS3_CTL_61_DATA 0x00000068 #define DDRSS3_CTL_62_DATA 0x0000032B #define DDRSS3_CTL_63_DATA 0x00001035 #define DDRSS3_CTL_64_DATA 0x0000032B #define DDRSS3_CTL_65_DATA 0x00001035 #define DDRSS3_CTL_66_DATA 0x00000005 #define DDRSS3_CTL_67_DATA 0x00050000 -#define DDRSS3_CTL_68_DATA 0x00CB0012 -#define DDRSS3_CTL_69_DATA 0x00CB0408 -#define DDRSS3_CTL_70_DATA 0x00400408 +#define DDRSS3_CTL_68_DATA 0x00CB0005 +#define DDRSS3_CTL_69_DATA 0x00CB0200 +#define DDRSS3_CTL_70_DATA 0x00400200 #define DDRSS3_CTL_71_DATA 0x00120103 #define DDRSS3_CTL_72_DATA 0x00100005 #define DDRSS3_CTL_73_DATA 0x2F080010 @@ -6747,22 +6776,22 @@ #define DDRSS3_CTL_173_DATA 0x00000000 #define DDRSS3_CTL_174_DATA 0x00000000 #define DDRSS3_CTL_175_DATA 0x3FF40084 -#define DDRSS3_CTL_176_DATA 0x33003FF4 -#define DDRSS3_CTL_177_DATA 0x00003333 -#define DDRSS3_CTL_178_DATA 0x35000000 +#define DDRSS3_CTL_176_DATA 0xF3003FF4 +#define DDRSS3_CTL_177_DATA 0x0000F3F3 +#define DDRSS3_CTL_178_DATA 0x35350000 #define DDRSS3_CTL_179_DATA 0x27270035 #define DDRSS3_CTL_180_DATA 0x0F0F0000 #define DDRSS3_CTL_181_DATA 0x16000000 #define DDRSS3_CTL_182_DATA 0x00841616 #define DDRSS3_CTL_183_DATA 0x3FF43FF4 -#define DDRSS3_CTL_184_DATA 0x33333300 +#define DDRSS3_CTL_184_DATA 0xF3F3F300 #define DDRSS3_CTL_185_DATA 0x00000000 -#define DDRSS3_CTL_186_DATA 0x00353500 +#define DDRSS3_CTL_186_DATA 0x00353535 #define DDRSS3_CTL_187_DATA 0x00002727 #define DDRSS3_CTL_188_DATA 0x00000F0F #define DDRSS3_CTL_189_DATA 0x16161600 #define DDRSS3_CTL_190_DATA 0x00000020 -#define DDRSS3_CTL_191_DATA 0x00000000 +#define DDRSS3_CTL_191_DATA 0x01000000 #define DDRSS3_CTL_192_DATA 0x00000001 #define DDRSS3_CTL_193_DATA 0x00000000 #define DDRSS3_CTL_194_DATA 0x01000000 @@ -6862,14 +6891,14 @@ #define DDRSS3_CTL_288_DATA 0x00000000 #define DDRSS3_CTL_289_DATA 0x00000000 #define DDRSS3_CTL_290_DATA 0x03030300 -#define DDRSS3_CTL_291_DATA 0x00000001 +#define DDRSS3_CTL_291_DATA 0x00010101 #define DDRSS3_CTL_292_DATA 0x00000000 #define DDRSS3_CTL_293_DATA 0x00000000 #define DDRSS3_CTL_294_DATA 0x00000000 #define DDRSS3_CTL_295_DATA 0x00000000 #define DDRSS3_CTL_296_DATA 0x00000000 -#define DDRSS3_CTL_297_DATA 0x00000000 -#define DDRSS3_CTL_298_DATA 0x00000000 +#define DDRSS3_CTL_297_DATA 0xFFFFFFFF +#define DDRSS3_CTL_298_DATA 0x00000FFF #define DDRSS3_CTL_299_DATA 0x00000000 #define DDRSS3_CTL_300_DATA 0x00000000 #define DDRSS3_CTL_301_DATA 0x00000000 @@ -6890,7 +6919,7 @@ #define DDRSS3_CTL_316_DATA 0x01010001 #define DDRSS3_CTL_317_DATA 0x00010101 #define DDRSS3_CTL_318_DATA 0x050A0A03 -#define DDRSS3_CTL_319_DATA 0x10081F1F +#define DDRSS3_CTL_319_DATA 0x10082323 #define DDRSS3_CTL_320_DATA 0x00090310 #define DDRSS3_CTL_321_DATA 0x0B0C030F #define DDRSS3_CTL_322_DATA 0x0B0C0306 @@ -6965,7 +6994,7 @@ #define DDRSS3_CTL_391_DATA 0x00000200 #define DDRSS3_CTL_392_DATA 0x00000200 #define DDRSS3_CTL_393_DATA 0x00000200 -#define DDRSS3_CTL_394_DATA 0x00000252 +#define DDRSS3_CTL_394_DATA 0x00000270 #define DDRSS3_CTL_395_DATA 0x000007BC #define DDRSS3_CTL_396_DATA 0x00000204 #define DDRSS3_CTL_397_DATA 0x0000206A @@ -6975,7 +7004,7 @@ #define DDRSS3_CTL_401_DATA 0x00000200 #define DDRSS3_CTL_402_DATA 0x0000613E #define DDRSS3_CTL_403_DATA 0x00014424 -#define DDRSS3_CTL_404_DATA 0x00000E15 +#define DDRSS3_CTL_404_DATA 0x00000E19 #define DDRSS3_CTL_405_DATA 0x0000206A #define DDRSS3_CTL_406_DATA 0x00000200 #define DDRSS3_CTL_407_DATA 0x00000200 @@ -6983,7 +7012,7 @@ #define DDRSS3_CTL_409_DATA 0x00000200 #define DDRSS3_CTL_410_DATA 0x0000613E #define DDRSS3_CTL_411_DATA 0x00014424 -#define DDRSS3_CTL_412_DATA 0x02020E15 +#define DDRSS3_CTL_412_DATA 0x02020E19 #define DDRSS3_CTL_413_DATA 0x03030202 #define DDRSS3_CTL_414_DATA 0x00000022 #define DDRSS3_CTL_415_DATA 0x00000000 @@ -7000,7 +7029,7 @@ #define DDRSS3_CTL_426_DATA 0x00000000 #define DDRSS3_CTL_427_DATA 0x02000000 #define DDRSS3_CTL_428_DATA 0x01000404 -#define DDRSS3_CTL_429_DATA 0x0B1E0B1E +#define DDRSS3_CTL_429_DATA 0x0B220B22 #define DDRSS3_CTL_430_DATA 0x00000105 #define DDRSS3_CTL_431_DATA 0x00010101 #define DDRSS3_CTL_432_DATA 0x00010101 @@ -7043,8 +7072,8 @@ #define DDRSS3_PI_09_DATA 0x00000000 #define DDRSS3_PI_10_DATA 0x00000000 #define DDRSS3_PI_11_DATA 0x00000000 -#define DDRSS3_PI_12_DATA 0x00000007 -#define DDRSS3_PI_13_DATA 0x00010002 +#define DDRSS3_PI_12_DATA 0x00000003 +#define DDRSS3_PI_13_DATA 0x00010001 #define DDRSS3_PI_14_DATA 0x0800000F #define DDRSS3_PI_15_DATA 0x00000103 #define DDRSS3_PI_16_DATA 0x00000005 @@ -7092,18 +7121,18 @@ #define DDRSS3_PI_58_DATA 0x00000000 #define DDRSS3_PI_59_DATA 0x00000000 #define DDRSS3_PI_60_DATA 0x0A0A140A -#define DDRSS3_PI_61_DATA 0x10020101 +#define DDRSS3_PI_61_DATA 0x10020201 #define DDRSS3_PI_62_DATA 0x00020805 #define DDRSS3_PI_63_DATA 0x01000404 #define DDRSS3_PI_64_DATA 0x00000000 #define DDRSS3_PI_65_DATA 0x00000000 #define DDRSS3_PI_66_DATA 0x00000100 -#define DDRSS3_PI_67_DATA 0x0001010F +#define DDRSS3_PI_67_DATA 0x0002020F #define DDRSS3_PI_68_DATA 0x00340000 #define DDRSS3_PI_69_DATA 0x00000000 #define DDRSS3_PI_70_DATA 0x00000000 #define DDRSS3_PI_71_DATA 0x0000FFFF -#define DDRSS3_PI_72_DATA 0x00000000 +#define DDRSS3_PI_72_DATA 0x01000000 #define DDRSS3_PI_73_DATA 0x00080000 #define DDRSS3_PI_74_DATA 0x02000200 #define DDRSS3_PI_75_DATA 0x01000100 @@ -7192,37 +7221,37 @@ #define DDRSS3_PI_158_DATA 0x00000000 #define DDRSS3_PI_159_DATA 0x00000401 #define DDRSS3_PI_160_DATA 0x00000000 -#define DDRSS3_PI_161_DATA 0x00010000 -#define DDRSS3_PI_162_DATA 0x00000000 -#define DDRSS3_PI_163_DATA 0x2B2B0200 +#define DDRSS3_PI_161_DATA 0x05010000 +#define DDRSS3_PI_162_DATA 0x00000001 +#define DDRSS3_PI_163_DATA 0x2B2B0201 #define DDRSS3_PI_164_DATA 0x00000034 -#define DDRSS3_PI_165_DATA 0x00000064 -#define DDRSS3_PI_166_DATA 0x00020064 +#define DDRSS3_PI_165_DATA 0x00000068 +#define DDRSS3_PI_166_DATA 0x00020068 #define DDRSS3_PI_167_DATA 0x02000200 -#define DDRSS3_PI_168_DATA 0x48120C04 -#define DDRSS3_PI_169_DATA 0x00154812 -#define DDRSS3_PI_170_DATA 0x00000063 +#define DDRSS3_PI_168_DATA 0x50120C04 +#define DDRSS3_PI_169_DATA 0x00155012 +#define DDRSS3_PI_170_DATA 0x00000068 #define DDRSS3_PI_171_DATA 0x0000032B #define DDRSS3_PI_172_DATA 0x00001035 #define DDRSS3_PI_173_DATA 0x0000032B #define DDRSS3_PI_174_DATA 0x04001035 #define DDRSS3_PI_175_DATA 0x01010404 -#define DDRSS3_PI_176_DATA 0x00001501 +#define DDRSS3_PI_176_DATA 0x00001500 #define DDRSS3_PI_177_DATA 0x00150015 #define DDRSS3_PI_178_DATA 0x01000100 #define DDRSS3_PI_179_DATA 0x00000100 #define DDRSS3_PI_180_DATA 0x00000000 #define DDRSS3_PI_181_DATA 0x01010101 -#define DDRSS3_PI_182_DATA 0x00000101 +#define DDRSS3_PI_182_DATA 0x00000000 #define DDRSS3_PI_183_DATA 0x00000000 #define DDRSS3_PI_184_DATA 0x00000000 -#define DDRSS3_PI_185_DATA 0x15040000 -#define DDRSS3_PI_186_DATA 0x0E0E0215 +#define DDRSS3_PI_185_DATA 0x19040000 +#define DDRSS3_PI_186_DATA 0x0E0E0219 #define DDRSS3_PI_187_DATA 0x00040402 #define DDRSS3_PI_188_DATA 0x000D0035 #define DDRSS3_PI_189_DATA 0x00218049 #define DDRSS3_PI_190_DATA 0x00218049 -#define DDRSS3_PI_191_DATA 0x01010101 +#define DDRSS3_PI_191_DATA 0x01000101 #define DDRSS3_PI_192_DATA 0x0004000E #define DDRSS3_PI_193_DATA 0x00040216 #define DDRSS3_PI_194_DATA 0x01000216 @@ -7230,8 +7259,8 @@ #define DDRSS3_PI_196_DATA 0x02170100 #define DDRSS3_PI_197_DATA 0x01000217 #define DDRSS3_PI_198_DATA 0x02170217 -#define DDRSS3_PI_199_DATA 0x32103200 -#define DDRSS3_PI_200_DATA 0x01013210 +#define DDRSS3_PI_199_DATA 0x2F1B3200 +#define DDRSS3_PI_200_DATA 0x01012F1B #define DDRSS3_PI_201_DATA 0x0A070601 #define DDRSS3_PI_202_DATA 0x1F130A0D #define DDRSS3_PI_203_DATA 0x1F130A14 @@ -7243,13 +7272,13 @@ #define DDRSS3_PI_209_DATA 0x00240216 #define DDRSS3_PI_210_DATA 0x00110216 #define DDRSS3_PI_211_DATA 0x32000056 -#define DDRSS3_PI_212_DATA 0x00000301 -#define DDRSS3_PI_213_DATA 0x005B0036 +#define DDRSS3_PI_212_DATA 0x00000101 +#define DDRSS3_PI_213_DATA 0x005F0036 #define DDRSS3_PI_214_DATA 0x03013212 #define DDRSS3_PI_215_DATA 0x00003600 -#define DDRSS3_PI_216_DATA 0x3212005B -#define DDRSS3_PI_217_DATA 0x09000301 -#define DDRSS3_PI_218_DATA 0x04010504 +#define DDRSS3_PI_216_DATA 0x3212005F +#define DDRSS3_PI_217_DATA 0x09000001 +#define DDRSS3_PI_218_DATA 0x06010504 #define DDRSS3_PI_219_DATA 0x04000364 #define DDRSS3_PI_220_DATA 0x0A032001 #define DDRSS3_PI_221_DATA 0x2C31110A @@ -7306,29 +7335,29 @@ #define DDRSS3_PI_272_DATA 0x00080804 #define DDRSS3_PI_273_DATA 0x00000000 #define DDRSS3_PI_274_DATA 0x00000000 -#define DDRSS3_PI_275_DATA 0x00330084 +#define DDRSS3_PI_275_DATA 0x35F30084 #define DDRSS3_PI_276_DATA 0x00160000 -#define DDRSS3_PI_277_DATA 0x35333FF4 +#define DDRSS3_PI_277_DATA 0x35F33FF4 #define DDRSS3_PI_278_DATA 0x00160F27 -#define DDRSS3_PI_279_DATA 0x35333FF4 +#define DDRSS3_PI_279_DATA 0x35F33FF4 #define DDRSS3_PI_280_DATA 0x00160F27 -#define DDRSS3_PI_281_DATA 0x00330084 +#define DDRSS3_PI_281_DATA 0x35F30084 #define DDRSS3_PI_282_DATA 0x00160000 -#define DDRSS3_PI_283_DATA 0x35333FF4 +#define DDRSS3_PI_283_DATA 0x35F33FF4 #define DDRSS3_PI_284_DATA 0x00160F27 -#define DDRSS3_PI_285_DATA 0x35333FF4 +#define DDRSS3_PI_285_DATA 0x35F33FF4 #define DDRSS3_PI_286_DATA 0x00160F27 -#define DDRSS3_PI_287_DATA 0x00330084 +#define DDRSS3_PI_287_DATA 0x35F30084 #define DDRSS3_PI_288_DATA 0x00160000 -#define DDRSS3_PI_289_DATA 0x35333FF4 +#define DDRSS3_PI_289_DATA 0x35F33FF4 #define DDRSS3_PI_290_DATA 0x00160F27 -#define DDRSS3_PI_291_DATA 0x35333FF4 +#define DDRSS3_PI_291_DATA 0x35F33FF4 #define DDRSS3_PI_292_DATA 0x00160F27 -#define DDRSS3_PI_293_DATA 0x00330084 +#define DDRSS3_PI_293_DATA 0x35F30084 #define DDRSS3_PI_294_DATA 0x00160000 -#define DDRSS3_PI_295_DATA 0x35333FF4 +#define DDRSS3_PI_295_DATA 0x35F33FF4 #define DDRSS3_PI_296_DATA 0x00160F27 -#define DDRSS3_PI_297_DATA 0x35333FF4 +#define DDRSS3_PI_297_DATA 0x35F33FF4 #define DDRSS3_PI_298_DATA 0x00160F27 #define DDRSS3_PI_299_DATA 0x00000000 @@ -7344,7 +7373,7 @@ #define DDRSS3_PHY_09_DATA 0x00000000 #define DDRSS3_PHY_10_DATA 0x00000000 #define DDRSS3_PHY_11_DATA 0x01000001 -#define DDRSS3_PHY_12_DATA 0x00000100 +#define DDRSS3_PHY_12_DATA 0x00000200 #define DDRSS3_PHY_13_DATA 0x000800C0 #define DDRSS3_PHY_14_DATA 0x060100CC #define DDRSS3_PHY_15_DATA 0x00030066 @@ -7363,7 +7392,7 @@ #define DDRSS3_PHY_28_DATA 0x2A000000 #define DDRSS3_PHY_29_DATA 0x00000808 #define DDRSS3_PHY_30_DATA 0x0F000000 -#define DDRSS3_PHY_31_DATA 0x00000F0F +#define DDRSS3_PHY_31_DATA 0x00000F08 #define DDRSS3_PHY_32_DATA 0x10400000 #define DDRSS3_PHY_33_DATA 0x0C002006 #define DDRSS3_PHY_34_DATA 0x00000000 @@ -7432,9 +7461,9 @@ #define DDRSS3_PHY_97_DATA 0x00050010 #define DDRSS3_PHY_98_DATA 0x51517041 #define DDRSS3_PHY_99_DATA 0x31C06001 -#define DDRSS3_PHY_100_DATA 0x07AB0340 +#define DDRSS3_PHY_100_DATA 0x07AB01AB #define DDRSS3_PHY_101_DATA 0x00C0C001 -#define DDRSS3_PHY_102_DATA 0x0E0D0001 +#define DDRSS3_PHY_102_DATA 0x0E0D0101 #define DDRSS3_PHY_103_DATA 0x10001000 #define DDRSS3_PHY_104_DATA 0x0C083E42 #define DDRSS3_PHY_105_DATA 0x0F0C3701 @@ -7600,7 +7629,7 @@ #define DDRSS3_PHY_265_DATA 0x00000000 #define DDRSS3_PHY_266_DATA 0x00000000 #define DDRSS3_PHY_267_DATA 0x01000001 -#define DDRSS3_PHY_268_DATA 0x00000100 +#define DDRSS3_PHY_268_DATA 0x00000200 #define DDRSS3_PHY_269_DATA 0x000800C0 #define DDRSS3_PHY_270_DATA 0x060100CC #define DDRSS3_PHY_271_DATA 0x00030066 @@ -7619,7 +7648,7 @@ #define DDRSS3_PHY_284_DATA 0x2A000000 #define DDRSS3_PHY_285_DATA 0x00000808 #define DDRSS3_PHY_286_DATA 0x0F000000 -#define DDRSS3_PHY_287_DATA 0x00000F0F +#define DDRSS3_PHY_287_DATA 0x00000F08 #define DDRSS3_PHY_288_DATA 0x10400000 #define DDRSS3_PHY_289_DATA 0x0C002006 #define DDRSS3_PHY_290_DATA 0x00000000 @@ -7688,9 +7717,9 @@ #define DDRSS3_PHY_353_DATA 0x00050010 #define DDRSS3_PHY_354_DATA 0x51517041 #define DDRSS3_PHY_355_DATA 0x31C06001 -#define DDRSS3_PHY_356_DATA 0x07AB0340 +#define DDRSS3_PHY_356_DATA 0x07AB01AB #define DDRSS3_PHY_357_DATA 0x00C0C001 -#define DDRSS3_PHY_358_DATA 0x0E0D0001 +#define DDRSS3_PHY_358_DATA 0x0E0D0101 #define DDRSS3_PHY_359_DATA 0x10001000 #define DDRSS3_PHY_360_DATA 0x0C083E42 #define DDRSS3_PHY_361_DATA 0x0F0C3701 @@ -7856,7 +7885,7 @@ #define DDRSS3_PHY_521_DATA 0x00000000 #define DDRSS3_PHY_522_DATA 0x00000000 #define DDRSS3_PHY_523_DATA 0x01000001 -#define DDRSS3_PHY_524_DATA 0x00000100 +#define DDRSS3_PHY_524_DATA 0x00000200 #define DDRSS3_PHY_525_DATA 0x000800C0 #define DDRSS3_PHY_526_DATA 0x060100CC #define DDRSS3_PHY_527_DATA 0x00030066 @@ -7875,7 +7904,7 @@ #define DDRSS3_PHY_540_DATA 0x2A000000 #define DDRSS3_PHY_541_DATA 0x00000808 #define DDRSS3_PHY_542_DATA 0x0F000000 -#define DDRSS3_PHY_543_DATA 0x00000F0F +#define DDRSS3_PHY_543_DATA 0x00000F08 #define DDRSS3_PHY_544_DATA 0x10400000 #define DDRSS3_PHY_545_DATA 0x0C002006 #define DDRSS3_PHY_546_DATA 0x00000000 @@ -7944,9 +7973,9 @@ #define DDRSS3_PHY_609_DATA 0x00050010 #define DDRSS3_PHY_610_DATA 0x51517041 #define DDRSS3_PHY_611_DATA 0x31C06001 -#define DDRSS3_PHY_612_DATA 0x07AB0340 +#define DDRSS3_PHY_612_DATA 0x07AB01AB #define DDRSS3_PHY_613_DATA 0x00C0C001 -#define DDRSS3_PHY_614_DATA 0x0E0D0001 +#define DDRSS3_PHY_614_DATA 0x0E0D0101 #define DDRSS3_PHY_615_DATA 0x10001000 #define DDRSS3_PHY_616_DATA 0x0C083E42 #define DDRSS3_PHY_617_DATA 0x0F0C3701 @@ -8112,7 +8141,7 @@ #define DDRSS3_PHY_777_DATA 0x00000000 #define DDRSS3_PHY_778_DATA 0x00000000 #define DDRSS3_PHY_779_DATA 0x01000001 -#define DDRSS3_PHY_780_DATA 0x00000100 +#define DDRSS3_PHY_780_DATA 0x00000200 #define DDRSS3_PHY_781_DATA 0x000800C0 #define DDRSS3_PHY_782_DATA 0x060100CC #define DDRSS3_PHY_783_DATA 0x00030066 @@ -8131,7 +8160,7 @@ #define DDRSS3_PHY_796_DATA 0x2A000000 #define DDRSS3_PHY_797_DATA 0x00000808 #define DDRSS3_PHY_798_DATA 0x0F000000 -#define DDRSS3_PHY_799_DATA 0x00000F0F +#define DDRSS3_PHY_799_DATA 0x00000F08 #define DDRSS3_PHY_800_DATA 0x10400000 #define DDRSS3_PHY_801_DATA 0x0C002006 #define DDRSS3_PHY_802_DATA 0x00000000 @@ -8200,9 +8229,9 @@ #define DDRSS3_PHY_865_DATA 0x00050010 #define DDRSS3_PHY_866_DATA 0x51517041 #define DDRSS3_PHY_867_DATA 0x31C06001 -#define DDRSS3_PHY_868_DATA 0x07AB0340 +#define DDRSS3_PHY_868_DATA 0x07AB01AB #define DDRSS3_PHY_869_DATA 0x00C0C001 -#define DDRSS3_PHY_870_DATA 0x0E0D0001 +#define DDRSS3_PHY_870_DATA 0x0E0D0101 #define DDRSS3_PHY_871_DATA 0x10001000 #define DDRSS3_PHY_872_DATA 0x0C083E42 #define DDRSS3_PHY_873_DATA 0x0F0C3701 @@ -8387,7 +8416,7 @@ #define DDRSS3_PHY_1052_DATA 0x00000033 #define DDRSS3_PHY_1053_DATA 0x00543210 #define DDRSS3_PHY_1054_DATA 0x003F0000 -#define DDRSS3_PHY_1055_DATA 0x000F013F +#define DDRSS3_PHY_1055_DATA 0x000F3F3F #define DDRSS3_PHY_1056_DATA 0x20202003 #define DDRSS3_PHY_1057_DATA 0x00202020 #define DDRSS3_PHY_1058_DATA 0x20008008 @@ -8635,7 +8664,7 @@ #define DDRSS3_PHY_1300_DATA 0x00040101 #define DDRSS3_PHY_1301_DATA 0x0000010F #define DDRSS3_PHY_1302_DATA 0x00000000 -#define DDRSS3_PHY_1303_DATA 0x0000FFFF +#define DDRSS3_PHY_1303_DATA 0x00000064 #define DDRSS3_PHY_1304_DATA 0x00000000 #define DDRSS3_PHY_1305_DATA 0x01010000 #define DDRSS3_PHY_1306_DATA 0x01080402 @@ -8729,7 +8758,7 @@ #define DDRSS3_PHY_1394_DATA 0x00000003 #define DDRSS3_PHY_1395_DATA 0x00000000 #define DDRSS3_PHY_1396_DATA 0x00001142 -#define DDRSS3_PHY_1397_DATA 0x010207AB +#define DDRSS3_PHY_1397_DATA 0x040207AB #define DDRSS3_PHY_1398_DATA 0x01000080 #define DDRSS3_PHY_1399_DATA 0x03900390 #define DDRSS3_PHY_1400_DATA 0x03900390 From fe22382b6454d9e92b5f32343ba8eac2e0d838d8 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 3 Nov 2025 12:40:33 +0530 Subject: [PATCH 26/65] arm: dts: k3-am69: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for AM69 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi | 8786 +++++++++++++++++++++ arch/arm/dts/k3-am69-r5-sk.dts | 2 +- 2 files changed, 8787 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi diff --git a/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi b/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi new file mode 100644 index 00000000000..6d9c7a6bb06 --- /dev/null +++ b/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi @@ -0,0 +1,8786 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:56:24 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 2 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 3 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 +#define DDRSS2_PLL_FHS_CNT 5 +#define DDRSS3_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_0 27500000 +#define DDRSS_PLL_FREQUENCY_1 1066500000 +#define DDRSS_PLL_FREQUENCY_2 1066500000 + +#define MULTI_DDR_CFG_INTRLV_GRAN 0 +#define MULTI_DDR_CFG_INTRLV_SIZE 12 +#define MULTI_DDR_CFG_ECC_ENABLE 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 24 +#define MULTI_DDR_CFG_EMIFS_ACTIVE 15 + +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay +#define DDR2_CTL_NODE_STAT okay +#define DDR3_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000007 +#define DDR_REG1_SIZE_LSB 0x80000000 + + +#define DDRSS0_CTL_00_DATA 0x00000B00 +#define DDRSS0_CTL_01_DATA 0x00000000 +#define DDRSS0_CTL_02_DATA 0x00000000 +#define DDRSS0_CTL_03_DATA 0x00000000 +#define DDRSS0_CTL_04_DATA 0x00000000 +#define DDRSS0_CTL_05_DATA 0x00000000 +#define DDRSS0_CTL_06_DATA 0x00000000 +#define DDRSS0_CTL_07_DATA 0x00002AF8 +#define DDRSS0_CTL_08_DATA 0x0001ADAF +#define DDRSS0_CTL_09_DATA 0x00000005 +#define DDRSS0_CTL_10_DATA 0x0000006E +#define DDRSS0_CTL_11_DATA 0x000681C8 +#define DDRSS0_CTL_12_DATA 0x004111C9 +#define DDRSS0_CTL_13_DATA 0x00000005 +#define DDRSS0_CTL_14_DATA 0x000010A9 +#define DDRSS0_CTL_15_DATA 0x000681C8 +#define DDRSS0_CTL_16_DATA 0x004111C9 +#define DDRSS0_CTL_17_DATA 0x00000005 +#define DDRSS0_CTL_18_DATA 0x000010A9 +#define DDRSS0_CTL_19_DATA 0x01010000 +#define DDRSS0_CTL_20_DATA 0x01011001 +#define DDRSS0_CTL_21_DATA 0x02010000 +#define DDRSS0_CTL_22_DATA 0x00020100 +#define DDRSS0_CTL_23_DATA 0x0000000B +#define DDRSS0_CTL_24_DATA 0x0000001C +#define DDRSS0_CTL_25_DATA 0x00000000 +#define DDRSS0_CTL_26_DATA 0x00000000 +#define DDRSS0_CTL_27_DATA 0x03020200 +#define DDRSS0_CTL_28_DATA 0x00005656 +#define DDRSS0_CTL_29_DATA 0x00100000 +#define DDRSS0_CTL_30_DATA 0x00000000 +#define DDRSS0_CTL_31_DATA 0x00000000 +#define DDRSS0_CTL_32_DATA 0x00000000 +#define DDRSS0_CTL_33_DATA 0x00000000 +#define DDRSS0_CTL_34_DATA 0x040C0000 +#define DDRSS0_CTL_35_DATA 0x12501250 +#define DDRSS0_CTL_36_DATA 0x00050804 +#define DDRSS0_CTL_37_DATA 0x09040008 +#define DDRSS0_CTL_38_DATA 0x15000204 +#define DDRSS0_CTL_39_DATA 0x1760008B +#define DDRSS0_CTL_40_DATA 0x1500422B +#define DDRSS0_CTL_41_DATA 0x1760008B +#define DDRSS0_CTL_42_DATA 0x2000422B +#define DDRSS0_CTL_43_DATA 0x000A0A09 +#define DDRSS0_CTL_44_DATA 0x040003C5 +#define DDRSS0_CTL_45_DATA 0x1E161104 +#define DDRSS0_CTL_46_DATA 0x1000922C +#define DDRSS0_CTL_47_DATA 0x1E161110 +#define DDRSS0_CTL_48_DATA 0x1000922C +#define DDRSS0_CTL_49_DATA 0x02030410 +#define DDRSS0_CTL_50_DATA 0x2C060500 +#define DDRSS0_CTL_51_DATA 0x08292C29 +#define DDRSS0_CTL_52_DATA 0x14000E0A +#define DDRSS0_CTL_53_DATA 0x04010A0A +#define DDRSS0_CTL_54_DATA 0x01010004 +#define DDRSS0_CTL_55_DATA 0x0454540A +#define DDRSS0_CTL_56_DATA 0x04313104 +#define DDRSS0_CTL_57_DATA 0x00003131 +#define DDRSS0_CTL_58_DATA 0x00010100 +#define DDRSS0_CTL_59_DATA 0x03010000 +#define DDRSS0_CTL_60_DATA 0x00001508 +#define DDRSS0_CTL_61_DATA 0x00000068 +#define DDRSS0_CTL_62_DATA 0x0000032B +#define DDRSS0_CTL_63_DATA 0x00001035 +#define DDRSS0_CTL_64_DATA 0x0000032B +#define DDRSS0_CTL_65_DATA 0x00001035 +#define DDRSS0_CTL_66_DATA 0x00000005 +#define DDRSS0_CTL_67_DATA 0x00050000 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 +#define DDRSS0_CTL_71_DATA 0x00120103 +#define DDRSS0_CTL_72_DATA 0x00100005 +#define DDRSS0_CTL_73_DATA 0x2F080010 +#define DDRSS0_CTL_74_DATA 0x0505012F +#define DDRSS0_CTL_75_DATA 0x0401030A +#define DDRSS0_CTL_76_DATA 0x041E100B +#define DDRSS0_CTL_77_DATA 0x100B0401 +#define DDRSS0_CTL_78_DATA 0x0001041E +#define DDRSS0_CTL_79_DATA 0x00160016 +#define DDRSS0_CTL_80_DATA 0x033B033B +#define DDRSS0_CTL_81_DATA 0x033B033B +#define DDRSS0_CTL_82_DATA 0x03050505 +#define DDRSS0_CTL_83_DATA 0x03010303 +#define DDRSS0_CTL_84_DATA 0x200B100B +#define DDRSS0_CTL_85_DATA 0x04041004 +#define DDRSS0_CTL_86_DATA 0x200B100B +#define DDRSS0_CTL_87_DATA 0x04041004 +#define DDRSS0_CTL_88_DATA 0x03010000 +#define DDRSS0_CTL_89_DATA 0x00010000 +#define DDRSS0_CTL_90_DATA 0x00000000 +#define DDRSS0_CTL_91_DATA 0x00000000 +#define DDRSS0_CTL_92_DATA 0x01000000 +#define DDRSS0_CTL_93_DATA 0x80104002 +#define DDRSS0_CTL_94_DATA 0x00000000 +#define DDRSS0_CTL_95_DATA 0x00040005 +#define DDRSS0_CTL_96_DATA 0x00000000 +#define DDRSS0_CTL_97_DATA 0x00050000 +#define DDRSS0_CTL_98_DATA 0x00000004 +#define DDRSS0_CTL_99_DATA 0x00000000 +#define DDRSS0_CTL_100_DATA 0x00040005 +#define DDRSS0_CTL_101_DATA 0x00000000 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 +#define DDRSS0_CTL_107_DATA 0x00000000 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 +#define DDRSS0_CTL_114_DATA 0x00000000 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 +#define DDRSS0_CTL_121_DATA 0x00000000 +#define DDRSS0_CTL_122_DATA 0x00007173 +#define DDRSS0_CTL_123_DATA 0x00000000 +#define DDRSS0_CTL_124_DATA 0x00000000 +#define DDRSS0_CTL_125_DATA 0x00000000 +#define DDRSS0_CTL_126_DATA 0x00000000 +#define DDRSS0_CTL_127_DATA 0x00000000 +#define DDRSS0_CTL_128_DATA 0x00000000 +#define DDRSS0_CTL_129_DATA 0x00000000 +#define DDRSS0_CTL_130_DATA 0x00000000 +#define DDRSS0_CTL_131_DATA 0x0B030500 +#define DDRSS0_CTL_132_DATA 0x00040B04 +#define DDRSS0_CTL_133_DATA 0x0A090000 +#define DDRSS0_CTL_134_DATA 0x0A090701 +#define DDRSS0_CTL_135_DATA 0x0900000E +#define DDRSS0_CTL_136_DATA 0x0907010A +#define DDRSS0_CTL_137_DATA 0x00000E0A +#define DDRSS0_CTL_138_DATA 0x07010A09 +#define DDRSS0_CTL_139_DATA 0x000E0A09 +#define DDRSS0_CTL_140_DATA 0x07000401 +#define DDRSS0_CTL_141_DATA 0x00000000 +#define DDRSS0_CTL_142_DATA 0x00000000 +#define DDRSS0_CTL_143_DATA 0x00000000 +#define DDRSS0_CTL_144_DATA 0x00000000 +#define DDRSS0_CTL_145_DATA 0x00000000 +#define DDRSS0_CTL_146_DATA 0x00000000 +#define DDRSS0_CTL_147_DATA 0x00000000 +#define DDRSS0_CTL_148_DATA 0x08080000 +#define DDRSS0_CTL_149_DATA 0x01000000 +#define DDRSS0_CTL_150_DATA 0x800000C0 +#define DDRSS0_CTL_151_DATA 0x800000C0 +#define DDRSS0_CTL_152_DATA 0x800000C0 +#define DDRSS0_CTL_153_DATA 0x00000000 +#define DDRSS0_CTL_154_DATA 0x00001500 +#define DDRSS0_CTL_155_DATA 0x00000000 +#define DDRSS0_CTL_156_DATA 0x00000001 +#define DDRSS0_CTL_157_DATA 0x00000002 +#define DDRSS0_CTL_158_DATA 0x0000100E +#define DDRSS0_CTL_159_DATA 0x00000000 +#define DDRSS0_CTL_160_DATA 0x00000000 +#define DDRSS0_CTL_161_DATA 0x00000000 +#define DDRSS0_CTL_162_DATA 0x00000000 +#define DDRSS0_CTL_163_DATA 0x00000000 +#define DDRSS0_CTL_164_DATA 0x000B0000 +#define DDRSS0_CTL_165_DATA 0x000E0006 +#define DDRSS0_CTL_166_DATA 0x000E0404 +#define DDRSS0_CTL_167_DATA 0x00D601AB +#define DDRSS0_CTL_168_DATA 0x10100216 +#define DDRSS0_CTL_169_DATA 0x01AB0216 +#define DDRSS0_CTL_170_DATA 0x021600D6 +#define DDRSS0_CTL_171_DATA 0x02161010 +#define DDRSS0_CTL_172_DATA 0x00000000 +#define DDRSS0_CTL_173_DATA 0x00000000 +#define DDRSS0_CTL_174_DATA 0x00000000 +#define DDRSS0_CTL_175_DATA 0x3FF40084 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 +#define DDRSS0_CTL_178_DATA 0x35000000 +#define DDRSS0_CTL_179_DATA 0x27270035 +#define DDRSS0_CTL_180_DATA 0x0F0F0000 +#define DDRSS0_CTL_181_DATA 0x16000000 +#define DDRSS0_CTL_182_DATA 0x00841616 +#define DDRSS0_CTL_183_DATA 0x3FF43FF4 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 +#define DDRSS0_CTL_185_DATA 0x00000000 +#define DDRSS0_CTL_186_DATA 0x00353500 +#define DDRSS0_CTL_187_DATA 0x00002727 +#define DDRSS0_CTL_188_DATA 0x00000F0F +#define DDRSS0_CTL_189_DATA 0x16161600 +#define DDRSS0_CTL_190_DATA 0x00000020 +#define DDRSS0_CTL_191_DATA 0x01000000 +#define DDRSS0_CTL_192_DATA 0x00000001 +#define DDRSS0_CTL_193_DATA 0x00000000 +#define DDRSS0_CTL_194_DATA 0x01000000 +#define DDRSS0_CTL_195_DATA 0x00000001 +#define DDRSS0_CTL_196_DATA 0x00000000 +#define DDRSS0_CTL_197_DATA 0x00000000 +#define DDRSS0_CTL_198_DATA 0x00000000 +#define DDRSS0_CTL_199_DATA 0x00000000 +#define DDRSS0_CTL_200_DATA 0x00000000 +#define DDRSS0_CTL_201_DATA 0x00000000 +#define DDRSS0_CTL_202_DATA 0x00000000 +#define DDRSS0_CTL_203_DATA 0x00000000 +#define DDRSS0_CTL_204_DATA 0x00000000 +#define DDRSS0_CTL_205_DATA 0x00000000 +#define DDRSS0_CTL_206_DATA 0x02000000 +#define DDRSS0_CTL_207_DATA 0x01080101 +#define DDRSS0_CTL_208_DATA 0x00000000 +#define DDRSS0_CTL_209_DATA 0x00000000 +#define DDRSS0_CTL_210_DATA 0x00000000 +#define DDRSS0_CTL_211_DATA 0x00000000 +#define DDRSS0_CTL_212_DATA 0x00000000 +#define DDRSS0_CTL_213_DATA 0x00000000 +#define DDRSS0_CTL_214_DATA 0x00000000 +#define DDRSS0_CTL_215_DATA 0x00000000 +#define DDRSS0_CTL_216_DATA 0x00000000 +#define DDRSS0_CTL_217_DATA 0x00000000 +#define DDRSS0_CTL_218_DATA 0x00000000 +#define DDRSS0_CTL_219_DATA 0x00000000 +#define DDRSS0_CTL_220_DATA 0x00000000 +#define DDRSS0_CTL_221_DATA 0x00000000 +#define DDRSS0_CTL_222_DATA 0x00001000 +#define DDRSS0_CTL_223_DATA 0x006403E8 +#define DDRSS0_CTL_224_DATA 0x00000000 +#define DDRSS0_CTL_225_DATA 0x00000000 +#define DDRSS0_CTL_226_DATA 0x00000000 +#define DDRSS0_CTL_227_DATA 0x15110000 +#define DDRSS0_CTL_228_DATA 0x00040C18 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 +#define DDRSS0_CTL_231_DATA 0x00000000 +#define DDRSS0_CTL_232_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 +#define DDRSS0_CTL_235_DATA 0x00000000 +#define DDRSS0_CTL_236_DATA 0x00000000 +#define DDRSS0_CTL_237_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 +#define DDRSS0_CTL_240_DATA 0x00000000 +#define DDRSS0_CTL_241_DATA 0x00000000 +#define DDRSS0_CTL_242_DATA 0x00030000 +#define DDRSS0_CTL_243_DATA 0x00000000 +#define DDRSS0_CTL_244_DATA 0x00000000 +#define DDRSS0_CTL_245_DATA 0x00000000 +#define DDRSS0_CTL_246_DATA 0x00000000 +#define DDRSS0_CTL_247_DATA 0x00000000 +#define DDRSS0_CTL_248_DATA 0x00000000 +#define DDRSS0_CTL_249_DATA 0x00000000 +#define DDRSS0_CTL_250_DATA 0x00000000 +#define DDRSS0_CTL_251_DATA 0x00000000 +#define DDRSS0_CTL_252_DATA 0x00000000 +#define DDRSS0_CTL_253_DATA 0x00000000 +#define DDRSS0_CTL_254_DATA 0x00000000 +#define DDRSS0_CTL_255_DATA 0x00000000 +#define DDRSS0_CTL_256_DATA 0x00000000 +#define DDRSS0_CTL_257_DATA 0x01000200 +#define DDRSS0_CTL_258_DATA 0x00370040 +#define DDRSS0_CTL_259_DATA 0x00020008 +#define DDRSS0_CTL_260_DATA 0x00400100 +#define DDRSS0_CTL_261_DATA 0x00400855 +#define DDRSS0_CTL_262_DATA 0x01000200 +#define DDRSS0_CTL_263_DATA 0x08550040 +#define DDRSS0_CTL_264_DATA 0x00000040 +#define DDRSS0_CTL_265_DATA 0x006B0003 +#define DDRSS0_CTL_266_DATA 0x0100006B +#define DDRSS0_CTL_267_DATA 0x03030303 +#define DDRSS0_CTL_268_DATA 0x00000000 +#define DDRSS0_CTL_269_DATA 0x00000202 +#define DDRSS0_CTL_270_DATA 0x00001FFF +#define DDRSS0_CTL_271_DATA 0x3FFF2000 +#define DDRSS0_CTL_272_DATA 0x03FF0000 +#define DDRSS0_CTL_273_DATA 0x000103FF +#define DDRSS0_CTL_274_DATA 0x0FFF0B00 +#define DDRSS0_CTL_275_DATA 0x01010001 +#define DDRSS0_CTL_276_DATA 0x01010101 +#define DDRSS0_CTL_277_DATA 0x01180101 +#define DDRSS0_CTL_278_DATA 0x00030000 +#define DDRSS0_CTL_279_DATA 0x00000000 +#define DDRSS0_CTL_280_DATA 0x00000000 +#define DDRSS0_CTL_281_DATA 0x00000000 +#define DDRSS0_CTL_282_DATA 0x00000000 +#define DDRSS0_CTL_283_DATA 0x00000000 +#define DDRSS0_CTL_284_DATA 0x00000000 +#define DDRSS0_CTL_285_DATA 0x00000000 +#define DDRSS0_CTL_286_DATA 0x00040101 +#define DDRSS0_CTL_287_DATA 0x04010100 +#define DDRSS0_CTL_288_DATA 0x00000000 +#define DDRSS0_CTL_289_DATA 0x00000000 +#define DDRSS0_CTL_290_DATA 0x03030300 +#define DDRSS0_CTL_291_DATA 0x00010101 +#define DDRSS0_CTL_292_DATA 0x00000000 +#define DDRSS0_CTL_293_DATA 0x00000000 +#define DDRSS0_CTL_294_DATA 0x00000000 +#define DDRSS0_CTL_295_DATA 0x00000000 +#define DDRSS0_CTL_296_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF +#define DDRSS0_CTL_299_DATA 0x00000000 +#define DDRSS0_CTL_300_DATA 0x00000000 +#define DDRSS0_CTL_301_DATA 0x00000000 +#define DDRSS0_CTL_302_DATA 0x00000000 +#define DDRSS0_CTL_303_DATA 0x00000000 +#define DDRSS0_CTL_304_DATA 0x00000000 +#define DDRSS0_CTL_305_DATA 0x00000000 +#define DDRSS0_CTL_306_DATA 0x00000000 +#define DDRSS0_CTL_307_DATA 0x00000000 +#define DDRSS0_CTL_308_DATA 0x00000000 +#define DDRSS0_CTL_309_DATA 0x00000000 +#define DDRSS0_CTL_310_DATA 0x00000000 +#define DDRSS0_CTL_311_DATA 0x00000000 +#define DDRSS0_CTL_312_DATA 0x00000000 +#define DDRSS0_CTL_313_DATA 0x01000000 +#define DDRSS0_CTL_314_DATA 0x00020201 +#define DDRSS0_CTL_315_DATA 0x01000101 +#define DDRSS0_CTL_316_DATA 0x01010001 +#define DDRSS0_CTL_317_DATA 0x00010101 +#define DDRSS0_CTL_318_DATA 0x050A0A03 +#define DDRSS0_CTL_319_DATA 0x10082323 +#define DDRSS0_CTL_320_DATA 0x00090310 +#define DDRSS0_CTL_321_DATA 0x0B0C030F +#define DDRSS0_CTL_322_DATA 0x0B0C0306 +#define DDRSS0_CTL_323_DATA 0x0C090006 +#define DDRSS0_CTL_324_DATA 0x0100000C +#define DDRSS0_CTL_325_DATA 0x08040801 +#define DDRSS0_CTL_326_DATA 0x00000004 +#define DDRSS0_CTL_327_DATA 0x00000000 +#define DDRSS0_CTL_328_DATA 0x00010000 +#define DDRSS0_CTL_329_DATA 0x00280D00 +#define DDRSS0_CTL_330_DATA 0x00000001 +#define DDRSS0_CTL_331_DATA 0x00030001 +#define DDRSS0_CTL_332_DATA 0x00000000 +#define DDRSS0_CTL_333_DATA 0x00000000 +#define DDRSS0_CTL_334_DATA 0x00000000 +#define DDRSS0_CTL_335_DATA 0x00000000 +#define DDRSS0_CTL_336_DATA 0x00000000 +#define DDRSS0_CTL_337_DATA 0x00000000 +#define DDRSS0_CTL_338_DATA 0x00000000 +#define DDRSS0_CTL_339_DATA 0x00000000 +#define DDRSS0_CTL_340_DATA 0x01000000 +#define DDRSS0_CTL_341_DATA 0x00000001 +#define DDRSS0_CTL_342_DATA 0x00010100 +#define DDRSS0_CTL_343_DATA 0x03030000 +#define DDRSS0_CTL_344_DATA 0x00000000 +#define DDRSS0_CTL_345_DATA 0x00000000 +#define DDRSS0_CTL_346_DATA 0x00000000 +#define DDRSS0_CTL_347_DATA 0x00000000 +#define DDRSS0_CTL_348_DATA 0x00000000 +#define DDRSS0_CTL_349_DATA 0x00000000 +#define DDRSS0_CTL_350_DATA 0x00000000 +#define DDRSS0_CTL_351_DATA 0x00000000 +#define DDRSS0_CTL_352_DATA 0x00000000 +#define DDRSS0_CTL_353_DATA 0x00000000 +#define DDRSS0_CTL_354_DATA 0x00000000 +#define DDRSS0_CTL_355_DATA 0x00000000 +#define DDRSS0_CTL_356_DATA 0x00000000 +#define DDRSS0_CTL_357_DATA 0x00000000 +#define DDRSS0_CTL_358_DATA 0x00000000 +#define DDRSS0_CTL_359_DATA 0x00000000 +#define DDRSS0_CTL_360_DATA 0x000556AA +#define DDRSS0_CTL_361_DATA 0x000AAAAA +#define DDRSS0_CTL_362_DATA 0x000AA955 +#define DDRSS0_CTL_363_DATA 0x00055555 +#define DDRSS0_CTL_364_DATA 0x000B3133 +#define DDRSS0_CTL_365_DATA 0x0004CD33 +#define DDRSS0_CTL_366_DATA 0x0004CECC +#define DDRSS0_CTL_367_DATA 0x000B32CC +#define DDRSS0_CTL_368_DATA 0x00010300 +#define DDRSS0_CTL_369_DATA 0x03000100 +#define DDRSS0_CTL_370_DATA 0x00000000 +#define DDRSS0_CTL_371_DATA 0x00000000 +#define DDRSS0_CTL_372_DATA 0x00000000 +#define DDRSS0_CTL_373_DATA 0x00000000 +#define DDRSS0_CTL_374_DATA 0x00000000 +#define DDRSS0_CTL_375_DATA 0x00000000 +#define DDRSS0_CTL_376_DATA 0x00000000 +#define DDRSS0_CTL_377_DATA 0x00010000 +#define DDRSS0_CTL_378_DATA 0x00000404 +#define DDRSS0_CTL_379_DATA 0x00000000 +#define DDRSS0_CTL_380_DATA 0x00000000 +#define DDRSS0_CTL_381_DATA 0x00000000 +#define DDRSS0_CTL_382_DATA 0x00000000 +#define DDRSS0_CTL_383_DATA 0x00000000 +#define DDRSS0_CTL_384_DATA 0x00000000 +#define DDRSS0_CTL_385_DATA 0x00000000 +#define DDRSS0_CTL_386_DATA 0x00000000 +#define DDRSS0_CTL_387_DATA 0x3A3A1B00 +#define DDRSS0_CTL_388_DATA 0x000A0000 +#define DDRSS0_CTL_389_DATA 0x000000C6 +#define DDRSS0_CTL_390_DATA 0x00000200 +#define DDRSS0_CTL_391_DATA 0x00000200 +#define DDRSS0_CTL_392_DATA 0x00000200 +#define DDRSS0_CTL_393_DATA 0x00000200 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC +#define DDRSS0_CTL_396_DATA 0x00000204 +#define DDRSS0_CTL_397_DATA 0x0000206A +#define DDRSS0_CTL_398_DATA 0x00000200 +#define DDRSS0_CTL_399_DATA 0x00000200 +#define DDRSS0_CTL_400_DATA 0x00000200 +#define DDRSS0_CTL_401_DATA 0x00000200 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A +#define DDRSS0_CTL_406_DATA 0x00000200 +#define DDRSS0_CTL_407_DATA 0x00000200 +#define DDRSS0_CTL_408_DATA 0x00000200 +#define DDRSS0_CTL_409_DATA 0x00000200 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 +#define DDRSS0_CTL_413_DATA 0x03030202 +#define DDRSS0_CTL_414_DATA 0x00000022 +#define DDRSS0_CTL_415_DATA 0x00000000 +#define DDRSS0_CTL_416_DATA 0x00000000 +#define DDRSS0_CTL_417_DATA 0x00001403 +#define DDRSS0_CTL_418_DATA 0x000007D0 +#define DDRSS0_CTL_419_DATA 0x00000000 +#define DDRSS0_CTL_420_DATA 0x00000000 +#define DDRSS0_CTL_421_DATA 0x00030000 +#define DDRSS0_CTL_422_DATA 0x0007001F +#define DDRSS0_CTL_423_DATA 0x001B0033 +#define DDRSS0_CTL_424_DATA 0x001B0033 +#define DDRSS0_CTL_425_DATA 0x00000000 +#define DDRSS0_CTL_426_DATA 0x00000000 +#define DDRSS0_CTL_427_DATA 0x02000000 +#define DDRSS0_CTL_428_DATA 0x01000404 +#define DDRSS0_CTL_429_DATA 0x0B220B22 +#define DDRSS0_CTL_430_DATA 0x00000105 +#define DDRSS0_CTL_431_DATA 0x00010101 +#define DDRSS0_CTL_432_DATA 0x00010101 +#define DDRSS0_CTL_433_DATA 0x00010001 +#define DDRSS0_CTL_434_DATA 0x00000101 +#define DDRSS0_CTL_435_DATA 0x02000201 +#define DDRSS0_CTL_436_DATA 0x02010000 +#define DDRSS0_CTL_437_DATA 0x00000200 +#define DDRSS0_CTL_438_DATA 0x28060000 +#define DDRSS0_CTL_439_DATA 0x00000128 +#define DDRSS0_CTL_440_DATA 0xFFFFFFFF +#define DDRSS0_CTL_441_DATA 0xFFFFFFFF +#define DDRSS0_CTL_442_DATA 0x00000000 +#define DDRSS0_CTL_443_DATA 0x00000000 +#define DDRSS0_CTL_444_DATA 0x00000000 +#define DDRSS0_CTL_445_DATA 0x00000000 +#define DDRSS0_CTL_446_DATA 0x00000000 +#define DDRSS0_CTL_447_DATA 0x00000000 +#define DDRSS0_CTL_448_DATA 0x00000000 +#define DDRSS0_CTL_449_DATA 0x00000000 +#define DDRSS0_CTL_450_DATA 0x00000000 +#define DDRSS0_CTL_451_DATA 0x00000000 +#define DDRSS0_CTL_452_DATA 0x00000000 +#define DDRSS0_CTL_453_DATA 0x00000000 +#define DDRSS0_CTL_454_DATA 0x00000000 +#define DDRSS0_CTL_455_DATA 0x00000000 +#define DDRSS0_CTL_456_DATA 0x00000000 +#define DDRSS0_CTL_457_DATA 0x00000000 +#define DDRSS0_CTL_458_DATA 0x00000000 + +#define DDRSS0_PI_00_DATA 0x00000B00 +#define DDRSS0_PI_01_DATA 0x00000000 +#define DDRSS0_PI_02_DATA 0x00000000 +#define DDRSS0_PI_03_DATA 0x00000000 +#define DDRSS0_PI_04_DATA 0x00000000 +#define DDRSS0_PI_05_DATA 0x00000101 +#define DDRSS0_PI_06_DATA 0x00640000 +#define DDRSS0_PI_07_DATA 0x00000001 +#define DDRSS0_PI_08_DATA 0x00000000 +#define DDRSS0_PI_09_DATA 0x00000000 +#define DDRSS0_PI_10_DATA 0x00000000 +#define DDRSS0_PI_11_DATA 0x00000000 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 +#define DDRSS0_PI_14_DATA 0x0800000F +#define DDRSS0_PI_15_DATA 0x00000103 +#define DDRSS0_PI_16_DATA 0x00000005 +#define DDRSS0_PI_17_DATA 0x00000000 +#define DDRSS0_PI_18_DATA 0x00000000 +#define DDRSS0_PI_19_DATA 0x00000000 +#define DDRSS0_PI_20_DATA 0x00000000 +#define DDRSS0_PI_21_DATA 0x00000000 +#define DDRSS0_PI_22_DATA 0x00000000 +#define DDRSS0_PI_23_DATA 0x00000000 +#define DDRSS0_PI_24_DATA 0x00000000 +#define DDRSS0_PI_25_DATA 0x00000000 +#define DDRSS0_PI_26_DATA 0x00010100 +#define DDRSS0_PI_27_DATA 0x00280A00 +#define DDRSS0_PI_28_DATA 0x00000000 +#define DDRSS0_PI_29_DATA 0x0F000000 +#define DDRSS0_PI_30_DATA 0x00003200 +#define DDRSS0_PI_31_DATA 0x00000000 +#define DDRSS0_PI_32_DATA 0x00000000 +#define DDRSS0_PI_33_DATA 0x01010102 +#define DDRSS0_PI_34_DATA 0x00000000 +#define DDRSS0_PI_35_DATA 0x000000AA +#define DDRSS0_PI_36_DATA 0x00000055 +#define DDRSS0_PI_37_DATA 0x000000B5 +#define DDRSS0_PI_38_DATA 0x0000004A +#define DDRSS0_PI_39_DATA 0x00000056 +#define DDRSS0_PI_40_DATA 0x000000A9 +#define DDRSS0_PI_41_DATA 0x000000A9 +#define DDRSS0_PI_42_DATA 0x000000B5 +#define DDRSS0_PI_43_DATA 0x00000000 +#define DDRSS0_PI_44_DATA 0x00000000 +#define DDRSS0_PI_45_DATA 0x000F0F00 +#define DDRSS0_PI_46_DATA 0x0000001B +#define DDRSS0_PI_47_DATA 0x000007D0 +#define DDRSS0_PI_48_DATA 0x00000300 +#define DDRSS0_PI_49_DATA 0x00000000 +#define DDRSS0_PI_50_DATA 0x00000000 +#define DDRSS0_PI_51_DATA 0x01000000 +#define DDRSS0_PI_52_DATA 0x00010101 +#define DDRSS0_PI_53_DATA 0x00000000 +#define DDRSS0_PI_54_DATA 0x00030000 +#define DDRSS0_PI_55_DATA 0x0F000000 +#define DDRSS0_PI_56_DATA 0x00000017 +#define DDRSS0_PI_57_DATA 0x00000000 +#define DDRSS0_PI_58_DATA 0x00000000 +#define DDRSS0_PI_59_DATA 0x00000000 +#define DDRSS0_PI_60_DATA 0x0A0A140A +#define DDRSS0_PI_61_DATA 0x10020201 +#define DDRSS0_PI_62_DATA 0x00020805 +#define DDRSS0_PI_63_DATA 0x01000404 +#define DDRSS0_PI_64_DATA 0x00000000 +#define DDRSS0_PI_65_DATA 0x00000000 +#define DDRSS0_PI_66_DATA 0x00000100 +#define DDRSS0_PI_67_DATA 0x0002020F +#define DDRSS0_PI_68_DATA 0x00340000 +#define DDRSS0_PI_69_DATA 0x00000000 +#define DDRSS0_PI_70_DATA 0x00000000 +#define DDRSS0_PI_71_DATA 0x0000FFFF +#define DDRSS0_PI_72_DATA 0x01000000 +#define DDRSS0_PI_73_DATA 0x00080000 +#define DDRSS0_PI_74_DATA 0x02000200 +#define DDRSS0_PI_75_DATA 0x01000100 +#define DDRSS0_PI_76_DATA 0x01000000 +#define DDRSS0_PI_77_DATA 0x02000200 +#define DDRSS0_PI_78_DATA 0x00000200 +#define DDRSS0_PI_79_DATA 0x00000000 +#define DDRSS0_PI_80_DATA 0x00000000 +#define DDRSS0_PI_81_DATA 0x00000000 +#define DDRSS0_PI_82_DATA 0x00000000 +#define DDRSS0_PI_83_DATA 0x00000000 +#define DDRSS0_PI_84_DATA 0x00000000 +#define DDRSS0_PI_85_DATA 0x00000000 +#define DDRSS0_PI_86_DATA 0x00000000 +#define DDRSS0_PI_87_DATA 0x00000000 +#define DDRSS0_PI_88_DATA 0x00000000 +#define DDRSS0_PI_89_DATA 0x00000000 +#define DDRSS0_PI_90_DATA 0x00000000 +#define DDRSS0_PI_91_DATA 0x00000400 +#define DDRSS0_PI_92_DATA 0x02010000 +#define DDRSS0_PI_93_DATA 0x00080003 +#define DDRSS0_PI_94_DATA 0x00080000 +#define DDRSS0_PI_95_DATA 0x00000001 +#define DDRSS0_PI_96_DATA 0x00000000 +#define DDRSS0_PI_97_DATA 0x0000AA00 +#define DDRSS0_PI_98_DATA 0x00000000 +#define DDRSS0_PI_99_DATA 0x00000000 +#define DDRSS0_PI_100_DATA 0x00010000 +#define DDRSS0_PI_101_DATA 0x00000000 +#define DDRSS0_PI_102_DATA 0x00000000 +#define DDRSS0_PI_103_DATA 0x00000000 +#define DDRSS0_PI_104_DATA 0x00000000 +#define DDRSS0_PI_105_DATA 0x00000000 +#define DDRSS0_PI_106_DATA 0x00000000 +#define DDRSS0_PI_107_DATA 0x00000000 +#define DDRSS0_PI_108_DATA 0x00000000 +#define DDRSS0_PI_109_DATA 0x00000000 +#define DDRSS0_PI_110_DATA 0x00000000 +#define DDRSS0_PI_111_DATA 0x00000000 +#define DDRSS0_PI_112_DATA 0x00000000 +#define DDRSS0_PI_113_DATA 0x00000000 +#define DDRSS0_PI_114_DATA 0x00000000 +#define DDRSS0_PI_115_DATA 0x00000000 +#define DDRSS0_PI_116_DATA 0x00000000 +#define DDRSS0_PI_117_DATA 0x00000000 +#define DDRSS0_PI_118_DATA 0x00000000 +#define DDRSS0_PI_119_DATA 0x00000000 +#define DDRSS0_PI_120_DATA 0x00000000 +#define DDRSS0_PI_121_DATA 0x00000000 +#define DDRSS0_PI_122_DATA 0x00000000 +#define DDRSS0_PI_123_DATA 0x00000000 +#define DDRSS0_PI_124_DATA 0x00000000 +#define DDRSS0_PI_125_DATA 0x00000008 +#define DDRSS0_PI_126_DATA 0x00000000 +#define DDRSS0_PI_127_DATA 0x00000000 +#define DDRSS0_PI_128_DATA 0x00000000 +#define DDRSS0_PI_129_DATA 0x00000000 +#define DDRSS0_PI_130_DATA 0x00000000 +#define DDRSS0_PI_131_DATA 0x00000000 +#define DDRSS0_PI_132_DATA 0x00000000 +#define DDRSS0_PI_133_DATA 0x00000000 +#define DDRSS0_PI_134_DATA 0x00000002 +#define DDRSS0_PI_135_DATA 0x00000000 +#define DDRSS0_PI_136_DATA 0x00000000 +#define DDRSS0_PI_137_DATA 0x0000000A +#define DDRSS0_PI_138_DATA 0x00000019 +#define DDRSS0_PI_139_DATA 0x00000100 +#define DDRSS0_PI_140_DATA 0x00000000 +#define DDRSS0_PI_141_DATA 0x00000000 +#define DDRSS0_PI_142_DATA 0x00000000 +#define DDRSS0_PI_143_DATA 0x00000000 +#define DDRSS0_PI_144_DATA 0x01000000 +#define DDRSS0_PI_145_DATA 0x00010003 +#define DDRSS0_PI_146_DATA 0x02000101 +#define DDRSS0_PI_147_DATA 0x01030001 +#define DDRSS0_PI_148_DATA 0x00010400 +#define DDRSS0_PI_149_DATA 0x06000105 +#define DDRSS0_PI_150_DATA 0x01070001 +#define DDRSS0_PI_151_DATA 0x00000000 +#define DDRSS0_PI_152_DATA 0x00000000 +#define DDRSS0_PI_153_DATA 0x00000000 +#define DDRSS0_PI_154_DATA 0x00010001 +#define DDRSS0_PI_155_DATA 0x00000000 +#define DDRSS0_PI_156_DATA 0x00000000 +#define DDRSS0_PI_157_DATA 0x00000000 +#define DDRSS0_PI_158_DATA 0x00000000 +#define DDRSS0_PI_159_DATA 0x00000401 +#define DDRSS0_PI_160_DATA 0x00000000 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 +#define DDRSS0_PI_164_DATA 0x00000034 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 +#define DDRSS0_PI_167_DATA 0x02000200 +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 +#define DDRSS0_PI_171_DATA 0x0000032B +#define DDRSS0_PI_172_DATA 0x00001035 +#define DDRSS0_PI_173_DATA 0x0000032B +#define DDRSS0_PI_174_DATA 0x04001035 +#define DDRSS0_PI_175_DATA 0x01010404 +#define DDRSS0_PI_176_DATA 0x00001500 +#define DDRSS0_PI_177_DATA 0x00150015 +#define DDRSS0_PI_178_DATA 0x01000100 +#define DDRSS0_PI_179_DATA 0x00000100 +#define DDRSS0_PI_180_DATA 0x00000000 +#define DDRSS0_PI_181_DATA 0x01010101 +#define DDRSS0_PI_182_DATA 0x00000000 +#define DDRSS0_PI_183_DATA 0x00000000 +#define DDRSS0_PI_184_DATA 0x00000000 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 +#define DDRSS0_PI_187_DATA 0x00040402 +#define DDRSS0_PI_188_DATA 0x000D0035 +#define DDRSS0_PI_189_DATA 0x00218049 +#define DDRSS0_PI_190_DATA 0x00218049 +#define DDRSS0_PI_191_DATA 0x01000101 +#define DDRSS0_PI_192_DATA 0x0004000E +#define DDRSS0_PI_193_DATA 0x00040216 +#define DDRSS0_PI_194_DATA 0x01000216 +#define DDRSS0_PI_195_DATA 0x000F000F +#define DDRSS0_PI_196_DATA 0x02170100 +#define DDRSS0_PI_197_DATA 0x01000217 +#define DDRSS0_PI_198_DATA 0x02170217 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B +#define DDRSS0_PI_201_DATA 0x0A070601 +#define DDRSS0_PI_202_DATA 0x1F130A0D +#define DDRSS0_PI_203_DATA 0x1F130A14 +#define DDRSS0_PI_204_DATA 0x0000C014 +#define DDRSS0_PI_205_DATA 0x00C01000 +#define DDRSS0_PI_206_DATA 0x00C01000 +#define DDRSS0_PI_207_DATA 0x00021000 +#define DDRSS0_PI_208_DATA 0x0024000E +#define DDRSS0_PI_209_DATA 0x00240216 +#define DDRSS0_PI_210_DATA 0x00110216 +#define DDRSS0_PI_211_DATA 0x32000056 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 +#define DDRSS0_PI_214_DATA 0x03013212 +#define DDRSS0_PI_215_DATA 0x00003600 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 +#define DDRSS0_PI_220_DATA 0x0A032001 +#define DDRSS0_PI_221_DATA 0x2C31110A +#define DDRSS0_PI_222_DATA 0x00002918 +#define DDRSS0_PI_223_DATA 0x6000838E +#define DDRSS0_PI_224_DATA 0x1E202008 +#define DDRSS0_PI_225_DATA 0x2C311116 +#define DDRSS0_PI_226_DATA 0x00002918 +#define DDRSS0_PI_227_DATA 0x6000838E +#define DDRSS0_PI_228_DATA 0x1E202008 +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 +#define DDRSS0_PI_235_DATA 0x033B0016 +#define DDRSS0_PI_236_DATA 0x0303033B +#define DDRSS0_PI_237_DATA 0x002AF803 +#define DDRSS0_PI_238_DATA 0x0001ADAF +#define DDRSS0_PI_239_DATA 0x00000005 +#define DDRSS0_PI_240_DATA 0x0000006E +#define DDRSS0_PI_241_DATA 0x00000016 +#define DDRSS0_PI_242_DATA 0x000681C8 +#define DDRSS0_PI_243_DATA 0x0001ADAF +#define DDRSS0_PI_244_DATA 0x00000005 +#define DDRSS0_PI_245_DATA 0x000010A9 +#define DDRSS0_PI_246_DATA 0x0000033B +#define DDRSS0_PI_247_DATA 0x000681C8 +#define DDRSS0_PI_248_DATA 0x0001ADAF +#define DDRSS0_PI_249_DATA 0x00000005 +#define DDRSS0_PI_250_DATA 0x000010A9 +#define DDRSS0_PI_251_DATA 0x0100033B +#define DDRSS0_PI_252_DATA 0x00370040 +#define DDRSS0_PI_253_DATA 0x00010008 +#define DDRSS0_PI_254_DATA 0x08550040 +#define DDRSS0_PI_255_DATA 0x00010040 +#define DDRSS0_PI_256_DATA 0x08550040 +#define DDRSS0_PI_257_DATA 0x00000340 +#define DDRSS0_PI_258_DATA 0x006B006B +#define DDRSS0_PI_259_DATA 0x08040404 +#define DDRSS0_PI_260_DATA 0x00000055 +#define DDRSS0_PI_261_DATA 0x55083C5A +#define DDRSS0_PI_262_DATA 0x5A000000 +#define DDRSS0_PI_263_DATA 0x0055083C +#define DDRSS0_PI_264_DATA 0x3C5A0000 +#define DDRSS0_PI_265_DATA 0x00005508 +#define DDRSS0_PI_266_DATA 0x0C3C5A00 +#define DDRSS0_PI_267_DATA 0x080F0E0D +#define DDRSS0_PI_268_DATA 0x000B0A09 +#define DDRSS0_PI_269_DATA 0x00030201 +#define DDRSS0_PI_270_DATA 0x01000000 +#define DDRSS0_PI_271_DATA 0x04020201 +#define DDRSS0_PI_272_DATA 0x00080804 +#define DDRSS0_PI_273_DATA 0x00000000 +#define DDRSS0_PI_274_DATA 0x00000000 +#define DDRSS0_PI_275_DATA 0x00F30084 +#define DDRSS0_PI_276_DATA 0x00160000 +#define DDRSS0_PI_277_DATA 0x35F33FF4 +#define DDRSS0_PI_278_DATA 0x00160F27 +#define DDRSS0_PI_279_DATA 0x35F33FF4 +#define DDRSS0_PI_280_DATA 0x00160F27 +#define DDRSS0_PI_281_DATA 0x00F30084 +#define DDRSS0_PI_282_DATA 0x00160000 +#define DDRSS0_PI_283_DATA 0x35F33FF4 +#define DDRSS0_PI_284_DATA 0x00160F27 +#define DDRSS0_PI_285_DATA 0x35F33FF4 +#define DDRSS0_PI_286_DATA 0x00160F27 +#define DDRSS0_PI_287_DATA 0x00F30084 +#define DDRSS0_PI_288_DATA 0x00160000 +#define DDRSS0_PI_289_DATA 0x35F33FF4 +#define DDRSS0_PI_290_DATA 0x00160F27 +#define DDRSS0_PI_291_DATA 0x35F33FF4 +#define DDRSS0_PI_292_DATA 0x00160F27 +#define DDRSS0_PI_293_DATA 0x00F30084 +#define DDRSS0_PI_294_DATA 0x00160000 +#define DDRSS0_PI_295_DATA 0x35F33FF4 +#define DDRSS0_PI_296_DATA 0x00160F27 +#define DDRSS0_PI_297_DATA 0x35F33FF4 +#define DDRSS0_PI_298_DATA 0x00160F27 +#define DDRSS0_PI_299_DATA 0x00000000 + +#define DDRSS0_PHY_00_DATA 0x000004F0 +#define DDRSS0_PHY_01_DATA 0x00000000 +#define DDRSS0_PHY_02_DATA 0x00030200 +#define DDRSS0_PHY_03_DATA 0x00000000 +#define DDRSS0_PHY_04_DATA 0x00000000 +#define DDRSS0_PHY_05_DATA 0x01030000 +#define DDRSS0_PHY_06_DATA 0x00010000 +#define DDRSS0_PHY_07_DATA 0x01030004 +#define DDRSS0_PHY_08_DATA 0x01000000 +#define DDRSS0_PHY_09_DATA 0x00000000 +#define DDRSS0_PHY_10_DATA 0x00000000 +#define DDRSS0_PHY_11_DATA 0x01000001 +#define DDRSS0_PHY_12_DATA 0x00000200 +#define DDRSS0_PHY_13_DATA 0x000800C0 +#define DDRSS0_PHY_14_DATA 0x060100CC +#define DDRSS0_PHY_15_DATA 0x00030066 +#define DDRSS0_PHY_16_DATA 0x00000000 +#define DDRSS0_PHY_17_DATA 0x00000301 +#define DDRSS0_PHY_18_DATA 0x0000AAAA +#define DDRSS0_PHY_19_DATA 0x00005555 +#define DDRSS0_PHY_20_DATA 0x0000B5B5 +#define DDRSS0_PHY_21_DATA 0x00004A4A +#define DDRSS0_PHY_22_DATA 0x00005656 +#define DDRSS0_PHY_23_DATA 0x0000A9A9 +#define DDRSS0_PHY_24_DATA 0x0000A9A9 +#define DDRSS0_PHY_25_DATA 0x0000B5B5 +#define DDRSS0_PHY_26_DATA 0x00000000 +#define DDRSS0_PHY_27_DATA 0x00000000 +#define DDRSS0_PHY_28_DATA 0x2A000000 +#define DDRSS0_PHY_29_DATA 0x00000808 +#define DDRSS0_PHY_30_DATA 0x0F000000 +#define DDRSS0_PHY_31_DATA 0x00000F08 +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002006 +#define DDRSS0_PHY_34_DATA 0x00000000 +#define DDRSS0_PHY_35_DATA 0x00000000 +#define DDRSS0_PHY_36_DATA 0x55555555 +#define DDRSS0_PHY_37_DATA 0xAAAAAAAA +#define DDRSS0_PHY_38_DATA 0x55555555 +#define DDRSS0_PHY_39_DATA 0xAAAAAAAA +#define DDRSS0_PHY_40_DATA 0x00005555 +#define DDRSS0_PHY_41_DATA 0x01000100 +#define DDRSS0_PHY_42_DATA 0x00800180 +#define DDRSS0_PHY_43_DATA 0x00000001 +#define DDRSS0_PHY_44_DATA 0x00000000 +#define DDRSS0_PHY_45_DATA 0x00000000 +#define DDRSS0_PHY_46_DATA 0x00000000 +#define DDRSS0_PHY_47_DATA 0x00000000 +#define DDRSS0_PHY_48_DATA 0x00000000 +#define DDRSS0_PHY_49_DATA 0x00000000 +#define DDRSS0_PHY_50_DATA 0x00000000 +#define DDRSS0_PHY_51_DATA 0x00000000 +#define DDRSS0_PHY_52_DATA 0x00000000 +#define DDRSS0_PHY_53_DATA 0x00000000 +#define DDRSS0_PHY_54_DATA 0x00000000 +#define DDRSS0_PHY_55_DATA 0x00000000 +#define DDRSS0_PHY_56_DATA 0x00000000 +#define DDRSS0_PHY_57_DATA 0x00000000 +#define DDRSS0_PHY_58_DATA 0x00000000 +#define DDRSS0_PHY_59_DATA 0x00000000 +#define DDRSS0_PHY_60_DATA 0x00000000 +#define DDRSS0_PHY_61_DATA 0x00000000 +#define DDRSS0_PHY_62_DATA 0x00000000 +#define DDRSS0_PHY_63_DATA 0x00000000 +#define DDRSS0_PHY_64_DATA 0x00000000 +#define DDRSS0_PHY_65_DATA 0x00000000 +#define DDRSS0_PHY_66_DATA 0x00000104 +#define DDRSS0_PHY_67_DATA 0x00000120 +#define DDRSS0_PHY_68_DATA 0x00000000 +#define DDRSS0_PHY_69_DATA 0x00000000 +#define DDRSS0_PHY_70_DATA 0x00000000 +#define DDRSS0_PHY_71_DATA 0x00000000 +#define DDRSS0_PHY_72_DATA 0x00000000 +#define DDRSS0_PHY_73_DATA 0x00000000 +#define DDRSS0_PHY_74_DATA 0x00000000 +#define DDRSS0_PHY_75_DATA 0x00000001 +#define DDRSS0_PHY_76_DATA 0x07FF0000 +#define DDRSS0_PHY_77_DATA 0x0080081F +#define DDRSS0_PHY_78_DATA 0x00081020 +#define DDRSS0_PHY_79_DATA 0x04010000 +#define DDRSS0_PHY_80_DATA 0x00000000 +#define DDRSS0_PHY_81_DATA 0x00000000 +#define DDRSS0_PHY_82_DATA 0x00000000 +#define DDRSS0_PHY_83_DATA 0x00000100 +#define DDRSS0_PHY_84_DATA 0x01CC0C01 +#define DDRSS0_PHY_85_DATA 0x1003CC0C +#define DDRSS0_PHY_86_DATA 0x20000140 +#define DDRSS0_PHY_87_DATA 0x07FF0200 +#define DDRSS0_PHY_88_DATA 0x0000DD01 +#define DDRSS0_PHY_89_DATA 0x10100303 +#define DDRSS0_PHY_90_DATA 0x10101010 +#define DDRSS0_PHY_91_DATA 0x10101010 +#define DDRSS0_PHY_92_DATA 0x00021010 +#define DDRSS0_PHY_93_DATA 0x00100010 +#define DDRSS0_PHY_94_DATA 0x00100010 +#define DDRSS0_PHY_95_DATA 0x00100010 +#define DDRSS0_PHY_96_DATA 0x00100010 +#define DDRSS0_PHY_97_DATA 0x00050010 +#define DDRSS0_PHY_98_DATA 0x51517041 +#define DDRSS0_PHY_99_DATA 0x31C06001 +#define DDRSS0_PHY_100_DATA 0x07AB01AB +#define DDRSS0_PHY_101_DATA 0x00C0C001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 +#define DDRSS0_PHY_103_DATA 0x10001000 +#define DDRSS0_PHY_104_DATA 0x0C083E42 +#define DDRSS0_PHY_105_DATA 0x0F0C3701 +#define DDRSS0_PHY_106_DATA 0x01000140 +#define DDRSS0_PHY_107_DATA 0x0C000420 +#define DDRSS0_PHY_108_DATA 0x00000198 +#define DDRSS0_PHY_109_DATA 0x0A0000D0 +#define DDRSS0_PHY_110_DATA 0x00030200 +#define DDRSS0_PHY_111_DATA 0x02800000 +#define DDRSS0_PHY_112_DATA 0x80800000 +#define DDRSS0_PHY_113_DATA 0x000E2010 +#define DDRSS0_PHY_114_DATA 0x76543210 +#define DDRSS0_PHY_115_DATA 0x00000008 +#define DDRSS0_PHY_116_DATA 0x02800280 +#define DDRSS0_PHY_117_DATA 0x02800280 +#define DDRSS0_PHY_118_DATA 0x02800280 +#define DDRSS0_PHY_119_DATA 0x02800280 +#define DDRSS0_PHY_120_DATA 0x00000280 +#define DDRSS0_PHY_121_DATA 0x0000A000 +#define DDRSS0_PHY_122_DATA 0x00A000A0 +#define DDRSS0_PHY_123_DATA 0x00A000A0 +#define DDRSS0_PHY_124_DATA 0x00A000A0 +#define DDRSS0_PHY_125_DATA 0x00A000A0 +#define DDRSS0_PHY_126_DATA 0x00A000A0 +#define DDRSS0_PHY_127_DATA 0x00A000A0 +#define DDRSS0_PHY_128_DATA 0x00A000A0 +#define DDRSS0_PHY_129_DATA 0x00A000A0 +#define DDRSS0_PHY_130_DATA 0x01C200A0 +#define DDRSS0_PHY_131_DATA 0x01A00005 +#define DDRSS0_PHY_132_DATA 0x00000000 +#define DDRSS0_PHY_133_DATA 0x00000000 +#define DDRSS0_PHY_134_DATA 0x00080200 +#define DDRSS0_PHY_135_DATA 0x00000000 +#define DDRSS0_PHY_136_DATA 0x20202000 +#define DDRSS0_PHY_137_DATA 0x20202020 +#define DDRSS0_PHY_138_DATA 0xF0F02020 +#define DDRSS0_PHY_139_DATA 0x00000000 +#define DDRSS0_PHY_140_DATA 0x00000000 +#define DDRSS0_PHY_141_DATA 0x00000000 +#define DDRSS0_PHY_142_DATA 0x00000000 +#define DDRSS0_PHY_143_DATA 0x00000000 +#define DDRSS0_PHY_144_DATA 0x00000000 +#define DDRSS0_PHY_145_DATA 0x00000000 +#define DDRSS0_PHY_146_DATA 0x00000000 +#define DDRSS0_PHY_147_DATA 0x00000000 +#define DDRSS0_PHY_148_DATA 0x00000000 +#define DDRSS0_PHY_149_DATA 0x00000000 +#define DDRSS0_PHY_150_DATA 0x00000000 +#define DDRSS0_PHY_151_DATA 0x00000000 +#define DDRSS0_PHY_152_DATA 0x00000000 +#define DDRSS0_PHY_153_DATA 0x00000000 +#define DDRSS0_PHY_154_DATA 0x00000000 +#define DDRSS0_PHY_155_DATA 0x00000000 +#define DDRSS0_PHY_156_DATA 0x00000000 +#define DDRSS0_PHY_157_DATA 0x00000000 +#define DDRSS0_PHY_158_DATA 0x00000000 +#define DDRSS0_PHY_159_DATA 0x00000000 +#define DDRSS0_PHY_160_DATA 0x00000000 +#define DDRSS0_PHY_161_DATA 0x00000000 +#define DDRSS0_PHY_162_DATA 0x00000000 +#define DDRSS0_PHY_163_DATA 0x00000000 +#define DDRSS0_PHY_164_DATA 0x00000000 +#define DDRSS0_PHY_165_DATA 0x00000000 +#define DDRSS0_PHY_166_DATA 0x00000000 +#define DDRSS0_PHY_167_DATA 0x00000000 +#define DDRSS0_PHY_168_DATA 0x00000000 +#define DDRSS0_PHY_169_DATA 0x00000000 +#define DDRSS0_PHY_170_DATA 0x00000000 +#define DDRSS0_PHY_171_DATA 0x00000000 +#define DDRSS0_PHY_172_DATA 0x00000000 +#define DDRSS0_PHY_173_DATA 0x00000000 +#define DDRSS0_PHY_174_DATA 0x00000000 +#define DDRSS0_PHY_175_DATA 0x00000000 +#define DDRSS0_PHY_176_DATA 0x00000000 +#define DDRSS0_PHY_177_DATA 0x00000000 +#define DDRSS0_PHY_178_DATA 0x00000000 +#define DDRSS0_PHY_179_DATA 0x00000000 +#define DDRSS0_PHY_180_DATA 0x00000000 +#define DDRSS0_PHY_181_DATA 0x00000000 +#define DDRSS0_PHY_182_DATA 0x00000000 +#define DDRSS0_PHY_183_DATA 0x00000000 +#define DDRSS0_PHY_184_DATA 0x00000000 +#define DDRSS0_PHY_185_DATA 0x00000000 +#define DDRSS0_PHY_186_DATA 0x00000000 +#define DDRSS0_PHY_187_DATA 0x00000000 +#define DDRSS0_PHY_188_DATA 0x00000000 +#define DDRSS0_PHY_189_DATA 0x00000000 +#define DDRSS0_PHY_190_DATA 0x00000000 +#define DDRSS0_PHY_191_DATA 0x00000000 +#define DDRSS0_PHY_192_DATA 0x00000000 +#define DDRSS0_PHY_193_DATA 0x00000000 +#define DDRSS0_PHY_194_DATA 0x00000000 +#define DDRSS0_PHY_195_DATA 0x00000000 +#define DDRSS0_PHY_196_DATA 0x00000000 +#define DDRSS0_PHY_197_DATA 0x00000000 +#define DDRSS0_PHY_198_DATA 0x00000000 +#define DDRSS0_PHY_199_DATA 0x00000000 +#define DDRSS0_PHY_200_DATA 0x00000000 +#define DDRSS0_PHY_201_DATA 0x00000000 +#define DDRSS0_PHY_202_DATA 0x00000000 +#define DDRSS0_PHY_203_DATA 0x00000000 +#define DDRSS0_PHY_204_DATA 0x00000000 +#define DDRSS0_PHY_205_DATA 0x00000000 +#define DDRSS0_PHY_206_DATA 0x00000000 +#define DDRSS0_PHY_207_DATA 0x00000000 +#define DDRSS0_PHY_208_DATA 0x00000000 +#define DDRSS0_PHY_209_DATA 0x00000000 +#define DDRSS0_PHY_210_DATA 0x00000000 +#define DDRSS0_PHY_211_DATA 0x00000000 +#define DDRSS0_PHY_212_DATA 0x00000000 +#define DDRSS0_PHY_213_DATA 0x00000000 +#define DDRSS0_PHY_214_DATA 0x00000000 +#define DDRSS0_PHY_215_DATA 0x00000000 +#define DDRSS0_PHY_216_DATA 0x00000000 +#define DDRSS0_PHY_217_DATA 0x00000000 +#define DDRSS0_PHY_218_DATA 0x00000000 +#define DDRSS0_PHY_219_DATA 0x00000000 +#define DDRSS0_PHY_220_DATA 0x00000000 +#define DDRSS0_PHY_221_DATA 0x00000000 +#define DDRSS0_PHY_222_DATA 0x00000000 +#define DDRSS0_PHY_223_DATA 0x00000000 +#define DDRSS0_PHY_224_DATA 0x00000000 +#define DDRSS0_PHY_225_DATA 0x00000000 +#define DDRSS0_PHY_226_DATA 0x00000000 +#define DDRSS0_PHY_227_DATA 0x00000000 +#define DDRSS0_PHY_228_DATA 0x00000000 +#define DDRSS0_PHY_229_DATA 0x00000000 +#define DDRSS0_PHY_230_DATA 0x00000000 +#define DDRSS0_PHY_231_DATA 0x00000000 +#define DDRSS0_PHY_232_DATA 0x00000000 +#define DDRSS0_PHY_233_DATA 0x00000000 +#define DDRSS0_PHY_234_DATA 0x00000000 +#define DDRSS0_PHY_235_DATA 0x00000000 +#define DDRSS0_PHY_236_DATA 0x00000000 +#define DDRSS0_PHY_237_DATA 0x00000000 +#define DDRSS0_PHY_238_DATA 0x00000000 +#define DDRSS0_PHY_239_DATA 0x00000000 +#define DDRSS0_PHY_240_DATA 0x00000000 +#define DDRSS0_PHY_241_DATA 0x00000000 +#define DDRSS0_PHY_242_DATA 0x00000000 +#define DDRSS0_PHY_243_DATA 0x00000000 +#define DDRSS0_PHY_244_DATA 0x00000000 +#define DDRSS0_PHY_245_DATA 0x00000000 +#define DDRSS0_PHY_246_DATA 0x00000000 +#define DDRSS0_PHY_247_DATA 0x00000000 +#define DDRSS0_PHY_248_DATA 0x00000000 +#define DDRSS0_PHY_249_DATA 0x00000000 +#define DDRSS0_PHY_250_DATA 0x00000000 +#define DDRSS0_PHY_251_DATA 0x00000000 +#define DDRSS0_PHY_252_DATA 0x00000000 +#define DDRSS0_PHY_253_DATA 0x00000000 +#define DDRSS0_PHY_254_DATA 0x00000000 +#define DDRSS0_PHY_255_DATA 0x00000000 +#define DDRSS0_PHY_256_DATA 0x000004F0 +#define DDRSS0_PHY_257_DATA 0x00000000 +#define DDRSS0_PHY_258_DATA 0x00030200 +#define DDRSS0_PHY_259_DATA 0x00000000 +#define DDRSS0_PHY_260_DATA 0x00000000 +#define DDRSS0_PHY_261_DATA 0x01030000 +#define DDRSS0_PHY_262_DATA 0x00010000 +#define DDRSS0_PHY_263_DATA 0x01030004 +#define DDRSS0_PHY_264_DATA 0x01000000 +#define DDRSS0_PHY_265_DATA 0x00000000 +#define DDRSS0_PHY_266_DATA 0x00000000 +#define DDRSS0_PHY_267_DATA 0x01000001 +#define DDRSS0_PHY_268_DATA 0x00000200 +#define DDRSS0_PHY_269_DATA 0x000800C0 +#define DDRSS0_PHY_270_DATA 0x060100CC +#define DDRSS0_PHY_271_DATA 0x00030066 +#define DDRSS0_PHY_272_DATA 0x00000000 +#define DDRSS0_PHY_273_DATA 0x00000301 +#define DDRSS0_PHY_274_DATA 0x0000AAAA +#define DDRSS0_PHY_275_DATA 0x00005555 +#define DDRSS0_PHY_276_DATA 0x0000B5B5 +#define DDRSS0_PHY_277_DATA 0x00004A4A +#define DDRSS0_PHY_278_DATA 0x00005656 +#define DDRSS0_PHY_279_DATA 0x0000A9A9 +#define DDRSS0_PHY_280_DATA 0x0000A9A9 +#define DDRSS0_PHY_281_DATA 0x0000B5B5 +#define DDRSS0_PHY_282_DATA 0x00000000 +#define DDRSS0_PHY_283_DATA 0x00000000 +#define DDRSS0_PHY_284_DATA 0x2A000000 +#define DDRSS0_PHY_285_DATA 0x00000808 +#define DDRSS0_PHY_286_DATA 0x0F000000 +#define DDRSS0_PHY_287_DATA 0x00000F08 +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002006 +#define DDRSS0_PHY_290_DATA 0x00000000 +#define DDRSS0_PHY_291_DATA 0x00000000 +#define DDRSS0_PHY_292_DATA 0x55555555 +#define DDRSS0_PHY_293_DATA 0xAAAAAAAA +#define DDRSS0_PHY_294_DATA 0x55555555 +#define DDRSS0_PHY_295_DATA 0xAAAAAAAA +#define DDRSS0_PHY_296_DATA 0x00005555 +#define DDRSS0_PHY_297_DATA 0x01000100 +#define DDRSS0_PHY_298_DATA 0x00800180 +#define DDRSS0_PHY_299_DATA 0x00000000 +#define DDRSS0_PHY_300_DATA 0x00000000 +#define DDRSS0_PHY_301_DATA 0x00000000 +#define DDRSS0_PHY_302_DATA 0x00000000 +#define DDRSS0_PHY_303_DATA 0x00000000 +#define DDRSS0_PHY_304_DATA 0x00000000 +#define DDRSS0_PHY_305_DATA 0x00000000 +#define DDRSS0_PHY_306_DATA 0x00000000 +#define DDRSS0_PHY_307_DATA 0x00000000 +#define DDRSS0_PHY_308_DATA 0x00000000 +#define DDRSS0_PHY_309_DATA 0x00000000 +#define DDRSS0_PHY_310_DATA 0x00000000 +#define DDRSS0_PHY_311_DATA 0x00000000 +#define DDRSS0_PHY_312_DATA 0x00000000 +#define DDRSS0_PHY_313_DATA 0x00000000 +#define DDRSS0_PHY_314_DATA 0x00000000 +#define DDRSS0_PHY_315_DATA 0x00000000 +#define DDRSS0_PHY_316_DATA 0x00000000 +#define DDRSS0_PHY_317_DATA 0x00000000 +#define DDRSS0_PHY_318_DATA 0x00000000 +#define DDRSS0_PHY_319_DATA 0x00000000 +#define DDRSS0_PHY_320_DATA 0x00000000 +#define DDRSS0_PHY_321_DATA 0x00000000 +#define DDRSS0_PHY_322_DATA 0x00000104 +#define DDRSS0_PHY_323_DATA 0x00000120 +#define DDRSS0_PHY_324_DATA 0x00000000 +#define DDRSS0_PHY_325_DATA 0x00000000 +#define DDRSS0_PHY_326_DATA 0x00000000 +#define DDRSS0_PHY_327_DATA 0x00000000 +#define DDRSS0_PHY_328_DATA 0x00000000 +#define DDRSS0_PHY_329_DATA 0x00000000 +#define DDRSS0_PHY_330_DATA 0x00000000 +#define DDRSS0_PHY_331_DATA 0x00000001 +#define DDRSS0_PHY_332_DATA 0x07FF0000 +#define DDRSS0_PHY_333_DATA 0x0080081F +#define DDRSS0_PHY_334_DATA 0x00081020 +#define DDRSS0_PHY_335_DATA 0x04010000 +#define DDRSS0_PHY_336_DATA 0x00000000 +#define DDRSS0_PHY_337_DATA 0x00000000 +#define DDRSS0_PHY_338_DATA 0x00000000 +#define DDRSS0_PHY_339_DATA 0x00000100 +#define DDRSS0_PHY_340_DATA 0x01CC0C01 +#define DDRSS0_PHY_341_DATA 0x1003CC0C +#define DDRSS0_PHY_342_DATA 0x20000140 +#define DDRSS0_PHY_343_DATA 0x07FF0200 +#define DDRSS0_PHY_344_DATA 0x0000DD01 +#define DDRSS0_PHY_345_DATA 0x10100303 +#define DDRSS0_PHY_346_DATA 0x10101010 +#define DDRSS0_PHY_347_DATA 0x10101010 +#define DDRSS0_PHY_348_DATA 0x00021010 +#define DDRSS0_PHY_349_DATA 0x00100010 +#define DDRSS0_PHY_350_DATA 0x00100010 +#define DDRSS0_PHY_351_DATA 0x00100010 +#define DDRSS0_PHY_352_DATA 0x00100010 +#define DDRSS0_PHY_353_DATA 0x00050010 +#define DDRSS0_PHY_354_DATA 0x51517041 +#define DDRSS0_PHY_355_DATA 0x31C06001 +#define DDRSS0_PHY_356_DATA 0x07AB01AB +#define DDRSS0_PHY_357_DATA 0x00C0C001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 +#define DDRSS0_PHY_359_DATA 0x10001000 +#define DDRSS0_PHY_360_DATA 0x0C083E42 +#define DDRSS0_PHY_361_DATA 0x0F0C3701 +#define DDRSS0_PHY_362_DATA 0x01000140 +#define DDRSS0_PHY_363_DATA 0x0C000420 +#define DDRSS0_PHY_364_DATA 0x00000198 +#define DDRSS0_PHY_365_DATA 0x0A0000D0 +#define DDRSS0_PHY_366_DATA 0x00030200 +#define DDRSS0_PHY_367_DATA 0x02800000 +#define DDRSS0_PHY_368_DATA 0x80800000 +#define DDRSS0_PHY_369_DATA 0x000E2010 +#define DDRSS0_PHY_370_DATA 0x76543210 +#define DDRSS0_PHY_371_DATA 0x00000008 +#define DDRSS0_PHY_372_DATA 0x02800280 +#define DDRSS0_PHY_373_DATA 0x02800280 +#define DDRSS0_PHY_374_DATA 0x02800280 +#define DDRSS0_PHY_375_DATA 0x02800280 +#define DDRSS0_PHY_376_DATA 0x00000280 +#define DDRSS0_PHY_377_DATA 0x0000A000 +#define DDRSS0_PHY_378_DATA 0x00A000A0 +#define DDRSS0_PHY_379_DATA 0x00A000A0 +#define DDRSS0_PHY_380_DATA 0x00A000A0 +#define DDRSS0_PHY_381_DATA 0x00A000A0 +#define DDRSS0_PHY_382_DATA 0x00A000A0 +#define DDRSS0_PHY_383_DATA 0x00A000A0 +#define DDRSS0_PHY_384_DATA 0x00A000A0 +#define DDRSS0_PHY_385_DATA 0x00A000A0 +#define DDRSS0_PHY_386_DATA 0x01C200A0 +#define DDRSS0_PHY_387_DATA 0x01A00005 +#define DDRSS0_PHY_388_DATA 0x00000000 +#define DDRSS0_PHY_389_DATA 0x00000000 +#define DDRSS0_PHY_390_DATA 0x00080200 +#define DDRSS0_PHY_391_DATA 0x00000000 +#define DDRSS0_PHY_392_DATA 0x20202000 +#define DDRSS0_PHY_393_DATA 0x20202020 +#define DDRSS0_PHY_394_DATA 0xF0F02020 +#define DDRSS0_PHY_395_DATA 0x00000000 +#define DDRSS0_PHY_396_DATA 0x00000000 +#define DDRSS0_PHY_397_DATA 0x00000000 +#define DDRSS0_PHY_398_DATA 0x00000000 +#define DDRSS0_PHY_399_DATA 0x00000000 +#define DDRSS0_PHY_400_DATA 0x00000000 +#define DDRSS0_PHY_401_DATA 0x00000000 +#define DDRSS0_PHY_402_DATA 0x00000000 +#define DDRSS0_PHY_403_DATA 0x00000000 +#define DDRSS0_PHY_404_DATA 0x00000000 +#define DDRSS0_PHY_405_DATA 0x00000000 +#define DDRSS0_PHY_406_DATA 0x00000000 +#define DDRSS0_PHY_407_DATA 0x00000000 +#define DDRSS0_PHY_408_DATA 0x00000000 +#define DDRSS0_PHY_409_DATA 0x00000000 +#define DDRSS0_PHY_410_DATA 0x00000000 +#define DDRSS0_PHY_411_DATA 0x00000000 +#define DDRSS0_PHY_412_DATA 0x00000000 +#define DDRSS0_PHY_413_DATA 0x00000000 +#define DDRSS0_PHY_414_DATA 0x00000000 +#define DDRSS0_PHY_415_DATA 0x00000000 +#define DDRSS0_PHY_416_DATA 0x00000000 +#define DDRSS0_PHY_417_DATA 0x00000000 +#define DDRSS0_PHY_418_DATA 0x00000000 +#define DDRSS0_PHY_419_DATA 0x00000000 +#define DDRSS0_PHY_420_DATA 0x00000000 +#define DDRSS0_PHY_421_DATA 0x00000000 +#define DDRSS0_PHY_422_DATA 0x00000000 +#define DDRSS0_PHY_423_DATA 0x00000000 +#define DDRSS0_PHY_424_DATA 0x00000000 +#define DDRSS0_PHY_425_DATA 0x00000000 +#define DDRSS0_PHY_426_DATA 0x00000000 +#define DDRSS0_PHY_427_DATA 0x00000000 +#define DDRSS0_PHY_428_DATA 0x00000000 +#define DDRSS0_PHY_429_DATA 0x00000000 +#define DDRSS0_PHY_430_DATA 0x00000000 +#define DDRSS0_PHY_431_DATA 0x00000000 +#define DDRSS0_PHY_432_DATA 0x00000000 +#define DDRSS0_PHY_433_DATA 0x00000000 +#define DDRSS0_PHY_434_DATA 0x00000000 +#define DDRSS0_PHY_435_DATA 0x00000000 +#define DDRSS0_PHY_436_DATA 0x00000000 +#define DDRSS0_PHY_437_DATA 0x00000000 +#define DDRSS0_PHY_438_DATA 0x00000000 +#define DDRSS0_PHY_439_DATA 0x00000000 +#define DDRSS0_PHY_440_DATA 0x00000000 +#define DDRSS0_PHY_441_DATA 0x00000000 +#define DDRSS0_PHY_442_DATA 0x00000000 +#define DDRSS0_PHY_443_DATA 0x00000000 +#define DDRSS0_PHY_444_DATA 0x00000000 +#define DDRSS0_PHY_445_DATA 0x00000000 +#define DDRSS0_PHY_446_DATA 0x00000000 +#define DDRSS0_PHY_447_DATA 0x00000000 +#define DDRSS0_PHY_448_DATA 0x00000000 +#define DDRSS0_PHY_449_DATA 0x00000000 +#define DDRSS0_PHY_450_DATA 0x00000000 +#define DDRSS0_PHY_451_DATA 0x00000000 +#define DDRSS0_PHY_452_DATA 0x00000000 +#define DDRSS0_PHY_453_DATA 0x00000000 +#define DDRSS0_PHY_454_DATA 0x00000000 +#define DDRSS0_PHY_455_DATA 0x00000000 +#define DDRSS0_PHY_456_DATA 0x00000000 +#define DDRSS0_PHY_457_DATA 0x00000000 +#define DDRSS0_PHY_458_DATA 0x00000000 +#define DDRSS0_PHY_459_DATA 0x00000000 +#define DDRSS0_PHY_460_DATA 0x00000000 +#define DDRSS0_PHY_461_DATA 0x00000000 +#define DDRSS0_PHY_462_DATA 0x00000000 +#define DDRSS0_PHY_463_DATA 0x00000000 +#define DDRSS0_PHY_464_DATA 0x00000000 +#define DDRSS0_PHY_465_DATA 0x00000000 +#define DDRSS0_PHY_466_DATA 0x00000000 +#define DDRSS0_PHY_467_DATA 0x00000000 +#define DDRSS0_PHY_468_DATA 0x00000000 +#define DDRSS0_PHY_469_DATA 0x00000000 +#define DDRSS0_PHY_470_DATA 0x00000000 +#define DDRSS0_PHY_471_DATA 0x00000000 +#define DDRSS0_PHY_472_DATA 0x00000000 +#define DDRSS0_PHY_473_DATA 0x00000000 +#define DDRSS0_PHY_474_DATA 0x00000000 +#define DDRSS0_PHY_475_DATA 0x00000000 +#define DDRSS0_PHY_476_DATA 0x00000000 +#define DDRSS0_PHY_477_DATA 0x00000000 +#define DDRSS0_PHY_478_DATA 0x00000000 +#define DDRSS0_PHY_479_DATA 0x00000000 +#define DDRSS0_PHY_480_DATA 0x00000000 +#define DDRSS0_PHY_481_DATA 0x00000000 +#define DDRSS0_PHY_482_DATA 0x00000000 +#define DDRSS0_PHY_483_DATA 0x00000000 +#define DDRSS0_PHY_484_DATA 0x00000000 +#define DDRSS0_PHY_485_DATA 0x00000000 +#define DDRSS0_PHY_486_DATA 0x00000000 +#define DDRSS0_PHY_487_DATA 0x00000000 +#define DDRSS0_PHY_488_DATA 0x00000000 +#define DDRSS0_PHY_489_DATA 0x00000000 +#define DDRSS0_PHY_490_DATA 0x00000000 +#define DDRSS0_PHY_491_DATA 0x00000000 +#define DDRSS0_PHY_492_DATA 0x00000000 +#define DDRSS0_PHY_493_DATA 0x00000000 +#define DDRSS0_PHY_494_DATA 0x00000000 +#define DDRSS0_PHY_495_DATA 0x00000000 +#define DDRSS0_PHY_496_DATA 0x00000000 +#define DDRSS0_PHY_497_DATA 0x00000000 +#define DDRSS0_PHY_498_DATA 0x00000000 +#define DDRSS0_PHY_499_DATA 0x00000000 +#define DDRSS0_PHY_500_DATA 0x00000000 +#define DDRSS0_PHY_501_DATA 0x00000000 +#define DDRSS0_PHY_502_DATA 0x00000000 +#define DDRSS0_PHY_503_DATA 0x00000000 +#define DDRSS0_PHY_504_DATA 0x00000000 +#define DDRSS0_PHY_505_DATA 0x00000000 +#define DDRSS0_PHY_506_DATA 0x00000000 +#define DDRSS0_PHY_507_DATA 0x00000000 +#define DDRSS0_PHY_508_DATA 0x00000000 +#define DDRSS0_PHY_509_DATA 0x00000000 +#define DDRSS0_PHY_510_DATA 0x00000000 +#define DDRSS0_PHY_511_DATA 0x00000000 +#define DDRSS0_PHY_512_DATA 0x000004F0 +#define DDRSS0_PHY_513_DATA 0x00000000 +#define DDRSS0_PHY_514_DATA 0x00030200 +#define DDRSS0_PHY_515_DATA 0x00000000 +#define DDRSS0_PHY_516_DATA 0x00000000 +#define DDRSS0_PHY_517_DATA 0x01030000 +#define DDRSS0_PHY_518_DATA 0x00010000 +#define DDRSS0_PHY_519_DATA 0x01030004 +#define DDRSS0_PHY_520_DATA 0x01000000 +#define DDRSS0_PHY_521_DATA 0x00000000 +#define DDRSS0_PHY_522_DATA 0x00000000 +#define DDRSS0_PHY_523_DATA 0x01000001 +#define DDRSS0_PHY_524_DATA 0x00000200 +#define DDRSS0_PHY_525_DATA 0x000800C0 +#define DDRSS0_PHY_526_DATA 0x060100CC +#define DDRSS0_PHY_527_DATA 0x00030066 +#define DDRSS0_PHY_528_DATA 0x00000000 +#define DDRSS0_PHY_529_DATA 0x00000301 +#define DDRSS0_PHY_530_DATA 0x0000AAAA +#define DDRSS0_PHY_531_DATA 0x00005555 +#define DDRSS0_PHY_532_DATA 0x0000B5B5 +#define DDRSS0_PHY_533_DATA 0x00004A4A +#define DDRSS0_PHY_534_DATA 0x00005656 +#define DDRSS0_PHY_535_DATA 0x0000A9A9 +#define DDRSS0_PHY_536_DATA 0x0000A9A9 +#define DDRSS0_PHY_537_DATA 0x0000B5B5 +#define DDRSS0_PHY_538_DATA 0x00000000 +#define DDRSS0_PHY_539_DATA 0x00000000 +#define DDRSS0_PHY_540_DATA 0x2A000000 +#define DDRSS0_PHY_541_DATA 0x00000808 +#define DDRSS0_PHY_542_DATA 0x0F000000 +#define DDRSS0_PHY_543_DATA 0x00000F08 +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002006 +#define DDRSS0_PHY_546_DATA 0x00000000 +#define DDRSS0_PHY_547_DATA 0x00000000 +#define DDRSS0_PHY_548_DATA 0x55555555 +#define DDRSS0_PHY_549_DATA 0xAAAAAAAA +#define DDRSS0_PHY_550_DATA 0x55555555 +#define DDRSS0_PHY_551_DATA 0xAAAAAAAA +#define DDRSS0_PHY_552_DATA 0x00005555 +#define DDRSS0_PHY_553_DATA 0x01000100 +#define DDRSS0_PHY_554_DATA 0x00800180 +#define DDRSS0_PHY_555_DATA 0x00000001 +#define DDRSS0_PHY_556_DATA 0x00000000 +#define DDRSS0_PHY_557_DATA 0x00000000 +#define DDRSS0_PHY_558_DATA 0x00000000 +#define DDRSS0_PHY_559_DATA 0x00000000 +#define DDRSS0_PHY_560_DATA 0x00000000 +#define DDRSS0_PHY_561_DATA 0x00000000 +#define DDRSS0_PHY_562_DATA 0x00000000 +#define DDRSS0_PHY_563_DATA 0x00000000 +#define DDRSS0_PHY_564_DATA 0x00000000 +#define DDRSS0_PHY_565_DATA 0x00000000 +#define DDRSS0_PHY_566_DATA 0x00000000 +#define DDRSS0_PHY_567_DATA 0x00000000 +#define DDRSS0_PHY_568_DATA 0x00000000 +#define DDRSS0_PHY_569_DATA 0x00000000 +#define DDRSS0_PHY_570_DATA 0x00000000 +#define DDRSS0_PHY_571_DATA 0x00000000 +#define DDRSS0_PHY_572_DATA 0x00000000 +#define DDRSS0_PHY_573_DATA 0x00000000 +#define DDRSS0_PHY_574_DATA 0x00000000 +#define DDRSS0_PHY_575_DATA 0x00000000 +#define DDRSS0_PHY_576_DATA 0x00000000 +#define DDRSS0_PHY_577_DATA 0x00000000 +#define DDRSS0_PHY_578_DATA 0x00000104 +#define DDRSS0_PHY_579_DATA 0x00000120 +#define DDRSS0_PHY_580_DATA 0x00000000 +#define DDRSS0_PHY_581_DATA 0x00000000 +#define DDRSS0_PHY_582_DATA 0x00000000 +#define DDRSS0_PHY_583_DATA 0x00000000 +#define DDRSS0_PHY_584_DATA 0x00000000 +#define DDRSS0_PHY_585_DATA 0x00000000 +#define DDRSS0_PHY_586_DATA 0x00000000 +#define DDRSS0_PHY_587_DATA 0x00000001 +#define DDRSS0_PHY_588_DATA 0x07FF0000 +#define DDRSS0_PHY_589_DATA 0x0080081F +#define DDRSS0_PHY_590_DATA 0x00081020 +#define DDRSS0_PHY_591_DATA 0x04010000 +#define DDRSS0_PHY_592_DATA 0x00000000 +#define DDRSS0_PHY_593_DATA 0x00000000 +#define DDRSS0_PHY_594_DATA 0x00000000 +#define DDRSS0_PHY_595_DATA 0x00000100 +#define DDRSS0_PHY_596_DATA 0x01CC0C01 +#define DDRSS0_PHY_597_DATA 0x1003CC0C +#define DDRSS0_PHY_598_DATA 0x20000140 +#define DDRSS0_PHY_599_DATA 0x07FF0200 +#define DDRSS0_PHY_600_DATA 0x0000DD01 +#define DDRSS0_PHY_601_DATA 0x10100303 +#define DDRSS0_PHY_602_DATA 0x10101010 +#define DDRSS0_PHY_603_DATA 0x10101010 +#define DDRSS0_PHY_604_DATA 0x00021010 +#define DDRSS0_PHY_605_DATA 0x00100010 +#define DDRSS0_PHY_606_DATA 0x00100010 +#define DDRSS0_PHY_607_DATA 0x00100010 +#define DDRSS0_PHY_608_DATA 0x00100010 +#define DDRSS0_PHY_609_DATA 0x00050010 +#define DDRSS0_PHY_610_DATA 0x51517041 +#define DDRSS0_PHY_611_DATA 0x31C06001 +#define DDRSS0_PHY_612_DATA 0x07AB01AB +#define DDRSS0_PHY_613_DATA 0x00C0C001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 +#define DDRSS0_PHY_615_DATA 0x10001000 +#define DDRSS0_PHY_616_DATA 0x0C083E42 +#define DDRSS0_PHY_617_DATA 0x0F0C3701 +#define DDRSS0_PHY_618_DATA 0x01000140 +#define DDRSS0_PHY_619_DATA 0x0C000420 +#define DDRSS0_PHY_620_DATA 0x00000198 +#define DDRSS0_PHY_621_DATA 0x0A0000D0 +#define DDRSS0_PHY_622_DATA 0x00030200 +#define DDRSS0_PHY_623_DATA 0x02800000 +#define DDRSS0_PHY_624_DATA 0x80800000 +#define DDRSS0_PHY_625_DATA 0x000E2010 +#define DDRSS0_PHY_626_DATA 0x76543210 +#define DDRSS0_PHY_627_DATA 0x00000008 +#define DDRSS0_PHY_628_DATA 0x02800280 +#define DDRSS0_PHY_629_DATA 0x02800280 +#define DDRSS0_PHY_630_DATA 0x02800280 +#define DDRSS0_PHY_631_DATA 0x02800280 +#define DDRSS0_PHY_632_DATA 0x00000280 +#define DDRSS0_PHY_633_DATA 0x0000A000 +#define DDRSS0_PHY_634_DATA 0x00A000A0 +#define DDRSS0_PHY_635_DATA 0x00A000A0 +#define DDRSS0_PHY_636_DATA 0x00A000A0 +#define DDRSS0_PHY_637_DATA 0x00A000A0 +#define DDRSS0_PHY_638_DATA 0x00A000A0 +#define DDRSS0_PHY_639_DATA 0x00A000A0 +#define DDRSS0_PHY_640_DATA 0x00A000A0 +#define DDRSS0_PHY_641_DATA 0x00A000A0 +#define DDRSS0_PHY_642_DATA 0x01C200A0 +#define DDRSS0_PHY_643_DATA 0x01A00005 +#define DDRSS0_PHY_644_DATA 0x00000000 +#define DDRSS0_PHY_645_DATA 0x00000000 +#define DDRSS0_PHY_646_DATA 0x00080200 +#define DDRSS0_PHY_647_DATA 0x00000000 +#define DDRSS0_PHY_648_DATA 0x20202000 +#define DDRSS0_PHY_649_DATA 0x20202020 +#define DDRSS0_PHY_650_DATA 0xF0F02020 +#define DDRSS0_PHY_651_DATA 0x00000000 +#define DDRSS0_PHY_652_DATA 0x00000000 +#define DDRSS0_PHY_653_DATA 0x00000000 +#define DDRSS0_PHY_654_DATA 0x00000000 +#define DDRSS0_PHY_655_DATA 0x00000000 +#define DDRSS0_PHY_656_DATA 0x00000000 +#define DDRSS0_PHY_657_DATA 0x00000000 +#define DDRSS0_PHY_658_DATA 0x00000000 +#define DDRSS0_PHY_659_DATA 0x00000000 +#define DDRSS0_PHY_660_DATA 0x00000000 +#define DDRSS0_PHY_661_DATA 0x00000000 +#define DDRSS0_PHY_662_DATA 0x00000000 +#define DDRSS0_PHY_663_DATA 0x00000000 +#define DDRSS0_PHY_664_DATA 0x00000000 +#define DDRSS0_PHY_665_DATA 0x00000000 +#define DDRSS0_PHY_666_DATA 0x00000000 +#define DDRSS0_PHY_667_DATA 0x00000000 +#define DDRSS0_PHY_668_DATA 0x00000000 +#define DDRSS0_PHY_669_DATA 0x00000000 +#define DDRSS0_PHY_670_DATA 0x00000000 +#define DDRSS0_PHY_671_DATA 0x00000000 +#define DDRSS0_PHY_672_DATA 0x00000000 +#define DDRSS0_PHY_673_DATA 0x00000000 +#define DDRSS0_PHY_674_DATA 0x00000000 +#define DDRSS0_PHY_675_DATA 0x00000000 +#define DDRSS0_PHY_676_DATA 0x00000000 +#define DDRSS0_PHY_677_DATA 0x00000000 +#define DDRSS0_PHY_678_DATA 0x00000000 +#define DDRSS0_PHY_679_DATA 0x00000000 +#define DDRSS0_PHY_680_DATA 0x00000000 +#define DDRSS0_PHY_681_DATA 0x00000000 +#define DDRSS0_PHY_682_DATA 0x00000000 +#define DDRSS0_PHY_683_DATA 0x00000000 +#define DDRSS0_PHY_684_DATA 0x00000000 +#define DDRSS0_PHY_685_DATA 0x00000000 +#define DDRSS0_PHY_686_DATA 0x00000000 +#define DDRSS0_PHY_687_DATA 0x00000000 +#define DDRSS0_PHY_688_DATA 0x00000000 +#define DDRSS0_PHY_689_DATA 0x00000000 +#define DDRSS0_PHY_690_DATA 0x00000000 +#define DDRSS0_PHY_691_DATA 0x00000000 +#define DDRSS0_PHY_692_DATA 0x00000000 +#define DDRSS0_PHY_693_DATA 0x00000000 +#define DDRSS0_PHY_694_DATA 0x00000000 +#define DDRSS0_PHY_695_DATA 0x00000000 +#define DDRSS0_PHY_696_DATA 0x00000000 +#define DDRSS0_PHY_697_DATA 0x00000000 +#define DDRSS0_PHY_698_DATA 0x00000000 +#define DDRSS0_PHY_699_DATA 0x00000000 +#define DDRSS0_PHY_700_DATA 0x00000000 +#define DDRSS0_PHY_701_DATA 0x00000000 +#define DDRSS0_PHY_702_DATA 0x00000000 +#define DDRSS0_PHY_703_DATA 0x00000000 +#define DDRSS0_PHY_704_DATA 0x00000000 +#define DDRSS0_PHY_705_DATA 0x00000000 +#define DDRSS0_PHY_706_DATA 0x00000000 +#define DDRSS0_PHY_707_DATA 0x00000000 +#define DDRSS0_PHY_708_DATA 0x00000000 +#define DDRSS0_PHY_709_DATA 0x00000000 +#define DDRSS0_PHY_710_DATA 0x00000000 +#define DDRSS0_PHY_711_DATA 0x00000000 +#define DDRSS0_PHY_712_DATA 0x00000000 +#define DDRSS0_PHY_713_DATA 0x00000000 +#define DDRSS0_PHY_714_DATA 0x00000000 +#define DDRSS0_PHY_715_DATA 0x00000000 +#define DDRSS0_PHY_716_DATA 0x00000000 +#define DDRSS0_PHY_717_DATA 0x00000000 +#define DDRSS0_PHY_718_DATA 0x00000000 +#define DDRSS0_PHY_719_DATA 0x00000000 +#define DDRSS0_PHY_720_DATA 0x00000000 +#define DDRSS0_PHY_721_DATA 0x00000000 +#define DDRSS0_PHY_722_DATA 0x00000000 +#define DDRSS0_PHY_723_DATA 0x00000000 +#define DDRSS0_PHY_724_DATA 0x00000000 +#define DDRSS0_PHY_725_DATA 0x00000000 +#define DDRSS0_PHY_726_DATA 0x00000000 +#define DDRSS0_PHY_727_DATA 0x00000000 +#define DDRSS0_PHY_728_DATA 0x00000000 +#define DDRSS0_PHY_729_DATA 0x00000000 +#define DDRSS0_PHY_730_DATA 0x00000000 +#define DDRSS0_PHY_731_DATA 0x00000000 +#define DDRSS0_PHY_732_DATA 0x00000000 +#define DDRSS0_PHY_733_DATA 0x00000000 +#define DDRSS0_PHY_734_DATA 0x00000000 +#define DDRSS0_PHY_735_DATA 0x00000000 +#define DDRSS0_PHY_736_DATA 0x00000000 +#define DDRSS0_PHY_737_DATA 0x00000000 +#define DDRSS0_PHY_738_DATA 0x00000000 +#define DDRSS0_PHY_739_DATA 0x00000000 +#define DDRSS0_PHY_740_DATA 0x00000000 +#define DDRSS0_PHY_741_DATA 0x00000000 +#define DDRSS0_PHY_742_DATA 0x00000000 +#define DDRSS0_PHY_743_DATA 0x00000000 +#define DDRSS0_PHY_744_DATA 0x00000000 +#define DDRSS0_PHY_745_DATA 0x00000000 +#define DDRSS0_PHY_746_DATA 0x00000000 +#define DDRSS0_PHY_747_DATA 0x00000000 +#define DDRSS0_PHY_748_DATA 0x00000000 +#define DDRSS0_PHY_749_DATA 0x00000000 +#define DDRSS0_PHY_750_DATA 0x00000000 +#define DDRSS0_PHY_751_DATA 0x00000000 +#define DDRSS0_PHY_752_DATA 0x00000000 +#define DDRSS0_PHY_753_DATA 0x00000000 +#define DDRSS0_PHY_754_DATA 0x00000000 +#define DDRSS0_PHY_755_DATA 0x00000000 +#define DDRSS0_PHY_756_DATA 0x00000000 +#define DDRSS0_PHY_757_DATA 0x00000000 +#define DDRSS0_PHY_758_DATA 0x00000000 +#define DDRSS0_PHY_759_DATA 0x00000000 +#define DDRSS0_PHY_760_DATA 0x00000000 +#define DDRSS0_PHY_761_DATA 0x00000000 +#define DDRSS0_PHY_762_DATA 0x00000000 +#define DDRSS0_PHY_763_DATA 0x00000000 +#define DDRSS0_PHY_764_DATA 0x00000000 +#define DDRSS0_PHY_765_DATA 0x00000000 +#define DDRSS0_PHY_766_DATA 0x00000000 +#define DDRSS0_PHY_767_DATA 0x00000000 +#define DDRSS0_PHY_768_DATA 0x000004F0 +#define DDRSS0_PHY_769_DATA 0x00000000 +#define DDRSS0_PHY_770_DATA 0x00030200 +#define DDRSS0_PHY_771_DATA 0x00000000 +#define DDRSS0_PHY_772_DATA 0x00000000 +#define DDRSS0_PHY_773_DATA 0x01030000 +#define DDRSS0_PHY_774_DATA 0x00010000 +#define DDRSS0_PHY_775_DATA 0x01030004 +#define DDRSS0_PHY_776_DATA 0x01000000 +#define DDRSS0_PHY_777_DATA 0x00000000 +#define DDRSS0_PHY_778_DATA 0x00000000 +#define DDRSS0_PHY_779_DATA 0x01000001 +#define DDRSS0_PHY_780_DATA 0x00000200 +#define DDRSS0_PHY_781_DATA 0x000800C0 +#define DDRSS0_PHY_782_DATA 0x060100CC +#define DDRSS0_PHY_783_DATA 0x00030066 +#define DDRSS0_PHY_784_DATA 0x00000000 +#define DDRSS0_PHY_785_DATA 0x00000301 +#define DDRSS0_PHY_786_DATA 0x0000AAAA +#define DDRSS0_PHY_787_DATA 0x00005555 +#define DDRSS0_PHY_788_DATA 0x0000B5B5 +#define DDRSS0_PHY_789_DATA 0x00004A4A +#define DDRSS0_PHY_790_DATA 0x00005656 +#define DDRSS0_PHY_791_DATA 0x0000A9A9 +#define DDRSS0_PHY_792_DATA 0x0000A9A9 +#define DDRSS0_PHY_793_DATA 0x0000B5B5 +#define DDRSS0_PHY_794_DATA 0x00000000 +#define DDRSS0_PHY_795_DATA 0x00000000 +#define DDRSS0_PHY_796_DATA 0x2A000000 +#define DDRSS0_PHY_797_DATA 0x00000808 +#define DDRSS0_PHY_798_DATA 0x0F000000 +#define DDRSS0_PHY_799_DATA 0x00000F08 +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002006 +#define DDRSS0_PHY_802_DATA 0x00000000 +#define DDRSS0_PHY_803_DATA 0x00000000 +#define DDRSS0_PHY_804_DATA 0x55555555 +#define DDRSS0_PHY_805_DATA 0xAAAAAAAA +#define DDRSS0_PHY_806_DATA 0x55555555 +#define DDRSS0_PHY_807_DATA 0xAAAAAAAA +#define DDRSS0_PHY_808_DATA 0x00005555 +#define DDRSS0_PHY_809_DATA 0x01000100 +#define DDRSS0_PHY_810_DATA 0x00800180 +#define DDRSS0_PHY_811_DATA 0x00000000 +#define DDRSS0_PHY_812_DATA 0x00000000 +#define DDRSS0_PHY_813_DATA 0x00000000 +#define DDRSS0_PHY_814_DATA 0x00000000 +#define DDRSS0_PHY_815_DATA 0x00000000 +#define DDRSS0_PHY_816_DATA 0x00000000 +#define DDRSS0_PHY_817_DATA 0x00000000 +#define DDRSS0_PHY_818_DATA 0x00000000 +#define DDRSS0_PHY_819_DATA 0x00000000 +#define DDRSS0_PHY_820_DATA 0x00000000 +#define DDRSS0_PHY_821_DATA 0x00000000 +#define DDRSS0_PHY_822_DATA 0x00000000 +#define DDRSS0_PHY_823_DATA 0x00000000 +#define DDRSS0_PHY_824_DATA 0x00000000 +#define DDRSS0_PHY_825_DATA 0x00000000 +#define DDRSS0_PHY_826_DATA 0x00000000 +#define DDRSS0_PHY_827_DATA 0x00000000 +#define DDRSS0_PHY_828_DATA 0x00000000 +#define DDRSS0_PHY_829_DATA 0x00000000 +#define DDRSS0_PHY_830_DATA 0x00000000 +#define DDRSS0_PHY_831_DATA 0x00000000 +#define DDRSS0_PHY_832_DATA 0x00000000 +#define DDRSS0_PHY_833_DATA 0x00000000 +#define DDRSS0_PHY_834_DATA 0x00000104 +#define DDRSS0_PHY_835_DATA 0x00000120 +#define DDRSS0_PHY_836_DATA 0x00000000 +#define DDRSS0_PHY_837_DATA 0x00000000 +#define DDRSS0_PHY_838_DATA 0x00000000 +#define DDRSS0_PHY_839_DATA 0x00000000 +#define DDRSS0_PHY_840_DATA 0x00000000 +#define DDRSS0_PHY_841_DATA 0x00000000 +#define DDRSS0_PHY_842_DATA 0x00000000 +#define DDRSS0_PHY_843_DATA 0x00000001 +#define DDRSS0_PHY_844_DATA 0x07FF0000 +#define DDRSS0_PHY_845_DATA 0x0080081F +#define DDRSS0_PHY_846_DATA 0x00081020 +#define DDRSS0_PHY_847_DATA 0x04010000 +#define DDRSS0_PHY_848_DATA 0x00000000 +#define DDRSS0_PHY_849_DATA 0x00000000 +#define DDRSS0_PHY_850_DATA 0x00000000 +#define DDRSS0_PHY_851_DATA 0x00000100 +#define DDRSS0_PHY_852_DATA 0x01CC0C01 +#define DDRSS0_PHY_853_DATA 0x1003CC0C +#define DDRSS0_PHY_854_DATA 0x20000140 +#define DDRSS0_PHY_855_DATA 0x07FF0200 +#define DDRSS0_PHY_856_DATA 0x0000DD01 +#define DDRSS0_PHY_857_DATA 0x10100303 +#define DDRSS0_PHY_858_DATA 0x10101010 +#define DDRSS0_PHY_859_DATA 0x10101010 +#define DDRSS0_PHY_860_DATA 0x00021010 +#define DDRSS0_PHY_861_DATA 0x00100010 +#define DDRSS0_PHY_862_DATA 0x00100010 +#define DDRSS0_PHY_863_DATA 0x00100010 +#define DDRSS0_PHY_864_DATA 0x00100010 +#define DDRSS0_PHY_865_DATA 0x00050010 +#define DDRSS0_PHY_866_DATA 0x51517041 +#define DDRSS0_PHY_867_DATA 0x31C06001 +#define DDRSS0_PHY_868_DATA 0x07AB01AB +#define DDRSS0_PHY_869_DATA 0x00C0C001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 +#define DDRSS0_PHY_871_DATA 0x10001000 +#define DDRSS0_PHY_872_DATA 0x0C083E42 +#define DDRSS0_PHY_873_DATA 0x0F0C3701 +#define DDRSS0_PHY_874_DATA 0x01000140 +#define DDRSS0_PHY_875_DATA 0x0C000420 +#define DDRSS0_PHY_876_DATA 0x00000198 +#define DDRSS0_PHY_877_DATA 0x0A0000D0 +#define DDRSS0_PHY_878_DATA 0x00030200 +#define DDRSS0_PHY_879_DATA 0x02800000 +#define DDRSS0_PHY_880_DATA 0x80800000 +#define DDRSS0_PHY_881_DATA 0x000E2010 +#define DDRSS0_PHY_882_DATA 0x76543210 +#define DDRSS0_PHY_883_DATA 0x00000008 +#define DDRSS0_PHY_884_DATA 0x02800280 +#define DDRSS0_PHY_885_DATA 0x02800280 +#define DDRSS0_PHY_886_DATA 0x02800280 +#define DDRSS0_PHY_887_DATA 0x02800280 +#define DDRSS0_PHY_888_DATA 0x00000280 +#define DDRSS0_PHY_889_DATA 0x0000A000 +#define DDRSS0_PHY_890_DATA 0x00A000A0 +#define DDRSS0_PHY_891_DATA 0x00A000A0 +#define DDRSS0_PHY_892_DATA 0x00A000A0 +#define DDRSS0_PHY_893_DATA 0x00A000A0 +#define DDRSS0_PHY_894_DATA 0x00A000A0 +#define DDRSS0_PHY_895_DATA 0x00A000A0 +#define DDRSS0_PHY_896_DATA 0x00A000A0 +#define DDRSS0_PHY_897_DATA 0x00A000A0 +#define DDRSS0_PHY_898_DATA 0x01C200A0 +#define DDRSS0_PHY_899_DATA 0x01A00005 +#define DDRSS0_PHY_900_DATA 0x00000000 +#define DDRSS0_PHY_901_DATA 0x00000000 +#define DDRSS0_PHY_902_DATA 0x00080200 +#define DDRSS0_PHY_903_DATA 0x00000000 +#define DDRSS0_PHY_904_DATA 0x20202000 +#define DDRSS0_PHY_905_DATA 0x20202020 +#define DDRSS0_PHY_906_DATA 0xF0F02020 +#define DDRSS0_PHY_907_DATA 0x00000000 +#define DDRSS0_PHY_908_DATA 0x00000000 +#define DDRSS0_PHY_909_DATA 0x00000000 +#define DDRSS0_PHY_910_DATA 0x00000000 +#define DDRSS0_PHY_911_DATA 0x00000000 +#define DDRSS0_PHY_912_DATA 0x00000000 +#define DDRSS0_PHY_913_DATA 0x00000000 +#define DDRSS0_PHY_914_DATA 0x00000000 +#define DDRSS0_PHY_915_DATA 0x00000000 +#define DDRSS0_PHY_916_DATA 0x00000000 +#define DDRSS0_PHY_917_DATA 0x00000000 +#define DDRSS0_PHY_918_DATA 0x00000000 +#define DDRSS0_PHY_919_DATA 0x00000000 +#define DDRSS0_PHY_920_DATA 0x00000000 +#define DDRSS0_PHY_921_DATA 0x00000000 +#define DDRSS0_PHY_922_DATA 0x00000000 +#define DDRSS0_PHY_923_DATA 0x00000000 +#define DDRSS0_PHY_924_DATA 0x00000000 +#define DDRSS0_PHY_925_DATA 0x00000000 +#define DDRSS0_PHY_926_DATA 0x00000000 +#define DDRSS0_PHY_927_DATA 0x00000000 +#define DDRSS0_PHY_928_DATA 0x00000000 +#define DDRSS0_PHY_929_DATA 0x00000000 +#define DDRSS0_PHY_930_DATA 0x00000000 +#define DDRSS0_PHY_931_DATA 0x00000000 +#define DDRSS0_PHY_932_DATA 0x00000000 +#define DDRSS0_PHY_933_DATA 0x00000000 +#define DDRSS0_PHY_934_DATA 0x00000000 +#define DDRSS0_PHY_935_DATA 0x00000000 +#define DDRSS0_PHY_936_DATA 0x00000000 +#define DDRSS0_PHY_937_DATA 0x00000000 +#define DDRSS0_PHY_938_DATA 0x00000000 +#define DDRSS0_PHY_939_DATA 0x00000000 +#define DDRSS0_PHY_940_DATA 0x00000000 +#define DDRSS0_PHY_941_DATA 0x00000000 +#define DDRSS0_PHY_942_DATA 0x00000000 +#define DDRSS0_PHY_943_DATA 0x00000000 +#define DDRSS0_PHY_944_DATA 0x00000000 +#define DDRSS0_PHY_945_DATA 0x00000000 +#define DDRSS0_PHY_946_DATA 0x00000000 +#define DDRSS0_PHY_947_DATA 0x00000000 +#define DDRSS0_PHY_948_DATA 0x00000000 +#define DDRSS0_PHY_949_DATA 0x00000000 +#define DDRSS0_PHY_950_DATA 0x00000000 +#define DDRSS0_PHY_951_DATA 0x00000000 +#define DDRSS0_PHY_952_DATA 0x00000000 +#define DDRSS0_PHY_953_DATA 0x00000000 +#define DDRSS0_PHY_954_DATA 0x00000000 +#define DDRSS0_PHY_955_DATA 0x00000000 +#define DDRSS0_PHY_956_DATA 0x00000000 +#define DDRSS0_PHY_957_DATA 0x00000000 +#define DDRSS0_PHY_958_DATA 0x00000000 +#define DDRSS0_PHY_959_DATA 0x00000000 +#define DDRSS0_PHY_960_DATA 0x00000000 +#define DDRSS0_PHY_961_DATA 0x00000000 +#define DDRSS0_PHY_962_DATA 0x00000000 +#define DDRSS0_PHY_963_DATA 0x00000000 +#define DDRSS0_PHY_964_DATA 0x00000000 +#define DDRSS0_PHY_965_DATA 0x00000000 +#define DDRSS0_PHY_966_DATA 0x00000000 +#define DDRSS0_PHY_967_DATA 0x00000000 +#define DDRSS0_PHY_968_DATA 0x00000000 +#define DDRSS0_PHY_969_DATA 0x00000000 +#define DDRSS0_PHY_970_DATA 0x00000000 +#define DDRSS0_PHY_971_DATA 0x00000000 +#define DDRSS0_PHY_972_DATA 0x00000000 +#define DDRSS0_PHY_973_DATA 0x00000000 +#define DDRSS0_PHY_974_DATA 0x00000000 +#define DDRSS0_PHY_975_DATA 0x00000000 +#define DDRSS0_PHY_976_DATA 0x00000000 +#define DDRSS0_PHY_977_DATA 0x00000000 +#define DDRSS0_PHY_978_DATA 0x00000000 +#define DDRSS0_PHY_979_DATA 0x00000000 +#define DDRSS0_PHY_980_DATA 0x00000000 +#define DDRSS0_PHY_981_DATA 0x00000000 +#define DDRSS0_PHY_982_DATA 0x00000000 +#define DDRSS0_PHY_983_DATA 0x00000000 +#define DDRSS0_PHY_984_DATA 0x00000000 +#define DDRSS0_PHY_985_DATA 0x00000000 +#define DDRSS0_PHY_986_DATA 0x00000000 +#define DDRSS0_PHY_987_DATA 0x00000000 +#define DDRSS0_PHY_988_DATA 0x00000000 +#define DDRSS0_PHY_989_DATA 0x00000000 +#define DDRSS0_PHY_990_DATA 0x00000000 +#define DDRSS0_PHY_991_DATA 0x00000000 +#define DDRSS0_PHY_992_DATA 0x00000000 +#define DDRSS0_PHY_993_DATA 0x00000000 +#define DDRSS0_PHY_994_DATA 0x00000000 +#define DDRSS0_PHY_995_DATA 0x00000000 +#define DDRSS0_PHY_996_DATA 0x00000000 +#define DDRSS0_PHY_997_DATA 0x00000000 +#define DDRSS0_PHY_998_DATA 0x00000000 +#define DDRSS0_PHY_999_DATA 0x00000000 +#define DDRSS0_PHY_1000_DATA 0x00000000 +#define DDRSS0_PHY_1001_DATA 0x00000000 +#define DDRSS0_PHY_1002_DATA 0x00000000 +#define DDRSS0_PHY_1003_DATA 0x00000000 +#define DDRSS0_PHY_1004_DATA 0x00000000 +#define DDRSS0_PHY_1005_DATA 0x00000000 +#define DDRSS0_PHY_1006_DATA 0x00000000 +#define DDRSS0_PHY_1007_DATA 0x00000000 +#define DDRSS0_PHY_1008_DATA 0x00000000 +#define DDRSS0_PHY_1009_DATA 0x00000000 +#define DDRSS0_PHY_1010_DATA 0x00000000 +#define DDRSS0_PHY_1011_DATA 0x00000000 +#define DDRSS0_PHY_1012_DATA 0x00000000 +#define DDRSS0_PHY_1013_DATA 0x00000000 +#define DDRSS0_PHY_1014_DATA 0x00000000 +#define DDRSS0_PHY_1015_DATA 0x00000000 +#define DDRSS0_PHY_1016_DATA 0x00000000 +#define DDRSS0_PHY_1017_DATA 0x00000000 +#define DDRSS0_PHY_1018_DATA 0x00000000 +#define DDRSS0_PHY_1019_DATA 0x00000000 +#define DDRSS0_PHY_1020_DATA 0x00000000 +#define DDRSS0_PHY_1021_DATA 0x00000000 +#define DDRSS0_PHY_1022_DATA 0x00000000 +#define DDRSS0_PHY_1023_DATA 0x00000000 +#define DDRSS0_PHY_1024_DATA 0x00000000 +#define DDRSS0_PHY_1025_DATA 0x00000000 +#define DDRSS0_PHY_1026_DATA 0x00000000 +#define DDRSS0_PHY_1027_DATA 0x00000000 +#define DDRSS0_PHY_1028_DATA 0x00000000 +#define DDRSS0_PHY_1029_DATA 0x00000100 +#define DDRSS0_PHY_1030_DATA 0x00000200 +#define DDRSS0_PHY_1031_DATA 0x00000000 +#define DDRSS0_PHY_1032_DATA 0x00000000 +#define DDRSS0_PHY_1033_DATA 0x00000000 +#define DDRSS0_PHY_1034_DATA 0x00000000 +#define DDRSS0_PHY_1035_DATA 0x00400000 +#define DDRSS0_PHY_1036_DATA 0x00000080 +#define DDRSS0_PHY_1037_DATA 0x00DCBA98 +#define DDRSS0_PHY_1038_DATA 0x03000000 +#define DDRSS0_PHY_1039_DATA 0x00200000 +#define DDRSS0_PHY_1040_DATA 0x00000000 +#define DDRSS0_PHY_1041_DATA 0x00000000 +#define DDRSS0_PHY_1042_DATA 0x00000000 +#define DDRSS0_PHY_1043_DATA 0x00000000 +#define DDRSS0_PHY_1044_DATA 0x00000000 +#define DDRSS0_PHY_1045_DATA 0x0000002A +#define DDRSS0_PHY_1046_DATA 0x00000015 +#define DDRSS0_PHY_1047_DATA 0x00000015 +#define DDRSS0_PHY_1048_DATA 0x0000002A +#define DDRSS0_PHY_1049_DATA 0x00000033 +#define DDRSS0_PHY_1050_DATA 0x0000000C +#define DDRSS0_PHY_1051_DATA 0x0000000C +#define DDRSS0_PHY_1052_DATA 0x00000033 +#define DDRSS0_PHY_1053_DATA 0x00543210 +#define DDRSS0_PHY_1054_DATA 0x003F0000 +#define DDRSS0_PHY_1055_DATA 0x000F3F3F +#define DDRSS0_PHY_1056_DATA 0x20202003 +#define DDRSS0_PHY_1057_DATA 0x00202020 +#define DDRSS0_PHY_1058_DATA 0x20008008 +#define DDRSS0_PHY_1059_DATA 0x00000810 +#define DDRSS0_PHY_1060_DATA 0x00000F00 +#define DDRSS0_PHY_1061_DATA 0x00000000 +#define DDRSS0_PHY_1062_DATA 0x00000000 +#define DDRSS0_PHY_1063_DATA 0x00000000 +#define DDRSS0_PHY_1064_DATA 0x000305CC +#define DDRSS0_PHY_1065_DATA 0x00030000 +#define DDRSS0_PHY_1066_DATA 0x00000300 +#define DDRSS0_PHY_1067_DATA 0x00000300 +#define DDRSS0_PHY_1068_DATA 0x00000300 +#define DDRSS0_PHY_1069_DATA 0x00000300 +#define DDRSS0_PHY_1070_DATA 0x00000300 +#define DDRSS0_PHY_1071_DATA 0x42080010 +#define DDRSS0_PHY_1072_DATA 0x0000803E +#define DDRSS0_PHY_1073_DATA 0x00000001 +#define DDRSS0_PHY_1074_DATA 0x01000102 +#define DDRSS0_PHY_1075_DATA 0x00008000 +#define DDRSS0_PHY_1076_DATA 0x00000000 +#define DDRSS0_PHY_1077_DATA 0x00000000 +#define DDRSS0_PHY_1078_DATA 0x00000000 +#define DDRSS0_PHY_1079_DATA 0x00000000 +#define DDRSS0_PHY_1080_DATA 0x00000000 +#define DDRSS0_PHY_1081_DATA 0x00000000 +#define DDRSS0_PHY_1082_DATA 0x00000000 +#define DDRSS0_PHY_1083_DATA 0x00000000 +#define DDRSS0_PHY_1084_DATA 0x00000000 +#define DDRSS0_PHY_1085_DATA 0x00000000 +#define DDRSS0_PHY_1086_DATA 0x00000000 +#define DDRSS0_PHY_1087_DATA 0x00000000 +#define DDRSS0_PHY_1088_DATA 0x00000000 +#define DDRSS0_PHY_1089_DATA 0x00000000 +#define DDRSS0_PHY_1090_DATA 0x00000000 +#define DDRSS0_PHY_1091_DATA 0x00000000 +#define DDRSS0_PHY_1092_DATA 0x00000000 +#define DDRSS0_PHY_1093_DATA 0x00000000 +#define DDRSS0_PHY_1094_DATA 0x00000000 +#define DDRSS0_PHY_1095_DATA 0x00000000 +#define DDRSS0_PHY_1096_DATA 0x00000000 +#define DDRSS0_PHY_1097_DATA 0x00000000 +#define DDRSS0_PHY_1098_DATA 0x00000000 +#define DDRSS0_PHY_1099_DATA 0x00000000 +#define DDRSS0_PHY_1100_DATA 0x00000000 +#define DDRSS0_PHY_1101_DATA 0x00000000 +#define DDRSS0_PHY_1102_DATA 0x00000000 +#define DDRSS0_PHY_1103_DATA 0x00000000 +#define DDRSS0_PHY_1104_DATA 0x00000000 +#define DDRSS0_PHY_1105_DATA 0x00000000 +#define DDRSS0_PHY_1106_DATA 0x00000000 +#define DDRSS0_PHY_1107_DATA 0x00000000 +#define DDRSS0_PHY_1108_DATA 0x00000000 +#define DDRSS0_PHY_1109_DATA 0x00000000 +#define DDRSS0_PHY_1110_DATA 0x00000000 +#define DDRSS0_PHY_1111_DATA 0x00000000 +#define DDRSS0_PHY_1112_DATA 0x00000000 +#define DDRSS0_PHY_1113_DATA 0x00000000 +#define DDRSS0_PHY_1114_DATA 0x00000000 +#define DDRSS0_PHY_1115_DATA 0x00000000 +#define DDRSS0_PHY_1116_DATA 0x00000000 +#define DDRSS0_PHY_1117_DATA 0x00000000 +#define DDRSS0_PHY_1118_DATA 0x00000000 +#define DDRSS0_PHY_1119_DATA 0x00000000 +#define DDRSS0_PHY_1120_DATA 0x00000000 +#define DDRSS0_PHY_1121_DATA 0x00000000 +#define DDRSS0_PHY_1122_DATA 0x00000000 +#define DDRSS0_PHY_1123_DATA 0x00000000 +#define DDRSS0_PHY_1124_DATA 0x00000000 +#define DDRSS0_PHY_1125_DATA 0x00000000 +#define DDRSS0_PHY_1126_DATA 0x00000000 +#define DDRSS0_PHY_1127_DATA 0x00000000 +#define DDRSS0_PHY_1128_DATA 0x00000000 +#define DDRSS0_PHY_1129_DATA 0x00000000 +#define DDRSS0_PHY_1130_DATA 0x00000000 +#define DDRSS0_PHY_1131_DATA 0x00000000 +#define DDRSS0_PHY_1132_DATA 0x00000000 +#define DDRSS0_PHY_1133_DATA 0x00000000 +#define DDRSS0_PHY_1134_DATA 0x00000000 +#define DDRSS0_PHY_1135_DATA 0x00000000 +#define DDRSS0_PHY_1136_DATA 0x00000000 +#define DDRSS0_PHY_1137_DATA 0x00000000 +#define DDRSS0_PHY_1138_DATA 0x00000000 +#define DDRSS0_PHY_1139_DATA 0x00000000 +#define DDRSS0_PHY_1140_DATA 0x00000000 +#define DDRSS0_PHY_1141_DATA 0x00000000 +#define DDRSS0_PHY_1142_DATA 0x00000000 +#define DDRSS0_PHY_1143_DATA 0x00000000 +#define DDRSS0_PHY_1144_DATA 0x00000000 +#define DDRSS0_PHY_1145_DATA 0x00000000 +#define DDRSS0_PHY_1146_DATA 0x00000000 +#define DDRSS0_PHY_1147_DATA 0x00000000 +#define DDRSS0_PHY_1148_DATA 0x00000000 +#define DDRSS0_PHY_1149_DATA 0x00000000 +#define DDRSS0_PHY_1150_DATA 0x00000000 +#define DDRSS0_PHY_1151_DATA 0x00000000 +#define DDRSS0_PHY_1152_DATA 0x00000000 +#define DDRSS0_PHY_1153_DATA 0x00000000 +#define DDRSS0_PHY_1154_DATA 0x00000000 +#define DDRSS0_PHY_1155_DATA 0x00000000 +#define DDRSS0_PHY_1156_DATA 0x00000000 +#define DDRSS0_PHY_1157_DATA 0x00000000 +#define DDRSS0_PHY_1158_DATA 0x00000000 +#define DDRSS0_PHY_1159_DATA 0x00000000 +#define DDRSS0_PHY_1160_DATA 0x00000000 +#define DDRSS0_PHY_1161_DATA 0x00000000 +#define DDRSS0_PHY_1162_DATA 0x00000000 +#define DDRSS0_PHY_1163_DATA 0x00000000 +#define DDRSS0_PHY_1164_DATA 0x00000000 +#define DDRSS0_PHY_1165_DATA 0x00000000 +#define DDRSS0_PHY_1166_DATA 0x00000000 +#define DDRSS0_PHY_1167_DATA 0x00000000 +#define DDRSS0_PHY_1168_DATA 0x00000000 +#define DDRSS0_PHY_1169_DATA 0x00000000 +#define DDRSS0_PHY_1170_DATA 0x00000000 +#define DDRSS0_PHY_1171_DATA 0x00000000 +#define DDRSS0_PHY_1172_DATA 0x00000000 +#define DDRSS0_PHY_1173_DATA 0x00000000 +#define DDRSS0_PHY_1174_DATA 0x00000000 +#define DDRSS0_PHY_1175_DATA 0x00000000 +#define DDRSS0_PHY_1176_DATA 0x00000000 +#define DDRSS0_PHY_1177_DATA 0x00000000 +#define DDRSS0_PHY_1178_DATA 0x00000000 +#define DDRSS0_PHY_1179_DATA 0x00000000 +#define DDRSS0_PHY_1180_DATA 0x00000000 +#define DDRSS0_PHY_1181_DATA 0x00000000 +#define DDRSS0_PHY_1182_DATA 0x00000000 +#define DDRSS0_PHY_1183_DATA 0x00000000 +#define DDRSS0_PHY_1184_DATA 0x00000000 +#define DDRSS0_PHY_1185_DATA 0x00000000 +#define DDRSS0_PHY_1186_DATA 0x00000000 +#define DDRSS0_PHY_1187_DATA 0x00000000 +#define DDRSS0_PHY_1188_DATA 0x00000000 +#define DDRSS0_PHY_1189_DATA 0x00000000 +#define DDRSS0_PHY_1190_DATA 0x00000000 +#define DDRSS0_PHY_1191_DATA 0x00000000 +#define DDRSS0_PHY_1192_DATA 0x00000000 +#define DDRSS0_PHY_1193_DATA 0x00000000 +#define DDRSS0_PHY_1194_DATA 0x00000000 +#define DDRSS0_PHY_1195_DATA 0x00000000 +#define DDRSS0_PHY_1196_DATA 0x00000000 +#define DDRSS0_PHY_1197_DATA 0x00000000 +#define DDRSS0_PHY_1198_DATA 0x00000000 +#define DDRSS0_PHY_1199_DATA 0x00000000 +#define DDRSS0_PHY_1200_DATA 0x00000000 +#define DDRSS0_PHY_1201_DATA 0x00000000 +#define DDRSS0_PHY_1202_DATA 0x00000000 +#define DDRSS0_PHY_1203_DATA 0x00000000 +#define DDRSS0_PHY_1204_DATA 0x00000000 +#define DDRSS0_PHY_1205_DATA 0x00000000 +#define DDRSS0_PHY_1206_DATA 0x00000000 +#define DDRSS0_PHY_1207_DATA 0x00000000 +#define DDRSS0_PHY_1208_DATA 0x00000000 +#define DDRSS0_PHY_1209_DATA 0x00000000 +#define DDRSS0_PHY_1210_DATA 0x00000000 +#define DDRSS0_PHY_1211_DATA 0x00000000 +#define DDRSS0_PHY_1212_DATA 0x00000000 +#define DDRSS0_PHY_1213_DATA 0x00000000 +#define DDRSS0_PHY_1214_DATA 0x00000000 +#define DDRSS0_PHY_1215_DATA 0x00000000 +#define DDRSS0_PHY_1216_DATA 0x00000000 +#define DDRSS0_PHY_1217_DATA 0x00000000 +#define DDRSS0_PHY_1218_DATA 0x00000000 +#define DDRSS0_PHY_1219_DATA 0x00000000 +#define DDRSS0_PHY_1220_DATA 0x00000000 +#define DDRSS0_PHY_1221_DATA 0x00000000 +#define DDRSS0_PHY_1222_DATA 0x00000000 +#define DDRSS0_PHY_1223_DATA 0x00000000 +#define DDRSS0_PHY_1224_DATA 0x00000000 +#define DDRSS0_PHY_1225_DATA 0x00000000 +#define DDRSS0_PHY_1226_DATA 0x00000000 +#define DDRSS0_PHY_1227_DATA 0x00000000 +#define DDRSS0_PHY_1228_DATA 0x00000000 +#define DDRSS0_PHY_1229_DATA 0x00000000 +#define DDRSS0_PHY_1230_DATA 0x00000000 +#define DDRSS0_PHY_1231_DATA 0x00000000 +#define DDRSS0_PHY_1232_DATA 0x00000000 +#define DDRSS0_PHY_1233_DATA 0x00000000 +#define DDRSS0_PHY_1234_DATA 0x00000000 +#define DDRSS0_PHY_1235_DATA 0x00000000 +#define DDRSS0_PHY_1236_DATA 0x00000000 +#define DDRSS0_PHY_1237_DATA 0x00000000 +#define DDRSS0_PHY_1238_DATA 0x00000000 +#define DDRSS0_PHY_1239_DATA 0x00000000 +#define DDRSS0_PHY_1240_DATA 0x00000000 +#define DDRSS0_PHY_1241_DATA 0x00000000 +#define DDRSS0_PHY_1242_DATA 0x00000000 +#define DDRSS0_PHY_1243_DATA 0x00000000 +#define DDRSS0_PHY_1244_DATA 0x00000000 +#define DDRSS0_PHY_1245_DATA 0x00000000 +#define DDRSS0_PHY_1246_DATA 0x00000000 +#define DDRSS0_PHY_1247_DATA 0x00000000 +#define DDRSS0_PHY_1248_DATA 0x00000000 +#define DDRSS0_PHY_1249_DATA 0x00000000 +#define DDRSS0_PHY_1250_DATA 0x00000000 +#define DDRSS0_PHY_1251_DATA 0x00000000 +#define DDRSS0_PHY_1252_DATA 0x00000000 +#define DDRSS0_PHY_1253_DATA 0x00000000 +#define DDRSS0_PHY_1254_DATA 0x00000000 +#define DDRSS0_PHY_1255_DATA 0x00000000 +#define DDRSS0_PHY_1256_DATA 0x00000000 +#define DDRSS0_PHY_1257_DATA 0x00000000 +#define DDRSS0_PHY_1258_DATA 0x00000000 +#define DDRSS0_PHY_1259_DATA 0x00000000 +#define DDRSS0_PHY_1260_DATA 0x00000000 +#define DDRSS0_PHY_1261_DATA 0x00000000 +#define DDRSS0_PHY_1262_DATA 0x00000000 +#define DDRSS0_PHY_1263_DATA 0x00000000 +#define DDRSS0_PHY_1264_DATA 0x00000000 +#define DDRSS0_PHY_1265_DATA 0x00000000 +#define DDRSS0_PHY_1266_DATA 0x00000000 +#define DDRSS0_PHY_1267_DATA 0x00000000 +#define DDRSS0_PHY_1268_DATA 0x00000000 +#define DDRSS0_PHY_1269_DATA 0x00000000 +#define DDRSS0_PHY_1270_DATA 0x00000000 +#define DDRSS0_PHY_1271_DATA 0x00000000 +#define DDRSS0_PHY_1272_DATA 0x00000000 +#define DDRSS0_PHY_1273_DATA 0x00000000 +#define DDRSS0_PHY_1274_DATA 0x00000000 +#define DDRSS0_PHY_1275_DATA 0x00000000 +#define DDRSS0_PHY_1276_DATA 0x00000000 +#define DDRSS0_PHY_1277_DATA 0x00000000 +#define DDRSS0_PHY_1278_DATA 0x00000000 +#define DDRSS0_PHY_1279_DATA 0x00000000 +#define DDRSS0_PHY_1280_DATA 0x00000000 +#define DDRSS0_PHY_1281_DATA 0x00010100 +#define DDRSS0_PHY_1282_DATA 0x00000000 +#define DDRSS0_PHY_1283_DATA 0x00000000 +#define DDRSS0_PHY_1284_DATA 0x00050000 +#define DDRSS0_PHY_1285_DATA 0x04000000 +#define DDRSS0_PHY_1286_DATA 0x00000055 +#define DDRSS0_PHY_1287_DATA 0x00000000 +#define DDRSS0_PHY_1288_DATA 0x00000000 +#define DDRSS0_PHY_1289_DATA 0x00000000 +#define DDRSS0_PHY_1290_DATA 0x00000000 +#define DDRSS0_PHY_1291_DATA 0x00002001 +#define DDRSS0_PHY_1292_DATA 0x0000400F +#define DDRSS0_PHY_1293_DATA 0x50020028 +#define DDRSS0_PHY_1294_DATA 0x01010000 +#define DDRSS0_PHY_1295_DATA 0x80080001 +#define DDRSS0_PHY_1296_DATA 0x10200000 +#define DDRSS0_PHY_1297_DATA 0x00000008 +#define DDRSS0_PHY_1298_DATA 0x00000000 +#define DDRSS0_PHY_1299_DATA 0x01090E00 +#define DDRSS0_PHY_1300_DATA 0x00040101 +#define DDRSS0_PHY_1301_DATA 0x0000010F +#define DDRSS0_PHY_1302_DATA 0x00000000 +#define DDRSS0_PHY_1303_DATA 0x00000064 +#define DDRSS0_PHY_1304_DATA 0x00000000 +#define DDRSS0_PHY_1305_DATA 0x01010000 +#define DDRSS0_PHY_1306_DATA 0x01080402 +#define DDRSS0_PHY_1307_DATA 0x01200F02 +#define DDRSS0_PHY_1308_DATA 0x00194280 +#define DDRSS0_PHY_1309_DATA 0x00000004 +#define DDRSS0_PHY_1310_DATA 0x00042000 +#define DDRSS0_PHY_1311_DATA 0x00000000 +#define DDRSS0_PHY_1312_DATA 0x00000000 +#define DDRSS0_PHY_1313_DATA 0x00000000 +#define DDRSS0_PHY_1314_DATA 0x00000000 +#define DDRSS0_PHY_1315_DATA 0x00000000 +#define DDRSS0_PHY_1316_DATA 0x00000000 +#define DDRSS0_PHY_1317_DATA 0x01000000 +#define DDRSS0_PHY_1318_DATA 0x00000705 +#define DDRSS0_PHY_1319_DATA 0x00000054 +#define DDRSS0_PHY_1320_DATA 0x00030820 +#define DDRSS0_PHY_1321_DATA 0x00010820 +#define DDRSS0_PHY_1322_DATA 0x00010820 +#define DDRSS0_PHY_1323_DATA 0x00010820 +#define DDRSS0_PHY_1324_DATA 0x00010820 +#define DDRSS0_PHY_1325_DATA 0x00010820 +#define DDRSS0_PHY_1326_DATA 0x00010820 +#define DDRSS0_PHY_1327_DATA 0x00010820 +#define DDRSS0_PHY_1328_DATA 0x00010820 +#define DDRSS0_PHY_1329_DATA 0x00000000 +#define DDRSS0_PHY_1330_DATA 0x00000074 +#define DDRSS0_PHY_1331_DATA 0x00000400 +#define DDRSS0_PHY_1332_DATA 0x00000108 +#define DDRSS0_PHY_1333_DATA 0x00000000 +#define DDRSS0_PHY_1334_DATA 0x00000000 +#define DDRSS0_PHY_1335_DATA 0x00000000 +#define DDRSS0_PHY_1336_DATA 0x00000000 +#define DDRSS0_PHY_1337_DATA 0x00000000 +#define DDRSS0_PHY_1338_DATA 0x03000000 +#define DDRSS0_PHY_1339_DATA 0x00000000 +#define DDRSS0_PHY_1340_DATA 0x00000000 +#define DDRSS0_PHY_1341_DATA 0x00000000 +#define DDRSS0_PHY_1342_DATA 0x04102006 +#define DDRSS0_PHY_1343_DATA 0x00041020 +#define DDRSS0_PHY_1344_DATA 0x01C98C98 +#define DDRSS0_PHY_1345_DATA 0x3F400000 +#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS0_PHY_1347_DATA 0x0000001F +#define DDRSS0_PHY_1348_DATA 0x00000000 +#define DDRSS0_PHY_1349_DATA 0x00000000 +#define DDRSS0_PHY_1350_DATA 0x00000000 +#define DDRSS0_PHY_1351_DATA 0x00010000 +#define DDRSS0_PHY_1352_DATA 0x00000000 +#define DDRSS0_PHY_1353_DATA 0x00000000 +#define DDRSS0_PHY_1354_DATA 0x00000000 +#define DDRSS0_PHY_1355_DATA 0x00000000 +#define DDRSS0_PHY_1356_DATA 0x76543210 +#define DDRSS0_PHY_1357_DATA 0x00010198 +#define DDRSS0_PHY_1358_DATA 0x00000000 +#define DDRSS0_PHY_1359_DATA 0x00000000 +#define DDRSS0_PHY_1360_DATA 0x00000000 +#define DDRSS0_PHY_1361_DATA 0x00040700 +#define DDRSS0_PHY_1362_DATA 0x00000000 +#define DDRSS0_PHY_1363_DATA 0x00000000 +#define DDRSS0_PHY_1364_DATA 0x00000000 +#define DDRSS0_PHY_1365_DATA 0x00000000 +#define DDRSS0_PHY_1366_DATA 0x00000000 +#define DDRSS0_PHY_1367_DATA 0x00000002 +#define DDRSS0_PHY_1368_DATA 0x00000000 +#define DDRSS0_PHY_1369_DATA 0x00000000 +#define DDRSS0_PHY_1370_DATA 0x00000000 +#define DDRSS0_PHY_1371_DATA 0x00000000 +#define DDRSS0_PHY_1372_DATA 0x00000000 +#define DDRSS0_PHY_1373_DATA 0x00000000 +#define DDRSS0_PHY_1374_DATA 0x00080000 +#define DDRSS0_PHY_1375_DATA 0x000007FF +#define DDRSS0_PHY_1376_DATA 0x00000000 +#define DDRSS0_PHY_1377_DATA 0x00000000 +#define DDRSS0_PHY_1378_DATA 0x00000000 +#define DDRSS0_PHY_1379_DATA 0x00000000 +#define DDRSS0_PHY_1380_DATA 0x00000000 +#define DDRSS0_PHY_1381_DATA 0x00000000 +#define DDRSS0_PHY_1382_DATA 0x000FFFFF +#define DDRSS0_PHY_1383_DATA 0x000FFFFF +#define DDRSS0_PHY_1384_DATA 0x0000FFFF +#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS0_PHY_1386_DATA 0x030FFFFF +#define DDRSS0_PHY_1387_DATA 0x01FFFFFF +#define DDRSS0_PHY_1388_DATA 0x0000FFFF +#define DDRSS0_PHY_1389_DATA 0x00000000 +#define DDRSS0_PHY_1390_DATA 0x00000000 +#define DDRSS0_PHY_1391_DATA 0x00000000 +#define DDRSS0_PHY_1392_DATA 0x00000000 +#define DDRSS0_PHY_1393_DATA 0x0001F7C0 +#define DDRSS0_PHY_1394_DATA 0x00000003 +#define DDRSS0_PHY_1395_DATA 0x00000000 +#define DDRSS0_PHY_1396_DATA 0x00001142 +#define DDRSS0_PHY_1397_DATA 0x040207AB +#define DDRSS0_PHY_1398_DATA 0x01000080 +#define DDRSS0_PHY_1399_DATA 0x03900390 +#define DDRSS0_PHY_1400_DATA 0x03900390 +#define DDRSS0_PHY_1401_DATA 0x00000390 +#define DDRSS0_PHY_1402_DATA 0x00000390 +#define DDRSS0_PHY_1403_DATA 0x00000390 +#define DDRSS0_PHY_1404_DATA 0x00000390 +#define DDRSS0_PHY_1405_DATA 0x00000005 +#define DDRSS0_PHY_1406_DATA 0x01813FCC +#define DDRSS0_PHY_1407_DATA 0x000000CC +#define DDRSS0_PHY_1408_DATA 0x0C000DFF +#define DDRSS0_PHY_1409_DATA 0x30000DFF +#define DDRSS0_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1411_DATA 0x000100F0 +#define DDRSS0_PHY_1412_DATA 0x780DFFCC +#define DDRSS0_PHY_1413_DATA 0x00007E31 +#define DDRSS0_PHY_1414_DATA 0x000CBF11 +#define DDRSS0_PHY_1415_DATA 0x01990010 +#define DDRSS0_PHY_1416_DATA 0x000CBF11 +#define DDRSS0_PHY_1417_DATA 0x01990010 +#define DDRSS0_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1419_DATA 0x00EF00F0 +#define DDRSS0_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1421_DATA 0x01FF00F0 +#define DDRSS0_PHY_1422_DATA 0x20040006 + +#define DDRSS1_CTL_00_DATA 0x00000B00 +#define DDRSS1_CTL_01_DATA 0x00000000 +#define DDRSS1_CTL_02_DATA 0x00000000 +#define DDRSS1_CTL_03_DATA 0x00000000 +#define DDRSS1_CTL_04_DATA 0x00000000 +#define DDRSS1_CTL_05_DATA 0x00000000 +#define DDRSS1_CTL_06_DATA 0x00000000 +#define DDRSS1_CTL_07_DATA 0x00002AF8 +#define DDRSS1_CTL_08_DATA 0x0001ADAF +#define DDRSS1_CTL_09_DATA 0x00000005 +#define DDRSS1_CTL_10_DATA 0x0000006E +#define DDRSS1_CTL_11_DATA 0x000681C8 +#define DDRSS1_CTL_12_DATA 0x004111C9 +#define DDRSS1_CTL_13_DATA 0x00000005 +#define DDRSS1_CTL_14_DATA 0x000010A9 +#define DDRSS1_CTL_15_DATA 0x000681C8 +#define DDRSS1_CTL_16_DATA 0x004111C9 +#define DDRSS1_CTL_17_DATA 0x00000005 +#define DDRSS1_CTL_18_DATA 0x000010A9 +#define DDRSS1_CTL_19_DATA 0x01010000 +#define DDRSS1_CTL_20_DATA 0x01011001 +#define DDRSS1_CTL_21_DATA 0x02010000 +#define DDRSS1_CTL_22_DATA 0x00020100 +#define DDRSS1_CTL_23_DATA 0x0000000B +#define DDRSS1_CTL_24_DATA 0x0000001C +#define DDRSS1_CTL_25_DATA 0x00000000 +#define DDRSS1_CTL_26_DATA 0x00000000 +#define DDRSS1_CTL_27_DATA 0x03020200 +#define DDRSS1_CTL_28_DATA 0x00005656 +#define DDRSS1_CTL_29_DATA 0x00100000 +#define DDRSS1_CTL_30_DATA 0x00000000 +#define DDRSS1_CTL_31_DATA 0x00000000 +#define DDRSS1_CTL_32_DATA 0x00000000 +#define DDRSS1_CTL_33_DATA 0x00000000 +#define DDRSS1_CTL_34_DATA 0x040C0000 +#define DDRSS1_CTL_35_DATA 0x12501250 +#define DDRSS1_CTL_36_DATA 0x00050804 +#define DDRSS1_CTL_37_DATA 0x09040008 +#define DDRSS1_CTL_38_DATA 0x15000204 +#define DDRSS1_CTL_39_DATA 0x1760008B +#define DDRSS1_CTL_40_DATA 0x1500422B +#define DDRSS1_CTL_41_DATA 0x1760008B +#define DDRSS1_CTL_42_DATA 0x2000422B +#define DDRSS1_CTL_43_DATA 0x000A0A09 +#define DDRSS1_CTL_44_DATA 0x040003C5 +#define DDRSS1_CTL_45_DATA 0x1E161104 +#define DDRSS1_CTL_46_DATA 0x1000922C +#define DDRSS1_CTL_47_DATA 0x1E161110 +#define DDRSS1_CTL_48_DATA 0x1000922C +#define DDRSS1_CTL_49_DATA 0x02030410 +#define DDRSS1_CTL_50_DATA 0x2C060500 +#define DDRSS1_CTL_51_DATA 0x08292C29 +#define DDRSS1_CTL_52_DATA 0x14000E0A +#define DDRSS1_CTL_53_DATA 0x04010A0A +#define DDRSS1_CTL_54_DATA 0x01010004 +#define DDRSS1_CTL_55_DATA 0x0454540A +#define DDRSS1_CTL_56_DATA 0x04313104 +#define DDRSS1_CTL_57_DATA 0x00003131 +#define DDRSS1_CTL_58_DATA 0x00010100 +#define DDRSS1_CTL_59_DATA 0x03010000 +#define DDRSS1_CTL_60_DATA 0x00001508 +#define DDRSS1_CTL_61_DATA 0x00000068 +#define DDRSS1_CTL_62_DATA 0x0000032B +#define DDRSS1_CTL_63_DATA 0x00001035 +#define DDRSS1_CTL_64_DATA 0x0000032B +#define DDRSS1_CTL_65_DATA 0x00001035 +#define DDRSS1_CTL_66_DATA 0x00000005 +#define DDRSS1_CTL_67_DATA 0x00050000 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 +#define DDRSS1_CTL_71_DATA 0x00120103 +#define DDRSS1_CTL_72_DATA 0x00100005 +#define DDRSS1_CTL_73_DATA 0x2F080010 +#define DDRSS1_CTL_74_DATA 0x0505012F +#define DDRSS1_CTL_75_DATA 0x0401030A +#define DDRSS1_CTL_76_DATA 0x041E100B +#define DDRSS1_CTL_77_DATA 0x100B0401 +#define DDRSS1_CTL_78_DATA 0x0001041E +#define DDRSS1_CTL_79_DATA 0x00160016 +#define DDRSS1_CTL_80_DATA 0x033B033B +#define DDRSS1_CTL_81_DATA 0x033B033B +#define DDRSS1_CTL_82_DATA 0x03050505 +#define DDRSS1_CTL_83_DATA 0x03010303 +#define DDRSS1_CTL_84_DATA 0x200B100B +#define DDRSS1_CTL_85_DATA 0x04041004 +#define DDRSS1_CTL_86_DATA 0x200B100B +#define DDRSS1_CTL_87_DATA 0x04041004 +#define DDRSS1_CTL_88_DATA 0x03010000 +#define DDRSS1_CTL_89_DATA 0x00010000 +#define DDRSS1_CTL_90_DATA 0x00000000 +#define DDRSS1_CTL_91_DATA 0x00000000 +#define DDRSS1_CTL_92_DATA 0x01000000 +#define DDRSS1_CTL_93_DATA 0x80104002 +#define DDRSS1_CTL_94_DATA 0x00000000 +#define DDRSS1_CTL_95_DATA 0x00040005 +#define DDRSS1_CTL_96_DATA 0x00000000 +#define DDRSS1_CTL_97_DATA 0x00050000 +#define DDRSS1_CTL_98_DATA 0x00000004 +#define DDRSS1_CTL_99_DATA 0x00000000 +#define DDRSS1_CTL_100_DATA 0x00040005 +#define DDRSS1_CTL_101_DATA 0x00000000 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 +#define DDRSS1_CTL_107_DATA 0x00000000 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 +#define DDRSS1_CTL_114_DATA 0x00000000 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 +#define DDRSS1_CTL_121_DATA 0x00000000 +#define DDRSS1_CTL_122_DATA 0x00007173 +#define DDRSS1_CTL_123_DATA 0x00000000 +#define DDRSS1_CTL_124_DATA 0x00000000 +#define DDRSS1_CTL_125_DATA 0x00000000 +#define DDRSS1_CTL_126_DATA 0x00000000 +#define DDRSS1_CTL_127_DATA 0x00000000 +#define DDRSS1_CTL_128_DATA 0x00000000 +#define DDRSS1_CTL_129_DATA 0x00000000 +#define DDRSS1_CTL_130_DATA 0x00000000 +#define DDRSS1_CTL_131_DATA 0x0B030500 +#define DDRSS1_CTL_132_DATA 0x00040B04 +#define DDRSS1_CTL_133_DATA 0x0A090000 +#define DDRSS1_CTL_134_DATA 0x0A090701 +#define DDRSS1_CTL_135_DATA 0x0900000E +#define DDRSS1_CTL_136_DATA 0x0907010A +#define DDRSS1_CTL_137_DATA 0x00000E0A +#define DDRSS1_CTL_138_DATA 0x07010A09 +#define DDRSS1_CTL_139_DATA 0x000E0A09 +#define DDRSS1_CTL_140_DATA 0x07000401 +#define DDRSS1_CTL_141_DATA 0x00000000 +#define DDRSS1_CTL_142_DATA 0x00000000 +#define DDRSS1_CTL_143_DATA 0x00000000 +#define DDRSS1_CTL_144_DATA 0x00000000 +#define DDRSS1_CTL_145_DATA 0x00000000 +#define DDRSS1_CTL_146_DATA 0x00000000 +#define DDRSS1_CTL_147_DATA 0x00000000 +#define DDRSS1_CTL_148_DATA 0x08080000 +#define DDRSS1_CTL_149_DATA 0x01000000 +#define DDRSS1_CTL_150_DATA 0x800000C0 +#define DDRSS1_CTL_151_DATA 0x800000C0 +#define DDRSS1_CTL_152_DATA 0x800000C0 +#define DDRSS1_CTL_153_DATA 0x00000000 +#define DDRSS1_CTL_154_DATA 0x00001500 +#define DDRSS1_CTL_155_DATA 0x00000000 +#define DDRSS1_CTL_156_DATA 0x00000001 +#define DDRSS1_CTL_157_DATA 0x00000002 +#define DDRSS1_CTL_158_DATA 0x0000100E +#define DDRSS1_CTL_159_DATA 0x00000000 +#define DDRSS1_CTL_160_DATA 0x00000000 +#define DDRSS1_CTL_161_DATA 0x00000000 +#define DDRSS1_CTL_162_DATA 0x00000000 +#define DDRSS1_CTL_163_DATA 0x00000000 +#define DDRSS1_CTL_164_DATA 0x000B0000 +#define DDRSS1_CTL_165_DATA 0x000E0006 +#define DDRSS1_CTL_166_DATA 0x000E0404 +#define DDRSS1_CTL_167_DATA 0x00D601AB +#define DDRSS1_CTL_168_DATA 0x10100216 +#define DDRSS1_CTL_169_DATA 0x01AB0216 +#define DDRSS1_CTL_170_DATA 0x021600D6 +#define DDRSS1_CTL_171_DATA 0x02161010 +#define DDRSS1_CTL_172_DATA 0x00000000 +#define DDRSS1_CTL_173_DATA 0x00000000 +#define DDRSS1_CTL_174_DATA 0x00000000 +#define DDRSS1_CTL_175_DATA 0x3FF40084 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 +#define DDRSS1_CTL_178_DATA 0x35000000 +#define DDRSS1_CTL_179_DATA 0x27270035 +#define DDRSS1_CTL_180_DATA 0x0F0F0000 +#define DDRSS1_CTL_181_DATA 0x16000000 +#define DDRSS1_CTL_182_DATA 0x00841616 +#define DDRSS1_CTL_183_DATA 0x3FF43FF4 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 +#define DDRSS1_CTL_185_DATA 0x00000000 +#define DDRSS1_CTL_186_DATA 0x00353500 +#define DDRSS1_CTL_187_DATA 0x00002727 +#define DDRSS1_CTL_188_DATA 0x00000F0F +#define DDRSS1_CTL_189_DATA 0x16161600 +#define DDRSS1_CTL_190_DATA 0x00000020 +#define DDRSS1_CTL_191_DATA 0x01000000 +#define DDRSS1_CTL_192_DATA 0x00000001 +#define DDRSS1_CTL_193_DATA 0x00000000 +#define DDRSS1_CTL_194_DATA 0x01000000 +#define DDRSS1_CTL_195_DATA 0x00000001 +#define DDRSS1_CTL_196_DATA 0x00000000 +#define DDRSS1_CTL_197_DATA 0x00000000 +#define DDRSS1_CTL_198_DATA 0x00000000 +#define DDRSS1_CTL_199_DATA 0x00000000 +#define DDRSS1_CTL_200_DATA 0x00000000 +#define DDRSS1_CTL_201_DATA 0x00000000 +#define DDRSS1_CTL_202_DATA 0x00000000 +#define DDRSS1_CTL_203_DATA 0x00000000 +#define DDRSS1_CTL_204_DATA 0x00000000 +#define DDRSS1_CTL_205_DATA 0x00000000 +#define DDRSS1_CTL_206_DATA 0x02000000 +#define DDRSS1_CTL_207_DATA 0x01080101 +#define DDRSS1_CTL_208_DATA 0x00000000 +#define DDRSS1_CTL_209_DATA 0x00000000 +#define DDRSS1_CTL_210_DATA 0x00000000 +#define DDRSS1_CTL_211_DATA 0x00000000 +#define DDRSS1_CTL_212_DATA 0x00000000 +#define DDRSS1_CTL_213_DATA 0x00000000 +#define DDRSS1_CTL_214_DATA 0x00000000 +#define DDRSS1_CTL_215_DATA 0x00000000 +#define DDRSS1_CTL_216_DATA 0x00000000 +#define DDRSS1_CTL_217_DATA 0x00000000 +#define DDRSS1_CTL_218_DATA 0x00000000 +#define DDRSS1_CTL_219_DATA 0x00000000 +#define DDRSS1_CTL_220_DATA 0x00000000 +#define DDRSS1_CTL_221_DATA 0x00000000 +#define DDRSS1_CTL_222_DATA 0x00001000 +#define DDRSS1_CTL_223_DATA 0x006403E8 +#define DDRSS1_CTL_224_DATA 0x00000000 +#define DDRSS1_CTL_225_DATA 0x00000000 +#define DDRSS1_CTL_226_DATA 0x00000000 +#define DDRSS1_CTL_227_DATA 0x15110000 +#define DDRSS1_CTL_228_DATA 0x00040C18 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 +#define DDRSS1_CTL_231_DATA 0x00000000 +#define DDRSS1_CTL_232_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 +#define DDRSS1_CTL_235_DATA 0x00000000 +#define DDRSS1_CTL_236_DATA 0x00000000 +#define DDRSS1_CTL_237_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 +#define DDRSS1_CTL_240_DATA 0x00000000 +#define DDRSS1_CTL_241_DATA 0x00000000 +#define DDRSS1_CTL_242_DATA 0x00030000 +#define DDRSS1_CTL_243_DATA 0x00000000 +#define DDRSS1_CTL_244_DATA 0x00000000 +#define DDRSS1_CTL_245_DATA 0x00000000 +#define DDRSS1_CTL_246_DATA 0x00000000 +#define DDRSS1_CTL_247_DATA 0x00000000 +#define DDRSS1_CTL_248_DATA 0x00000000 +#define DDRSS1_CTL_249_DATA 0x00000000 +#define DDRSS1_CTL_250_DATA 0x00000000 +#define DDRSS1_CTL_251_DATA 0x00000000 +#define DDRSS1_CTL_252_DATA 0x00000000 +#define DDRSS1_CTL_253_DATA 0x00000000 +#define DDRSS1_CTL_254_DATA 0x00000000 +#define DDRSS1_CTL_255_DATA 0x00000000 +#define DDRSS1_CTL_256_DATA 0x00000000 +#define DDRSS1_CTL_257_DATA 0x01000200 +#define DDRSS1_CTL_258_DATA 0x00370040 +#define DDRSS1_CTL_259_DATA 0x00020008 +#define DDRSS1_CTL_260_DATA 0x00400100 +#define DDRSS1_CTL_261_DATA 0x00400855 +#define DDRSS1_CTL_262_DATA 0x01000200 +#define DDRSS1_CTL_263_DATA 0x08550040 +#define DDRSS1_CTL_264_DATA 0x00000040 +#define DDRSS1_CTL_265_DATA 0x006B0003 +#define DDRSS1_CTL_266_DATA 0x0100006B +#define DDRSS1_CTL_267_DATA 0x03030303 +#define DDRSS1_CTL_268_DATA 0x00000000 +#define DDRSS1_CTL_269_DATA 0x00000202 +#define DDRSS1_CTL_270_DATA 0x00001FFF +#define DDRSS1_CTL_271_DATA 0x3FFF2000 +#define DDRSS1_CTL_272_DATA 0x03FF0000 +#define DDRSS1_CTL_273_DATA 0x000103FF +#define DDRSS1_CTL_274_DATA 0x0FFF0B00 +#define DDRSS1_CTL_275_DATA 0x01010001 +#define DDRSS1_CTL_276_DATA 0x01010101 +#define DDRSS1_CTL_277_DATA 0x01180101 +#define DDRSS1_CTL_278_DATA 0x00030000 +#define DDRSS1_CTL_279_DATA 0x00000000 +#define DDRSS1_CTL_280_DATA 0x00000000 +#define DDRSS1_CTL_281_DATA 0x00000000 +#define DDRSS1_CTL_282_DATA 0x00000000 +#define DDRSS1_CTL_283_DATA 0x00000000 +#define DDRSS1_CTL_284_DATA 0x00000000 +#define DDRSS1_CTL_285_DATA 0x00000000 +#define DDRSS1_CTL_286_DATA 0x00040101 +#define DDRSS1_CTL_287_DATA 0x04010100 +#define DDRSS1_CTL_288_DATA 0x00000000 +#define DDRSS1_CTL_289_DATA 0x00000000 +#define DDRSS1_CTL_290_DATA 0x03030300 +#define DDRSS1_CTL_291_DATA 0x00010101 +#define DDRSS1_CTL_292_DATA 0x00000000 +#define DDRSS1_CTL_293_DATA 0x00000000 +#define DDRSS1_CTL_294_DATA 0x00000000 +#define DDRSS1_CTL_295_DATA 0x00000000 +#define DDRSS1_CTL_296_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF +#define DDRSS1_CTL_299_DATA 0x00000000 +#define DDRSS1_CTL_300_DATA 0x00000000 +#define DDRSS1_CTL_301_DATA 0x00000000 +#define DDRSS1_CTL_302_DATA 0x00000000 +#define DDRSS1_CTL_303_DATA 0x00000000 +#define DDRSS1_CTL_304_DATA 0x00000000 +#define DDRSS1_CTL_305_DATA 0x00000000 +#define DDRSS1_CTL_306_DATA 0x00000000 +#define DDRSS1_CTL_307_DATA 0x00000000 +#define DDRSS1_CTL_308_DATA 0x00000000 +#define DDRSS1_CTL_309_DATA 0x00000000 +#define DDRSS1_CTL_310_DATA 0x00000000 +#define DDRSS1_CTL_311_DATA 0x00000000 +#define DDRSS1_CTL_312_DATA 0x00000000 +#define DDRSS1_CTL_313_DATA 0x01000000 +#define DDRSS1_CTL_314_DATA 0x00020201 +#define DDRSS1_CTL_315_DATA 0x01000101 +#define DDRSS1_CTL_316_DATA 0x01010001 +#define DDRSS1_CTL_317_DATA 0x00010101 +#define DDRSS1_CTL_318_DATA 0x050A0A03 +#define DDRSS1_CTL_319_DATA 0x10082323 +#define DDRSS1_CTL_320_DATA 0x00090310 +#define DDRSS1_CTL_321_DATA 0x0B0C030F +#define DDRSS1_CTL_322_DATA 0x0B0C0306 +#define DDRSS1_CTL_323_DATA 0x0C090006 +#define DDRSS1_CTL_324_DATA 0x0100000C +#define DDRSS1_CTL_325_DATA 0x08040801 +#define DDRSS1_CTL_326_DATA 0x00000004 +#define DDRSS1_CTL_327_DATA 0x00000000 +#define DDRSS1_CTL_328_DATA 0x00010000 +#define DDRSS1_CTL_329_DATA 0x00280D00 +#define DDRSS1_CTL_330_DATA 0x00000001 +#define DDRSS1_CTL_331_DATA 0x00030001 +#define DDRSS1_CTL_332_DATA 0x00000000 +#define DDRSS1_CTL_333_DATA 0x00000000 +#define DDRSS1_CTL_334_DATA 0x00000000 +#define DDRSS1_CTL_335_DATA 0x00000000 +#define DDRSS1_CTL_336_DATA 0x00000000 +#define DDRSS1_CTL_337_DATA 0x00000000 +#define DDRSS1_CTL_338_DATA 0x00000000 +#define DDRSS1_CTL_339_DATA 0x00000000 +#define DDRSS1_CTL_340_DATA 0x01000000 +#define DDRSS1_CTL_341_DATA 0x00000001 +#define DDRSS1_CTL_342_DATA 0x00010100 +#define DDRSS1_CTL_343_DATA 0x03030000 +#define DDRSS1_CTL_344_DATA 0x00000000 +#define DDRSS1_CTL_345_DATA 0x00000000 +#define DDRSS1_CTL_346_DATA 0x00000000 +#define DDRSS1_CTL_347_DATA 0x00000000 +#define DDRSS1_CTL_348_DATA 0x00000000 +#define DDRSS1_CTL_349_DATA 0x00000000 +#define DDRSS1_CTL_350_DATA 0x00000000 +#define DDRSS1_CTL_351_DATA 0x00000000 +#define DDRSS1_CTL_352_DATA 0x00000000 +#define DDRSS1_CTL_353_DATA 0x00000000 +#define DDRSS1_CTL_354_DATA 0x00000000 +#define DDRSS1_CTL_355_DATA 0x00000000 +#define DDRSS1_CTL_356_DATA 0x00000000 +#define DDRSS1_CTL_357_DATA 0x00000000 +#define DDRSS1_CTL_358_DATA 0x00000000 +#define DDRSS1_CTL_359_DATA 0x00000000 +#define DDRSS1_CTL_360_DATA 0x000556AA +#define DDRSS1_CTL_361_DATA 0x000AAAAA +#define DDRSS1_CTL_362_DATA 0x000AA955 +#define DDRSS1_CTL_363_DATA 0x00055555 +#define DDRSS1_CTL_364_DATA 0x000B3133 +#define DDRSS1_CTL_365_DATA 0x0004CD33 +#define DDRSS1_CTL_366_DATA 0x0004CECC +#define DDRSS1_CTL_367_DATA 0x000B32CC +#define DDRSS1_CTL_368_DATA 0x00010300 +#define DDRSS1_CTL_369_DATA 0x03000100 +#define DDRSS1_CTL_370_DATA 0x00000000 +#define DDRSS1_CTL_371_DATA 0x00000000 +#define DDRSS1_CTL_372_DATA 0x00000000 +#define DDRSS1_CTL_373_DATA 0x00000000 +#define DDRSS1_CTL_374_DATA 0x00000000 +#define DDRSS1_CTL_375_DATA 0x00000000 +#define DDRSS1_CTL_376_DATA 0x00000000 +#define DDRSS1_CTL_377_DATA 0x00010000 +#define DDRSS1_CTL_378_DATA 0x00000404 +#define DDRSS1_CTL_379_DATA 0x00000000 +#define DDRSS1_CTL_380_DATA 0x00000000 +#define DDRSS1_CTL_381_DATA 0x00000000 +#define DDRSS1_CTL_382_DATA 0x00000000 +#define DDRSS1_CTL_383_DATA 0x00000000 +#define DDRSS1_CTL_384_DATA 0x00000000 +#define DDRSS1_CTL_385_DATA 0x00000000 +#define DDRSS1_CTL_386_DATA 0x00000000 +#define DDRSS1_CTL_387_DATA 0x3A3A1B00 +#define DDRSS1_CTL_388_DATA 0x000A0000 +#define DDRSS1_CTL_389_DATA 0x000000C6 +#define DDRSS1_CTL_390_DATA 0x00000200 +#define DDRSS1_CTL_391_DATA 0x00000200 +#define DDRSS1_CTL_392_DATA 0x00000200 +#define DDRSS1_CTL_393_DATA 0x00000200 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC +#define DDRSS1_CTL_396_DATA 0x00000204 +#define DDRSS1_CTL_397_DATA 0x0000206A +#define DDRSS1_CTL_398_DATA 0x00000200 +#define DDRSS1_CTL_399_DATA 0x00000200 +#define DDRSS1_CTL_400_DATA 0x00000200 +#define DDRSS1_CTL_401_DATA 0x00000200 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A +#define DDRSS1_CTL_406_DATA 0x00000200 +#define DDRSS1_CTL_407_DATA 0x00000200 +#define DDRSS1_CTL_408_DATA 0x00000200 +#define DDRSS1_CTL_409_DATA 0x00000200 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 +#define DDRSS1_CTL_413_DATA 0x03030202 +#define DDRSS1_CTL_414_DATA 0x00000022 +#define DDRSS1_CTL_415_DATA 0x00000000 +#define DDRSS1_CTL_416_DATA 0x00000000 +#define DDRSS1_CTL_417_DATA 0x00001403 +#define DDRSS1_CTL_418_DATA 0x000007D0 +#define DDRSS1_CTL_419_DATA 0x00000000 +#define DDRSS1_CTL_420_DATA 0x00000000 +#define DDRSS1_CTL_421_DATA 0x00030000 +#define DDRSS1_CTL_422_DATA 0x0007001F +#define DDRSS1_CTL_423_DATA 0x001B0033 +#define DDRSS1_CTL_424_DATA 0x001B0033 +#define DDRSS1_CTL_425_DATA 0x00000000 +#define DDRSS1_CTL_426_DATA 0x00000000 +#define DDRSS1_CTL_427_DATA 0x02000000 +#define DDRSS1_CTL_428_DATA 0x01000404 +#define DDRSS1_CTL_429_DATA 0x0B220B22 +#define DDRSS1_CTL_430_DATA 0x00000105 +#define DDRSS1_CTL_431_DATA 0x00010101 +#define DDRSS1_CTL_432_DATA 0x00010101 +#define DDRSS1_CTL_433_DATA 0x00010001 +#define DDRSS1_CTL_434_DATA 0x00000101 +#define DDRSS1_CTL_435_DATA 0x02000201 +#define DDRSS1_CTL_436_DATA 0x02010000 +#define DDRSS1_CTL_437_DATA 0x00000200 +#define DDRSS1_CTL_438_DATA 0x28060000 +#define DDRSS1_CTL_439_DATA 0x00000128 +#define DDRSS1_CTL_440_DATA 0xFFFFFFFF +#define DDRSS1_CTL_441_DATA 0xFFFFFFFF +#define DDRSS1_CTL_442_DATA 0x00000000 +#define DDRSS1_CTL_443_DATA 0x00000000 +#define DDRSS1_CTL_444_DATA 0x00000000 +#define DDRSS1_CTL_445_DATA 0x00000000 +#define DDRSS1_CTL_446_DATA 0x00000000 +#define DDRSS1_CTL_447_DATA 0x00000000 +#define DDRSS1_CTL_448_DATA 0x00000000 +#define DDRSS1_CTL_449_DATA 0x00000000 +#define DDRSS1_CTL_450_DATA 0x00000000 +#define DDRSS1_CTL_451_DATA 0x00000000 +#define DDRSS1_CTL_452_DATA 0x00000000 +#define DDRSS1_CTL_453_DATA 0x00000000 +#define DDRSS1_CTL_454_DATA 0x00000000 +#define DDRSS1_CTL_455_DATA 0x00000000 +#define DDRSS1_CTL_456_DATA 0x00000000 +#define DDRSS1_CTL_457_DATA 0x00000000 +#define DDRSS1_CTL_458_DATA 0x00000000 + +#define DDRSS1_PI_00_DATA 0x00000B00 +#define DDRSS1_PI_01_DATA 0x00000000 +#define DDRSS1_PI_02_DATA 0x00000000 +#define DDRSS1_PI_03_DATA 0x00000000 +#define DDRSS1_PI_04_DATA 0x00000000 +#define DDRSS1_PI_05_DATA 0x00000101 +#define DDRSS1_PI_06_DATA 0x00640000 +#define DDRSS1_PI_07_DATA 0x00000001 +#define DDRSS1_PI_08_DATA 0x00000000 +#define DDRSS1_PI_09_DATA 0x00000000 +#define DDRSS1_PI_10_DATA 0x00000000 +#define DDRSS1_PI_11_DATA 0x00000000 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 +#define DDRSS1_PI_14_DATA 0x0800000F +#define DDRSS1_PI_15_DATA 0x00000103 +#define DDRSS1_PI_16_DATA 0x00000005 +#define DDRSS1_PI_17_DATA 0x00000000 +#define DDRSS1_PI_18_DATA 0x00000000 +#define DDRSS1_PI_19_DATA 0x00000000 +#define DDRSS1_PI_20_DATA 0x00000000 +#define DDRSS1_PI_21_DATA 0x00000000 +#define DDRSS1_PI_22_DATA 0x00000000 +#define DDRSS1_PI_23_DATA 0x00000000 +#define DDRSS1_PI_24_DATA 0x00000000 +#define DDRSS1_PI_25_DATA 0x00000000 +#define DDRSS1_PI_26_DATA 0x00010100 +#define DDRSS1_PI_27_DATA 0x00280A00 +#define DDRSS1_PI_28_DATA 0x00000000 +#define DDRSS1_PI_29_DATA 0x0F000000 +#define DDRSS1_PI_30_DATA 0x00003200 +#define DDRSS1_PI_31_DATA 0x00000000 +#define DDRSS1_PI_32_DATA 0x00000000 +#define DDRSS1_PI_33_DATA 0x01010102 +#define DDRSS1_PI_34_DATA 0x00000000 +#define DDRSS1_PI_35_DATA 0x000000AA +#define DDRSS1_PI_36_DATA 0x00000055 +#define DDRSS1_PI_37_DATA 0x000000B5 +#define DDRSS1_PI_38_DATA 0x0000004A +#define DDRSS1_PI_39_DATA 0x00000056 +#define DDRSS1_PI_40_DATA 0x000000A9 +#define DDRSS1_PI_41_DATA 0x000000A9 +#define DDRSS1_PI_42_DATA 0x000000B5 +#define DDRSS1_PI_43_DATA 0x00000000 +#define DDRSS1_PI_44_DATA 0x00000000 +#define DDRSS1_PI_45_DATA 0x000F0F00 +#define DDRSS1_PI_46_DATA 0x0000001B +#define DDRSS1_PI_47_DATA 0x000007D0 +#define DDRSS1_PI_48_DATA 0x00000300 +#define DDRSS1_PI_49_DATA 0x00000000 +#define DDRSS1_PI_50_DATA 0x00000000 +#define DDRSS1_PI_51_DATA 0x01000000 +#define DDRSS1_PI_52_DATA 0x00010101 +#define DDRSS1_PI_53_DATA 0x00000000 +#define DDRSS1_PI_54_DATA 0x00030000 +#define DDRSS1_PI_55_DATA 0x0F000000 +#define DDRSS1_PI_56_DATA 0x00000017 +#define DDRSS1_PI_57_DATA 0x00000000 +#define DDRSS1_PI_58_DATA 0x00000000 +#define DDRSS1_PI_59_DATA 0x00000000 +#define DDRSS1_PI_60_DATA 0x0A0A140A +#define DDRSS1_PI_61_DATA 0x10020201 +#define DDRSS1_PI_62_DATA 0x00020805 +#define DDRSS1_PI_63_DATA 0x01000404 +#define DDRSS1_PI_64_DATA 0x00000000 +#define DDRSS1_PI_65_DATA 0x00000000 +#define DDRSS1_PI_66_DATA 0x00000100 +#define DDRSS1_PI_67_DATA 0x0002020F +#define DDRSS1_PI_68_DATA 0x00340000 +#define DDRSS1_PI_69_DATA 0x00000000 +#define DDRSS1_PI_70_DATA 0x00000000 +#define DDRSS1_PI_71_DATA 0x0000FFFF +#define DDRSS1_PI_72_DATA 0x01000000 +#define DDRSS1_PI_73_DATA 0x00080000 +#define DDRSS1_PI_74_DATA 0x02000200 +#define DDRSS1_PI_75_DATA 0x01000100 +#define DDRSS1_PI_76_DATA 0x01000000 +#define DDRSS1_PI_77_DATA 0x02000200 +#define DDRSS1_PI_78_DATA 0x00000200 +#define DDRSS1_PI_79_DATA 0x00000000 +#define DDRSS1_PI_80_DATA 0x00000000 +#define DDRSS1_PI_81_DATA 0x00000000 +#define DDRSS1_PI_82_DATA 0x00000000 +#define DDRSS1_PI_83_DATA 0x00000000 +#define DDRSS1_PI_84_DATA 0x00000000 +#define DDRSS1_PI_85_DATA 0x00000000 +#define DDRSS1_PI_86_DATA 0x00000000 +#define DDRSS1_PI_87_DATA 0x00000000 +#define DDRSS1_PI_88_DATA 0x00000000 +#define DDRSS1_PI_89_DATA 0x00000000 +#define DDRSS1_PI_90_DATA 0x00000000 +#define DDRSS1_PI_91_DATA 0x00000400 +#define DDRSS1_PI_92_DATA 0x02010000 +#define DDRSS1_PI_93_DATA 0x00080003 +#define DDRSS1_PI_94_DATA 0x00080000 +#define DDRSS1_PI_95_DATA 0x00000001 +#define DDRSS1_PI_96_DATA 0x00000000 +#define DDRSS1_PI_97_DATA 0x0000AA00 +#define DDRSS1_PI_98_DATA 0x00000000 +#define DDRSS1_PI_99_DATA 0x00000000 +#define DDRSS1_PI_100_DATA 0x00010000 +#define DDRSS1_PI_101_DATA 0x00000000 +#define DDRSS1_PI_102_DATA 0x00000000 +#define DDRSS1_PI_103_DATA 0x00000000 +#define DDRSS1_PI_104_DATA 0x00000000 +#define DDRSS1_PI_105_DATA 0x00000000 +#define DDRSS1_PI_106_DATA 0x00000000 +#define DDRSS1_PI_107_DATA 0x00000000 +#define DDRSS1_PI_108_DATA 0x00000000 +#define DDRSS1_PI_109_DATA 0x00000000 +#define DDRSS1_PI_110_DATA 0x00000000 +#define DDRSS1_PI_111_DATA 0x00000000 +#define DDRSS1_PI_112_DATA 0x00000000 +#define DDRSS1_PI_113_DATA 0x00000000 +#define DDRSS1_PI_114_DATA 0x00000000 +#define DDRSS1_PI_115_DATA 0x00000000 +#define DDRSS1_PI_116_DATA 0x00000000 +#define DDRSS1_PI_117_DATA 0x00000000 +#define DDRSS1_PI_118_DATA 0x00000000 +#define DDRSS1_PI_119_DATA 0x00000000 +#define DDRSS1_PI_120_DATA 0x00000000 +#define DDRSS1_PI_121_DATA 0x00000000 +#define DDRSS1_PI_122_DATA 0x00000000 +#define DDRSS1_PI_123_DATA 0x00000000 +#define DDRSS1_PI_124_DATA 0x00000000 +#define DDRSS1_PI_125_DATA 0x00000008 +#define DDRSS1_PI_126_DATA 0x00000000 +#define DDRSS1_PI_127_DATA 0x00000000 +#define DDRSS1_PI_128_DATA 0x00000000 +#define DDRSS1_PI_129_DATA 0x00000000 +#define DDRSS1_PI_130_DATA 0x00000000 +#define DDRSS1_PI_131_DATA 0x00000000 +#define DDRSS1_PI_132_DATA 0x00000000 +#define DDRSS1_PI_133_DATA 0x00000000 +#define DDRSS1_PI_134_DATA 0x00000002 +#define DDRSS1_PI_135_DATA 0x00000000 +#define DDRSS1_PI_136_DATA 0x00000000 +#define DDRSS1_PI_137_DATA 0x0000000A +#define DDRSS1_PI_138_DATA 0x00000019 +#define DDRSS1_PI_139_DATA 0x00000100 +#define DDRSS1_PI_140_DATA 0x00000000 +#define DDRSS1_PI_141_DATA 0x00000000 +#define DDRSS1_PI_142_DATA 0x00000000 +#define DDRSS1_PI_143_DATA 0x00000000 +#define DDRSS1_PI_144_DATA 0x01000000 +#define DDRSS1_PI_145_DATA 0x00010003 +#define DDRSS1_PI_146_DATA 0x02000101 +#define DDRSS1_PI_147_DATA 0x01030001 +#define DDRSS1_PI_148_DATA 0x00010400 +#define DDRSS1_PI_149_DATA 0x06000105 +#define DDRSS1_PI_150_DATA 0x01070001 +#define DDRSS1_PI_151_DATA 0x00000000 +#define DDRSS1_PI_152_DATA 0x00000000 +#define DDRSS1_PI_153_DATA 0x00000000 +#define DDRSS1_PI_154_DATA 0x00010001 +#define DDRSS1_PI_155_DATA 0x00000000 +#define DDRSS1_PI_156_DATA 0x00000000 +#define DDRSS1_PI_157_DATA 0x00000000 +#define DDRSS1_PI_158_DATA 0x00000000 +#define DDRSS1_PI_159_DATA 0x00000401 +#define DDRSS1_PI_160_DATA 0x00000000 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 +#define DDRSS1_PI_164_DATA 0x00000034 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 +#define DDRSS1_PI_167_DATA 0x02000200 +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 +#define DDRSS1_PI_171_DATA 0x0000032B +#define DDRSS1_PI_172_DATA 0x00001035 +#define DDRSS1_PI_173_DATA 0x0000032B +#define DDRSS1_PI_174_DATA 0x04001035 +#define DDRSS1_PI_175_DATA 0x01010404 +#define DDRSS1_PI_176_DATA 0x00001500 +#define DDRSS1_PI_177_DATA 0x00150015 +#define DDRSS1_PI_178_DATA 0x01000100 +#define DDRSS1_PI_179_DATA 0x00000100 +#define DDRSS1_PI_180_DATA 0x00000000 +#define DDRSS1_PI_181_DATA 0x01010101 +#define DDRSS1_PI_182_DATA 0x00000000 +#define DDRSS1_PI_183_DATA 0x00000000 +#define DDRSS1_PI_184_DATA 0x00000000 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 +#define DDRSS1_PI_187_DATA 0x00040402 +#define DDRSS1_PI_188_DATA 0x000D0035 +#define DDRSS1_PI_189_DATA 0x00218049 +#define DDRSS1_PI_190_DATA 0x00218049 +#define DDRSS1_PI_191_DATA 0x01000101 +#define DDRSS1_PI_192_DATA 0x0004000E +#define DDRSS1_PI_193_DATA 0x00040216 +#define DDRSS1_PI_194_DATA 0x01000216 +#define DDRSS1_PI_195_DATA 0x000F000F +#define DDRSS1_PI_196_DATA 0x02170100 +#define DDRSS1_PI_197_DATA 0x01000217 +#define DDRSS1_PI_198_DATA 0x02170217 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B +#define DDRSS1_PI_201_DATA 0x0A070601 +#define DDRSS1_PI_202_DATA 0x1F130A0D +#define DDRSS1_PI_203_DATA 0x1F130A14 +#define DDRSS1_PI_204_DATA 0x0000C014 +#define DDRSS1_PI_205_DATA 0x00C01000 +#define DDRSS1_PI_206_DATA 0x00C01000 +#define DDRSS1_PI_207_DATA 0x00021000 +#define DDRSS1_PI_208_DATA 0x0024000E +#define DDRSS1_PI_209_DATA 0x00240216 +#define DDRSS1_PI_210_DATA 0x00110216 +#define DDRSS1_PI_211_DATA 0x32000056 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 +#define DDRSS1_PI_214_DATA 0x03013212 +#define DDRSS1_PI_215_DATA 0x00003600 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 +#define DDRSS1_PI_220_DATA 0x0A032001 +#define DDRSS1_PI_221_DATA 0x2C31110A +#define DDRSS1_PI_222_DATA 0x00002918 +#define DDRSS1_PI_223_DATA 0x6000838E +#define DDRSS1_PI_224_DATA 0x1E202008 +#define DDRSS1_PI_225_DATA 0x2C311116 +#define DDRSS1_PI_226_DATA 0x00002918 +#define DDRSS1_PI_227_DATA 0x6000838E +#define DDRSS1_PI_228_DATA 0x1E202008 +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 +#define DDRSS1_PI_235_DATA 0x033B0016 +#define DDRSS1_PI_236_DATA 0x0303033B +#define DDRSS1_PI_237_DATA 0x002AF803 +#define DDRSS1_PI_238_DATA 0x0001ADAF +#define DDRSS1_PI_239_DATA 0x00000005 +#define DDRSS1_PI_240_DATA 0x0000006E +#define DDRSS1_PI_241_DATA 0x00000016 +#define DDRSS1_PI_242_DATA 0x000681C8 +#define DDRSS1_PI_243_DATA 0x0001ADAF +#define DDRSS1_PI_244_DATA 0x00000005 +#define DDRSS1_PI_245_DATA 0x000010A9 +#define DDRSS1_PI_246_DATA 0x0000033B +#define DDRSS1_PI_247_DATA 0x000681C8 +#define DDRSS1_PI_248_DATA 0x0001ADAF +#define DDRSS1_PI_249_DATA 0x00000005 +#define DDRSS1_PI_250_DATA 0x000010A9 +#define DDRSS1_PI_251_DATA 0x0100033B +#define DDRSS1_PI_252_DATA 0x00370040 +#define DDRSS1_PI_253_DATA 0x00010008 +#define DDRSS1_PI_254_DATA 0x08550040 +#define DDRSS1_PI_255_DATA 0x00010040 +#define DDRSS1_PI_256_DATA 0x08550040 +#define DDRSS1_PI_257_DATA 0x00000340 +#define DDRSS1_PI_258_DATA 0x006B006B +#define DDRSS1_PI_259_DATA 0x08040404 +#define DDRSS1_PI_260_DATA 0x00000055 +#define DDRSS1_PI_261_DATA 0x55083C5A +#define DDRSS1_PI_262_DATA 0x5A000000 +#define DDRSS1_PI_263_DATA 0x0055083C +#define DDRSS1_PI_264_DATA 0x3C5A0000 +#define DDRSS1_PI_265_DATA 0x00005508 +#define DDRSS1_PI_266_DATA 0x0C3C5A00 +#define DDRSS1_PI_267_DATA 0x080F0E0D +#define DDRSS1_PI_268_DATA 0x000B0A09 +#define DDRSS1_PI_269_DATA 0x00030201 +#define DDRSS1_PI_270_DATA 0x01000000 +#define DDRSS1_PI_271_DATA 0x04020201 +#define DDRSS1_PI_272_DATA 0x00080804 +#define DDRSS1_PI_273_DATA 0x00000000 +#define DDRSS1_PI_274_DATA 0x00000000 +#define DDRSS1_PI_275_DATA 0x00F30084 +#define DDRSS1_PI_276_DATA 0x00160000 +#define DDRSS1_PI_277_DATA 0x35F33FF4 +#define DDRSS1_PI_278_DATA 0x00160F27 +#define DDRSS1_PI_279_DATA 0x35F33FF4 +#define DDRSS1_PI_280_DATA 0x00160F27 +#define DDRSS1_PI_281_DATA 0x00F30084 +#define DDRSS1_PI_282_DATA 0x00160000 +#define DDRSS1_PI_283_DATA 0x35F33FF4 +#define DDRSS1_PI_284_DATA 0x00160F27 +#define DDRSS1_PI_285_DATA 0x35F33FF4 +#define DDRSS1_PI_286_DATA 0x00160F27 +#define DDRSS1_PI_287_DATA 0x00F30084 +#define DDRSS1_PI_288_DATA 0x00160000 +#define DDRSS1_PI_289_DATA 0x35F33FF4 +#define DDRSS1_PI_290_DATA 0x00160F27 +#define DDRSS1_PI_291_DATA 0x35F33FF4 +#define DDRSS1_PI_292_DATA 0x00160F27 +#define DDRSS1_PI_293_DATA 0x00F30084 +#define DDRSS1_PI_294_DATA 0x00160000 +#define DDRSS1_PI_295_DATA 0x35F33FF4 +#define DDRSS1_PI_296_DATA 0x00160F27 +#define DDRSS1_PI_297_DATA 0x35F33FF4 +#define DDRSS1_PI_298_DATA 0x00160F27 +#define DDRSS1_PI_299_DATA 0x00000000 + +#define DDRSS1_PHY_00_DATA 0x000004F0 +#define DDRSS1_PHY_01_DATA 0x00000000 +#define DDRSS1_PHY_02_DATA 0x00030200 +#define DDRSS1_PHY_03_DATA 0x00000000 +#define DDRSS1_PHY_04_DATA 0x00000000 +#define DDRSS1_PHY_05_DATA 0x01030000 +#define DDRSS1_PHY_06_DATA 0x00010000 +#define DDRSS1_PHY_07_DATA 0x01030004 +#define DDRSS1_PHY_08_DATA 0x01000000 +#define DDRSS1_PHY_09_DATA 0x00000000 +#define DDRSS1_PHY_10_DATA 0x00000000 +#define DDRSS1_PHY_11_DATA 0x01000001 +#define DDRSS1_PHY_12_DATA 0x00000200 +#define DDRSS1_PHY_13_DATA 0x000800C0 +#define DDRSS1_PHY_14_DATA 0x060100CC +#define DDRSS1_PHY_15_DATA 0x00030066 +#define DDRSS1_PHY_16_DATA 0x00000000 +#define DDRSS1_PHY_17_DATA 0x00000301 +#define DDRSS1_PHY_18_DATA 0x0000AAAA +#define DDRSS1_PHY_19_DATA 0x00005555 +#define DDRSS1_PHY_20_DATA 0x0000B5B5 +#define DDRSS1_PHY_21_DATA 0x00004A4A +#define DDRSS1_PHY_22_DATA 0x00005656 +#define DDRSS1_PHY_23_DATA 0x0000A9A9 +#define DDRSS1_PHY_24_DATA 0x0000A9A9 +#define DDRSS1_PHY_25_DATA 0x0000B5B5 +#define DDRSS1_PHY_26_DATA 0x00000000 +#define DDRSS1_PHY_27_DATA 0x00000000 +#define DDRSS1_PHY_28_DATA 0x2A000000 +#define DDRSS1_PHY_29_DATA 0x00000808 +#define DDRSS1_PHY_30_DATA 0x0F000000 +#define DDRSS1_PHY_31_DATA 0x00000F08 +#define DDRSS1_PHY_32_DATA 0x10400000 +#define DDRSS1_PHY_33_DATA 0x0C002006 +#define DDRSS1_PHY_34_DATA 0x00000000 +#define DDRSS1_PHY_35_DATA 0x00000000 +#define DDRSS1_PHY_36_DATA 0x55555555 +#define DDRSS1_PHY_37_DATA 0xAAAAAAAA +#define DDRSS1_PHY_38_DATA 0x55555555 +#define DDRSS1_PHY_39_DATA 0xAAAAAAAA +#define DDRSS1_PHY_40_DATA 0x00005555 +#define DDRSS1_PHY_41_DATA 0x01000100 +#define DDRSS1_PHY_42_DATA 0x00800180 +#define DDRSS1_PHY_43_DATA 0x00000001 +#define DDRSS1_PHY_44_DATA 0x00000000 +#define DDRSS1_PHY_45_DATA 0x00000000 +#define DDRSS1_PHY_46_DATA 0x00000000 +#define DDRSS1_PHY_47_DATA 0x00000000 +#define DDRSS1_PHY_48_DATA 0x00000000 +#define DDRSS1_PHY_49_DATA 0x00000000 +#define DDRSS1_PHY_50_DATA 0x00000000 +#define DDRSS1_PHY_51_DATA 0x00000000 +#define DDRSS1_PHY_52_DATA 0x00000000 +#define DDRSS1_PHY_53_DATA 0x00000000 +#define DDRSS1_PHY_54_DATA 0x00000000 +#define DDRSS1_PHY_55_DATA 0x00000000 +#define DDRSS1_PHY_56_DATA 0x00000000 +#define DDRSS1_PHY_57_DATA 0x00000000 +#define DDRSS1_PHY_58_DATA 0x00000000 +#define DDRSS1_PHY_59_DATA 0x00000000 +#define DDRSS1_PHY_60_DATA 0x00000000 +#define DDRSS1_PHY_61_DATA 0x00000000 +#define DDRSS1_PHY_62_DATA 0x00000000 +#define DDRSS1_PHY_63_DATA 0x00000000 +#define DDRSS1_PHY_64_DATA 0x00000000 +#define DDRSS1_PHY_65_DATA 0x00000000 +#define DDRSS1_PHY_66_DATA 0x00000104 +#define DDRSS1_PHY_67_DATA 0x00000120 +#define DDRSS1_PHY_68_DATA 0x00000000 +#define DDRSS1_PHY_69_DATA 0x00000000 +#define DDRSS1_PHY_70_DATA 0x00000000 +#define DDRSS1_PHY_71_DATA 0x00000000 +#define DDRSS1_PHY_72_DATA 0x00000000 +#define DDRSS1_PHY_73_DATA 0x00000000 +#define DDRSS1_PHY_74_DATA 0x00000000 +#define DDRSS1_PHY_75_DATA 0x00000001 +#define DDRSS1_PHY_76_DATA 0x07FF0000 +#define DDRSS1_PHY_77_DATA 0x0080081F +#define DDRSS1_PHY_78_DATA 0x00081020 +#define DDRSS1_PHY_79_DATA 0x04010000 +#define DDRSS1_PHY_80_DATA 0x00000000 +#define DDRSS1_PHY_81_DATA 0x00000000 +#define DDRSS1_PHY_82_DATA 0x00000000 +#define DDRSS1_PHY_83_DATA 0x00000100 +#define DDRSS1_PHY_84_DATA 0x01CC0C01 +#define DDRSS1_PHY_85_DATA 0x1003CC0C +#define DDRSS1_PHY_86_DATA 0x20000140 +#define DDRSS1_PHY_87_DATA 0x07FF0200 +#define DDRSS1_PHY_88_DATA 0x0000DD01 +#define DDRSS1_PHY_89_DATA 0x10100303 +#define DDRSS1_PHY_90_DATA 0x10101010 +#define DDRSS1_PHY_91_DATA 0x10101010 +#define DDRSS1_PHY_92_DATA 0x00021010 +#define DDRSS1_PHY_93_DATA 0x00100010 +#define DDRSS1_PHY_94_DATA 0x00100010 +#define DDRSS1_PHY_95_DATA 0x00100010 +#define DDRSS1_PHY_96_DATA 0x00100010 +#define DDRSS1_PHY_97_DATA 0x00050010 +#define DDRSS1_PHY_98_DATA 0x51517041 +#define DDRSS1_PHY_99_DATA 0x31C06001 +#define DDRSS1_PHY_100_DATA 0x07AB01AB +#define DDRSS1_PHY_101_DATA 0x00C0C001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 +#define DDRSS1_PHY_103_DATA 0x10001000 +#define DDRSS1_PHY_104_DATA 0x0C083E42 +#define DDRSS1_PHY_105_DATA 0x0F0C3701 +#define DDRSS1_PHY_106_DATA 0x01000140 +#define DDRSS1_PHY_107_DATA 0x0C000420 +#define DDRSS1_PHY_108_DATA 0x00000198 +#define DDRSS1_PHY_109_DATA 0x0A0000D0 +#define DDRSS1_PHY_110_DATA 0x00030200 +#define DDRSS1_PHY_111_DATA 0x02800000 +#define DDRSS1_PHY_112_DATA 0x80800000 +#define DDRSS1_PHY_113_DATA 0x000E2010 +#define DDRSS1_PHY_114_DATA 0x76543210 +#define DDRSS1_PHY_115_DATA 0x00000008 +#define DDRSS1_PHY_116_DATA 0x02800280 +#define DDRSS1_PHY_117_DATA 0x02800280 +#define DDRSS1_PHY_118_DATA 0x02800280 +#define DDRSS1_PHY_119_DATA 0x02800280 +#define DDRSS1_PHY_120_DATA 0x00000280 +#define DDRSS1_PHY_121_DATA 0x0000A000 +#define DDRSS1_PHY_122_DATA 0x00A000A0 +#define DDRSS1_PHY_123_DATA 0x00A000A0 +#define DDRSS1_PHY_124_DATA 0x00A000A0 +#define DDRSS1_PHY_125_DATA 0x00A000A0 +#define DDRSS1_PHY_126_DATA 0x00A000A0 +#define DDRSS1_PHY_127_DATA 0x00A000A0 +#define DDRSS1_PHY_128_DATA 0x00A000A0 +#define DDRSS1_PHY_129_DATA 0x00A000A0 +#define DDRSS1_PHY_130_DATA 0x01C200A0 +#define DDRSS1_PHY_131_DATA 0x01A00005 +#define DDRSS1_PHY_132_DATA 0x00000000 +#define DDRSS1_PHY_133_DATA 0x00000000 +#define DDRSS1_PHY_134_DATA 0x00080200 +#define DDRSS1_PHY_135_DATA 0x00000000 +#define DDRSS1_PHY_136_DATA 0x20202000 +#define DDRSS1_PHY_137_DATA 0x20202020 +#define DDRSS1_PHY_138_DATA 0xF0F02020 +#define DDRSS1_PHY_139_DATA 0x00000000 +#define DDRSS1_PHY_140_DATA 0x00000000 +#define DDRSS1_PHY_141_DATA 0x00000000 +#define DDRSS1_PHY_142_DATA 0x00000000 +#define DDRSS1_PHY_143_DATA 0x00000000 +#define DDRSS1_PHY_144_DATA 0x00000000 +#define DDRSS1_PHY_145_DATA 0x00000000 +#define DDRSS1_PHY_146_DATA 0x00000000 +#define DDRSS1_PHY_147_DATA 0x00000000 +#define DDRSS1_PHY_148_DATA 0x00000000 +#define DDRSS1_PHY_149_DATA 0x00000000 +#define DDRSS1_PHY_150_DATA 0x00000000 +#define DDRSS1_PHY_151_DATA 0x00000000 +#define DDRSS1_PHY_152_DATA 0x00000000 +#define DDRSS1_PHY_153_DATA 0x00000000 +#define DDRSS1_PHY_154_DATA 0x00000000 +#define DDRSS1_PHY_155_DATA 0x00000000 +#define DDRSS1_PHY_156_DATA 0x00000000 +#define DDRSS1_PHY_157_DATA 0x00000000 +#define DDRSS1_PHY_158_DATA 0x00000000 +#define DDRSS1_PHY_159_DATA 0x00000000 +#define DDRSS1_PHY_160_DATA 0x00000000 +#define DDRSS1_PHY_161_DATA 0x00000000 +#define DDRSS1_PHY_162_DATA 0x00000000 +#define DDRSS1_PHY_163_DATA 0x00000000 +#define DDRSS1_PHY_164_DATA 0x00000000 +#define DDRSS1_PHY_165_DATA 0x00000000 +#define DDRSS1_PHY_166_DATA 0x00000000 +#define DDRSS1_PHY_167_DATA 0x00000000 +#define DDRSS1_PHY_168_DATA 0x00000000 +#define DDRSS1_PHY_169_DATA 0x00000000 +#define DDRSS1_PHY_170_DATA 0x00000000 +#define DDRSS1_PHY_171_DATA 0x00000000 +#define DDRSS1_PHY_172_DATA 0x00000000 +#define DDRSS1_PHY_173_DATA 0x00000000 +#define DDRSS1_PHY_174_DATA 0x00000000 +#define DDRSS1_PHY_175_DATA 0x00000000 +#define DDRSS1_PHY_176_DATA 0x00000000 +#define DDRSS1_PHY_177_DATA 0x00000000 +#define DDRSS1_PHY_178_DATA 0x00000000 +#define DDRSS1_PHY_179_DATA 0x00000000 +#define DDRSS1_PHY_180_DATA 0x00000000 +#define DDRSS1_PHY_181_DATA 0x00000000 +#define DDRSS1_PHY_182_DATA 0x00000000 +#define DDRSS1_PHY_183_DATA 0x00000000 +#define DDRSS1_PHY_184_DATA 0x00000000 +#define DDRSS1_PHY_185_DATA 0x00000000 +#define DDRSS1_PHY_186_DATA 0x00000000 +#define DDRSS1_PHY_187_DATA 0x00000000 +#define DDRSS1_PHY_188_DATA 0x00000000 +#define DDRSS1_PHY_189_DATA 0x00000000 +#define DDRSS1_PHY_190_DATA 0x00000000 +#define DDRSS1_PHY_191_DATA 0x00000000 +#define DDRSS1_PHY_192_DATA 0x00000000 +#define DDRSS1_PHY_193_DATA 0x00000000 +#define DDRSS1_PHY_194_DATA 0x00000000 +#define DDRSS1_PHY_195_DATA 0x00000000 +#define DDRSS1_PHY_196_DATA 0x00000000 +#define DDRSS1_PHY_197_DATA 0x00000000 +#define DDRSS1_PHY_198_DATA 0x00000000 +#define DDRSS1_PHY_199_DATA 0x00000000 +#define DDRSS1_PHY_200_DATA 0x00000000 +#define DDRSS1_PHY_201_DATA 0x00000000 +#define DDRSS1_PHY_202_DATA 0x00000000 +#define DDRSS1_PHY_203_DATA 0x00000000 +#define DDRSS1_PHY_204_DATA 0x00000000 +#define DDRSS1_PHY_205_DATA 0x00000000 +#define DDRSS1_PHY_206_DATA 0x00000000 +#define DDRSS1_PHY_207_DATA 0x00000000 +#define DDRSS1_PHY_208_DATA 0x00000000 +#define DDRSS1_PHY_209_DATA 0x00000000 +#define DDRSS1_PHY_210_DATA 0x00000000 +#define DDRSS1_PHY_211_DATA 0x00000000 +#define DDRSS1_PHY_212_DATA 0x00000000 +#define DDRSS1_PHY_213_DATA 0x00000000 +#define DDRSS1_PHY_214_DATA 0x00000000 +#define DDRSS1_PHY_215_DATA 0x00000000 +#define DDRSS1_PHY_216_DATA 0x00000000 +#define DDRSS1_PHY_217_DATA 0x00000000 +#define DDRSS1_PHY_218_DATA 0x00000000 +#define DDRSS1_PHY_219_DATA 0x00000000 +#define DDRSS1_PHY_220_DATA 0x00000000 +#define DDRSS1_PHY_221_DATA 0x00000000 +#define DDRSS1_PHY_222_DATA 0x00000000 +#define DDRSS1_PHY_223_DATA 0x00000000 +#define DDRSS1_PHY_224_DATA 0x00000000 +#define DDRSS1_PHY_225_DATA 0x00000000 +#define DDRSS1_PHY_226_DATA 0x00000000 +#define DDRSS1_PHY_227_DATA 0x00000000 +#define DDRSS1_PHY_228_DATA 0x00000000 +#define DDRSS1_PHY_229_DATA 0x00000000 +#define DDRSS1_PHY_230_DATA 0x00000000 +#define DDRSS1_PHY_231_DATA 0x00000000 +#define DDRSS1_PHY_232_DATA 0x00000000 +#define DDRSS1_PHY_233_DATA 0x00000000 +#define DDRSS1_PHY_234_DATA 0x00000000 +#define DDRSS1_PHY_235_DATA 0x00000000 +#define DDRSS1_PHY_236_DATA 0x00000000 +#define DDRSS1_PHY_237_DATA 0x00000000 +#define DDRSS1_PHY_238_DATA 0x00000000 +#define DDRSS1_PHY_239_DATA 0x00000000 +#define DDRSS1_PHY_240_DATA 0x00000000 +#define DDRSS1_PHY_241_DATA 0x00000000 +#define DDRSS1_PHY_242_DATA 0x00000000 +#define DDRSS1_PHY_243_DATA 0x00000000 +#define DDRSS1_PHY_244_DATA 0x00000000 +#define DDRSS1_PHY_245_DATA 0x00000000 +#define DDRSS1_PHY_246_DATA 0x00000000 +#define DDRSS1_PHY_247_DATA 0x00000000 +#define DDRSS1_PHY_248_DATA 0x00000000 +#define DDRSS1_PHY_249_DATA 0x00000000 +#define DDRSS1_PHY_250_DATA 0x00000000 +#define DDRSS1_PHY_251_DATA 0x00000000 +#define DDRSS1_PHY_252_DATA 0x00000000 +#define DDRSS1_PHY_253_DATA 0x00000000 +#define DDRSS1_PHY_254_DATA 0x00000000 +#define DDRSS1_PHY_255_DATA 0x00000000 +#define DDRSS1_PHY_256_DATA 0x000004F0 +#define DDRSS1_PHY_257_DATA 0x00000000 +#define DDRSS1_PHY_258_DATA 0x00030200 +#define DDRSS1_PHY_259_DATA 0x00000000 +#define DDRSS1_PHY_260_DATA 0x00000000 +#define DDRSS1_PHY_261_DATA 0x01030000 +#define DDRSS1_PHY_262_DATA 0x00010000 +#define DDRSS1_PHY_263_DATA 0x01030004 +#define DDRSS1_PHY_264_DATA 0x01000000 +#define DDRSS1_PHY_265_DATA 0x00000000 +#define DDRSS1_PHY_266_DATA 0x00000000 +#define DDRSS1_PHY_267_DATA 0x01000001 +#define DDRSS1_PHY_268_DATA 0x00000200 +#define DDRSS1_PHY_269_DATA 0x000800C0 +#define DDRSS1_PHY_270_DATA 0x060100CC +#define DDRSS1_PHY_271_DATA 0x00030066 +#define DDRSS1_PHY_272_DATA 0x00000000 +#define DDRSS1_PHY_273_DATA 0x00000301 +#define DDRSS1_PHY_274_DATA 0x0000AAAA +#define DDRSS1_PHY_275_DATA 0x00005555 +#define DDRSS1_PHY_276_DATA 0x0000B5B5 +#define DDRSS1_PHY_277_DATA 0x00004A4A +#define DDRSS1_PHY_278_DATA 0x00005656 +#define DDRSS1_PHY_279_DATA 0x0000A9A9 +#define DDRSS1_PHY_280_DATA 0x0000A9A9 +#define DDRSS1_PHY_281_DATA 0x0000B5B5 +#define DDRSS1_PHY_282_DATA 0x00000000 +#define DDRSS1_PHY_283_DATA 0x00000000 +#define DDRSS1_PHY_284_DATA 0x2A000000 +#define DDRSS1_PHY_285_DATA 0x00000808 +#define DDRSS1_PHY_286_DATA 0x0F000000 +#define DDRSS1_PHY_287_DATA 0x00000F08 +#define DDRSS1_PHY_288_DATA 0x10400000 +#define DDRSS1_PHY_289_DATA 0x0C002006 +#define DDRSS1_PHY_290_DATA 0x00000000 +#define DDRSS1_PHY_291_DATA 0x00000000 +#define DDRSS1_PHY_292_DATA 0x55555555 +#define DDRSS1_PHY_293_DATA 0xAAAAAAAA +#define DDRSS1_PHY_294_DATA 0x55555555 +#define DDRSS1_PHY_295_DATA 0xAAAAAAAA +#define DDRSS1_PHY_296_DATA 0x00005555 +#define DDRSS1_PHY_297_DATA 0x01000100 +#define DDRSS1_PHY_298_DATA 0x00800180 +#define DDRSS1_PHY_299_DATA 0x00000000 +#define DDRSS1_PHY_300_DATA 0x00000000 +#define DDRSS1_PHY_301_DATA 0x00000000 +#define DDRSS1_PHY_302_DATA 0x00000000 +#define DDRSS1_PHY_303_DATA 0x00000000 +#define DDRSS1_PHY_304_DATA 0x00000000 +#define DDRSS1_PHY_305_DATA 0x00000000 +#define DDRSS1_PHY_306_DATA 0x00000000 +#define DDRSS1_PHY_307_DATA 0x00000000 +#define DDRSS1_PHY_308_DATA 0x00000000 +#define DDRSS1_PHY_309_DATA 0x00000000 +#define DDRSS1_PHY_310_DATA 0x00000000 +#define DDRSS1_PHY_311_DATA 0x00000000 +#define DDRSS1_PHY_312_DATA 0x00000000 +#define DDRSS1_PHY_313_DATA 0x00000000 +#define DDRSS1_PHY_314_DATA 0x00000000 +#define DDRSS1_PHY_315_DATA 0x00000000 +#define DDRSS1_PHY_316_DATA 0x00000000 +#define DDRSS1_PHY_317_DATA 0x00000000 +#define DDRSS1_PHY_318_DATA 0x00000000 +#define DDRSS1_PHY_319_DATA 0x00000000 +#define DDRSS1_PHY_320_DATA 0x00000000 +#define DDRSS1_PHY_321_DATA 0x00000000 +#define DDRSS1_PHY_322_DATA 0x00000104 +#define DDRSS1_PHY_323_DATA 0x00000120 +#define DDRSS1_PHY_324_DATA 0x00000000 +#define DDRSS1_PHY_325_DATA 0x00000000 +#define DDRSS1_PHY_326_DATA 0x00000000 +#define DDRSS1_PHY_327_DATA 0x00000000 +#define DDRSS1_PHY_328_DATA 0x00000000 +#define DDRSS1_PHY_329_DATA 0x00000000 +#define DDRSS1_PHY_330_DATA 0x00000000 +#define DDRSS1_PHY_331_DATA 0x00000001 +#define DDRSS1_PHY_332_DATA 0x07FF0000 +#define DDRSS1_PHY_333_DATA 0x0080081F +#define DDRSS1_PHY_334_DATA 0x00081020 +#define DDRSS1_PHY_335_DATA 0x04010000 +#define DDRSS1_PHY_336_DATA 0x00000000 +#define DDRSS1_PHY_337_DATA 0x00000000 +#define DDRSS1_PHY_338_DATA 0x00000000 +#define DDRSS1_PHY_339_DATA 0x00000100 +#define DDRSS1_PHY_340_DATA 0x01CC0C01 +#define DDRSS1_PHY_341_DATA 0x1003CC0C +#define DDRSS1_PHY_342_DATA 0x20000140 +#define DDRSS1_PHY_343_DATA 0x07FF0200 +#define DDRSS1_PHY_344_DATA 0x0000DD01 +#define DDRSS1_PHY_345_DATA 0x10100303 +#define DDRSS1_PHY_346_DATA 0x10101010 +#define DDRSS1_PHY_347_DATA 0x10101010 +#define DDRSS1_PHY_348_DATA 0x00021010 +#define DDRSS1_PHY_349_DATA 0x00100010 +#define DDRSS1_PHY_350_DATA 0x00100010 +#define DDRSS1_PHY_351_DATA 0x00100010 +#define DDRSS1_PHY_352_DATA 0x00100010 +#define DDRSS1_PHY_353_DATA 0x00050010 +#define DDRSS1_PHY_354_DATA 0x51517041 +#define DDRSS1_PHY_355_DATA 0x31C06001 +#define DDRSS1_PHY_356_DATA 0x07AB01AB +#define DDRSS1_PHY_357_DATA 0x00C0C001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 +#define DDRSS1_PHY_359_DATA 0x10001000 +#define DDRSS1_PHY_360_DATA 0x0C083E42 +#define DDRSS1_PHY_361_DATA 0x0F0C3701 +#define DDRSS1_PHY_362_DATA 0x01000140 +#define DDRSS1_PHY_363_DATA 0x0C000420 +#define DDRSS1_PHY_364_DATA 0x00000198 +#define DDRSS1_PHY_365_DATA 0x0A0000D0 +#define DDRSS1_PHY_366_DATA 0x00030200 +#define DDRSS1_PHY_367_DATA 0x02800000 +#define DDRSS1_PHY_368_DATA 0x80800000 +#define DDRSS1_PHY_369_DATA 0x000E2010 +#define DDRSS1_PHY_370_DATA 0x76543210 +#define DDRSS1_PHY_371_DATA 0x00000008 +#define DDRSS1_PHY_372_DATA 0x02800280 +#define DDRSS1_PHY_373_DATA 0x02800280 +#define DDRSS1_PHY_374_DATA 0x02800280 +#define DDRSS1_PHY_375_DATA 0x02800280 +#define DDRSS1_PHY_376_DATA 0x00000280 +#define DDRSS1_PHY_377_DATA 0x0000A000 +#define DDRSS1_PHY_378_DATA 0x00A000A0 +#define DDRSS1_PHY_379_DATA 0x00A000A0 +#define DDRSS1_PHY_380_DATA 0x00A000A0 +#define DDRSS1_PHY_381_DATA 0x00A000A0 +#define DDRSS1_PHY_382_DATA 0x00A000A0 +#define DDRSS1_PHY_383_DATA 0x00A000A0 +#define DDRSS1_PHY_384_DATA 0x00A000A0 +#define DDRSS1_PHY_385_DATA 0x00A000A0 +#define DDRSS1_PHY_386_DATA 0x01C200A0 +#define DDRSS1_PHY_387_DATA 0x01A00005 +#define DDRSS1_PHY_388_DATA 0x00000000 +#define DDRSS1_PHY_389_DATA 0x00000000 +#define DDRSS1_PHY_390_DATA 0x00080200 +#define DDRSS1_PHY_391_DATA 0x00000000 +#define DDRSS1_PHY_392_DATA 0x20202000 +#define DDRSS1_PHY_393_DATA 0x20202020 +#define DDRSS1_PHY_394_DATA 0xF0F02020 +#define DDRSS1_PHY_395_DATA 0x00000000 +#define DDRSS1_PHY_396_DATA 0x00000000 +#define DDRSS1_PHY_397_DATA 0x00000000 +#define DDRSS1_PHY_398_DATA 0x00000000 +#define DDRSS1_PHY_399_DATA 0x00000000 +#define DDRSS1_PHY_400_DATA 0x00000000 +#define DDRSS1_PHY_401_DATA 0x00000000 +#define DDRSS1_PHY_402_DATA 0x00000000 +#define DDRSS1_PHY_403_DATA 0x00000000 +#define DDRSS1_PHY_404_DATA 0x00000000 +#define DDRSS1_PHY_405_DATA 0x00000000 +#define DDRSS1_PHY_406_DATA 0x00000000 +#define DDRSS1_PHY_407_DATA 0x00000000 +#define DDRSS1_PHY_408_DATA 0x00000000 +#define DDRSS1_PHY_409_DATA 0x00000000 +#define DDRSS1_PHY_410_DATA 0x00000000 +#define DDRSS1_PHY_411_DATA 0x00000000 +#define DDRSS1_PHY_412_DATA 0x00000000 +#define DDRSS1_PHY_413_DATA 0x00000000 +#define DDRSS1_PHY_414_DATA 0x00000000 +#define DDRSS1_PHY_415_DATA 0x00000000 +#define DDRSS1_PHY_416_DATA 0x00000000 +#define DDRSS1_PHY_417_DATA 0x00000000 +#define DDRSS1_PHY_418_DATA 0x00000000 +#define DDRSS1_PHY_419_DATA 0x00000000 +#define DDRSS1_PHY_420_DATA 0x00000000 +#define DDRSS1_PHY_421_DATA 0x00000000 +#define DDRSS1_PHY_422_DATA 0x00000000 +#define DDRSS1_PHY_423_DATA 0x00000000 +#define DDRSS1_PHY_424_DATA 0x00000000 +#define DDRSS1_PHY_425_DATA 0x00000000 +#define DDRSS1_PHY_426_DATA 0x00000000 +#define DDRSS1_PHY_427_DATA 0x00000000 +#define DDRSS1_PHY_428_DATA 0x00000000 +#define DDRSS1_PHY_429_DATA 0x00000000 +#define DDRSS1_PHY_430_DATA 0x00000000 +#define DDRSS1_PHY_431_DATA 0x00000000 +#define DDRSS1_PHY_432_DATA 0x00000000 +#define DDRSS1_PHY_433_DATA 0x00000000 +#define DDRSS1_PHY_434_DATA 0x00000000 +#define DDRSS1_PHY_435_DATA 0x00000000 +#define DDRSS1_PHY_436_DATA 0x00000000 +#define DDRSS1_PHY_437_DATA 0x00000000 +#define DDRSS1_PHY_438_DATA 0x00000000 +#define DDRSS1_PHY_439_DATA 0x00000000 +#define DDRSS1_PHY_440_DATA 0x00000000 +#define DDRSS1_PHY_441_DATA 0x00000000 +#define DDRSS1_PHY_442_DATA 0x00000000 +#define DDRSS1_PHY_443_DATA 0x00000000 +#define DDRSS1_PHY_444_DATA 0x00000000 +#define DDRSS1_PHY_445_DATA 0x00000000 +#define DDRSS1_PHY_446_DATA 0x00000000 +#define DDRSS1_PHY_447_DATA 0x00000000 +#define DDRSS1_PHY_448_DATA 0x00000000 +#define DDRSS1_PHY_449_DATA 0x00000000 +#define DDRSS1_PHY_450_DATA 0x00000000 +#define DDRSS1_PHY_451_DATA 0x00000000 +#define DDRSS1_PHY_452_DATA 0x00000000 +#define DDRSS1_PHY_453_DATA 0x00000000 +#define DDRSS1_PHY_454_DATA 0x00000000 +#define DDRSS1_PHY_455_DATA 0x00000000 +#define DDRSS1_PHY_456_DATA 0x00000000 +#define DDRSS1_PHY_457_DATA 0x00000000 +#define DDRSS1_PHY_458_DATA 0x00000000 +#define DDRSS1_PHY_459_DATA 0x00000000 +#define DDRSS1_PHY_460_DATA 0x00000000 +#define DDRSS1_PHY_461_DATA 0x00000000 +#define DDRSS1_PHY_462_DATA 0x00000000 +#define DDRSS1_PHY_463_DATA 0x00000000 +#define DDRSS1_PHY_464_DATA 0x00000000 +#define DDRSS1_PHY_465_DATA 0x00000000 +#define DDRSS1_PHY_466_DATA 0x00000000 +#define DDRSS1_PHY_467_DATA 0x00000000 +#define DDRSS1_PHY_468_DATA 0x00000000 +#define DDRSS1_PHY_469_DATA 0x00000000 +#define DDRSS1_PHY_470_DATA 0x00000000 +#define DDRSS1_PHY_471_DATA 0x00000000 +#define DDRSS1_PHY_472_DATA 0x00000000 +#define DDRSS1_PHY_473_DATA 0x00000000 +#define DDRSS1_PHY_474_DATA 0x00000000 +#define DDRSS1_PHY_475_DATA 0x00000000 +#define DDRSS1_PHY_476_DATA 0x00000000 +#define DDRSS1_PHY_477_DATA 0x00000000 +#define DDRSS1_PHY_478_DATA 0x00000000 +#define DDRSS1_PHY_479_DATA 0x00000000 +#define DDRSS1_PHY_480_DATA 0x00000000 +#define DDRSS1_PHY_481_DATA 0x00000000 +#define DDRSS1_PHY_482_DATA 0x00000000 +#define DDRSS1_PHY_483_DATA 0x00000000 +#define DDRSS1_PHY_484_DATA 0x00000000 +#define DDRSS1_PHY_485_DATA 0x00000000 +#define DDRSS1_PHY_486_DATA 0x00000000 +#define DDRSS1_PHY_487_DATA 0x00000000 +#define DDRSS1_PHY_488_DATA 0x00000000 +#define DDRSS1_PHY_489_DATA 0x00000000 +#define DDRSS1_PHY_490_DATA 0x00000000 +#define DDRSS1_PHY_491_DATA 0x00000000 +#define DDRSS1_PHY_492_DATA 0x00000000 +#define DDRSS1_PHY_493_DATA 0x00000000 +#define DDRSS1_PHY_494_DATA 0x00000000 +#define DDRSS1_PHY_495_DATA 0x00000000 +#define DDRSS1_PHY_496_DATA 0x00000000 +#define DDRSS1_PHY_497_DATA 0x00000000 +#define DDRSS1_PHY_498_DATA 0x00000000 +#define DDRSS1_PHY_499_DATA 0x00000000 +#define DDRSS1_PHY_500_DATA 0x00000000 +#define DDRSS1_PHY_501_DATA 0x00000000 +#define DDRSS1_PHY_502_DATA 0x00000000 +#define DDRSS1_PHY_503_DATA 0x00000000 +#define DDRSS1_PHY_504_DATA 0x00000000 +#define DDRSS1_PHY_505_DATA 0x00000000 +#define DDRSS1_PHY_506_DATA 0x00000000 +#define DDRSS1_PHY_507_DATA 0x00000000 +#define DDRSS1_PHY_508_DATA 0x00000000 +#define DDRSS1_PHY_509_DATA 0x00000000 +#define DDRSS1_PHY_510_DATA 0x00000000 +#define DDRSS1_PHY_511_DATA 0x00000000 +#define DDRSS1_PHY_512_DATA 0x000004F0 +#define DDRSS1_PHY_513_DATA 0x00000000 +#define DDRSS1_PHY_514_DATA 0x00030200 +#define DDRSS1_PHY_515_DATA 0x00000000 +#define DDRSS1_PHY_516_DATA 0x00000000 +#define DDRSS1_PHY_517_DATA 0x01030000 +#define DDRSS1_PHY_518_DATA 0x00010000 +#define DDRSS1_PHY_519_DATA 0x01030004 +#define DDRSS1_PHY_520_DATA 0x01000000 +#define DDRSS1_PHY_521_DATA 0x00000000 +#define DDRSS1_PHY_522_DATA 0x00000000 +#define DDRSS1_PHY_523_DATA 0x01000001 +#define DDRSS1_PHY_524_DATA 0x00000200 +#define DDRSS1_PHY_525_DATA 0x000800C0 +#define DDRSS1_PHY_526_DATA 0x060100CC +#define DDRSS1_PHY_527_DATA 0x00030066 +#define DDRSS1_PHY_528_DATA 0x00000000 +#define DDRSS1_PHY_529_DATA 0x00000301 +#define DDRSS1_PHY_530_DATA 0x0000AAAA +#define DDRSS1_PHY_531_DATA 0x00005555 +#define DDRSS1_PHY_532_DATA 0x0000B5B5 +#define DDRSS1_PHY_533_DATA 0x00004A4A +#define DDRSS1_PHY_534_DATA 0x00005656 +#define DDRSS1_PHY_535_DATA 0x0000A9A9 +#define DDRSS1_PHY_536_DATA 0x0000A9A9 +#define DDRSS1_PHY_537_DATA 0x0000B5B5 +#define DDRSS1_PHY_538_DATA 0x00000000 +#define DDRSS1_PHY_539_DATA 0x00000000 +#define DDRSS1_PHY_540_DATA 0x2A000000 +#define DDRSS1_PHY_541_DATA 0x00000808 +#define DDRSS1_PHY_542_DATA 0x0F000000 +#define DDRSS1_PHY_543_DATA 0x00000F08 +#define DDRSS1_PHY_544_DATA 0x10400000 +#define DDRSS1_PHY_545_DATA 0x0C002006 +#define DDRSS1_PHY_546_DATA 0x00000000 +#define DDRSS1_PHY_547_DATA 0x00000000 +#define DDRSS1_PHY_548_DATA 0x55555555 +#define DDRSS1_PHY_549_DATA 0xAAAAAAAA +#define DDRSS1_PHY_550_DATA 0x55555555 +#define DDRSS1_PHY_551_DATA 0xAAAAAAAA +#define DDRSS1_PHY_552_DATA 0x00005555 +#define DDRSS1_PHY_553_DATA 0x01000100 +#define DDRSS1_PHY_554_DATA 0x00800180 +#define DDRSS1_PHY_555_DATA 0x00000001 +#define DDRSS1_PHY_556_DATA 0x00000000 +#define DDRSS1_PHY_557_DATA 0x00000000 +#define DDRSS1_PHY_558_DATA 0x00000000 +#define DDRSS1_PHY_559_DATA 0x00000000 +#define DDRSS1_PHY_560_DATA 0x00000000 +#define DDRSS1_PHY_561_DATA 0x00000000 +#define DDRSS1_PHY_562_DATA 0x00000000 +#define DDRSS1_PHY_563_DATA 0x00000000 +#define DDRSS1_PHY_564_DATA 0x00000000 +#define DDRSS1_PHY_565_DATA 0x00000000 +#define DDRSS1_PHY_566_DATA 0x00000000 +#define DDRSS1_PHY_567_DATA 0x00000000 +#define DDRSS1_PHY_568_DATA 0x00000000 +#define DDRSS1_PHY_569_DATA 0x00000000 +#define DDRSS1_PHY_570_DATA 0x00000000 +#define DDRSS1_PHY_571_DATA 0x00000000 +#define DDRSS1_PHY_572_DATA 0x00000000 +#define DDRSS1_PHY_573_DATA 0x00000000 +#define DDRSS1_PHY_574_DATA 0x00000000 +#define DDRSS1_PHY_575_DATA 0x00000000 +#define DDRSS1_PHY_576_DATA 0x00000000 +#define DDRSS1_PHY_577_DATA 0x00000000 +#define DDRSS1_PHY_578_DATA 0x00000104 +#define DDRSS1_PHY_579_DATA 0x00000120 +#define DDRSS1_PHY_580_DATA 0x00000000 +#define DDRSS1_PHY_581_DATA 0x00000000 +#define DDRSS1_PHY_582_DATA 0x00000000 +#define DDRSS1_PHY_583_DATA 0x00000000 +#define DDRSS1_PHY_584_DATA 0x00000000 +#define DDRSS1_PHY_585_DATA 0x00000000 +#define DDRSS1_PHY_586_DATA 0x00000000 +#define DDRSS1_PHY_587_DATA 0x00000001 +#define DDRSS1_PHY_588_DATA 0x07FF0000 +#define DDRSS1_PHY_589_DATA 0x0080081F +#define DDRSS1_PHY_590_DATA 0x00081020 +#define DDRSS1_PHY_591_DATA 0x04010000 +#define DDRSS1_PHY_592_DATA 0x00000000 +#define DDRSS1_PHY_593_DATA 0x00000000 +#define DDRSS1_PHY_594_DATA 0x00000000 +#define DDRSS1_PHY_595_DATA 0x00000100 +#define DDRSS1_PHY_596_DATA 0x01CC0C01 +#define DDRSS1_PHY_597_DATA 0x1003CC0C +#define DDRSS1_PHY_598_DATA 0x20000140 +#define DDRSS1_PHY_599_DATA 0x07FF0200 +#define DDRSS1_PHY_600_DATA 0x0000DD01 +#define DDRSS1_PHY_601_DATA 0x10100303 +#define DDRSS1_PHY_602_DATA 0x10101010 +#define DDRSS1_PHY_603_DATA 0x10101010 +#define DDRSS1_PHY_604_DATA 0x00021010 +#define DDRSS1_PHY_605_DATA 0x00100010 +#define DDRSS1_PHY_606_DATA 0x00100010 +#define DDRSS1_PHY_607_DATA 0x00100010 +#define DDRSS1_PHY_608_DATA 0x00100010 +#define DDRSS1_PHY_609_DATA 0x00050010 +#define DDRSS1_PHY_610_DATA 0x51517041 +#define DDRSS1_PHY_611_DATA 0x31C06001 +#define DDRSS1_PHY_612_DATA 0x07AB01AB +#define DDRSS1_PHY_613_DATA 0x00C0C001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 +#define DDRSS1_PHY_615_DATA 0x10001000 +#define DDRSS1_PHY_616_DATA 0x0C083E42 +#define DDRSS1_PHY_617_DATA 0x0F0C3701 +#define DDRSS1_PHY_618_DATA 0x01000140 +#define DDRSS1_PHY_619_DATA 0x0C000420 +#define DDRSS1_PHY_620_DATA 0x00000198 +#define DDRSS1_PHY_621_DATA 0x0A0000D0 +#define DDRSS1_PHY_622_DATA 0x00030200 +#define DDRSS1_PHY_623_DATA 0x02800000 +#define DDRSS1_PHY_624_DATA 0x80800000 +#define DDRSS1_PHY_625_DATA 0x000E2010 +#define DDRSS1_PHY_626_DATA 0x76543210 +#define DDRSS1_PHY_627_DATA 0x00000008 +#define DDRSS1_PHY_628_DATA 0x02800280 +#define DDRSS1_PHY_629_DATA 0x02800280 +#define DDRSS1_PHY_630_DATA 0x02800280 +#define DDRSS1_PHY_631_DATA 0x02800280 +#define DDRSS1_PHY_632_DATA 0x00000280 +#define DDRSS1_PHY_633_DATA 0x0000A000 +#define DDRSS1_PHY_634_DATA 0x00A000A0 +#define DDRSS1_PHY_635_DATA 0x00A000A0 +#define DDRSS1_PHY_636_DATA 0x00A000A0 +#define DDRSS1_PHY_637_DATA 0x00A000A0 +#define DDRSS1_PHY_638_DATA 0x00A000A0 +#define DDRSS1_PHY_639_DATA 0x00A000A0 +#define DDRSS1_PHY_640_DATA 0x00A000A0 +#define DDRSS1_PHY_641_DATA 0x00A000A0 +#define DDRSS1_PHY_642_DATA 0x01C200A0 +#define DDRSS1_PHY_643_DATA 0x01A00005 +#define DDRSS1_PHY_644_DATA 0x00000000 +#define DDRSS1_PHY_645_DATA 0x00000000 +#define DDRSS1_PHY_646_DATA 0x00080200 +#define DDRSS1_PHY_647_DATA 0x00000000 +#define DDRSS1_PHY_648_DATA 0x20202000 +#define DDRSS1_PHY_649_DATA 0x20202020 +#define DDRSS1_PHY_650_DATA 0xF0F02020 +#define DDRSS1_PHY_651_DATA 0x00000000 +#define DDRSS1_PHY_652_DATA 0x00000000 +#define DDRSS1_PHY_653_DATA 0x00000000 +#define DDRSS1_PHY_654_DATA 0x00000000 +#define DDRSS1_PHY_655_DATA 0x00000000 +#define DDRSS1_PHY_656_DATA 0x00000000 +#define DDRSS1_PHY_657_DATA 0x00000000 +#define DDRSS1_PHY_658_DATA 0x00000000 +#define DDRSS1_PHY_659_DATA 0x00000000 +#define DDRSS1_PHY_660_DATA 0x00000000 +#define DDRSS1_PHY_661_DATA 0x00000000 +#define DDRSS1_PHY_662_DATA 0x00000000 +#define DDRSS1_PHY_663_DATA 0x00000000 +#define DDRSS1_PHY_664_DATA 0x00000000 +#define DDRSS1_PHY_665_DATA 0x00000000 +#define DDRSS1_PHY_666_DATA 0x00000000 +#define DDRSS1_PHY_667_DATA 0x00000000 +#define DDRSS1_PHY_668_DATA 0x00000000 +#define DDRSS1_PHY_669_DATA 0x00000000 +#define DDRSS1_PHY_670_DATA 0x00000000 +#define DDRSS1_PHY_671_DATA 0x00000000 +#define DDRSS1_PHY_672_DATA 0x00000000 +#define DDRSS1_PHY_673_DATA 0x00000000 +#define DDRSS1_PHY_674_DATA 0x00000000 +#define DDRSS1_PHY_675_DATA 0x00000000 +#define DDRSS1_PHY_676_DATA 0x00000000 +#define DDRSS1_PHY_677_DATA 0x00000000 +#define DDRSS1_PHY_678_DATA 0x00000000 +#define DDRSS1_PHY_679_DATA 0x00000000 +#define DDRSS1_PHY_680_DATA 0x00000000 +#define DDRSS1_PHY_681_DATA 0x00000000 +#define DDRSS1_PHY_682_DATA 0x00000000 +#define DDRSS1_PHY_683_DATA 0x00000000 +#define DDRSS1_PHY_684_DATA 0x00000000 +#define DDRSS1_PHY_685_DATA 0x00000000 +#define DDRSS1_PHY_686_DATA 0x00000000 +#define DDRSS1_PHY_687_DATA 0x00000000 +#define DDRSS1_PHY_688_DATA 0x00000000 +#define DDRSS1_PHY_689_DATA 0x00000000 +#define DDRSS1_PHY_690_DATA 0x00000000 +#define DDRSS1_PHY_691_DATA 0x00000000 +#define DDRSS1_PHY_692_DATA 0x00000000 +#define DDRSS1_PHY_693_DATA 0x00000000 +#define DDRSS1_PHY_694_DATA 0x00000000 +#define DDRSS1_PHY_695_DATA 0x00000000 +#define DDRSS1_PHY_696_DATA 0x00000000 +#define DDRSS1_PHY_697_DATA 0x00000000 +#define DDRSS1_PHY_698_DATA 0x00000000 +#define DDRSS1_PHY_699_DATA 0x00000000 +#define DDRSS1_PHY_700_DATA 0x00000000 +#define DDRSS1_PHY_701_DATA 0x00000000 +#define DDRSS1_PHY_702_DATA 0x00000000 +#define DDRSS1_PHY_703_DATA 0x00000000 +#define DDRSS1_PHY_704_DATA 0x00000000 +#define DDRSS1_PHY_705_DATA 0x00000000 +#define DDRSS1_PHY_706_DATA 0x00000000 +#define DDRSS1_PHY_707_DATA 0x00000000 +#define DDRSS1_PHY_708_DATA 0x00000000 +#define DDRSS1_PHY_709_DATA 0x00000000 +#define DDRSS1_PHY_710_DATA 0x00000000 +#define DDRSS1_PHY_711_DATA 0x00000000 +#define DDRSS1_PHY_712_DATA 0x00000000 +#define DDRSS1_PHY_713_DATA 0x00000000 +#define DDRSS1_PHY_714_DATA 0x00000000 +#define DDRSS1_PHY_715_DATA 0x00000000 +#define DDRSS1_PHY_716_DATA 0x00000000 +#define DDRSS1_PHY_717_DATA 0x00000000 +#define DDRSS1_PHY_718_DATA 0x00000000 +#define DDRSS1_PHY_719_DATA 0x00000000 +#define DDRSS1_PHY_720_DATA 0x00000000 +#define DDRSS1_PHY_721_DATA 0x00000000 +#define DDRSS1_PHY_722_DATA 0x00000000 +#define DDRSS1_PHY_723_DATA 0x00000000 +#define DDRSS1_PHY_724_DATA 0x00000000 +#define DDRSS1_PHY_725_DATA 0x00000000 +#define DDRSS1_PHY_726_DATA 0x00000000 +#define DDRSS1_PHY_727_DATA 0x00000000 +#define DDRSS1_PHY_728_DATA 0x00000000 +#define DDRSS1_PHY_729_DATA 0x00000000 +#define DDRSS1_PHY_730_DATA 0x00000000 +#define DDRSS1_PHY_731_DATA 0x00000000 +#define DDRSS1_PHY_732_DATA 0x00000000 +#define DDRSS1_PHY_733_DATA 0x00000000 +#define DDRSS1_PHY_734_DATA 0x00000000 +#define DDRSS1_PHY_735_DATA 0x00000000 +#define DDRSS1_PHY_736_DATA 0x00000000 +#define DDRSS1_PHY_737_DATA 0x00000000 +#define DDRSS1_PHY_738_DATA 0x00000000 +#define DDRSS1_PHY_739_DATA 0x00000000 +#define DDRSS1_PHY_740_DATA 0x00000000 +#define DDRSS1_PHY_741_DATA 0x00000000 +#define DDRSS1_PHY_742_DATA 0x00000000 +#define DDRSS1_PHY_743_DATA 0x00000000 +#define DDRSS1_PHY_744_DATA 0x00000000 +#define DDRSS1_PHY_745_DATA 0x00000000 +#define DDRSS1_PHY_746_DATA 0x00000000 +#define DDRSS1_PHY_747_DATA 0x00000000 +#define DDRSS1_PHY_748_DATA 0x00000000 +#define DDRSS1_PHY_749_DATA 0x00000000 +#define DDRSS1_PHY_750_DATA 0x00000000 +#define DDRSS1_PHY_751_DATA 0x00000000 +#define DDRSS1_PHY_752_DATA 0x00000000 +#define DDRSS1_PHY_753_DATA 0x00000000 +#define DDRSS1_PHY_754_DATA 0x00000000 +#define DDRSS1_PHY_755_DATA 0x00000000 +#define DDRSS1_PHY_756_DATA 0x00000000 +#define DDRSS1_PHY_757_DATA 0x00000000 +#define DDRSS1_PHY_758_DATA 0x00000000 +#define DDRSS1_PHY_759_DATA 0x00000000 +#define DDRSS1_PHY_760_DATA 0x00000000 +#define DDRSS1_PHY_761_DATA 0x00000000 +#define DDRSS1_PHY_762_DATA 0x00000000 +#define DDRSS1_PHY_763_DATA 0x00000000 +#define DDRSS1_PHY_764_DATA 0x00000000 +#define DDRSS1_PHY_765_DATA 0x00000000 +#define DDRSS1_PHY_766_DATA 0x00000000 +#define DDRSS1_PHY_767_DATA 0x00000000 +#define DDRSS1_PHY_768_DATA 0x000004F0 +#define DDRSS1_PHY_769_DATA 0x00000000 +#define DDRSS1_PHY_770_DATA 0x00030200 +#define DDRSS1_PHY_771_DATA 0x00000000 +#define DDRSS1_PHY_772_DATA 0x00000000 +#define DDRSS1_PHY_773_DATA 0x01030000 +#define DDRSS1_PHY_774_DATA 0x00010000 +#define DDRSS1_PHY_775_DATA 0x01030004 +#define DDRSS1_PHY_776_DATA 0x01000000 +#define DDRSS1_PHY_777_DATA 0x00000000 +#define DDRSS1_PHY_778_DATA 0x00000000 +#define DDRSS1_PHY_779_DATA 0x01000001 +#define DDRSS1_PHY_780_DATA 0x00000200 +#define DDRSS1_PHY_781_DATA 0x000800C0 +#define DDRSS1_PHY_782_DATA 0x060100CC +#define DDRSS1_PHY_783_DATA 0x00030066 +#define DDRSS1_PHY_784_DATA 0x00000000 +#define DDRSS1_PHY_785_DATA 0x00000301 +#define DDRSS1_PHY_786_DATA 0x0000AAAA +#define DDRSS1_PHY_787_DATA 0x00005555 +#define DDRSS1_PHY_788_DATA 0x0000B5B5 +#define DDRSS1_PHY_789_DATA 0x00004A4A +#define DDRSS1_PHY_790_DATA 0x00005656 +#define DDRSS1_PHY_791_DATA 0x0000A9A9 +#define DDRSS1_PHY_792_DATA 0x0000A9A9 +#define DDRSS1_PHY_793_DATA 0x0000B5B5 +#define DDRSS1_PHY_794_DATA 0x00000000 +#define DDRSS1_PHY_795_DATA 0x00000000 +#define DDRSS1_PHY_796_DATA 0x2A000000 +#define DDRSS1_PHY_797_DATA 0x00000808 +#define DDRSS1_PHY_798_DATA 0x0F000000 +#define DDRSS1_PHY_799_DATA 0x00000F08 +#define DDRSS1_PHY_800_DATA 0x10400000 +#define DDRSS1_PHY_801_DATA 0x0C002006 +#define DDRSS1_PHY_802_DATA 0x00000000 +#define DDRSS1_PHY_803_DATA 0x00000000 +#define DDRSS1_PHY_804_DATA 0x55555555 +#define DDRSS1_PHY_805_DATA 0xAAAAAAAA +#define DDRSS1_PHY_806_DATA 0x55555555 +#define DDRSS1_PHY_807_DATA 0xAAAAAAAA +#define DDRSS1_PHY_808_DATA 0x00005555 +#define DDRSS1_PHY_809_DATA 0x01000100 +#define DDRSS1_PHY_810_DATA 0x00800180 +#define DDRSS1_PHY_811_DATA 0x00000000 +#define DDRSS1_PHY_812_DATA 0x00000000 +#define DDRSS1_PHY_813_DATA 0x00000000 +#define DDRSS1_PHY_814_DATA 0x00000000 +#define DDRSS1_PHY_815_DATA 0x00000000 +#define DDRSS1_PHY_816_DATA 0x00000000 +#define DDRSS1_PHY_817_DATA 0x00000000 +#define DDRSS1_PHY_818_DATA 0x00000000 +#define DDRSS1_PHY_819_DATA 0x00000000 +#define DDRSS1_PHY_820_DATA 0x00000000 +#define DDRSS1_PHY_821_DATA 0x00000000 +#define DDRSS1_PHY_822_DATA 0x00000000 +#define DDRSS1_PHY_823_DATA 0x00000000 +#define DDRSS1_PHY_824_DATA 0x00000000 +#define DDRSS1_PHY_825_DATA 0x00000000 +#define DDRSS1_PHY_826_DATA 0x00000000 +#define DDRSS1_PHY_827_DATA 0x00000000 +#define DDRSS1_PHY_828_DATA 0x00000000 +#define DDRSS1_PHY_829_DATA 0x00000000 +#define DDRSS1_PHY_830_DATA 0x00000000 +#define DDRSS1_PHY_831_DATA 0x00000000 +#define DDRSS1_PHY_832_DATA 0x00000000 +#define DDRSS1_PHY_833_DATA 0x00000000 +#define DDRSS1_PHY_834_DATA 0x00000104 +#define DDRSS1_PHY_835_DATA 0x00000120 +#define DDRSS1_PHY_836_DATA 0x00000000 +#define DDRSS1_PHY_837_DATA 0x00000000 +#define DDRSS1_PHY_838_DATA 0x00000000 +#define DDRSS1_PHY_839_DATA 0x00000000 +#define DDRSS1_PHY_840_DATA 0x00000000 +#define DDRSS1_PHY_841_DATA 0x00000000 +#define DDRSS1_PHY_842_DATA 0x00000000 +#define DDRSS1_PHY_843_DATA 0x00000001 +#define DDRSS1_PHY_844_DATA 0x07FF0000 +#define DDRSS1_PHY_845_DATA 0x0080081F +#define DDRSS1_PHY_846_DATA 0x00081020 +#define DDRSS1_PHY_847_DATA 0x04010000 +#define DDRSS1_PHY_848_DATA 0x00000000 +#define DDRSS1_PHY_849_DATA 0x00000000 +#define DDRSS1_PHY_850_DATA 0x00000000 +#define DDRSS1_PHY_851_DATA 0x00000100 +#define DDRSS1_PHY_852_DATA 0x01CC0C01 +#define DDRSS1_PHY_853_DATA 0x1003CC0C +#define DDRSS1_PHY_854_DATA 0x20000140 +#define DDRSS1_PHY_855_DATA 0x07FF0200 +#define DDRSS1_PHY_856_DATA 0x0000DD01 +#define DDRSS1_PHY_857_DATA 0x10100303 +#define DDRSS1_PHY_858_DATA 0x10101010 +#define DDRSS1_PHY_859_DATA 0x10101010 +#define DDRSS1_PHY_860_DATA 0x00021010 +#define DDRSS1_PHY_861_DATA 0x00100010 +#define DDRSS1_PHY_862_DATA 0x00100010 +#define DDRSS1_PHY_863_DATA 0x00100010 +#define DDRSS1_PHY_864_DATA 0x00100010 +#define DDRSS1_PHY_865_DATA 0x00050010 +#define DDRSS1_PHY_866_DATA 0x51517041 +#define DDRSS1_PHY_867_DATA 0x31C06001 +#define DDRSS1_PHY_868_DATA 0x07AB01AB +#define DDRSS1_PHY_869_DATA 0x00C0C001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 +#define DDRSS1_PHY_871_DATA 0x10001000 +#define DDRSS1_PHY_872_DATA 0x0C083E42 +#define DDRSS1_PHY_873_DATA 0x0F0C3701 +#define DDRSS1_PHY_874_DATA 0x01000140 +#define DDRSS1_PHY_875_DATA 0x0C000420 +#define DDRSS1_PHY_876_DATA 0x00000198 +#define DDRSS1_PHY_877_DATA 0x0A0000D0 +#define DDRSS1_PHY_878_DATA 0x00030200 +#define DDRSS1_PHY_879_DATA 0x02800000 +#define DDRSS1_PHY_880_DATA 0x80800000 +#define DDRSS1_PHY_881_DATA 0x000E2010 +#define DDRSS1_PHY_882_DATA 0x76543210 +#define DDRSS1_PHY_883_DATA 0x00000008 +#define DDRSS1_PHY_884_DATA 0x02800280 +#define DDRSS1_PHY_885_DATA 0x02800280 +#define DDRSS1_PHY_886_DATA 0x02800280 +#define DDRSS1_PHY_887_DATA 0x02800280 +#define DDRSS1_PHY_888_DATA 0x00000280 +#define DDRSS1_PHY_889_DATA 0x0000A000 +#define DDRSS1_PHY_890_DATA 0x00A000A0 +#define DDRSS1_PHY_891_DATA 0x00A000A0 +#define DDRSS1_PHY_892_DATA 0x00A000A0 +#define DDRSS1_PHY_893_DATA 0x00A000A0 +#define DDRSS1_PHY_894_DATA 0x00A000A0 +#define DDRSS1_PHY_895_DATA 0x00A000A0 +#define DDRSS1_PHY_896_DATA 0x00A000A0 +#define DDRSS1_PHY_897_DATA 0x00A000A0 +#define DDRSS1_PHY_898_DATA 0x01C200A0 +#define DDRSS1_PHY_899_DATA 0x01A00005 +#define DDRSS1_PHY_900_DATA 0x00000000 +#define DDRSS1_PHY_901_DATA 0x00000000 +#define DDRSS1_PHY_902_DATA 0x00080200 +#define DDRSS1_PHY_903_DATA 0x00000000 +#define DDRSS1_PHY_904_DATA 0x20202000 +#define DDRSS1_PHY_905_DATA 0x20202020 +#define DDRSS1_PHY_906_DATA 0xF0F02020 +#define DDRSS1_PHY_907_DATA 0x00000000 +#define DDRSS1_PHY_908_DATA 0x00000000 +#define DDRSS1_PHY_909_DATA 0x00000000 +#define DDRSS1_PHY_910_DATA 0x00000000 +#define DDRSS1_PHY_911_DATA 0x00000000 +#define DDRSS1_PHY_912_DATA 0x00000000 +#define DDRSS1_PHY_913_DATA 0x00000000 +#define DDRSS1_PHY_914_DATA 0x00000000 +#define DDRSS1_PHY_915_DATA 0x00000000 +#define DDRSS1_PHY_916_DATA 0x00000000 +#define DDRSS1_PHY_917_DATA 0x00000000 +#define DDRSS1_PHY_918_DATA 0x00000000 +#define DDRSS1_PHY_919_DATA 0x00000000 +#define DDRSS1_PHY_920_DATA 0x00000000 +#define DDRSS1_PHY_921_DATA 0x00000000 +#define DDRSS1_PHY_922_DATA 0x00000000 +#define DDRSS1_PHY_923_DATA 0x00000000 +#define DDRSS1_PHY_924_DATA 0x00000000 +#define DDRSS1_PHY_925_DATA 0x00000000 +#define DDRSS1_PHY_926_DATA 0x00000000 +#define DDRSS1_PHY_927_DATA 0x00000000 +#define DDRSS1_PHY_928_DATA 0x00000000 +#define DDRSS1_PHY_929_DATA 0x00000000 +#define DDRSS1_PHY_930_DATA 0x00000000 +#define DDRSS1_PHY_931_DATA 0x00000000 +#define DDRSS1_PHY_932_DATA 0x00000000 +#define DDRSS1_PHY_933_DATA 0x00000000 +#define DDRSS1_PHY_934_DATA 0x00000000 +#define DDRSS1_PHY_935_DATA 0x00000000 +#define DDRSS1_PHY_936_DATA 0x00000000 +#define DDRSS1_PHY_937_DATA 0x00000000 +#define DDRSS1_PHY_938_DATA 0x00000000 +#define DDRSS1_PHY_939_DATA 0x00000000 +#define DDRSS1_PHY_940_DATA 0x00000000 +#define DDRSS1_PHY_941_DATA 0x00000000 +#define DDRSS1_PHY_942_DATA 0x00000000 +#define DDRSS1_PHY_943_DATA 0x00000000 +#define DDRSS1_PHY_944_DATA 0x00000000 +#define DDRSS1_PHY_945_DATA 0x00000000 +#define DDRSS1_PHY_946_DATA 0x00000000 +#define DDRSS1_PHY_947_DATA 0x00000000 +#define DDRSS1_PHY_948_DATA 0x00000000 +#define DDRSS1_PHY_949_DATA 0x00000000 +#define DDRSS1_PHY_950_DATA 0x00000000 +#define DDRSS1_PHY_951_DATA 0x00000000 +#define DDRSS1_PHY_952_DATA 0x00000000 +#define DDRSS1_PHY_953_DATA 0x00000000 +#define DDRSS1_PHY_954_DATA 0x00000000 +#define DDRSS1_PHY_955_DATA 0x00000000 +#define DDRSS1_PHY_956_DATA 0x00000000 +#define DDRSS1_PHY_957_DATA 0x00000000 +#define DDRSS1_PHY_958_DATA 0x00000000 +#define DDRSS1_PHY_959_DATA 0x00000000 +#define DDRSS1_PHY_960_DATA 0x00000000 +#define DDRSS1_PHY_961_DATA 0x00000000 +#define DDRSS1_PHY_962_DATA 0x00000000 +#define DDRSS1_PHY_963_DATA 0x00000000 +#define DDRSS1_PHY_964_DATA 0x00000000 +#define DDRSS1_PHY_965_DATA 0x00000000 +#define DDRSS1_PHY_966_DATA 0x00000000 +#define DDRSS1_PHY_967_DATA 0x00000000 +#define DDRSS1_PHY_968_DATA 0x00000000 +#define DDRSS1_PHY_969_DATA 0x00000000 +#define DDRSS1_PHY_970_DATA 0x00000000 +#define DDRSS1_PHY_971_DATA 0x00000000 +#define DDRSS1_PHY_972_DATA 0x00000000 +#define DDRSS1_PHY_973_DATA 0x00000000 +#define DDRSS1_PHY_974_DATA 0x00000000 +#define DDRSS1_PHY_975_DATA 0x00000000 +#define DDRSS1_PHY_976_DATA 0x00000000 +#define DDRSS1_PHY_977_DATA 0x00000000 +#define DDRSS1_PHY_978_DATA 0x00000000 +#define DDRSS1_PHY_979_DATA 0x00000000 +#define DDRSS1_PHY_980_DATA 0x00000000 +#define DDRSS1_PHY_981_DATA 0x00000000 +#define DDRSS1_PHY_982_DATA 0x00000000 +#define DDRSS1_PHY_983_DATA 0x00000000 +#define DDRSS1_PHY_984_DATA 0x00000000 +#define DDRSS1_PHY_985_DATA 0x00000000 +#define DDRSS1_PHY_986_DATA 0x00000000 +#define DDRSS1_PHY_987_DATA 0x00000000 +#define DDRSS1_PHY_988_DATA 0x00000000 +#define DDRSS1_PHY_989_DATA 0x00000000 +#define DDRSS1_PHY_990_DATA 0x00000000 +#define DDRSS1_PHY_991_DATA 0x00000000 +#define DDRSS1_PHY_992_DATA 0x00000000 +#define DDRSS1_PHY_993_DATA 0x00000000 +#define DDRSS1_PHY_994_DATA 0x00000000 +#define DDRSS1_PHY_995_DATA 0x00000000 +#define DDRSS1_PHY_996_DATA 0x00000000 +#define DDRSS1_PHY_997_DATA 0x00000000 +#define DDRSS1_PHY_998_DATA 0x00000000 +#define DDRSS1_PHY_999_DATA 0x00000000 +#define DDRSS1_PHY_1000_DATA 0x00000000 +#define DDRSS1_PHY_1001_DATA 0x00000000 +#define DDRSS1_PHY_1002_DATA 0x00000000 +#define DDRSS1_PHY_1003_DATA 0x00000000 +#define DDRSS1_PHY_1004_DATA 0x00000000 +#define DDRSS1_PHY_1005_DATA 0x00000000 +#define DDRSS1_PHY_1006_DATA 0x00000000 +#define DDRSS1_PHY_1007_DATA 0x00000000 +#define DDRSS1_PHY_1008_DATA 0x00000000 +#define DDRSS1_PHY_1009_DATA 0x00000000 +#define DDRSS1_PHY_1010_DATA 0x00000000 +#define DDRSS1_PHY_1011_DATA 0x00000000 +#define DDRSS1_PHY_1012_DATA 0x00000000 +#define DDRSS1_PHY_1013_DATA 0x00000000 +#define DDRSS1_PHY_1014_DATA 0x00000000 +#define DDRSS1_PHY_1015_DATA 0x00000000 +#define DDRSS1_PHY_1016_DATA 0x00000000 +#define DDRSS1_PHY_1017_DATA 0x00000000 +#define DDRSS1_PHY_1018_DATA 0x00000000 +#define DDRSS1_PHY_1019_DATA 0x00000000 +#define DDRSS1_PHY_1020_DATA 0x00000000 +#define DDRSS1_PHY_1021_DATA 0x00000000 +#define DDRSS1_PHY_1022_DATA 0x00000000 +#define DDRSS1_PHY_1023_DATA 0x00000000 +#define DDRSS1_PHY_1024_DATA 0x00000000 +#define DDRSS1_PHY_1025_DATA 0x00000000 +#define DDRSS1_PHY_1026_DATA 0x00000000 +#define DDRSS1_PHY_1027_DATA 0x00000000 +#define DDRSS1_PHY_1028_DATA 0x00000000 +#define DDRSS1_PHY_1029_DATA 0x00000100 +#define DDRSS1_PHY_1030_DATA 0x00000200 +#define DDRSS1_PHY_1031_DATA 0x00000000 +#define DDRSS1_PHY_1032_DATA 0x00000000 +#define DDRSS1_PHY_1033_DATA 0x00000000 +#define DDRSS1_PHY_1034_DATA 0x00000000 +#define DDRSS1_PHY_1035_DATA 0x00400000 +#define DDRSS1_PHY_1036_DATA 0x00000080 +#define DDRSS1_PHY_1037_DATA 0x00DCBA98 +#define DDRSS1_PHY_1038_DATA 0x03000000 +#define DDRSS1_PHY_1039_DATA 0x00200000 +#define DDRSS1_PHY_1040_DATA 0x00000000 +#define DDRSS1_PHY_1041_DATA 0x00000000 +#define DDRSS1_PHY_1042_DATA 0x00000000 +#define DDRSS1_PHY_1043_DATA 0x00000000 +#define DDRSS1_PHY_1044_DATA 0x00000000 +#define DDRSS1_PHY_1045_DATA 0x0000002A +#define DDRSS1_PHY_1046_DATA 0x00000015 +#define DDRSS1_PHY_1047_DATA 0x00000015 +#define DDRSS1_PHY_1048_DATA 0x0000002A +#define DDRSS1_PHY_1049_DATA 0x00000033 +#define DDRSS1_PHY_1050_DATA 0x0000000C +#define DDRSS1_PHY_1051_DATA 0x0000000C +#define DDRSS1_PHY_1052_DATA 0x00000033 +#define DDRSS1_PHY_1053_DATA 0x00543210 +#define DDRSS1_PHY_1054_DATA 0x003F0000 +#define DDRSS1_PHY_1055_DATA 0x000F3F3F +#define DDRSS1_PHY_1056_DATA 0x20202003 +#define DDRSS1_PHY_1057_DATA 0x00202020 +#define DDRSS1_PHY_1058_DATA 0x20008008 +#define DDRSS1_PHY_1059_DATA 0x00000810 +#define DDRSS1_PHY_1060_DATA 0x00000F00 +#define DDRSS1_PHY_1061_DATA 0x00000000 +#define DDRSS1_PHY_1062_DATA 0x00000000 +#define DDRSS1_PHY_1063_DATA 0x00000000 +#define DDRSS1_PHY_1064_DATA 0x000305CC +#define DDRSS1_PHY_1065_DATA 0x00030000 +#define DDRSS1_PHY_1066_DATA 0x00000300 +#define DDRSS1_PHY_1067_DATA 0x00000300 +#define DDRSS1_PHY_1068_DATA 0x00000300 +#define DDRSS1_PHY_1069_DATA 0x00000300 +#define DDRSS1_PHY_1070_DATA 0x00000300 +#define DDRSS1_PHY_1071_DATA 0x42080010 +#define DDRSS1_PHY_1072_DATA 0x0000803E +#define DDRSS1_PHY_1073_DATA 0x00000001 +#define DDRSS1_PHY_1074_DATA 0x01000102 +#define DDRSS1_PHY_1075_DATA 0x00008000 +#define DDRSS1_PHY_1076_DATA 0x00000000 +#define DDRSS1_PHY_1077_DATA 0x00000000 +#define DDRSS1_PHY_1078_DATA 0x00000000 +#define DDRSS1_PHY_1079_DATA 0x00000000 +#define DDRSS1_PHY_1080_DATA 0x00000000 +#define DDRSS1_PHY_1081_DATA 0x00000000 +#define DDRSS1_PHY_1082_DATA 0x00000000 +#define DDRSS1_PHY_1083_DATA 0x00000000 +#define DDRSS1_PHY_1084_DATA 0x00000000 +#define DDRSS1_PHY_1085_DATA 0x00000000 +#define DDRSS1_PHY_1086_DATA 0x00000000 +#define DDRSS1_PHY_1087_DATA 0x00000000 +#define DDRSS1_PHY_1088_DATA 0x00000000 +#define DDRSS1_PHY_1089_DATA 0x00000000 +#define DDRSS1_PHY_1090_DATA 0x00000000 +#define DDRSS1_PHY_1091_DATA 0x00000000 +#define DDRSS1_PHY_1092_DATA 0x00000000 +#define DDRSS1_PHY_1093_DATA 0x00000000 +#define DDRSS1_PHY_1094_DATA 0x00000000 +#define DDRSS1_PHY_1095_DATA 0x00000000 +#define DDRSS1_PHY_1096_DATA 0x00000000 +#define DDRSS1_PHY_1097_DATA 0x00000000 +#define DDRSS1_PHY_1098_DATA 0x00000000 +#define DDRSS1_PHY_1099_DATA 0x00000000 +#define DDRSS1_PHY_1100_DATA 0x00000000 +#define DDRSS1_PHY_1101_DATA 0x00000000 +#define DDRSS1_PHY_1102_DATA 0x00000000 +#define DDRSS1_PHY_1103_DATA 0x00000000 +#define DDRSS1_PHY_1104_DATA 0x00000000 +#define DDRSS1_PHY_1105_DATA 0x00000000 +#define DDRSS1_PHY_1106_DATA 0x00000000 +#define DDRSS1_PHY_1107_DATA 0x00000000 +#define DDRSS1_PHY_1108_DATA 0x00000000 +#define DDRSS1_PHY_1109_DATA 0x00000000 +#define DDRSS1_PHY_1110_DATA 0x00000000 +#define DDRSS1_PHY_1111_DATA 0x00000000 +#define DDRSS1_PHY_1112_DATA 0x00000000 +#define DDRSS1_PHY_1113_DATA 0x00000000 +#define DDRSS1_PHY_1114_DATA 0x00000000 +#define DDRSS1_PHY_1115_DATA 0x00000000 +#define DDRSS1_PHY_1116_DATA 0x00000000 +#define DDRSS1_PHY_1117_DATA 0x00000000 +#define DDRSS1_PHY_1118_DATA 0x00000000 +#define DDRSS1_PHY_1119_DATA 0x00000000 +#define DDRSS1_PHY_1120_DATA 0x00000000 +#define DDRSS1_PHY_1121_DATA 0x00000000 +#define DDRSS1_PHY_1122_DATA 0x00000000 +#define DDRSS1_PHY_1123_DATA 0x00000000 +#define DDRSS1_PHY_1124_DATA 0x00000000 +#define DDRSS1_PHY_1125_DATA 0x00000000 +#define DDRSS1_PHY_1126_DATA 0x00000000 +#define DDRSS1_PHY_1127_DATA 0x00000000 +#define DDRSS1_PHY_1128_DATA 0x00000000 +#define DDRSS1_PHY_1129_DATA 0x00000000 +#define DDRSS1_PHY_1130_DATA 0x00000000 +#define DDRSS1_PHY_1131_DATA 0x00000000 +#define DDRSS1_PHY_1132_DATA 0x00000000 +#define DDRSS1_PHY_1133_DATA 0x00000000 +#define DDRSS1_PHY_1134_DATA 0x00000000 +#define DDRSS1_PHY_1135_DATA 0x00000000 +#define DDRSS1_PHY_1136_DATA 0x00000000 +#define DDRSS1_PHY_1137_DATA 0x00000000 +#define DDRSS1_PHY_1138_DATA 0x00000000 +#define DDRSS1_PHY_1139_DATA 0x00000000 +#define DDRSS1_PHY_1140_DATA 0x00000000 +#define DDRSS1_PHY_1141_DATA 0x00000000 +#define DDRSS1_PHY_1142_DATA 0x00000000 +#define DDRSS1_PHY_1143_DATA 0x00000000 +#define DDRSS1_PHY_1144_DATA 0x00000000 +#define DDRSS1_PHY_1145_DATA 0x00000000 +#define DDRSS1_PHY_1146_DATA 0x00000000 +#define DDRSS1_PHY_1147_DATA 0x00000000 +#define DDRSS1_PHY_1148_DATA 0x00000000 +#define DDRSS1_PHY_1149_DATA 0x00000000 +#define DDRSS1_PHY_1150_DATA 0x00000000 +#define DDRSS1_PHY_1151_DATA 0x00000000 +#define DDRSS1_PHY_1152_DATA 0x00000000 +#define DDRSS1_PHY_1153_DATA 0x00000000 +#define DDRSS1_PHY_1154_DATA 0x00000000 +#define DDRSS1_PHY_1155_DATA 0x00000000 +#define DDRSS1_PHY_1156_DATA 0x00000000 +#define DDRSS1_PHY_1157_DATA 0x00000000 +#define DDRSS1_PHY_1158_DATA 0x00000000 +#define DDRSS1_PHY_1159_DATA 0x00000000 +#define DDRSS1_PHY_1160_DATA 0x00000000 +#define DDRSS1_PHY_1161_DATA 0x00000000 +#define DDRSS1_PHY_1162_DATA 0x00000000 +#define DDRSS1_PHY_1163_DATA 0x00000000 +#define DDRSS1_PHY_1164_DATA 0x00000000 +#define DDRSS1_PHY_1165_DATA 0x00000000 +#define DDRSS1_PHY_1166_DATA 0x00000000 +#define DDRSS1_PHY_1167_DATA 0x00000000 +#define DDRSS1_PHY_1168_DATA 0x00000000 +#define DDRSS1_PHY_1169_DATA 0x00000000 +#define DDRSS1_PHY_1170_DATA 0x00000000 +#define DDRSS1_PHY_1171_DATA 0x00000000 +#define DDRSS1_PHY_1172_DATA 0x00000000 +#define DDRSS1_PHY_1173_DATA 0x00000000 +#define DDRSS1_PHY_1174_DATA 0x00000000 +#define DDRSS1_PHY_1175_DATA 0x00000000 +#define DDRSS1_PHY_1176_DATA 0x00000000 +#define DDRSS1_PHY_1177_DATA 0x00000000 +#define DDRSS1_PHY_1178_DATA 0x00000000 +#define DDRSS1_PHY_1179_DATA 0x00000000 +#define DDRSS1_PHY_1180_DATA 0x00000000 +#define DDRSS1_PHY_1181_DATA 0x00000000 +#define DDRSS1_PHY_1182_DATA 0x00000000 +#define DDRSS1_PHY_1183_DATA 0x00000000 +#define DDRSS1_PHY_1184_DATA 0x00000000 +#define DDRSS1_PHY_1185_DATA 0x00000000 +#define DDRSS1_PHY_1186_DATA 0x00000000 +#define DDRSS1_PHY_1187_DATA 0x00000000 +#define DDRSS1_PHY_1188_DATA 0x00000000 +#define DDRSS1_PHY_1189_DATA 0x00000000 +#define DDRSS1_PHY_1190_DATA 0x00000000 +#define DDRSS1_PHY_1191_DATA 0x00000000 +#define DDRSS1_PHY_1192_DATA 0x00000000 +#define DDRSS1_PHY_1193_DATA 0x00000000 +#define DDRSS1_PHY_1194_DATA 0x00000000 +#define DDRSS1_PHY_1195_DATA 0x00000000 +#define DDRSS1_PHY_1196_DATA 0x00000000 +#define DDRSS1_PHY_1197_DATA 0x00000000 +#define DDRSS1_PHY_1198_DATA 0x00000000 +#define DDRSS1_PHY_1199_DATA 0x00000000 +#define DDRSS1_PHY_1200_DATA 0x00000000 +#define DDRSS1_PHY_1201_DATA 0x00000000 +#define DDRSS1_PHY_1202_DATA 0x00000000 +#define DDRSS1_PHY_1203_DATA 0x00000000 +#define DDRSS1_PHY_1204_DATA 0x00000000 +#define DDRSS1_PHY_1205_DATA 0x00000000 +#define DDRSS1_PHY_1206_DATA 0x00000000 +#define DDRSS1_PHY_1207_DATA 0x00000000 +#define DDRSS1_PHY_1208_DATA 0x00000000 +#define DDRSS1_PHY_1209_DATA 0x00000000 +#define DDRSS1_PHY_1210_DATA 0x00000000 +#define DDRSS1_PHY_1211_DATA 0x00000000 +#define DDRSS1_PHY_1212_DATA 0x00000000 +#define DDRSS1_PHY_1213_DATA 0x00000000 +#define DDRSS1_PHY_1214_DATA 0x00000000 +#define DDRSS1_PHY_1215_DATA 0x00000000 +#define DDRSS1_PHY_1216_DATA 0x00000000 +#define DDRSS1_PHY_1217_DATA 0x00000000 +#define DDRSS1_PHY_1218_DATA 0x00000000 +#define DDRSS1_PHY_1219_DATA 0x00000000 +#define DDRSS1_PHY_1220_DATA 0x00000000 +#define DDRSS1_PHY_1221_DATA 0x00000000 +#define DDRSS1_PHY_1222_DATA 0x00000000 +#define DDRSS1_PHY_1223_DATA 0x00000000 +#define DDRSS1_PHY_1224_DATA 0x00000000 +#define DDRSS1_PHY_1225_DATA 0x00000000 +#define DDRSS1_PHY_1226_DATA 0x00000000 +#define DDRSS1_PHY_1227_DATA 0x00000000 +#define DDRSS1_PHY_1228_DATA 0x00000000 +#define DDRSS1_PHY_1229_DATA 0x00000000 +#define DDRSS1_PHY_1230_DATA 0x00000000 +#define DDRSS1_PHY_1231_DATA 0x00000000 +#define DDRSS1_PHY_1232_DATA 0x00000000 +#define DDRSS1_PHY_1233_DATA 0x00000000 +#define DDRSS1_PHY_1234_DATA 0x00000000 +#define DDRSS1_PHY_1235_DATA 0x00000000 +#define DDRSS1_PHY_1236_DATA 0x00000000 +#define DDRSS1_PHY_1237_DATA 0x00000000 +#define DDRSS1_PHY_1238_DATA 0x00000000 +#define DDRSS1_PHY_1239_DATA 0x00000000 +#define DDRSS1_PHY_1240_DATA 0x00000000 +#define DDRSS1_PHY_1241_DATA 0x00000000 +#define DDRSS1_PHY_1242_DATA 0x00000000 +#define DDRSS1_PHY_1243_DATA 0x00000000 +#define DDRSS1_PHY_1244_DATA 0x00000000 +#define DDRSS1_PHY_1245_DATA 0x00000000 +#define DDRSS1_PHY_1246_DATA 0x00000000 +#define DDRSS1_PHY_1247_DATA 0x00000000 +#define DDRSS1_PHY_1248_DATA 0x00000000 +#define DDRSS1_PHY_1249_DATA 0x00000000 +#define DDRSS1_PHY_1250_DATA 0x00000000 +#define DDRSS1_PHY_1251_DATA 0x00000000 +#define DDRSS1_PHY_1252_DATA 0x00000000 +#define DDRSS1_PHY_1253_DATA 0x00000000 +#define DDRSS1_PHY_1254_DATA 0x00000000 +#define DDRSS1_PHY_1255_DATA 0x00000000 +#define DDRSS1_PHY_1256_DATA 0x00000000 +#define DDRSS1_PHY_1257_DATA 0x00000000 +#define DDRSS1_PHY_1258_DATA 0x00000000 +#define DDRSS1_PHY_1259_DATA 0x00000000 +#define DDRSS1_PHY_1260_DATA 0x00000000 +#define DDRSS1_PHY_1261_DATA 0x00000000 +#define DDRSS1_PHY_1262_DATA 0x00000000 +#define DDRSS1_PHY_1263_DATA 0x00000000 +#define DDRSS1_PHY_1264_DATA 0x00000000 +#define DDRSS1_PHY_1265_DATA 0x00000000 +#define DDRSS1_PHY_1266_DATA 0x00000000 +#define DDRSS1_PHY_1267_DATA 0x00000000 +#define DDRSS1_PHY_1268_DATA 0x00000000 +#define DDRSS1_PHY_1269_DATA 0x00000000 +#define DDRSS1_PHY_1270_DATA 0x00000000 +#define DDRSS1_PHY_1271_DATA 0x00000000 +#define DDRSS1_PHY_1272_DATA 0x00000000 +#define DDRSS1_PHY_1273_DATA 0x00000000 +#define DDRSS1_PHY_1274_DATA 0x00000000 +#define DDRSS1_PHY_1275_DATA 0x00000000 +#define DDRSS1_PHY_1276_DATA 0x00000000 +#define DDRSS1_PHY_1277_DATA 0x00000000 +#define DDRSS1_PHY_1278_DATA 0x00000000 +#define DDRSS1_PHY_1279_DATA 0x00000000 +#define DDRSS1_PHY_1280_DATA 0x00000000 +#define DDRSS1_PHY_1281_DATA 0x00010100 +#define DDRSS1_PHY_1282_DATA 0x00000000 +#define DDRSS1_PHY_1283_DATA 0x00000000 +#define DDRSS1_PHY_1284_DATA 0x00050000 +#define DDRSS1_PHY_1285_DATA 0x04000000 +#define DDRSS1_PHY_1286_DATA 0x00000055 +#define DDRSS1_PHY_1287_DATA 0x00000000 +#define DDRSS1_PHY_1288_DATA 0x00000000 +#define DDRSS1_PHY_1289_DATA 0x00000000 +#define DDRSS1_PHY_1290_DATA 0x00000000 +#define DDRSS1_PHY_1291_DATA 0x00002001 +#define DDRSS1_PHY_1292_DATA 0x0000400F +#define DDRSS1_PHY_1293_DATA 0x50020028 +#define DDRSS1_PHY_1294_DATA 0x01010000 +#define DDRSS1_PHY_1295_DATA 0x80080001 +#define DDRSS1_PHY_1296_DATA 0x10200000 +#define DDRSS1_PHY_1297_DATA 0x00000008 +#define DDRSS1_PHY_1298_DATA 0x00000000 +#define DDRSS1_PHY_1299_DATA 0x01090E00 +#define DDRSS1_PHY_1300_DATA 0x00040101 +#define DDRSS1_PHY_1301_DATA 0x0000010F +#define DDRSS1_PHY_1302_DATA 0x00000000 +#define DDRSS1_PHY_1303_DATA 0x00000064 +#define DDRSS1_PHY_1304_DATA 0x00000000 +#define DDRSS1_PHY_1305_DATA 0x01010000 +#define DDRSS1_PHY_1306_DATA 0x01080402 +#define DDRSS1_PHY_1307_DATA 0x01200F02 +#define DDRSS1_PHY_1308_DATA 0x00194280 +#define DDRSS1_PHY_1309_DATA 0x00000004 +#define DDRSS1_PHY_1310_DATA 0x00042000 +#define DDRSS1_PHY_1311_DATA 0x00000000 +#define DDRSS1_PHY_1312_DATA 0x00000000 +#define DDRSS1_PHY_1313_DATA 0x00000000 +#define DDRSS1_PHY_1314_DATA 0x00000000 +#define DDRSS1_PHY_1315_DATA 0x00000000 +#define DDRSS1_PHY_1316_DATA 0x00000000 +#define DDRSS1_PHY_1317_DATA 0x01000000 +#define DDRSS1_PHY_1318_DATA 0x00000705 +#define DDRSS1_PHY_1319_DATA 0x00000054 +#define DDRSS1_PHY_1320_DATA 0x00030820 +#define DDRSS1_PHY_1321_DATA 0x00010820 +#define DDRSS1_PHY_1322_DATA 0x00010820 +#define DDRSS1_PHY_1323_DATA 0x00010820 +#define DDRSS1_PHY_1324_DATA 0x00010820 +#define DDRSS1_PHY_1325_DATA 0x00010820 +#define DDRSS1_PHY_1326_DATA 0x00010820 +#define DDRSS1_PHY_1327_DATA 0x00010820 +#define DDRSS1_PHY_1328_DATA 0x00010820 +#define DDRSS1_PHY_1329_DATA 0x00000000 +#define DDRSS1_PHY_1330_DATA 0x00000074 +#define DDRSS1_PHY_1331_DATA 0x00000400 +#define DDRSS1_PHY_1332_DATA 0x00000108 +#define DDRSS1_PHY_1333_DATA 0x00000000 +#define DDRSS1_PHY_1334_DATA 0x00000000 +#define DDRSS1_PHY_1335_DATA 0x00000000 +#define DDRSS1_PHY_1336_DATA 0x00000000 +#define DDRSS1_PHY_1337_DATA 0x00000000 +#define DDRSS1_PHY_1338_DATA 0x03000000 +#define DDRSS1_PHY_1339_DATA 0x00000000 +#define DDRSS1_PHY_1340_DATA 0x00000000 +#define DDRSS1_PHY_1341_DATA 0x00000000 +#define DDRSS1_PHY_1342_DATA 0x04102006 +#define DDRSS1_PHY_1343_DATA 0x00041020 +#define DDRSS1_PHY_1344_DATA 0x01C98C98 +#define DDRSS1_PHY_1345_DATA 0x3F400000 +#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS1_PHY_1347_DATA 0x0000001F +#define DDRSS1_PHY_1348_DATA 0x00000000 +#define DDRSS1_PHY_1349_DATA 0x00000000 +#define DDRSS1_PHY_1350_DATA 0x00000000 +#define DDRSS1_PHY_1351_DATA 0x00010000 +#define DDRSS1_PHY_1352_DATA 0x00000000 +#define DDRSS1_PHY_1353_DATA 0x00000000 +#define DDRSS1_PHY_1354_DATA 0x00000000 +#define DDRSS1_PHY_1355_DATA 0x00000000 +#define DDRSS1_PHY_1356_DATA 0x76543210 +#define DDRSS1_PHY_1357_DATA 0x00010198 +#define DDRSS1_PHY_1358_DATA 0x00000000 +#define DDRSS1_PHY_1359_DATA 0x00000000 +#define DDRSS1_PHY_1360_DATA 0x00000000 +#define DDRSS1_PHY_1361_DATA 0x00040700 +#define DDRSS1_PHY_1362_DATA 0x00000000 +#define DDRSS1_PHY_1363_DATA 0x00000000 +#define DDRSS1_PHY_1364_DATA 0x00000000 +#define DDRSS1_PHY_1365_DATA 0x00000000 +#define DDRSS1_PHY_1366_DATA 0x00000000 +#define DDRSS1_PHY_1367_DATA 0x00000002 +#define DDRSS1_PHY_1368_DATA 0x00000000 +#define DDRSS1_PHY_1369_DATA 0x00000000 +#define DDRSS1_PHY_1370_DATA 0x00000000 +#define DDRSS1_PHY_1371_DATA 0x00000000 +#define DDRSS1_PHY_1372_DATA 0x00000000 +#define DDRSS1_PHY_1373_DATA 0x00000000 +#define DDRSS1_PHY_1374_DATA 0x00080000 +#define DDRSS1_PHY_1375_DATA 0x000007FF +#define DDRSS1_PHY_1376_DATA 0x00000000 +#define DDRSS1_PHY_1377_DATA 0x00000000 +#define DDRSS1_PHY_1378_DATA 0x00000000 +#define DDRSS1_PHY_1379_DATA 0x00000000 +#define DDRSS1_PHY_1380_DATA 0x00000000 +#define DDRSS1_PHY_1381_DATA 0x00000000 +#define DDRSS1_PHY_1382_DATA 0x000FFFFF +#define DDRSS1_PHY_1383_DATA 0x000FFFFF +#define DDRSS1_PHY_1384_DATA 0x0000FFFF +#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS1_PHY_1386_DATA 0x030FFFFF +#define DDRSS1_PHY_1387_DATA 0x01FFFFFF +#define DDRSS1_PHY_1388_DATA 0x0000FFFF +#define DDRSS1_PHY_1389_DATA 0x00000000 +#define DDRSS1_PHY_1390_DATA 0x00000000 +#define DDRSS1_PHY_1391_DATA 0x00000000 +#define DDRSS1_PHY_1392_DATA 0x00000000 +#define DDRSS1_PHY_1393_DATA 0x0001F7C0 +#define DDRSS1_PHY_1394_DATA 0x00000003 +#define DDRSS1_PHY_1395_DATA 0x00000000 +#define DDRSS1_PHY_1396_DATA 0x00001142 +#define DDRSS1_PHY_1397_DATA 0x040207AB +#define DDRSS1_PHY_1398_DATA 0x01000080 +#define DDRSS1_PHY_1399_DATA 0x03900390 +#define DDRSS1_PHY_1400_DATA 0x03900390 +#define DDRSS1_PHY_1401_DATA 0x00000390 +#define DDRSS1_PHY_1402_DATA 0x00000390 +#define DDRSS1_PHY_1403_DATA 0x00000390 +#define DDRSS1_PHY_1404_DATA 0x00000390 +#define DDRSS1_PHY_1405_DATA 0x00000005 +#define DDRSS1_PHY_1406_DATA 0x01813FCC +#define DDRSS1_PHY_1407_DATA 0x000000CC +#define DDRSS1_PHY_1408_DATA 0x0C000DFF +#define DDRSS1_PHY_1409_DATA 0x30000DFF +#define DDRSS1_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1411_DATA 0x000100F0 +#define DDRSS1_PHY_1412_DATA 0x780DFFCC +#define DDRSS1_PHY_1413_DATA 0x00007E31 +#define DDRSS1_PHY_1414_DATA 0x000CBF11 +#define DDRSS1_PHY_1415_DATA 0x01990010 +#define DDRSS1_PHY_1416_DATA 0x000CBF11 +#define DDRSS1_PHY_1417_DATA 0x01990010 +#define DDRSS1_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1419_DATA 0x00EF00F0 +#define DDRSS1_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1421_DATA 0x01FF00F0 +#define DDRSS1_PHY_1422_DATA 0x20040006 + +#define DDRSS2_CTL_00_DATA 0x00000B00 +#define DDRSS2_CTL_01_DATA 0x00000000 +#define DDRSS2_CTL_02_DATA 0x00000000 +#define DDRSS2_CTL_03_DATA 0x00000000 +#define DDRSS2_CTL_04_DATA 0x00000000 +#define DDRSS2_CTL_05_DATA 0x00000000 +#define DDRSS2_CTL_06_DATA 0x00000000 +#define DDRSS2_CTL_07_DATA 0x00002AF8 +#define DDRSS2_CTL_08_DATA 0x0001ADAF +#define DDRSS2_CTL_09_DATA 0x00000005 +#define DDRSS2_CTL_10_DATA 0x0000006E +#define DDRSS2_CTL_11_DATA 0x000681C8 +#define DDRSS2_CTL_12_DATA 0x004111C9 +#define DDRSS2_CTL_13_DATA 0x00000005 +#define DDRSS2_CTL_14_DATA 0x000010A9 +#define DDRSS2_CTL_15_DATA 0x000681C8 +#define DDRSS2_CTL_16_DATA 0x004111C9 +#define DDRSS2_CTL_17_DATA 0x00000005 +#define DDRSS2_CTL_18_DATA 0x000010A9 +#define DDRSS2_CTL_19_DATA 0x01010000 +#define DDRSS2_CTL_20_DATA 0x01011001 +#define DDRSS2_CTL_21_DATA 0x02010000 +#define DDRSS2_CTL_22_DATA 0x00020100 +#define DDRSS2_CTL_23_DATA 0x0000000B +#define DDRSS2_CTL_24_DATA 0x0000001C +#define DDRSS2_CTL_25_DATA 0x00000000 +#define DDRSS2_CTL_26_DATA 0x00000000 +#define DDRSS2_CTL_27_DATA 0x03020200 +#define DDRSS2_CTL_28_DATA 0x00005656 +#define DDRSS2_CTL_29_DATA 0x00100000 +#define DDRSS2_CTL_30_DATA 0x00000000 +#define DDRSS2_CTL_31_DATA 0x00000000 +#define DDRSS2_CTL_32_DATA 0x00000000 +#define DDRSS2_CTL_33_DATA 0x00000000 +#define DDRSS2_CTL_34_DATA 0x040C0000 +#define DDRSS2_CTL_35_DATA 0x12501250 +#define DDRSS2_CTL_36_DATA 0x00050804 +#define DDRSS2_CTL_37_DATA 0x09040008 +#define DDRSS2_CTL_38_DATA 0x15000204 +#define DDRSS2_CTL_39_DATA 0x1760008B +#define DDRSS2_CTL_40_DATA 0x1500422B +#define DDRSS2_CTL_41_DATA 0x1760008B +#define DDRSS2_CTL_42_DATA 0x2000422B +#define DDRSS2_CTL_43_DATA 0x000A0A09 +#define DDRSS2_CTL_44_DATA 0x040003C5 +#define DDRSS2_CTL_45_DATA 0x1E161104 +#define DDRSS2_CTL_46_DATA 0x1000922C +#define DDRSS2_CTL_47_DATA 0x1E161110 +#define DDRSS2_CTL_48_DATA 0x1000922C +#define DDRSS2_CTL_49_DATA 0x02030410 +#define DDRSS2_CTL_50_DATA 0x2C060500 +#define DDRSS2_CTL_51_DATA 0x08292C29 +#define DDRSS2_CTL_52_DATA 0x14000E0A +#define DDRSS2_CTL_53_DATA 0x04010A0A +#define DDRSS2_CTL_54_DATA 0x01010004 +#define DDRSS2_CTL_55_DATA 0x0454540A +#define DDRSS2_CTL_56_DATA 0x04313104 +#define DDRSS2_CTL_57_DATA 0x00003131 +#define DDRSS2_CTL_58_DATA 0x00010100 +#define DDRSS2_CTL_59_DATA 0x03010000 +#define DDRSS2_CTL_60_DATA 0x00001508 +#define DDRSS2_CTL_61_DATA 0x00000068 +#define DDRSS2_CTL_62_DATA 0x0000032B +#define DDRSS2_CTL_63_DATA 0x00001035 +#define DDRSS2_CTL_64_DATA 0x0000032B +#define DDRSS2_CTL_65_DATA 0x00001035 +#define DDRSS2_CTL_66_DATA 0x00000005 +#define DDRSS2_CTL_67_DATA 0x00050000 +#define DDRSS2_CTL_68_DATA 0x00CB0005 +#define DDRSS2_CTL_69_DATA 0x00CB0200 +#define DDRSS2_CTL_70_DATA 0x00400200 +#define DDRSS2_CTL_71_DATA 0x00120103 +#define DDRSS2_CTL_72_DATA 0x00100005 +#define DDRSS2_CTL_73_DATA 0x2F080010 +#define DDRSS2_CTL_74_DATA 0x0505012F +#define DDRSS2_CTL_75_DATA 0x0401030A +#define DDRSS2_CTL_76_DATA 0x041E100B +#define DDRSS2_CTL_77_DATA 0x100B0401 +#define DDRSS2_CTL_78_DATA 0x0001041E +#define DDRSS2_CTL_79_DATA 0x00160016 +#define DDRSS2_CTL_80_DATA 0x033B033B +#define DDRSS2_CTL_81_DATA 0x033B033B +#define DDRSS2_CTL_82_DATA 0x03050505 +#define DDRSS2_CTL_83_DATA 0x03010303 +#define DDRSS2_CTL_84_DATA 0x200B100B +#define DDRSS2_CTL_85_DATA 0x04041004 +#define DDRSS2_CTL_86_DATA 0x200B100B +#define DDRSS2_CTL_87_DATA 0x04041004 +#define DDRSS2_CTL_88_DATA 0x03010000 +#define DDRSS2_CTL_89_DATA 0x00010000 +#define DDRSS2_CTL_90_DATA 0x00000000 +#define DDRSS2_CTL_91_DATA 0x00000000 +#define DDRSS2_CTL_92_DATA 0x01000000 +#define DDRSS2_CTL_93_DATA 0x80104002 +#define DDRSS2_CTL_94_DATA 0x00000000 +#define DDRSS2_CTL_95_DATA 0x00040005 +#define DDRSS2_CTL_96_DATA 0x00000000 +#define DDRSS2_CTL_97_DATA 0x00050000 +#define DDRSS2_CTL_98_DATA 0x00000004 +#define DDRSS2_CTL_99_DATA 0x00000000 +#define DDRSS2_CTL_100_DATA 0x00040005 +#define DDRSS2_CTL_101_DATA 0x00000000 +#define DDRSS2_CTL_102_DATA 0x000018C0 +#define DDRSS2_CTL_103_DATA 0x000018C0 +#define DDRSS2_CTL_104_DATA 0x000018C0 +#define DDRSS2_CTL_105_DATA 0x000018C0 +#define DDRSS2_CTL_106_DATA 0x000018C0 +#define DDRSS2_CTL_107_DATA 0x00000000 +#define DDRSS2_CTL_108_DATA 0x000002B5 +#define DDRSS2_CTL_109_DATA 0x00040D40 +#define DDRSS2_CTL_110_DATA 0x00040D40 +#define DDRSS2_CTL_111_DATA 0x00040D40 +#define DDRSS2_CTL_112_DATA 0x00040D40 +#define DDRSS2_CTL_113_DATA 0x00040D40 +#define DDRSS2_CTL_114_DATA 0x00000000 +#define DDRSS2_CTL_115_DATA 0x00007173 +#define DDRSS2_CTL_116_DATA 0x00040D40 +#define DDRSS2_CTL_117_DATA 0x00040D40 +#define DDRSS2_CTL_118_DATA 0x00040D40 +#define DDRSS2_CTL_119_DATA 0x00040D40 +#define DDRSS2_CTL_120_DATA 0x00040D40 +#define DDRSS2_CTL_121_DATA 0x00000000 +#define DDRSS2_CTL_122_DATA 0x00007173 +#define DDRSS2_CTL_123_DATA 0x00000000 +#define DDRSS2_CTL_124_DATA 0x00000000 +#define DDRSS2_CTL_125_DATA 0x00000000 +#define DDRSS2_CTL_126_DATA 0x00000000 +#define DDRSS2_CTL_127_DATA 0x00000000 +#define DDRSS2_CTL_128_DATA 0x00000000 +#define DDRSS2_CTL_129_DATA 0x00000000 +#define DDRSS2_CTL_130_DATA 0x00000000 +#define DDRSS2_CTL_131_DATA 0x0B030500 +#define DDRSS2_CTL_132_DATA 0x00040B04 +#define DDRSS2_CTL_133_DATA 0x0A090000 +#define DDRSS2_CTL_134_DATA 0x0A090701 +#define DDRSS2_CTL_135_DATA 0x0900000E +#define DDRSS2_CTL_136_DATA 0x0907010A +#define DDRSS2_CTL_137_DATA 0x00000E0A +#define DDRSS2_CTL_138_DATA 0x07010A09 +#define DDRSS2_CTL_139_DATA 0x000E0A09 +#define DDRSS2_CTL_140_DATA 0x07000401 +#define DDRSS2_CTL_141_DATA 0x00000000 +#define DDRSS2_CTL_142_DATA 0x00000000 +#define DDRSS2_CTL_143_DATA 0x00000000 +#define DDRSS2_CTL_144_DATA 0x00000000 +#define DDRSS2_CTL_145_DATA 0x00000000 +#define DDRSS2_CTL_146_DATA 0x00000000 +#define DDRSS2_CTL_147_DATA 0x00000000 +#define DDRSS2_CTL_148_DATA 0x08080000 +#define DDRSS2_CTL_149_DATA 0x01000000 +#define DDRSS2_CTL_150_DATA 0x800000C0 +#define DDRSS2_CTL_151_DATA 0x800000C0 +#define DDRSS2_CTL_152_DATA 0x800000C0 +#define DDRSS2_CTL_153_DATA 0x00000000 +#define DDRSS2_CTL_154_DATA 0x00001500 +#define DDRSS2_CTL_155_DATA 0x00000000 +#define DDRSS2_CTL_156_DATA 0x00000001 +#define DDRSS2_CTL_157_DATA 0x00000002 +#define DDRSS2_CTL_158_DATA 0x0000100E +#define DDRSS2_CTL_159_DATA 0x00000000 +#define DDRSS2_CTL_160_DATA 0x00000000 +#define DDRSS2_CTL_161_DATA 0x00000000 +#define DDRSS2_CTL_162_DATA 0x00000000 +#define DDRSS2_CTL_163_DATA 0x00000000 +#define DDRSS2_CTL_164_DATA 0x000B0000 +#define DDRSS2_CTL_165_DATA 0x000E0006 +#define DDRSS2_CTL_166_DATA 0x000E0404 +#define DDRSS2_CTL_167_DATA 0x00D601AB +#define DDRSS2_CTL_168_DATA 0x10100216 +#define DDRSS2_CTL_169_DATA 0x01AB0216 +#define DDRSS2_CTL_170_DATA 0x021600D6 +#define DDRSS2_CTL_171_DATA 0x02161010 +#define DDRSS2_CTL_172_DATA 0x00000000 +#define DDRSS2_CTL_173_DATA 0x00000000 +#define DDRSS2_CTL_174_DATA 0x00000000 +#define DDRSS2_CTL_175_DATA 0x3FF40084 +#define DDRSS2_CTL_176_DATA 0xF3003FF4 +#define DDRSS2_CTL_177_DATA 0x0000F3F3 +#define DDRSS2_CTL_178_DATA 0x35000000 +#define DDRSS2_CTL_179_DATA 0x27270035 +#define DDRSS2_CTL_180_DATA 0x0F0F0000 +#define DDRSS2_CTL_181_DATA 0x16000000 +#define DDRSS2_CTL_182_DATA 0x00841616 +#define DDRSS2_CTL_183_DATA 0x3FF43FF4 +#define DDRSS2_CTL_184_DATA 0xF3F3F300 +#define DDRSS2_CTL_185_DATA 0x00000000 +#define DDRSS2_CTL_186_DATA 0x00353500 +#define DDRSS2_CTL_187_DATA 0x00002727 +#define DDRSS2_CTL_188_DATA 0x00000F0F +#define DDRSS2_CTL_189_DATA 0x16161600 +#define DDRSS2_CTL_190_DATA 0x00000020 +#define DDRSS2_CTL_191_DATA 0x01000000 +#define DDRSS2_CTL_192_DATA 0x00000001 +#define DDRSS2_CTL_193_DATA 0x00000000 +#define DDRSS2_CTL_194_DATA 0x01000000 +#define DDRSS2_CTL_195_DATA 0x00000001 +#define DDRSS2_CTL_196_DATA 0x00000000 +#define DDRSS2_CTL_197_DATA 0x00000000 +#define DDRSS2_CTL_198_DATA 0x00000000 +#define DDRSS2_CTL_199_DATA 0x00000000 +#define DDRSS2_CTL_200_DATA 0x00000000 +#define DDRSS2_CTL_201_DATA 0x00000000 +#define DDRSS2_CTL_202_DATA 0x00000000 +#define DDRSS2_CTL_203_DATA 0x00000000 +#define DDRSS2_CTL_204_DATA 0x00000000 +#define DDRSS2_CTL_205_DATA 0x00000000 +#define DDRSS2_CTL_206_DATA 0x02000000 +#define DDRSS2_CTL_207_DATA 0x01080101 +#define DDRSS2_CTL_208_DATA 0x00000000 +#define DDRSS2_CTL_209_DATA 0x00000000 +#define DDRSS2_CTL_210_DATA 0x00000000 +#define DDRSS2_CTL_211_DATA 0x00000000 +#define DDRSS2_CTL_212_DATA 0x00000000 +#define DDRSS2_CTL_213_DATA 0x00000000 +#define DDRSS2_CTL_214_DATA 0x00000000 +#define DDRSS2_CTL_215_DATA 0x00000000 +#define DDRSS2_CTL_216_DATA 0x00000000 +#define DDRSS2_CTL_217_DATA 0x00000000 +#define DDRSS2_CTL_218_DATA 0x00000000 +#define DDRSS2_CTL_219_DATA 0x00000000 +#define DDRSS2_CTL_220_DATA 0x00000000 +#define DDRSS2_CTL_221_DATA 0x00000000 +#define DDRSS2_CTL_222_DATA 0x00001000 +#define DDRSS2_CTL_223_DATA 0x006403E8 +#define DDRSS2_CTL_224_DATA 0x00000000 +#define DDRSS2_CTL_225_DATA 0x00000000 +#define DDRSS2_CTL_226_DATA 0x00000000 +#define DDRSS2_CTL_227_DATA 0x15110000 +#define DDRSS2_CTL_228_DATA 0x00040C18 +#define DDRSS2_CTL_229_DATA 0xF000C000 +#define DDRSS2_CTL_230_DATA 0x0000F000 +#define DDRSS2_CTL_231_DATA 0x00000000 +#define DDRSS2_CTL_232_DATA 0x00000000 +#define DDRSS2_CTL_233_DATA 0xC0000000 +#define DDRSS2_CTL_234_DATA 0xF000F000 +#define DDRSS2_CTL_235_DATA 0x00000000 +#define DDRSS2_CTL_236_DATA 0x00000000 +#define DDRSS2_CTL_237_DATA 0x00000000 +#define DDRSS2_CTL_238_DATA 0xF000C000 +#define DDRSS2_CTL_239_DATA 0x0000F000 +#define DDRSS2_CTL_240_DATA 0x00000000 +#define DDRSS2_CTL_241_DATA 0x00000000 +#define DDRSS2_CTL_242_DATA 0x00030000 +#define DDRSS2_CTL_243_DATA 0x00000000 +#define DDRSS2_CTL_244_DATA 0x00000000 +#define DDRSS2_CTL_245_DATA 0x00000000 +#define DDRSS2_CTL_246_DATA 0x00000000 +#define DDRSS2_CTL_247_DATA 0x00000000 +#define DDRSS2_CTL_248_DATA 0x00000000 +#define DDRSS2_CTL_249_DATA 0x00000000 +#define DDRSS2_CTL_250_DATA 0x00000000 +#define DDRSS2_CTL_251_DATA 0x00000000 +#define DDRSS2_CTL_252_DATA 0x00000000 +#define DDRSS2_CTL_253_DATA 0x00000000 +#define DDRSS2_CTL_254_DATA 0x00000000 +#define DDRSS2_CTL_255_DATA 0x00000000 +#define DDRSS2_CTL_256_DATA 0x00000000 +#define DDRSS2_CTL_257_DATA 0x01000200 +#define DDRSS2_CTL_258_DATA 0x00370040 +#define DDRSS2_CTL_259_DATA 0x00020008 +#define DDRSS2_CTL_260_DATA 0x00400100 +#define DDRSS2_CTL_261_DATA 0x00400855 +#define DDRSS2_CTL_262_DATA 0x01000200 +#define DDRSS2_CTL_263_DATA 0x08550040 +#define DDRSS2_CTL_264_DATA 0x00000040 +#define DDRSS2_CTL_265_DATA 0x006B0003 +#define DDRSS2_CTL_266_DATA 0x0100006B +#define DDRSS2_CTL_267_DATA 0x03030303 +#define DDRSS2_CTL_268_DATA 0x00000000 +#define DDRSS2_CTL_269_DATA 0x00000202 +#define DDRSS2_CTL_270_DATA 0x00001FFF +#define DDRSS2_CTL_271_DATA 0x3FFF2000 +#define DDRSS2_CTL_272_DATA 0x03FF0000 +#define DDRSS2_CTL_273_DATA 0x000103FF +#define DDRSS2_CTL_274_DATA 0x0FFF0B00 +#define DDRSS2_CTL_275_DATA 0x01010001 +#define DDRSS2_CTL_276_DATA 0x01010101 +#define DDRSS2_CTL_277_DATA 0x01180101 +#define DDRSS2_CTL_278_DATA 0x00030000 +#define DDRSS2_CTL_279_DATA 0x00000000 +#define DDRSS2_CTL_280_DATA 0x00000000 +#define DDRSS2_CTL_281_DATA 0x00000000 +#define DDRSS2_CTL_282_DATA 0x00000000 +#define DDRSS2_CTL_283_DATA 0x00000000 +#define DDRSS2_CTL_284_DATA 0x00000000 +#define DDRSS2_CTL_285_DATA 0x00000000 +#define DDRSS2_CTL_286_DATA 0x00040101 +#define DDRSS2_CTL_287_DATA 0x04010100 +#define DDRSS2_CTL_288_DATA 0x00000000 +#define DDRSS2_CTL_289_DATA 0x00000000 +#define DDRSS2_CTL_290_DATA 0x03030300 +#define DDRSS2_CTL_291_DATA 0x00010101 +#define DDRSS2_CTL_292_DATA 0x00000000 +#define DDRSS2_CTL_293_DATA 0x00000000 +#define DDRSS2_CTL_294_DATA 0x00000000 +#define DDRSS2_CTL_295_DATA 0x00000000 +#define DDRSS2_CTL_296_DATA 0x00000000 +#define DDRSS2_CTL_297_DATA 0xFFFFFFFF +#define DDRSS2_CTL_298_DATA 0x00000FFF +#define DDRSS2_CTL_299_DATA 0x00000000 +#define DDRSS2_CTL_300_DATA 0x00000000 +#define DDRSS2_CTL_301_DATA 0x00000000 +#define DDRSS2_CTL_302_DATA 0x00000000 +#define DDRSS2_CTL_303_DATA 0x00000000 +#define DDRSS2_CTL_304_DATA 0x00000000 +#define DDRSS2_CTL_305_DATA 0x00000000 +#define DDRSS2_CTL_306_DATA 0x00000000 +#define DDRSS2_CTL_307_DATA 0x00000000 +#define DDRSS2_CTL_308_DATA 0x00000000 +#define DDRSS2_CTL_309_DATA 0x00000000 +#define DDRSS2_CTL_310_DATA 0x00000000 +#define DDRSS2_CTL_311_DATA 0x00000000 +#define DDRSS2_CTL_312_DATA 0x00000000 +#define DDRSS2_CTL_313_DATA 0x01000000 +#define DDRSS2_CTL_314_DATA 0x00020201 +#define DDRSS2_CTL_315_DATA 0x01000101 +#define DDRSS2_CTL_316_DATA 0x01010001 +#define DDRSS2_CTL_317_DATA 0x00010101 +#define DDRSS2_CTL_318_DATA 0x050A0A03 +#define DDRSS2_CTL_319_DATA 0x10082323 +#define DDRSS2_CTL_320_DATA 0x00090310 +#define DDRSS2_CTL_321_DATA 0x0B0C030F +#define DDRSS2_CTL_322_DATA 0x0B0C0306 +#define DDRSS2_CTL_323_DATA 0x0C090006 +#define DDRSS2_CTL_324_DATA 0x0100000C +#define DDRSS2_CTL_325_DATA 0x08040801 +#define DDRSS2_CTL_326_DATA 0x00000004 +#define DDRSS2_CTL_327_DATA 0x00000000 +#define DDRSS2_CTL_328_DATA 0x00010000 +#define DDRSS2_CTL_329_DATA 0x00280D00 +#define DDRSS2_CTL_330_DATA 0x00000001 +#define DDRSS2_CTL_331_DATA 0x00030001 +#define DDRSS2_CTL_332_DATA 0x00000000 +#define DDRSS2_CTL_333_DATA 0x00000000 +#define DDRSS2_CTL_334_DATA 0x00000000 +#define DDRSS2_CTL_335_DATA 0x00000000 +#define DDRSS2_CTL_336_DATA 0x00000000 +#define DDRSS2_CTL_337_DATA 0x00000000 +#define DDRSS2_CTL_338_DATA 0x00000000 +#define DDRSS2_CTL_339_DATA 0x00000000 +#define DDRSS2_CTL_340_DATA 0x01000000 +#define DDRSS2_CTL_341_DATA 0x00000001 +#define DDRSS2_CTL_342_DATA 0x00010100 +#define DDRSS2_CTL_343_DATA 0x03030000 +#define DDRSS2_CTL_344_DATA 0x00000000 +#define DDRSS2_CTL_345_DATA 0x00000000 +#define DDRSS2_CTL_346_DATA 0x00000000 +#define DDRSS2_CTL_347_DATA 0x00000000 +#define DDRSS2_CTL_348_DATA 0x00000000 +#define DDRSS2_CTL_349_DATA 0x00000000 +#define DDRSS2_CTL_350_DATA 0x00000000 +#define DDRSS2_CTL_351_DATA 0x00000000 +#define DDRSS2_CTL_352_DATA 0x00000000 +#define DDRSS2_CTL_353_DATA 0x00000000 +#define DDRSS2_CTL_354_DATA 0x00000000 +#define DDRSS2_CTL_355_DATA 0x00000000 +#define DDRSS2_CTL_356_DATA 0x00000000 +#define DDRSS2_CTL_357_DATA 0x00000000 +#define DDRSS2_CTL_358_DATA 0x00000000 +#define DDRSS2_CTL_359_DATA 0x00000000 +#define DDRSS2_CTL_360_DATA 0x000556AA +#define DDRSS2_CTL_361_DATA 0x000AAAAA +#define DDRSS2_CTL_362_DATA 0x000AA955 +#define DDRSS2_CTL_363_DATA 0x00055555 +#define DDRSS2_CTL_364_DATA 0x000B3133 +#define DDRSS2_CTL_365_DATA 0x0004CD33 +#define DDRSS2_CTL_366_DATA 0x0004CECC +#define DDRSS2_CTL_367_DATA 0x000B32CC +#define DDRSS2_CTL_368_DATA 0x00010300 +#define DDRSS2_CTL_369_DATA 0x03000100 +#define DDRSS2_CTL_370_DATA 0x00000000 +#define DDRSS2_CTL_371_DATA 0x00000000 +#define DDRSS2_CTL_372_DATA 0x00000000 +#define DDRSS2_CTL_373_DATA 0x00000000 +#define DDRSS2_CTL_374_DATA 0x00000000 +#define DDRSS2_CTL_375_DATA 0x00000000 +#define DDRSS2_CTL_376_DATA 0x00000000 +#define DDRSS2_CTL_377_DATA 0x00010000 +#define DDRSS2_CTL_378_DATA 0x00000404 +#define DDRSS2_CTL_379_DATA 0x00000000 +#define DDRSS2_CTL_380_DATA 0x00000000 +#define DDRSS2_CTL_381_DATA 0x00000000 +#define DDRSS2_CTL_382_DATA 0x00000000 +#define DDRSS2_CTL_383_DATA 0x00000000 +#define DDRSS2_CTL_384_DATA 0x00000000 +#define DDRSS2_CTL_385_DATA 0x00000000 +#define DDRSS2_CTL_386_DATA 0x00000000 +#define DDRSS2_CTL_387_DATA 0x3A3A1B00 +#define DDRSS2_CTL_388_DATA 0x000A0000 +#define DDRSS2_CTL_389_DATA 0x000000C6 +#define DDRSS2_CTL_390_DATA 0x00000200 +#define DDRSS2_CTL_391_DATA 0x00000200 +#define DDRSS2_CTL_392_DATA 0x00000200 +#define DDRSS2_CTL_393_DATA 0x00000200 +#define DDRSS2_CTL_394_DATA 0x00000270 +#define DDRSS2_CTL_395_DATA 0x000007BC +#define DDRSS2_CTL_396_DATA 0x00000204 +#define DDRSS2_CTL_397_DATA 0x0000206A +#define DDRSS2_CTL_398_DATA 0x00000200 +#define DDRSS2_CTL_399_DATA 0x00000200 +#define DDRSS2_CTL_400_DATA 0x00000200 +#define DDRSS2_CTL_401_DATA 0x00000200 +#define DDRSS2_CTL_402_DATA 0x0000613E +#define DDRSS2_CTL_403_DATA 0x00014424 +#define DDRSS2_CTL_404_DATA 0x00000E19 +#define DDRSS2_CTL_405_DATA 0x0000206A +#define DDRSS2_CTL_406_DATA 0x00000200 +#define DDRSS2_CTL_407_DATA 0x00000200 +#define DDRSS2_CTL_408_DATA 0x00000200 +#define DDRSS2_CTL_409_DATA 0x00000200 +#define DDRSS2_CTL_410_DATA 0x0000613E +#define DDRSS2_CTL_411_DATA 0x00014424 +#define DDRSS2_CTL_412_DATA 0x02020E19 +#define DDRSS2_CTL_413_DATA 0x03030202 +#define DDRSS2_CTL_414_DATA 0x00000022 +#define DDRSS2_CTL_415_DATA 0x00000000 +#define DDRSS2_CTL_416_DATA 0x00000000 +#define DDRSS2_CTL_417_DATA 0x00001403 +#define DDRSS2_CTL_418_DATA 0x000007D0 +#define DDRSS2_CTL_419_DATA 0x00000000 +#define DDRSS2_CTL_420_DATA 0x00000000 +#define DDRSS2_CTL_421_DATA 0x00030000 +#define DDRSS2_CTL_422_DATA 0x0007001F +#define DDRSS2_CTL_423_DATA 0x001B0033 +#define DDRSS2_CTL_424_DATA 0x001B0033 +#define DDRSS2_CTL_425_DATA 0x00000000 +#define DDRSS2_CTL_426_DATA 0x00000000 +#define DDRSS2_CTL_427_DATA 0x02000000 +#define DDRSS2_CTL_428_DATA 0x01000404 +#define DDRSS2_CTL_429_DATA 0x0B220B22 +#define DDRSS2_CTL_430_DATA 0x00000105 +#define DDRSS2_CTL_431_DATA 0x00010101 +#define DDRSS2_CTL_432_DATA 0x00010101 +#define DDRSS2_CTL_433_DATA 0x00010001 +#define DDRSS2_CTL_434_DATA 0x00000101 +#define DDRSS2_CTL_435_DATA 0x02000201 +#define DDRSS2_CTL_436_DATA 0x02010000 +#define DDRSS2_CTL_437_DATA 0x00000200 +#define DDRSS2_CTL_438_DATA 0x28060000 +#define DDRSS2_CTL_439_DATA 0x00000128 +#define DDRSS2_CTL_440_DATA 0xFFFFFFFF +#define DDRSS2_CTL_441_DATA 0xFFFFFFFF +#define DDRSS2_CTL_442_DATA 0x00000000 +#define DDRSS2_CTL_443_DATA 0x00000000 +#define DDRSS2_CTL_444_DATA 0x00000000 +#define DDRSS2_CTL_445_DATA 0x00000000 +#define DDRSS2_CTL_446_DATA 0x00000000 +#define DDRSS2_CTL_447_DATA 0x00000000 +#define DDRSS2_CTL_448_DATA 0x00000000 +#define DDRSS2_CTL_449_DATA 0x00000000 +#define DDRSS2_CTL_450_DATA 0x00000000 +#define DDRSS2_CTL_451_DATA 0x00000000 +#define DDRSS2_CTL_452_DATA 0x00000000 +#define DDRSS2_CTL_453_DATA 0x00000000 +#define DDRSS2_CTL_454_DATA 0x00000000 +#define DDRSS2_CTL_455_DATA 0x00000000 +#define DDRSS2_CTL_456_DATA 0x00000000 +#define DDRSS2_CTL_457_DATA 0x00000000 +#define DDRSS2_CTL_458_DATA 0x00000000 + +#define DDRSS2_PI_00_DATA 0x00000B00 +#define DDRSS2_PI_01_DATA 0x00000000 +#define DDRSS2_PI_02_DATA 0x00000000 +#define DDRSS2_PI_03_DATA 0x00000000 +#define DDRSS2_PI_04_DATA 0x00000000 +#define DDRSS2_PI_05_DATA 0x00000101 +#define DDRSS2_PI_06_DATA 0x00640000 +#define DDRSS2_PI_07_DATA 0x00000001 +#define DDRSS2_PI_08_DATA 0x00000000 +#define DDRSS2_PI_09_DATA 0x00000000 +#define DDRSS2_PI_10_DATA 0x00000000 +#define DDRSS2_PI_11_DATA 0x00000000 +#define DDRSS2_PI_12_DATA 0x00000003 +#define DDRSS2_PI_13_DATA 0x00010001 +#define DDRSS2_PI_14_DATA 0x0800000F +#define DDRSS2_PI_15_DATA 0x00000103 +#define DDRSS2_PI_16_DATA 0x00000005 +#define DDRSS2_PI_17_DATA 0x00000000 +#define DDRSS2_PI_18_DATA 0x00000000 +#define DDRSS2_PI_19_DATA 0x00000000 +#define DDRSS2_PI_20_DATA 0x00000000 +#define DDRSS2_PI_21_DATA 0x00000000 +#define DDRSS2_PI_22_DATA 0x00000000 +#define DDRSS2_PI_23_DATA 0x00000000 +#define DDRSS2_PI_24_DATA 0x00000000 +#define DDRSS2_PI_25_DATA 0x00000000 +#define DDRSS2_PI_26_DATA 0x00010100 +#define DDRSS2_PI_27_DATA 0x00280A00 +#define DDRSS2_PI_28_DATA 0x00000000 +#define DDRSS2_PI_29_DATA 0x0F000000 +#define DDRSS2_PI_30_DATA 0x00003200 +#define DDRSS2_PI_31_DATA 0x00000000 +#define DDRSS2_PI_32_DATA 0x00000000 +#define DDRSS2_PI_33_DATA 0x01010102 +#define DDRSS2_PI_34_DATA 0x00000000 +#define DDRSS2_PI_35_DATA 0x000000AA +#define DDRSS2_PI_36_DATA 0x00000055 +#define DDRSS2_PI_37_DATA 0x000000B5 +#define DDRSS2_PI_38_DATA 0x0000004A +#define DDRSS2_PI_39_DATA 0x00000056 +#define DDRSS2_PI_40_DATA 0x000000A9 +#define DDRSS2_PI_41_DATA 0x000000A9 +#define DDRSS2_PI_42_DATA 0x000000B5 +#define DDRSS2_PI_43_DATA 0x00000000 +#define DDRSS2_PI_44_DATA 0x00000000 +#define DDRSS2_PI_45_DATA 0x000F0F00 +#define DDRSS2_PI_46_DATA 0x0000001B +#define DDRSS2_PI_47_DATA 0x000007D0 +#define DDRSS2_PI_48_DATA 0x00000300 +#define DDRSS2_PI_49_DATA 0x00000000 +#define DDRSS2_PI_50_DATA 0x00000000 +#define DDRSS2_PI_51_DATA 0x01000000 +#define DDRSS2_PI_52_DATA 0x00010101 +#define DDRSS2_PI_53_DATA 0x00000000 +#define DDRSS2_PI_54_DATA 0x00030000 +#define DDRSS2_PI_55_DATA 0x0F000000 +#define DDRSS2_PI_56_DATA 0x00000017 +#define DDRSS2_PI_57_DATA 0x00000000 +#define DDRSS2_PI_58_DATA 0x00000000 +#define DDRSS2_PI_59_DATA 0x00000000 +#define DDRSS2_PI_60_DATA 0x0A0A140A +#define DDRSS2_PI_61_DATA 0x10020201 +#define DDRSS2_PI_62_DATA 0x00020805 +#define DDRSS2_PI_63_DATA 0x01000404 +#define DDRSS2_PI_64_DATA 0x00000000 +#define DDRSS2_PI_65_DATA 0x00000000 +#define DDRSS2_PI_66_DATA 0x00000100 +#define DDRSS2_PI_67_DATA 0x0002020F +#define DDRSS2_PI_68_DATA 0x00340000 +#define DDRSS2_PI_69_DATA 0x00000000 +#define DDRSS2_PI_70_DATA 0x00000000 +#define DDRSS2_PI_71_DATA 0x0000FFFF +#define DDRSS2_PI_72_DATA 0x01000000 +#define DDRSS2_PI_73_DATA 0x00080000 +#define DDRSS2_PI_74_DATA 0x02000200 +#define DDRSS2_PI_75_DATA 0x01000100 +#define DDRSS2_PI_76_DATA 0x01000000 +#define DDRSS2_PI_77_DATA 0x02000200 +#define DDRSS2_PI_78_DATA 0x00000200 +#define DDRSS2_PI_79_DATA 0x00000000 +#define DDRSS2_PI_80_DATA 0x00000000 +#define DDRSS2_PI_81_DATA 0x00000000 +#define DDRSS2_PI_82_DATA 0x00000000 +#define DDRSS2_PI_83_DATA 0x00000000 +#define DDRSS2_PI_84_DATA 0x00000000 +#define DDRSS2_PI_85_DATA 0x00000000 +#define DDRSS2_PI_86_DATA 0x00000000 +#define DDRSS2_PI_87_DATA 0x00000000 +#define DDRSS2_PI_88_DATA 0x00000000 +#define DDRSS2_PI_89_DATA 0x00000000 +#define DDRSS2_PI_90_DATA 0x00000000 +#define DDRSS2_PI_91_DATA 0x00000400 +#define DDRSS2_PI_92_DATA 0x02010000 +#define DDRSS2_PI_93_DATA 0x00080003 +#define DDRSS2_PI_94_DATA 0x00080000 +#define DDRSS2_PI_95_DATA 0x00000001 +#define DDRSS2_PI_96_DATA 0x00000000 +#define DDRSS2_PI_97_DATA 0x0000AA00 +#define DDRSS2_PI_98_DATA 0x00000000 +#define DDRSS2_PI_99_DATA 0x00000000 +#define DDRSS2_PI_100_DATA 0x00010000 +#define DDRSS2_PI_101_DATA 0x00000000 +#define DDRSS2_PI_102_DATA 0x00000000 +#define DDRSS2_PI_103_DATA 0x00000000 +#define DDRSS2_PI_104_DATA 0x00000000 +#define DDRSS2_PI_105_DATA 0x00000000 +#define DDRSS2_PI_106_DATA 0x00000000 +#define DDRSS2_PI_107_DATA 0x00000000 +#define DDRSS2_PI_108_DATA 0x00000000 +#define DDRSS2_PI_109_DATA 0x00000000 +#define DDRSS2_PI_110_DATA 0x00000000 +#define DDRSS2_PI_111_DATA 0x00000000 +#define DDRSS2_PI_112_DATA 0x00000000 +#define DDRSS2_PI_113_DATA 0x00000000 +#define DDRSS2_PI_114_DATA 0x00000000 +#define DDRSS2_PI_115_DATA 0x00000000 +#define DDRSS2_PI_116_DATA 0x00000000 +#define DDRSS2_PI_117_DATA 0x00000000 +#define DDRSS2_PI_118_DATA 0x00000000 +#define DDRSS2_PI_119_DATA 0x00000000 +#define DDRSS2_PI_120_DATA 0x00000000 +#define DDRSS2_PI_121_DATA 0x00000000 +#define DDRSS2_PI_122_DATA 0x00000000 +#define DDRSS2_PI_123_DATA 0x00000000 +#define DDRSS2_PI_124_DATA 0x00000000 +#define DDRSS2_PI_125_DATA 0x00000008 +#define DDRSS2_PI_126_DATA 0x00000000 +#define DDRSS2_PI_127_DATA 0x00000000 +#define DDRSS2_PI_128_DATA 0x00000000 +#define DDRSS2_PI_129_DATA 0x00000000 +#define DDRSS2_PI_130_DATA 0x00000000 +#define DDRSS2_PI_131_DATA 0x00000000 +#define DDRSS2_PI_132_DATA 0x00000000 +#define DDRSS2_PI_133_DATA 0x00000000 +#define DDRSS2_PI_134_DATA 0x00000002 +#define DDRSS2_PI_135_DATA 0x00000000 +#define DDRSS2_PI_136_DATA 0x00000000 +#define DDRSS2_PI_137_DATA 0x0000000A +#define DDRSS2_PI_138_DATA 0x00000019 +#define DDRSS2_PI_139_DATA 0x00000100 +#define DDRSS2_PI_140_DATA 0x00000000 +#define DDRSS2_PI_141_DATA 0x00000000 +#define DDRSS2_PI_142_DATA 0x00000000 +#define DDRSS2_PI_143_DATA 0x00000000 +#define DDRSS2_PI_144_DATA 0x01000000 +#define DDRSS2_PI_145_DATA 0x00010003 +#define DDRSS2_PI_146_DATA 0x02000101 +#define DDRSS2_PI_147_DATA 0x01030001 +#define DDRSS2_PI_148_DATA 0x00010400 +#define DDRSS2_PI_149_DATA 0x06000105 +#define DDRSS2_PI_150_DATA 0x01070001 +#define DDRSS2_PI_151_DATA 0x00000000 +#define DDRSS2_PI_152_DATA 0x00000000 +#define DDRSS2_PI_153_DATA 0x00000000 +#define DDRSS2_PI_154_DATA 0x00010001 +#define DDRSS2_PI_155_DATA 0x00000000 +#define DDRSS2_PI_156_DATA 0x00000000 +#define DDRSS2_PI_157_DATA 0x00000000 +#define DDRSS2_PI_158_DATA 0x00000000 +#define DDRSS2_PI_159_DATA 0x00000401 +#define DDRSS2_PI_160_DATA 0x00000000 +#define DDRSS2_PI_161_DATA 0x05010000 +#define DDRSS2_PI_162_DATA 0x00000001 +#define DDRSS2_PI_163_DATA 0x2B2B0201 +#define DDRSS2_PI_164_DATA 0x00000034 +#define DDRSS2_PI_165_DATA 0x00000068 +#define DDRSS2_PI_166_DATA 0x00020068 +#define DDRSS2_PI_167_DATA 0x02000200 +#define DDRSS2_PI_168_DATA 0x50120C04 +#define DDRSS2_PI_169_DATA 0x00155012 +#define DDRSS2_PI_170_DATA 0x00000068 +#define DDRSS2_PI_171_DATA 0x0000032B +#define DDRSS2_PI_172_DATA 0x00001035 +#define DDRSS2_PI_173_DATA 0x0000032B +#define DDRSS2_PI_174_DATA 0x04001035 +#define DDRSS2_PI_175_DATA 0x01010404 +#define DDRSS2_PI_176_DATA 0x00001500 +#define DDRSS2_PI_177_DATA 0x00150015 +#define DDRSS2_PI_178_DATA 0x01000100 +#define DDRSS2_PI_179_DATA 0x00000100 +#define DDRSS2_PI_180_DATA 0x00000000 +#define DDRSS2_PI_181_DATA 0x01010101 +#define DDRSS2_PI_182_DATA 0x00000000 +#define DDRSS2_PI_183_DATA 0x00000000 +#define DDRSS2_PI_184_DATA 0x00000000 +#define DDRSS2_PI_185_DATA 0x19040000 +#define DDRSS2_PI_186_DATA 0x0E0E0219 +#define DDRSS2_PI_187_DATA 0x00040402 +#define DDRSS2_PI_188_DATA 0x000D0035 +#define DDRSS2_PI_189_DATA 0x00218049 +#define DDRSS2_PI_190_DATA 0x00218049 +#define DDRSS2_PI_191_DATA 0x01000101 +#define DDRSS2_PI_192_DATA 0x0004000E +#define DDRSS2_PI_193_DATA 0x00040216 +#define DDRSS2_PI_194_DATA 0x01000216 +#define DDRSS2_PI_195_DATA 0x000F000F +#define DDRSS2_PI_196_DATA 0x02170100 +#define DDRSS2_PI_197_DATA 0x01000217 +#define DDRSS2_PI_198_DATA 0x02170217 +#define DDRSS2_PI_199_DATA 0x2F1B3200 +#define DDRSS2_PI_200_DATA 0x01012F1B +#define DDRSS2_PI_201_DATA 0x0A070601 +#define DDRSS2_PI_202_DATA 0x1F130A0D +#define DDRSS2_PI_203_DATA 0x1F130A14 +#define DDRSS2_PI_204_DATA 0x0000C014 +#define DDRSS2_PI_205_DATA 0x00C01000 +#define DDRSS2_PI_206_DATA 0x00C01000 +#define DDRSS2_PI_207_DATA 0x00021000 +#define DDRSS2_PI_208_DATA 0x0024000E +#define DDRSS2_PI_209_DATA 0x00240216 +#define DDRSS2_PI_210_DATA 0x00110216 +#define DDRSS2_PI_211_DATA 0x32000056 +#define DDRSS2_PI_212_DATA 0x00000101 +#define DDRSS2_PI_213_DATA 0x005F0036 +#define DDRSS2_PI_214_DATA 0x03013212 +#define DDRSS2_PI_215_DATA 0x00003600 +#define DDRSS2_PI_216_DATA 0x3212005F +#define DDRSS2_PI_217_DATA 0x09000001 +#define DDRSS2_PI_218_DATA 0x06010504 +#define DDRSS2_PI_219_DATA 0x04000364 +#define DDRSS2_PI_220_DATA 0x0A032001 +#define DDRSS2_PI_221_DATA 0x2C31110A +#define DDRSS2_PI_222_DATA 0x00002918 +#define DDRSS2_PI_223_DATA 0x6000838E +#define DDRSS2_PI_224_DATA 0x1E202008 +#define DDRSS2_PI_225_DATA 0x2C311116 +#define DDRSS2_PI_226_DATA 0x00002918 +#define DDRSS2_PI_227_DATA 0x6000838E +#define DDRSS2_PI_228_DATA 0x1E202008 +#define DDRSS2_PI_229_DATA 0x0000C616 +#define DDRSS2_PI_230_DATA 0x000007BC +#define DDRSS2_PI_231_DATA 0x0000206A +#define DDRSS2_PI_232_DATA 0x00014424 +#define DDRSS2_PI_233_DATA 0x0000206A +#define DDRSS2_PI_234_DATA 0x00014424 +#define DDRSS2_PI_235_DATA 0x033B0016 +#define DDRSS2_PI_236_DATA 0x0303033B +#define DDRSS2_PI_237_DATA 0x002AF803 +#define DDRSS2_PI_238_DATA 0x0001ADAF +#define DDRSS2_PI_239_DATA 0x00000005 +#define DDRSS2_PI_240_DATA 0x0000006E +#define DDRSS2_PI_241_DATA 0x00000016 +#define DDRSS2_PI_242_DATA 0x000681C8 +#define DDRSS2_PI_243_DATA 0x0001ADAF +#define DDRSS2_PI_244_DATA 0x00000005 +#define DDRSS2_PI_245_DATA 0x000010A9 +#define DDRSS2_PI_246_DATA 0x0000033B +#define DDRSS2_PI_247_DATA 0x000681C8 +#define DDRSS2_PI_248_DATA 0x0001ADAF +#define DDRSS2_PI_249_DATA 0x00000005 +#define DDRSS2_PI_250_DATA 0x000010A9 +#define DDRSS2_PI_251_DATA 0x0100033B +#define DDRSS2_PI_252_DATA 0x00370040 +#define DDRSS2_PI_253_DATA 0x00010008 +#define DDRSS2_PI_254_DATA 0x08550040 +#define DDRSS2_PI_255_DATA 0x00010040 +#define DDRSS2_PI_256_DATA 0x08550040 +#define DDRSS2_PI_257_DATA 0x00000340 +#define DDRSS2_PI_258_DATA 0x006B006B +#define DDRSS2_PI_259_DATA 0x08040404 +#define DDRSS2_PI_260_DATA 0x00000055 +#define DDRSS2_PI_261_DATA 0x55083C5A +#define DDRSS2_PI_262_DATA 0x5A000000 +#define DDRSS2_PI_263_DATA 0x0055083C +#define DDRSS2_PI_264_DATA 0x3C5A0000 +#define DDRSS2_PI_265_DATA 0x00005508 +#define DDRSS2_PI_266_DATA 0x0C3C5A00 +#define DDRSS2_PI_267_DATA 0x080F0E0D +#define DDRSS2_PI_268_DATA 0x000B0A09 +#define DDRSS2_PI_269_DATA 0x00030201 +#define DDRSS2_PI_270_DATA 0x01000000 +#define DDRSS2_PI_271_DATA 0x04020201 +#define DDRSS2_PI_272_DATA 0x00080804 +#define DDRSS2_PI_273_DATA 0x00000000 +#define DDRSS2_PI_274_DATA 0x00000000 +#define DDRSS2_PI_275_DATA 0x00F30084 +#define DDRSS2_PI_276_DATA 0x00160000 +#define DDRSS2_PI_277_DATA 0x35F33FF4 +#define DDRSS2_PI_278_DATA 0x00160F27 +#define DDRSS2_PI_279_DATA 0x35F33FF4 +#define DDRSS2_PI_280_DATA 0x00160F27 +#define DDRSS2_PI_281_DATA 0x00F30084 +#define DDRSS2_PI_282_DATA 0x00160000 +#define DDRSS2_PI_283_DATA 0x35F33FF4 +#define DDRSS2_PI_284_DATA 0x00160F27 +#define DDRSS2_PI_285_DATA 0x35F33FF4 +#define DDRSS2_PI_286_DATA 0x00160F27 +#define DDRSS2_PI_287_DATA 0x00F30084 +#define DDRSS2_PI_288_DATA 0x00160000 +#define DDRSS2_PI_289_DATA 0x35F33FF4 +#define DDRSS2_PI_290_DATA 0x00160F27 +#define DDRSS2_PI_291_DATA 0x35F33FF4 +#define DDRSS2_PI_292_DATA 0x00160F27 +#define DDRSS2_PI_293_DATA 0x00F30084 +#define DDRSS2_PI_294_DATA 0x00160000 +#define DDRSS2_PI_295_DATA 0x35F33FF4 +#define DDRSS2_PI_296_DATA 0x00160F27 +#define DDRSS2_PI_297_DATA 0x35F33FF4 +#define DDRSS2_PI_298_DATA 0x00160F27 +#define DDRSS2_PI_299_DATA 0x00000000 + +#define DDRSS2_PHY_00_DATA 0x000004F0 +#define DDRSS2_PHY_01_DATA 0x00000000 +#define DDRSS2_PHY_02_DATA 0x00030200 +#define DDRSS2_PHY_03_DATA 0x00000000 +#define DDRSS2_PHY_04_DATA 0x00000000 +#define DDRSS2_PHY_05_DATA 0x01030000 +#define DDRSS2_PHY_06_DATA 0x00010000 +#define DDRSS2_PHY_07_DATA 0x01030004 +#define DDRSS2_PHY_08_DATA 0x01000000 +#define DDRSS2_PHY_09_DATA 0x00000000 +#define DDRSS2_PHY_10_DATA 0x00000000 +#define DDRSS2_PHY_11_DATA 0x01000001 +#define DDRSS2_PHY_12_DATA 0x00000200 +#define DDRSS2_PHY_13_DATA 0x000800C0 +#define DDRSS2_PHY_14_DATA 0x060100CC +#define DDRSS2_PHY_15_DATA 0x00030066 +#define DDRSS2_PHY_16_DATA 0x00000000 +#define DDRSS2_PHY_17_DATA 0x00000301 +#define DDRSS2_PHY_18_DATA 0x0000AAAA +#define DDRSS2_PHY_19_DATA 0x00005555 +#define DDRSS2_PHY_20_DATA 0x0000B5B5 +#define DDRSS2_PHY_21_DATA 0x00004A4A +#define DDRSS2_PHY_22_DATA 0x00005656 +#define DDRSS2_PHY_23_DATA 0x0000A9A9 +#define DDRSS2_PHY_24_DATA 0x0000A9A9 +#define DDRSS2_PHY_25_DATA 0x0000B5B5 +#define DDRSS2_PHY_26_DATA 0x00000000 +#define DDRSS2_PHY_27_DATA 0x00000000 +#define DDRSS2_PHY_28_DATA 0x2A000000 +#define DDRSS2_PHY_29_DATA 0x00000808 +#define DDRSS2_PHY_30_DATA 0x0F000000 +#define DDRSS2_PHY_31_DATA 0x00000F08 +#define DDRSS2_PHY_32_DATA 0x10400000 +#define DDRSS2_PHY_33_DATA 0x0C002006 +#define DDRSS2_PHY_34_DATA 0x00000000 +#define DDRSS2_PHY_35_DATA 0x00000000 +#define DDRSS2_PHY_36_DATA 0x55555555 +#define DDRSS2_PHY_37_DATA 0xAAAAAAAA +#define DDRSS2_PHY_38_DATA 0x55555555 +#define DDRSS2_PHY_39_DATA 0xAAAAAAAA +#define DDRSS2_PHY_40_DATA 0x00005555 +#define DDRSS2_PHY_41_DATA 0x01000100 +#define DDRSS2_PHY_42_DATA 0x00800180 +#define DDRSS2_PHY_43_DATA 0x00000001 +#define DDRSS2_PHY_44_DATA 0x00000000 +#define DDRSS2_PHY_45_DATA 0x00000000 +#define DDRSS2_PHY_46_DATA 0x00000000 +#define DDRSS2_PHY_47_DATA 0x00000000 +#define DDRSS2_PHY_48_DATA 0x00000000 +#define DDRSS2_PHY_49_DATA 0x00000000 +#define DDRSS2_PHY_50_DATA 0x00000000 +#define DDRSS2_PHY_51_DATA 0x00000000 +#define DDRSS2_PHY_52_DATA 0x00000000 +#define DDRSS2_PHY_53_DATA 0x00000000 +#define DDRSS2_PHY_54_DATA 0x00000000 +#define DDRSS2_PHY_55_DATA 0x00000000 +#define DDRSS2_PHY_56_DATA 0x00000000 +#define DDRSS2_PHY_57_DATA 0x00000000 +#define DDRSS2_PHY_58_DATA 0x00000000 +#define DDRSS2_PHY_59_DATA 0x00000000 +#define DDRSS2_PHY_60_DATA 0x00000000 +#define DDRSS2_PHY_61_DATA 0x00000000 +#define DDRSS2_PHY_62_DATA 0x00000000 +#define DDRSS2_PHY_63_DATA 0x00000000 +#define DDRSS2_PHY_64_DATA 0x00000000 +#define DDRSS2_PHY_65_DATA 0x00000000 +#define DDRSS2_PHY_66_DATA 0x00000104 +#define DDRSS2_PHY_67_DATA 0x00000120 +#define DDRSS2_PHY_68_DATA 0x00000000 +#define DDRSS2_PHY_69_DATA 0x00000000 +#define DDRSS2_PHY_70_DATA 0x00000000 +#define DDRSS2_PHY_71_DATA 0x00000000 +#define DDRSS2_PHY_72_DATA 0x00000000 +#define DDRSS2_PHY_73_DATA 0x00000000 +#define DDRSS2_PHY_74_DATA 0x00000000 +#define DDRSS2_PHY_75_DATA 0x00000001 +#define DDRSS2_PHY_76_DATA 0x07FF0000 +#define DDRSS2_PHY_77_DATA 0x0080081F +#define DDRSS2_PHY_78_DATA 0x00081020 +#define DDRSS2_PHY_79_DATA 0x04010000 +#define DDRSS2_PHY_80_DATA 0x00000000 +#define DDRSS2_PHY_81_DATA 0x00000000 +#define DDRSS2_PHY_82_DATA 0x00000000 +#define DDRSS2_PHY_83_DATA 0x00000100 +#define DDRSS2_PHY_84_DATA 0x01CC0C01 +#define DDRSS2_PHY_85_DATA 0x1003CC0C +#define DDRSS2_PHY_86_DATA 0x20000140 +#define DDRSS2_PHY_87_DATA 0x07FF0200 +#define DDRSS2_PHY_88_DATA 0x0000DD01 +#define DDRSS2_PHY_89_DATA 0x10100303 +#define DDRSS2_PHY_90_DATA 0x10101010 +#define DDRSS2_PHY_91_DATA 0x10101010 +#define DDRSS2_PHY_92_DATA 0x00021010 +#define DDRSS2_PHY_93_DATA 0x00100010 +#define DDRSS2_PHY_94_DATA 0x00100010 +#define DDRSS2_PHY_95_DATA 0x00100010 +#define DDRSS2_PHY_96_DATA 0x00100010 +#define DDRSS2_PHY_97_DATA 0x00050010 +#define DDRSS2_PHY_98_DATA 0x51517041 +#define DDRSS2_PHY_99_DATA 0x31C06001 +#define DDRSS2_PHY_100_DATA 0x07AB01AB +#define DDRSS2_PHY_101_DATA 0x00C0C001 +#define DDRSS2_PHY_102_DATA 0x0E0D0101 +#define DDRSS2_PHY_103_DATA 0x10001000 +#define DDRSS2_PHY_104_DATA 0x0C083E42 +#define DDRSS2_PHY_105_DATA 0x0F0C3701 +#define DDRSS2_PHY_106_DATA 0x01000140 +#define DDRSS2_PHY_107_DATA 0x0C000420 +#define DDRSS2_PHY_108_DATA 0x00000198 +#define DDRSS2_PHY_109_DATA 0x0A0000D0 +#define DDRSS2_PHY_110_DATA 0x00030200 +#define DDRSS2_PHY_111_DATA 0x02800000 +#define DDRSS2_PHY_112_DATA 0x80800000 +#define DDRSS2_PHY_113_DATA 0x000E2010 +#define DDRSS2_PHY_114_DATA 0x76543210 +#define DDRSS2_PHY_115_DATA 0x00000008 +#define DDRSS2_PHY_116_DATA 0x02800280 +#define DDRSS2_PHY_117_DATA 0x02800280 +#define DDRSS2_PHY_118_DATA 0x02800280 +#define DDRSS2_PHY_119_DATA 0x02800280 +#define DDRSS2_PHY_120_DATA 0x00000280 +#define DDRSS2_PHY_121_DATA 0x0000A000 +#define DDRSS2_PHY_122_DATA 0x00A000A0 +#define DDRSS2_PHY_123_DATA 0x00A000A0 +#define DDRSS2_PHY_124_DATA 0x00A000A0 +#define DDRSS2_PHY_125_DATA 0x00A000A0 +#define DDRSS2_PHY_126_DATA 0x00A000A0 +#define DDRSS2_PHY_127_DATA 0x00A000A0 +#define DDRSS2_PHY_128_DATA 0x00A000A0 +#define DDRSS2_PHY_129_DATA 0x00A000A0 +#define DDRSS2_PHY_130_DATA 0x01C200A0 +#define DDRSS2_PHY_131_DATA 0x01A00005 +#define DDRSS2_PHY_132_DATA 0x00000000 +#define DDRSS2_PHY_133_DATA 0x00000000 +#define DDRSS2_PHY_134_DATA 0x00080200 +#define DDRSS2_PHY_135_DATA 0x00000000 +#define DDRSS2_PHY_136_DATA 0x20202000 +#define DDRSS2_PHY_137_DATA 0x20202020 +#define DDRSS2_PHY_138_DATA 0xF0F02020 +#define DDRSS2_PHY_139_DATA 0x00000000 +#define DDRSS2_PHY_140_DATA 0x00000000 +#define DDRSS2_PHY_141_DATA 0x00000000 +#define DDRSS2_PHY_142_DATA 0x00000000 +#define DDRSS2_PHY_143_DATA 0x00000000 +#define DDRSS2_PHY_144_DATA 0x00000000 +#define DDRSS2_PHY_145_DATA 0x00000000 +#define DDRSS2_PHY_146_DATA 0x00000000 +#define DDRSS2_PHY_147_DATA 0x00000000 +#define DDRSS2_PHY_148_DATA 0x00000000 +#define DDRSS2_PHY_149_DATA 0x00000000 +#define DDRSS2_PHY_150_DATA 0x00000000 +#define DDRSS2_PHY_151_DATA 0x00000000 +#define DDRSS2_PHY_152_DATA 0x00000000 +#define DDRSS2_PHY_153_DATA 0x00000000 +#define DDRSS2_PHY_154_DATA 0x00000000 +#define DDRSS2_PHY_155_DATA 0x00000000 +#define DDRSS2_PHY_156_DATA 0x00000000 +#define DDRSS2_PHY_157_DATA 0x00000000 +#define DDRSS2_PHY_158_DATA 0x00000000 +#define DDRSS2_PHY_159_DATA 0x00000000 +#define DDRSS2_PHY_160_DATA 0x00000000 +#define DDRSS2_PHY_161_DATA 0x00000000 +#define DDRSS2_PHY_162_DATA 0x00000000 +#define DDRSS2_PHY_163_DATA 0x00000000 +#define DDRSS2_PHY_164_DATA 0x00000000 +#define DDRSS2_PHY_165_DATA 0x00000000 +#define DDRSS2_PHY_166_DATA 0x00000000 +#define DDRSS2_PHY_167_DATA 0x00000000 +#define DDRSS2_PHY_168_DATA 0x00000000 +#define DDRSS2_PHY_169_DATA 0x00000000 +#define DDRSS2_PHY_170_DATA 0x00000000 +#define DDRSS2_PHY_171_DATA 0x00000000 +#define DDRSS2_PHY_172_DATA 0x00000000 +#define DDRSS2_PHY_173_DATA 0x00000000 +#define DDRSS2_PHY_174_DATA 0x00000000 +#define DDRSS2_PHY_175_DATA 0x00000000 +#define DDRSS2_PHY_176_DATA 0x00000000 +#define DDRSS2_PHY_177_DATA 0x00000000 +#define DDRSS2_PHY_178_DATA 0x00000000 +#define DDRSS2_PHY_179_DATA 0x00000000 +#define DDRSS2_PHY_180_DATA 0x00000000 +#define DDRSS2_PHY_181_DATA 0x00000000 +#define DDRSS2_PHY_182_DATA 0x00000000 +#define DDRSS2_PHY_183_DATA 0x00000000 +#define DDRSS2_PHY_184_DATA 0x00000000 +#define DDRSS2_PHY_185_DATA 0x00000000 +#define DDRSS2_PHY_186_DATA 0x00000000 +#define DDRSS2_PHY_187_DATA 0x00000000 +#define DDRSS2_PHY_188_DATA 0x00000000 +#define DDRSS2_PHY_189_DATA 0x00000000 +#define DDRSS2_PHY_190_DATA 0x00000000 +#define DDRSS2_PHY_191_DATA 0x00000000 +#define DDRSS2_PHY_192_DATA 0x00000000 +#define DDRSS2_PHY_193_DATA 0x00000000 +#define DDRSS2_PHY_194_DATA 0x00000000 +#define DDRSS2_PHY_195_DATA 0x00000000 +#define DDRSS2_PHY_196_DATA 0x00000000 +#define DDRSS2_PHY_197_DATA 0x00000000 +#define DDRSS2_PHY_198_DATA 0x00000000 +#define DDRSS2_PHY_199_DATA 0x00000000 +#define DDRSS2_PHY_200_DATA 0x00000000 +#define DDRSS2_PHY_201_DATA 0x00000000 +#define DDRSS2_PHY_202_DATA 0x00000000 +#define DDRSS2_PHY_203_DATA 0x00000000 +#define DDRSS2_PHY_204_DATA 0x00000000 +#define DDRSS2_PHY_205_DATA 0x00000000 +#define DDRSS2_PHY_206_DATA 0x00000000 +#define DDRSS2_PHY_207_DATA 0x00000000 +#define DDRSS2_PHY_208_DATA 0x00000000 +#define DDRSS2_PHY_209_DATA 0x00000000 +#define DDRSS2_PHY_210_DATA 0x00000000 +#define DDRSS2_PHY_211_DATA 0x00000000 +#define DDRSS2_PHY_212_DATA 0x00000000 +#define DDRSS2_PHY_213_DATA 0x00000000 +#define DDRSS2_PHY_214_DATA 0x00000000 +#define DDRSS2_PHY_215_DATA 0x00000000 +#define DDRSS2_PHY_216_DATA 0x00000000 +#define DDRSS2_PHY_217_DATA 0x00000000 +#define DDRSS2_PHY_218_DATA 0x00000000 +#define DDRSS2_PHY_219_DATA 0x00000000 +#define DDRSS2_PHY_220_DATA 0x00000000 +#define DDRSS2_PHY_221_DATA 0x00000000 +#define DDRSS2_PHY_222_DATA 0x00000000 +#define DDRSS2_PHY_223_DATA 0x00000000 +#define DDRSS2_PHY_224_DATA 0x00000000 +#define DDRSS2_PHY_225_DATA 0x00000000 +#define DDRSS2_PHY_226_DATA 0x00000000 +#define DDRSS2_PHY_227_DATA 0x00000000 +#define DDRSS2_PHY_228_DATA 0x00000000 +#define DDRSS2_PHY_229_DATA 0x00000000 +#define DDRSS2_PHY_230_DATA 0x00000000 +#define DDRSS2_PHY_231_DATA 0x00000000 +#define DDRSS2_PHY_232_DATA 0x00000000 +#define DDRSS2_PHY_233_DATA 0x00000000 +#define DDRSS2_PHY_234_DATA 0x00000000 +#define DDRSS2_PHY_235_DATA 0x00000000 +#define DDRSS2_PHY_236_DATA 0x00000000 +#define DDRSS2_PHY_237_DATA 0x00000000 +#define DDRSS2_PHY_238_DATA 0x00000000 +#define DDRSS2_PHY_239_DATA 0x00000000 +#define DDRSS2_PHY_240_DATA 0x00000000 +#define DDRSS2_PHY_241_DATA 0x00000000 +#define DDRSS2_PHY_242_DATA 0x00000000 +#define DDRSS2_PHY_243_DATA 0x00000000 +#define DDRSS2_PHY_244_DATA 0x00000000 +#define DDRSS2_PHY_245_DATA 0x00000000 +#define DDRSS2_PHY_246_DATA 0x00000000 +#define DDRSS2_PHY_247_DATA 0x00000000 +#define DDRSS2_PHY_248_DATA 0x00000000 +#define DDRSS2_PHY_249_DATA 0x00000000 +#define DDRSS2_PHY_250_DATA 0x00000000 +#define DDRSS2_PHY_251_DATA 0x00000000 +#define DDRSS2_PHY_252_DATA 0x00000000 +#define DDRSS2_PHY_253_DATA 0x00000000 +#define DDRSS2_PHY_254_DATA 0x00000000 +#define DDRSS2_PHY_255_DATA 0x00000000 +#define DDRSS2_PHY_256_DATA 0x000004F0 +#define DDRSS2_PHY_257_DATA 0x00000000 +#define DDRSS2_PHY_258_DATA 0x00030200 +#define DDRSS2_PHY_259_DATA 0x00000000 +#define DDRSS2_PHY_260_DATA 0x00000000 +#define DDRSS2_PHY_261_DATA 0x01030000 +#define DDRSS2_PHY_262_DATA 0x00010000 +#define DDRSS2_PHY_263_DATA 0x01030004 +#define DDRSS2_PHY_264_DATA 0x01000000 +#define DDRSS2_PHY_265_DATA 0x00000000 +#define DDRSS2_PHY_266_DATA 0x00000000 +#define DDRSS2_PHY_267_DATA 0x01000001 +#define DDRSS2_PHY_268_DATA 0x00000200 +#define DDRSS2_PHY_269_DATA 0x000800C0 +#define DDRSS2_PHY_270_DATA 0x060100CC +#define DDRSS2_PHY_271_DATA 0x00030066 +#define DDRSS2_PHY_272_DATA 0x00000000 +#define DDRSS2_PHY_273_DATA 0x00000301 +#define DDRSS2_PHY_274_DATA 0x0000AAAA +#define DDRSS2_PHY_275_DATA 0x00005555 +#define DDRSS2_PHY_276_DATA 0x0000B5B5 +#define DDRSS2_PHY_277_DATA 0x00004A4A +#define DDRSS2_PHY_278_DATA 0x00005656 +#define DDRSS2_PHY_279_DATA 0x0000A9A9 +#define DDRSS2_PHY_280_DATA 0x0000A9A9 +#define DDRSS2_PHY_281_DATA 0x0000B5B5 +#define DDRSS2_PHY_282_DATA 0x00000000 +#define DDRSS2_PHY_283_DATA 0x00000000 +#define DDRSS2_PHY_284_DATA 0x2A000000 +#define DDRSS2_PHY_285_DATA 0x00000808 +#define DDRSS2_PHY_286_DATA 0x0F000000 +#define DDRSS2_PHY_287_DATA 0x00000F08 +#define DDRSS2_PHY_288_DATA 0x10400000 +#define DDRSS2_PHY_289_DATA 0x0C002006 +#define DDRSS2_PHY_290_DATA 0x00000000 +#define DDRSS2_PHY_291_DATA 0x00000000 +#define DDRSS2_PHY_292_DATA 0x55555555 +#define DDRSS2_PHY_293_DATA 0xAAAAAAAA +#define DDRSS2_PHY_294_DATA 0x55555555 +#define DDRSS2_PHY_295_DATA 0xAAAAAAAA +#define DDRSS2_PHY_296_DATA 0x00005555 +#define DDRSS2_PHY_297_DATA 0x01000100 +#define DDRSS2_PHY_298_DATA 0x00800180 +#define DDRSS2_PHY_299_DATA 0x00000000 +#define DDRSS2_PHY_300_DATA 0x00000000 +#define DDRSS2_PHY_301_DATA 0x00000000 +#define DDRSS2_PHY_302_DATA 0x00000000 +#define DDRSS2_PHY_303_DATA 0x00000000 +#define DDRSS2_PHY_304_DATA 0x00000000 +#define DDRSS2_PHY_305_DATA 0x00000000 +#define DDRSS2_PHY_306_DATA 0x00000000 +#define DDRSS2_PHY_307_DATA 0x00000000 +#define DDRSS2_PHY_308_DATA 0x00000000 +#define DDRSS2_PHY_309_DATA 0x00000000 +#define DDRSS2_PHY_310_DATA 0x00000000 +#define DDRSS2_PHY_311_DATA 0x00000000 +#define DDRSS2_PHY_312_DATA 0x00000000 +#define DDRSS2_PHY_313_DATA 0x00000000 +#define DDRSS2_PHY_314_DATA 0x00000000 +#define DDRSS2_PHY_315_DATA 0x00000000 +#define DDRSS2_PHY_316_DATA 0x00000000 +#define DDRSS2_PHY_317_DATA 0x00000000 +#define DDRSS2_PHY_318_DATA 0x00000000 +#define DDRSS2_PHY_319_DATA 0x00000000 +#define DDRSS2_PHY_320_DATA 0x00000000 +#define DDRSS2_PHY_321_DATA 0x00000000 +#define DDRSS2_PHY_322_DATA 0x00000104 +#define DDRSS2_PHY_323_DATA 0x00000120 +#define DDRSS2_PHY_324_DATA 0x00000000 +#define DDRSS2_PHY_325_DATA 0x00000000 +#define DDRSS2_PHY_326_DATA 0x00000000 +#define DDRSS2_PHY_327_DATA 0x00000000 +#define DDRSS2_PHY_328_DATA 0x00000000 +#define DDRSS2_PHY_329_DATA 0x00000000 +#define DDRSS2_PHY_330_DATA 0x00000000 +#define DDRSS2_PHY_331_DATA 0x00000001 +#define DDRSS2_PHY_332_DATA 0x07FF0000 +#define DDRSS2_PHY_333_DATA 0x0080081F +#define DDRSS2_PHY_334_DATA 0x00081020 +#define DDRSS2_PHY_335_DATA 0x04010000 +#define DDRSS2_PHY_336_DATA 0x00000000 +#define DDRSS2_PHY_337_DATA 0x00000000 +#define DDRSS2_PHY_338_DATA 0x00000000 +#define DDRSS2_PHY_339_DATA 0x00000100 +#define DDRSS2_PHY_340_DATA 0x01CC0C01 +#define DDRSS2_PHY_341_DATA 0x1003CC0C +#define DDRSS2_PHY_342_DATA 0x20000140 +#define DDRSS2_PHY_343_DATA 0x07FF0200 +#define DDRSS2_PHY_344_DATA 0x0000DD01 +#define DDRSS2_PHY_345_DATA 0x10100303 +#define DDRSS2_PHY_346_DATA 0x10101010 +#define DDRSS2_PHY_347_DATA 0x10101010 +#define DDRSS2_PHY_348_DATA 0x00021010 +#define DDRSS2_PHY_349_DATA 0x00100010 +#define DDRSS2_PHY_350_DATA 0x00100010 +#define DDRSS2_PHY_351_DATA 0x00100010 +#define DDRSS2_PHY_352_DATA 0x00100010 +#define DDRSS2_PHY_353_DATA 0x00050010 +#define DDRSS2_PHY_354_DATA 0x51517041 +#define DDRSS2_PHY_355_DATA 0x31C06001 +#define DDRSS2_PHY_356_DATA 0x07AB01AB +#define DDRSS2_PHY_357_DATA 0x00C0C001 +#define DDRSS2_PHY_358_DATA 0x0E0D0101 +#define DDRSS2_PHY_359_DATA 0x10001000 +#define DDRSS2_PHY_360_DATA 0x0C083E42 +#define DDRSS2_PHY_361_DATA 0x0F0C3701 +#define DDRSS2_PHY_362_DATA 0x01000140 +#define DDRSS2_PHY_363_DATA 0x0C000420 +#define DDRSS2_PHY_364_DATA 0x00000198 +#define DDRSS2_PHY_365_DATA 0x0A0000D0 +#define DDRSS2_PHY_366_DATA 0x00030200 +#define DDRSS2_PHY_367_DATA 0x02800000 +#define DDRSS2_PHY_368_DATA 0x80800000 +#define DDRSS2_PHY_369_DATA 0x000E2010 +#define DDRSS2_PHY_370_DATA 0x76543210 +#define DDRSS2_PHY_371_DATA 0x00000008 +#define DDRSS2_PHY_372_DATA 0x02800280 +#define DDRSS2_PHY_373_DATA 0x02800280 +#define DDRSS2_PHY_374_DATA 0x02800280 +#define DDRSS2_PHY_375_DATA 0x02800280 +#define DDRSS2_PHY_376_DATA 0x00000280 +#define DDRSS2_PHY_377_DATA 0x0000A000 +#define DDRSS2_PHY_378_DATA 0x00A000A0 +#define DDRSS2_PHY_379_DATA 0x00A000A0 +#define DDRSS2_PHY_380_DATA 0x00A000A0 +#define DDRSS2_PHY_381_DATA 0x00A000A0 +#define DDRSS2_PHY_382_DATA 0x00A000A0 +#define DDRSS2_PHY_383_DATA 0x00A000A0 +#define DDRSS2_PHY_384_DATA 0x00A000A0 +#define DDRSS2_PHY_385_DATA 0x00A000A0 +#define DDRSS2_PHY_386_DATA 0x01C200A0 +#define DDRSS2_PHY_387_DATA 0x01A00005 +#define DDRSS2_PHY_388_DATA 0x00000000 +#define DDRSS2_PHY_389_DATA 0x00000000 +#define DDRSS2_PHY_390_DATA 0x00080200 +#define DDRSS2_PHY_391_DATA 0x00000000 +#define DDRSS2_PHY_392_DATA 0x20202000 +#define DDRSS2_PHY_393_DATA 0x20202020 +#define DDRSS2_PHY_394_DATA 0xF0F02020 +#define DDRSS2_PHY_395_DATA 0x00000000 +#define DDRSS2_PHY_396_DATA 0x00000000 +#define DDRSS2_PHY_397_DATA 0x00000000 +#define DDRSS2_PHY_398_DATA 0x00000000 +#define DDRSS2_PHY_399_DATA 0x00000000 +#define DDRSS2_PHY_400_DATA 0x00000000 +#define DDRSS2_PHY_401_DATA 0x00000000 +#define DDRSS2_PHY_402_DATA 0x00000000 +#define DDRSS2_PHY_403_DATA 0x00000000 +#define DDRSS2_PHY_404_DATA 0x00000000 +#define DDRSS2_PHY_405_DATA 0x00000000 +#define DDRSS2_PHY_406_DATA 0x00000000 +#define DDRSS2_PHY_407_DATA 0x00000000 +#define DDRSS2_PHY_408_DATA 0x00000000 +#define DDRSS2_PHY_409_DATA 0x00000000 +#define DDRSS2_PHY_410_DATA 0x00000000 +#define DDRSS2_PHY_411_DATA 0x00000000 +#define DDRSS2_PHY_412_DATA 0x00000000 +#define DDRSS2_PHY_413_DATA 0x00000000 +#define DDRSS2_PHY_414_DATA 0x00000000 +#define DDRSS2_PHY_415_DATA 0x00000000 +#define DDRSS2_PHY_416_DATA 0x00000000 +#define DDRSS2_PHY_417_DATA 0x00000000 +#define DDRSS2_PHY_418_DATA 0x00000000 +#define DDRSS2_PHY_419_DATA 0x00000000 +#define DDRSS2_PHY_420_DATA 0x00000000 +#define DDRSS2_PHY_421_DATA 0x00000000 +#define DDRSS2_PHY_422_DATA 0x00000000 +#define DDRSS2_PHY_423_DATA 0x00000000 +#define DDRSS2_PHY_424_DATA 0x00000000 +#define DDRSS2_PHY_425_DATA 0x00000000 +#define DDRSS2_PHY_426_DATA 0x00000000 +#define DDRSS2_PHY_427_DATA 0x00000000 +#define DDRSS2_PHY_428_DATA 0x00000000 +#define DDRSS2_PHY_429_DATA 0x00000000 +#define DDRSS2_PHY_430_DATA 0x00000000 +#define DDRSS2_PHY_431_DATA 0x00000000 +#define DDRSS2_PHY_432_DATA 0x00000000 +#define DDRSS2_PHY_433_DATA 0x00000000 +#define DDRSS2_PHY_434_DATA 0x00000000 +#define DDRSS2_PHY_435_DATA 0x00000000 +#define DDRSS2_PHY_436_DATA 0x00000000 +#define DDRSS2_PHY_437_DATA 0x00000000 +#define DDRSS2_PHY_438_DATA 0x00000000 +#define DDRSS2_PHY_439_DATA 0x00000000 +#define DDRSS2_PHY_440_DATA 0x00000000 +#define DDRSS2_PHY_441_DATA 0x00000000 +#define DDRSS2_PHY_442_DATA 0x00000000 +#define DDRSS2_PHY_443_DATA 0x00000000 +#define DDRSS2_PHY_444_DATA 0x00000000 +#define DDRSS2_PHY_445_DATA 0x00000000 +#define DDRSS2_PHY_446_DATA 0x00000000 +#define DDRSS2_PHY_447_DATA 0x00000000 +#define DDRSS2_PHY_448_DATA 0x00000000 +#define DDRSS2_PHY_449_DATA 0x00000000 +#define DDRSS2_PHY_450_DATA 0x00000000 +#define DDRSS2_PHY_451_DATA 0x00000000 +#define DDRSS2_PHY_452_DATA 0x00000000 +#define DDRSS2_PHY_453_DATA 0x00000000 +#define DDRSS2_PHY_454_DATA 0x00000000 +#define DDRSS2_PHY_455_DATA 0x00000000 +#define DDRSS2_PHY_456_DATA 0x00000000 +#define DDRSS2_PHY_457_DATA 0x00000000 +#define DDRSS2_PHY_458_DATA 0x00000000 +#define DDRSS2_PHY_459_DATA 0x00000000 +#define DDRSS2_PHY_460_DATA 0x00000000 +#define DDRSS2_PHY_461_DATA 0x00000000 +#define DDRSS2_PHY_462_DATA 0x00000000 +#define DDRSS2_PHY_463_DATA 0x00000000 +#define DDRSS2_PHY_464_DATA 0x00000000 +#define DDRSS2_PHY_465_DATA 0x00000000 +#define DDRSS2_PHY_466_DATA 0x00000000 +#define DDRSS2_PHY_467_DATA 0x00000000 +#define DDRSS2_PHY_468_DATA 0x00000000 +#define DDRSS2_PHY_469_DATA 0x00000000 +#define DDRSS2_PHY_470_DATA 0x00000000 +#define DDRSS2_PHY_471_DATA 0x00000000 +#define DDRSS2_PHY_472_DATA 0x00000000 +#define DDRSS2_PHY_473_DATA 0x00000000 +#define DDRSS2_PHY_474_DATA 0x00000000 +#define DDRSS2_PHY_475_DATA 0x00000000 +#define DDRSS2_PHY_476_DATA 0x00000000 +#define DDRSS2_PHY_477_DATA 0x00000000 +#define DDRSS2_PHY_478_DATA 0x00000000 +#define DDRSS2_PHY_479_DATA 0x00000000 +#define DDRSS2_PHY_480_DATA 0x00000000 +#define DDRSS2_PHY_481_DATA 0x00000000 +#define DDRSS2_PHY_482_DATA 0x00000000 +#define DDRSS2_PHY_483_DATA 0x00000000 +#define DDRSS2_PHY_484_DATA 0x00000000 +#define DDRSS2_PHY_485_DATA 0x00000000 +#define DDRSS2_PHY_486_DATA 0x00000000 +#define DDRSS2_PHY_487_DATA 0x00000000 +#define DDRSS2_PHY_488_DATA 0x00000000 +#define DDRSS2_PHY_489_DATA 0x00000000 +#define DDRSS2_PHY_490_DATA 0x00000000 +#define DDRSS2_PHY_491_DATA 0x00000000 +#define DDRSS2_PHY_492_DATA 0x00000000 +#define DDRSS2_PHY_493_DATA 0x00000000 +#define DDRSS2_PHY_494_DATA 0x00000000 +#define DDRSS2_PHY_495_DATA 0x00000000 +#define DDRSS2_PHY_496_DATA 0x00000000 +#define DDRSS2_PHY_497_DATA 0x00000000 +#define DDRSS2_PHY_498_DATA 0x00000000 +#define DDRSS2_PHY_499_DATA 0x00000000 +#define DDRSS2_PHY_500_DATA 0x00000000 +#define DDRSS2_PHY_501_DATA 0x00000000 +#define DDRSS2_PHY_502_DATA 0x00000000 +#define DDRSS2_PHY_503_DATA 0x00000000 +#define DDRSS2_PHY_504_DATA 0x00000000 +#define DDRSS2_PHY_505_DATA 0x00000000 +#define DDRSS2_PHY_506_DATA 0x00000000 +#define DDRSS2_PHY_507_DATA 0x00000000 +#define DDRSS2_PHY_508_DATA 0x00000000 +#define DDRSS2_PHY_509_DATA 0x00000000 +#define DDRSS2_PHY_510_DATA 0x00000000 +#define DDRSS2_PHY_511_DATA 0x00000000 +#define DDRSS2_PHY_512_DATA 0x000004F0 +#define DDRSS2_PHY_513_DATA 0x00000000 +#define DDRSS2_PHY_514_DATA 0x00030200 +#define DDRSS2_PHY_515_DATA 0x00000000 +#define DDRSS2_PHY_516_DATA 0x00000000 +#define DDRSS2_PHY_517_DATA 0x01030000 +#define DDRSS2_PHY_518_DATA 0x00010000 +#define DDRSS2_PHY_519_DATA 0x01030004 +#define DDRSS2_PHY_520_DATA 0x01000000 +#define DDRSS2_PHY_521_DATA 0x00000000 +#define DDRSS2_PHY_522_DATA 0x00000000 +#define DDRSS2_PHY_523_DATA 0x01000001 +#define DDRSS2_PHY_524_DATA 0x00000200 +#define DDRSS2_PHY_525_DATA 0x000800C0 +#define DDRSS2_PHY_526_DATA 0x060100CC +#define DDRSS2_PHY_527_DATA 0x00030066 +#define DDRSS2_PHY_528_DATA 0x00000000 +#define DDRSS2_PHY_529_DATA 0x00000301 +#define DDRSS2_PHY_530_DATA 0x0000AAAA +#define DDRSS2_PHY_531_DATA 0x00005555 +#define DDRSS2_PHY_532_DATA 0x0000B5B5 +#define DDRSS2_PHY_533_DATA 0x00004A4A +#define DDRSS2_PHY_534_DATA 0x00005656 +#define DDRSS2_PHY_535_DATA 0x0000A9A9 +#define DDRSS2_PHY_536_DATA 0x0000A9A9 +#define DDRSS2_PHY_537_DATA 0x0000B5B5 +#define DDRSS2_PHY_538_DATA 0x00000000 +#define DDRSS2_PHY_539_DATA 0x00000000 +#define DDRSS2_PHY_540_DATA 0x2A000000 +#define DDRSS2_PHY_541_DATA 0x00000808 +#define DDRSS2_PHY_542_DATA 0x0F000000 +#define DDRSS2_PHY_543_DATA 0x00000F08 +#define DDRSS2_PHY_544_DATA 0x10400000 +#define DDRSS2_PHY_545_DATA 0x0C002006 +#define DDRSS2_PHY_546_DATA 0x00000000 +#define DDRSS2_PHY_547_DATA 0x00000000 +#define DDRSS2_PHY_548_DATA 0x55555555 +#define DDRSS2_PHY_549_DATA 0xAAAAAAAA +#define DDRSS2_PHY_550_DATA 0x55555555 +#define DDRSS2_PHY_551_DATA 0xAAAAAAAA +#define DDRSS2_PHY_552_DATA 0x00005555 +#define DDRSS2_PHY_553_DATA 0x01000100 +#define DDRSS2_PHY_554_DATA 0x00800180 +#define DDRSS2_PHY_555_DATA 0x00000001 +#define DDRSS2_PHY_556_DATA 0x00000000 +#define DDRSS2_PHY_557_DATA 0x00000000 +#define DDRSS2_PHY_558_DATA 0x00000000 +#define DDRSS2_PHY_559_DATA 0x00000000 +#define DDRSS2_PHY_560_DATA 0x00000000 +#define DDRSS2_PHY_561_DATA 0x00000000 +#define DDRSS2_PHY_562_DATA 0x00000000 +#define DDRSS2_PHY_563_DATA 0x00000000 +#define DDRSS2_PHY_564_DATA 0x00000000 +#define DDRSS2_PHY_565_DATA 0x00000000 +#define DDRSS2_PHY_566_DATA 0x00000000 +#define DDRSS2_PHY_567_DATA 0x00000000 +#define DDRSS2_PHY_568_DATA 0x00000000 +#define DDRSS2_PHY_569_DATA 0x00000000 +#define DDRSS2_PHY_570_DATA 0x00000000 +#define DDRSS2_PHY_571_DATA 0x00000000 +#define DDRSS2_PHY_572_DATA 0x00000000 +#define DDRSS2_PHY_573_DATA 0x00000000 +#define DDRSS2_PHY_574_DATA 0x00000000 +#define DDRSS2_PHY_575_DATA 0x00000000 +#define DDRSS2_PHY_576_DATA 0x00000000 +#define DDRSS2_PHY_577_DATA 0x00000000 +#define DDRSS2_PHY_578_DATA 0x00000104 +#define DDRSS2_PHY_579_DATA 0x00000120 +#define DDRSS2_PHY_580_DATA 0x00000000 +#define DDRSS2_PHY_581_DATA 0x00000000 +#define DDRSS2_PHY_582_DATA 0x00000000 +#define DDRSS2_PHY_583_DATA 0x00000000 +#define DDRSS2_PHY_584_DATA 0x00000000 +#define DDRSS2_PHY_585_DATA 0x00000000 +#define DDRSS2_PHY_586_DATA 0x00000000 +#define DDRSS2_PHY_587_DATA 0x00000001 +#define DDRSS2_PHY_588_DATA 0x07FF0000 +#define DDRSS2_PHY_589_DATA 0x0080081F +#define DDRSS2_PHY_590_DATA 0x00081020 +#define DDRSS2_PHY_591_DATA 0x04010000 +#define DDRSS2_PHY_592_DATA 0x00000000 +#define DDRSS2_PHY_593_DATA 0x00000000 +#define DDRSS2_PHY_594_DATA 0x00000000 +#define DDRSS2_PHY_595_DATA 0x00000100 +#define DDRSS2_PHY_596_DATA 0x01CC0C01 +#define DDRSS2_PHY_597_DATA 0x1003CC0C +#define DDRSS2_PHY_598_DATA 0x20000140 +#define DDRSS2_PHY_599_DATA 0x07FF0200 +#define DDRSS2_PHY_600_DATA 0x0000DD01 +#define DDRSS2_PHY_601_DATA 0x10100303 +#define DDRSS2_PHY_602_DATA 0x10101010 +#define DDRSS2_PHY_603_DATA 0x10101010 +#define DDRSS2_PHY_604_DATA 0x00021010 +#define DDRSS2_PHY_605_DATA 0x00100010 +#define DDRSS2_PHY_606_DATA 0x00100010 +#define DDRSS2_PHY_607_DATA 0x00100010 +#define DDRSS2_PHY_608_DATA 0x00100010 +#define DDRSS2_PHY_609_DATA 0x00050010 +#define DDRSS2_PHY_610_DATA 0x51517041 +#define DDRSS2_PHY_611_DATA 0x31C06001 +#define DDRSS2_PHY_612_DATA 0x07AB01AB +#define DDRSS2_PHY_613_DATA 0x00C0C001 +#define DDRSS2_PHY_614_DATA 0x0E0D0101 +#define DDRSS2_PHY_615_DATA 0x10001000 +#define DDRSS2_PHY_616_DATA 0x0C083E42 +#define DDRSS2_PHY_617_DATA 0x0F0C3701 +#define DDRSS2_PHY_618_DATA 0x01000140 +#define DDRSS2_PHY_619_DATA 0x0C000420 +#define DDRSS2_PHY_620_DATA 0x00000198 +#define DDRSS2_PHY_621_DATA 0x0A0000D0 +#define DDRSS2_PHY_622_DATA 0x00030200 +#define DDRSS2_PHY_623_DATA 0x02800000 +#define DDRSS2_PHY_624_DATA 0x80800000 +#define DDRSS2_PHY_625_DATA 0x000E2010 +#define DDRSS2_PHY_626_DATA 0x76543210 +#define DDRSS2_PHY_627_DATA 0x00000008 +#define DDRSS2_PHY_628_DATA 0x02800280 +#define DDRSS2_PHY_629_DATA 0x02800280 +#define DDRSS2_PHY_630_DATA 0x02800280 +#define DDRSS2_PHY_631_DATA 0x02800280 +#define DDRSS2_PHY_632_DATA 0x00000280 +#define DDRSS2_PHY_633_DATA 0x0000A000 +#define DDRSS2_PHY_634_DATA 0x00A000A0 +#define DDRSS2_PHY_635_DATA 0x00A000A0 +#define DDRSS2_PHY_636_DATA 0x00A000A0 +#define DDRSS2_PHY_637_DATA 0x00A000A0 +#define DDRSS2_PHY_638_DATA 0x00A000A0 +#define DDRSS2_PHY_639_DATA 0x00A000A0 +#define DDRSS2_PHY_640_DATA 0x00A000A0 +#define DDRSS2_PHY_641_DATA 0x00A000A0 +#define DDRSS2_PHY_642_DATA 0x01C200A0 +#define DDRSS2_PHY_643_DATA 0x01A00005 +#define DDRSS2_PHY_644_DATA 0x00000000 +#define DDRSS2_PHY_645_DATA 0x00000000 +#define DDRSS2_PHY_646_DATA 0x00080200 +#define DDRSS2_PHY_647_DATA 0x00000000 +#define DDRSS2_PHY_648_DATA 0x20202000 +#define DDRSS2_PHY_649_DATA 0x20202020 +#define DDRSS2_PHY_650_DATA 0xF0F02020 +#define DDRSS2_PHY_651_DATA 0x00000000 +#define DDRSS2_PHY_652_DATA 0x00000000 +#define DDRSS2_PHY_653_DATA 0x00000000 +#define DDRSS2_PHY_654_DATA 0x00000000 +#define DDRSS2_PHY_655_DATA 0x00000000 +#define DDRSS2_PHY_656_DATA 0x00000000 +#define DDRSS2_PHY_657_DATA 0x00000000 +#define DDRSS2_PHY_658_DATA 0x00000000 +#define DDRSS2_PHY_659_DATA 0x00000000 +#define DDRSS2_PHY_660_DATA 0x00000000 +#define DDRSS2_PHY_661_DATA 0x00000000 +#define DDRSS2_PHY_662_DATA 0x00000000 +#define DDRSS2_PHY_663_DATA 0x00000000 +#define DDRSS2_PHY_664_DATA 0x00000000 +#define DDRSS2_PHY_665_DATA 0x00000000 +#define DDRSS2_PHY_666_DATA 0x00000000 +#define DDRSS2_PHY_667_DATA 0x00000000 +#define DDRSS2_PHY_668_DATA 0x00000000 +#define DDRSS2_PHY_669_DATA 0x00000000 +#define DDRSS2_PHY_670_DATA 0x00000000 +#define DDRSS2_PHY_671_DATA 0x00000000 +#define DDRSS2_PHY_672_DATA 0x00000000 +#define DDRSS2_PHY_673_DATA 0x00000000 +#define DDRSS2_PHY_674_DATA 0x00000000 +#define DDRSS2_PHY_675_DATA 0x00000000 +#define DDRSS2_PHY_676_DATA 0x00000000 +#define DDRSS2_PHY_677_DATA 0x00000000 +#define DDRSS2_PHY_678_DATA 0x00000000 +#define DDRSS2_PHY_679_DATA 0x00000000 +#define DDRSS2_PHY_680_DATA 0x00000000 +#define DDRSS2_PHY_681_DATA 0x00000000 +#define DDRSS2_PHY_682_DATA 0x00000000 +#define DDRSS2_PHY_683_DATA 0x00000000 +#define DDRSS2_PHY_684_DATA 0x00000000 +#define DDRSS2_PHY_685_DATA 0x00000000 +#define DDRSS2_PHY_686_DATA 0x00000000 +#define DDRSS2_PHY_687_DATA 0x00000000 +#define DDRSS2_PHY_688_DATA 0x00000000 +#define DDRSS2_PHY_689_DATA 0x00000000 +#define DDRSS2_PHY_690_DATA 0x00000000 +#define DDRSS2_PHY_691_DATA 0x00000000 +#define DDRSS2_PHY_692_DATA 0x00000000 +#define DDRSS2_PHY_693_DATA 0x00000000 +#define DDRSS2_PHY_694_DATA 0x00000000 +#define DDRSS2_PHY_695_DATA 0x00000000 +#define DDRSS2_PHY_696_DATA 0x00000000 +#define DDRSS2_PHY_697_DATA 0x00000000 +#define DDRSS2_PHY_698_DATA 0x00000000 +#define DDRSS2_PHY_699_DATA 0x00000000 +#define DDRSS2_PHY_700_DATA 0x00000000 +#define DDRSS2_PHY_701_DATA 0x00000000 +#define DDRSS2_PHY_702_DATA 0x00000000 +#define DDRSS2_PHY_703_DATA 0x00000000 +#define DDRSS2_PHY_704_DATA 0x00000000 +#define DDRSS2_PHY_705_DATA 0x00000000 +#define DDRSS2_PHY_706_DATA 0x00000000 +#define DDRSS2_PHY_707_DATA 0x00000000 +#define DDRSS2_PHY_708_DATA 0x00000000 +#define DDRSS2_PHY_709_DATA 0x00000000 +#define DDRSS2_PHY_710_DATA 0x00000000 +#define DDRSS2_PHY_711_DATA 0x00000000 +#define DDRSS2_PHY_712_DATA 0x00000000 +#define DDRSS2_PHY_713_DATA 0x00000000 +#define DDRSS2_PHY_714_DATA 0x00000000 +#define DDRSS2_PHY_715_DATA 0x00000000 +#define DDRSS2_PHY_716_DATA 0x00000000 +#define DDRSS2_PHY_717_DATA 0x00000000 +#define DDRSS2_PHY_718_DATA 0x00000000 +#define DDRSS2_PHY_719_DATA 0x00000000 +#define DDRSS2_PHY_720_DATA 0x00000000 +#define DDRSS2_PHY_721_DATA 0x00000000 +#define DDRSS2_PHY_722_DATA 0x00000000 +#define DDRSS2_PHY_723_DATA 0x00000000 +#define DDRSS2_PHY_724_DATA 0x00000000 +#define DDRSS2_PHY_725_DATA 0x00000000 +#define DDRSS2_PHY_726_DATA 0x00000000 +#define DDRSS2_PHY_727_DATA 0x00000000 +#define DDRSS2_PHY_728_DATA 0x00000000 +#define DDRSS2_PHY_729_DATA 0x00000000 +#define DDRSS2_PHY_730_DATA 0x00000000 +#define DDRSS2_PHY_731_DATA 0x00000000 +#define DDRSS2_PHY_732_DATA 0x00000000 +#define DDRSS2_PHY_733_DATA 0x00000000 +#define DDRSS2_PHY_734_DATA 0x00000000 +#define DDRSS2_PHY_735_DATA 0x00000000 +#define DDRSS2_PHY_736_DATA 0x00000000 +#define DDRSS2_PHY_737_DATA 0x00000000 +#define DDRSS2_PHY_738_DATA 0x00000000 +#define DDRSS2_PHY_739_DATA 0x00000000 +#define DDRSS2_PHY_740_DATA 0x00000000 +#define DDRSS2_PHY_741_DATA 0x00000000 +#define DDRSS2_PHY_742_DATA 0x00000000 +#define DDRSS2_PHY_743_DATA 0x00000000 +#define DDRSS2_PHY_744_DATA 0x00000000 +#define DDRSS2_PHY_745_DATA 0x00000000 +#define DDRSS2_PHY_746_DATA 0x00000000 +#define DDRSS2_PHY_747_DATA 0x00000000 +#define DDRSS2_PHY_748_DATA 0x00000000 +#define DDRSS2_PHY_749_DATA 0x00000000 +#define DDRSS2_PHY_750_DATA 0x00000000 +#define DDRSS2_PHY_751_DATA 0x00000000 +#define DDRSS2_PHY_752_DATA 0x00000000 +#define DDRSS2_PHY_753_DATA 0x00000000 +#define DDRSS2_PHY_754_DATA 0x00000000 +#define DDRSS2_PHY_755_DATA 0x00000000 +#define DDRSS2_PHY_756_DATA 0x00000000 +#define DDRSS2_PHY_757_DATA 0x00000000 +#define DDRSS2_PHY_758_DATA 0x00000000 +#define DDRSS2_PHY_759_DATA 0x00000000 +#define DDRSS2_PHY_760_DATA 0x00000000 +#define DDRSS2_PHY_761_DATA 0x00000000 +#define DDRSS2_PHY_762_DATA 0x00000000 +#define DDRSS2_PHY_763_DATA 0x00000000 +#define DDRSS2_PHY_764_DATA 0x00000000 +#define DDRSS2_PHY_765_DATA 0x00000000 +#define DDRSS2_PHY_766_DATA 0x00000000 +#define DDRSS2_PHY_767_DATA 0x00000000 +#define DDRSS2_PHY_768_DATA 0x000004F0 +#define DDRSS2_PHY_769_DATA 0x00000000 +#define DDRSS2_PHY_770_DATA 0x00030200 +#define DDRSS2_PHY_771_DATA 0x00000000 +#define DDRSS2_PHY_772_DATA 0x00000000 +#define DDRSS2_PHY_773_DATA 0x01030000 +#define DDRSS2_PHY_774_DATA 0x00010000 +#define DDRSS2_PHY_775_DATA 0x01030004 +#define DDRSS2_PHY_776_DATA 0x01000000 +#define DDRSS2_PHY_777_DATA 0x00000000 +#define DDRSS2_PHY_778_DATA 0x00000000 +#define DDRSS2_PHY_779_DATA 0x01000001 +#define DDRSS2_PHY_780_DATA 0x00000200 +#define DDRSS2_PHY_781_DATA 0x000800C0 +#define DDRSS2_PHY_782_DATA 0x060100CC +#define DDRSS2_PHY_783_DATA 0x00030066 +#define DDRSS2_PHY_784_DATA 0x00000000 +#define DDRSS2_PHY_785_DATA 0x00000301 +#define DDRSS2_PHY_786_DATA 0x0000AAAA +#define DDRSS2_PHY_787_DATA 0x00005555 +#define DDRSS2_PHY_788_DATA 0x0000B5B5 +#define DDRSS2_PHY_789_DATA 0x00004A4A +#define DDRSS2_PHY_790_DATA 0x00005656 +#define DDRSS2_PHY_791_DATA 0x0000A9A9 +#define DDRSS2_PHY_792_DATA 0x0000A9A9 +#define DDRSS2_PHY_793_DATA 0x0000B5B5 +#define DDRSS2_PHY_794_DATA 0x00000000 +#define DDRSS2_PHY_795_DATA 0x00000000 +#define DDRSS2_PHY_796_DATA 0x2A000000 +#define DDRSS2_PHY_797_DATA 0x00000808 +#define DDRSS2_PHY_798_DATA 0x0F000000 +#define DDRSS2_PHY_799_DATA 0x00000F08 +#define DDRSS2_PHY_800_DATA 0x10400000 +#define DDRSS2_PHY_801_DATA 0x0C002006 +#define DDRSS2_PHY_802_DATA 0x00000000 +#define DDRSS2_PHY_803_DATA 0x00000000 +#define DDRSS2_PHY_804_DATA 0x55555555 +#define DDRSS2_PHY_805_DATA 0xAAAAAAAA +#define DDRSS2_PHY_806_DATA 0x55555555 +#define DDRSS2_PHY_807_DATA 0xAAAAAAAA +#define DDRSS2_PHY_808_DATA 0x00005555 +#define DDRSS2_PHY_809_DATA 0x01000100 +#define DDRSS2_PHY_810_DATA 0x00800180 +#define DDRSS2_PHY_811_DATA 0x00000000 +#define DDRSS2_PHY_812_DATA 0x00000000 +#define DDRSS2_PHY_813_DATA 0x00000000 +#define DDRSS2_PHY_814_DATA 0x00000000 +#define DDRSS2_PHY_815_DATA 0x00000000 +#define DDRSS2_PHY_816_DATA 0x00000000 +#define DDRSS2_PHY_817_DATA 0x00000000 +#define DDRSS2_PHY_818_DATA 0x00000000 +#define DDRSS2_PHY_819_DATA 0x00000000 +#define DDRSS2_PHY_820_DATA 0x00000000 +#define DDRSS2_PHY_821_DATA 0x00000000 +#define DDRSS2_PHY_822_DATA 0x00000000 +#define DDRSS2_PHY_823_DATA 0x00000000 +#define DDRSS2_PHY_824_DATA 0x00000000 +#define DDRSS2_PHY_825_DATA 0x00000000 +#define DDRSS2_PHY_826_DATA 0x00000000 +#define DDRSS2_PHY_827_DATA 0x00000000 +#define DDRSS2_PHY_828_DATA 0x00000000 +#define DDRSS2_PHY_829_DATA 0x00000000 +#define DDRSS2_PHY_830_DATA 0x00000000 +#define DDRSS2_PHY_831_DATA 0x00000000 +#define DDRSS2_PHY_832_DATA 0x00000000 +#define DDRSS2_PHY_833_DATA 0x00000000 +#define DDRSS2_PHY_834_DATA 0x00000104 +#define DDRSS2_PHY_835_DATA 0x00000120 +#define DDRSS2_PHY_836_DATA 0x00000000 +#define DDRSS2_PHY_837_DATA 0x00000000 +#define DDRSS2_PHY_838_DATA 0x00000000 +#define DDRSS2_PHY_839_DATA 0x00000000 +#define DDRSS2_PHY_840_DATA 0x00000000 +#define DDRSS2_PHY_841_DATA 0x00000000 +#define DDRSS2_PHY_842_DATA 0x00000000 +#define DDRSS2_PHY_843_DATA 0x00000001 +#define DDRSS2_PHY_844_DATA 0x07FF0000 +#define DDRSS2_PHY_845_DATA 0x0080081F +#define DDRSS2_PHY_846_DATA 0x00081020 +#define DDRSS2_PHY_847_DATA 0x04010000 +#define DDRSS2_PHY_848_DATA 0x00000000 +#define DDRSS2_PHY_849_DATA 0x00000000 +#define DDRSS2_PHY_850_DATA 0x00000000 +#define DDRSS2_PHY_851_DATA 0x00000100 +#define DDRSS2_PHY_852_DATA 0x01CC0C01 +#define DDRSS2_PHY_853_DATA 0x1003CC0C +#define DDRSS2_PHY_854_DATA 0x20000140 +#define DDRSS2_PHY_855_DATA 0x07FF0200 +#define DDRSS2_PHY_856_DATA 0x0000DD01 +#define DDRSS2_PHY_857_DATA 0x10100303 +#define DDRSS2_PHY_858_DATA 0x10101010 +#define DDRSS2_PHY_859_DATA 0x10101010 +#define DDRSS2_PHY_860_DATA 0x00021010 +#define DDRSS2_PHY_861_DATA 0x00100010 +#define DDRSS2_PHY_862_DATA 0x00100010 +#define DDRSS2_PHY_863_DATA 0x00100010 +#define DDRSS2_PHY_864_DATA 0x00100010 +#define DDRSS2_PHY_865_DATA 0x00050010 +#define DDRSS2_PHY_866_DATA 0x51517041 +#define DDRSS2_PHY_867_DATA 0x31C06001 +#define DDRSS2_PHY_868_DATA 0x07AB01AB +#define DDRSS2_PHY_869_DATA 0x00C0C001 +#define DDRSS2_PHY_870_DATA 0x0E0D0101 +#define DDRSS2_PHY_871_DATA 0x10001000 +#define DDRSS2_PHY_872_DATA 0x0C083E42 +#define DDRSS2_PHY_873_DATA 0x0F0C3701 +#define DDRSS2_PHY_874_DATA 0x01000140 +#define DDRSS2_PHY_875_DATA 0x0C000420 +#define DDRSS2_PHY_876_DATA 0x00000198 +#define DDRSS2_PHY_877_DATA 0x0A0000D0 +#define DDRSS2_PHY_878_DATA 0x00030200 +#define DDRSS2_PHY_879_DATA 0x02800000 +#define DDRSS2_PHY_880_DATA 0x80800000 +#define DDRSS2_PHY_881_DATA 0x000E2010 +#define DDRSS2_PHY_882_DATA 0x76543210 +#define DDRSS2_PHY_883_DATA 0x00000008 +#define DDRSS2_PHY_884_DATA 0x02800280 +#define DDRSS2_PHY_885_DATA 0x02800280 +#define DDRSS2_PHY_886_DATA 0x02800280 +#define DDRSS2_PHY_887_DATA 0x02800280 +#define DDRSS2_PHY_888_DATA 0x00000280 +#define DDRSS2_PHY_889_DATA 0x0000A000 +#define DDRSS2_PHY_890_DATA 0x00A000A0 +#define DDRSS2_PHY_891_DATA 0x00A000A0 +#define DDRSS2_PHY_892_DATA 0x00A000A0 +#define DDRSS2_PHY_893_DATA 0x00A000A0 +#define DDRSS2_PHY_894_DATA 0x00A000A0 +#define DDRSS2_PHY_895_DATA 0x00A000A0 +#define DDRSS2_PHY_896_DATA 0x00A000A0 +#define DDRSS2_PHY_897_DATA 0x00A000A0 +#define DDRSS2_PHY_898_DATA 0x01C200A0 +#define DDRSS2_PHY_899_DATA 0x01A00005 +#define DDRSS2_PHY_900_DATA 0x00000000 +#define DDRSS2_PHY_901_DATA 0x00000000 +#define DDRSS2_PHY_902_DATA 0x00080200 +#define DDRSS2_PHY_903_DATA 0x00000000 +#define DDRSS2_PHY_904_DATA 0x20202000 +#define DDRSS2_PHY_905_DATA 0x20202020 +#define DDRSS2_PHY_906_DATA 0xF0F02020 +#define DDRSS2_PHY_907_DATA 0x00000000 +#define DDRSS2_PHY_908_DATA 0x00000000 +#define DDRSS2_PHY_909_DATA 0x00000000 +#define DDRSS2_PHY_910_DATA 0x00000000 +#define DDRSS2_PHY_911_DATA 0x00000000 +#define DDRSS2_PHY_912_DATA 0x00000000 +#define DDRSS2_PHY_913_DATA 0x00000000 +#define DDRSS2_PHY_914_DATA 0x00000000 +#define DDRSS2_PHY_915_DATA 0x00000000 +#define DDRSS2_PHY_916_DATA 0x00000000 +#define DDRSS2_PHY_917_DATA 0x00000000 +#define DDRSS2_PHY_918_DATA 0x00000000 +#define DDRSS2_PHY_919_DATA 0x00000000 +#define DDRSS2_PHY_920_DATA 0x00000000 +#define DDRSS2_PHY_921_DATA 0x00000000 +#define DDRSS2_PHY_922_DATA 0x00000000 +#define DDRSS2_PHY_923_DATA 0x00000000 +#define DDRSS2_PHY_924_DATA 0x00000000 +#define DDRSS2_PHY_925_DATA 0x00000000 +#define DDRSS2_PHY_926_DATA 0x00000000 +#define DDRSS2_PHY_927_DATA 0x00000000 +#define DDRSS2_PHY_928_DATA 0x00000000 +#define DDRSS2_PHY_929_DATA 0x00000000 +#define DDRSS2_PHY_930_DATA 0x00000000 +#define DDRSS2_PHY_931_DATA 0x00000000 +#define DDRSS2_PHY_932_DATA 0x00000000 +#define DDRSS2_PHY_933_DATA 0x00000000 +#define DDRSS2_PHY_934_DATA 0x00000000 +#define DDRSS2_PHY_935_DATA 0x00000000 +#define DDRSS2_PHY_936_DATA 0x00000000 +#define DDRSS2_PHY_937_DATA 0x00000000 +#define DDRSS2_PHY_938_DATA 0x00000000 +#define DDRSS2_PHY_939_DATA 0x00000000 +#define DDRSS2_PHY_940_DATA 0x00000000 +#define DDRSS2_PHY_941_DATA 0x00000000 +#define DDRSS2_PHY_942_DATA 0x00000000 +#define DDRSS2_PHY_943_DATA 0x00000000 +#define DDRSS2_PHY_944_DATA 0x00000000 +#define DDRSS2_PHY_945_DATA 0x00000000 +#define DDRSS2_PHY_946_DATA 0x00000000 +#define DDRSS2_PHY_947_DATA 0x00000000 +#define DDRSS2_PHY_948_DATA 0x00000000 +#define DDRSS2_PHY_949_DATA 0x00000000 +#define DDRSS2_PHY_950_DATA 0x00000000 +#define DDRSS2_PHY_951_DATA 0x00000000 +#define DDRSS2_PHY_952_DATA 0x00000000 +#define DDRSS2_PHY_953_DATA 0x00000000 +#define DDRSS2_PHY_954_DATA 0x00000000 +#define DDRSS2_PHY_955_DATA 0x00000000 +#define DDRSS2_PHY_956_DATA 0x00000000 +#define DDRSS2_PHY_957_DATA 0x00000000 +#define DDRSS2_PHY_958_DATA 0x00000000 +#define DDRSS2_PHY_959_DATA 0x00000000 +#define DDRSS2_PHY_960_DATA 0x00000000 +#define DDRSS2_PHY_961_DATA 0x00000000 +#define DDRSS2_PHY_962_DATA 0x00000000 +#define DDRSS2_PHY_963_DATA 0x00000000 +#define DDRSS2_PHY_964_DATA 0x00000000 +#define DDRSS2_PHY_965_DATA 0x00000000 +#define DDRSS2_PHY_966_DATA 0x00000000 +#define DDRSS2_PHY_967_DATA 0x00000000 +#define DDRSS2_PHY_968_DATA 0x00000000 +#define DDRSS2_PHY_969_DATA 0x00000000 +#define DDRSS2_PHY_970_DATA 0x00000000 +#define DDRSS2_PHY_971_DATA 0x00000000 +#define DDRSS2_PHY_972_DATA 0x00000000 +#define DDRSS2_PHY_973_DATA 0x00000000 +#define DDRSS2_PHY_974_DATA 0x00000000 +#define DDRSS2_PHY_975_DATA 0x00000000 +#define DDRSS2_PHY_976_DATA 0x00000000 +#define DDRSS2_PHY_977_DATA 0x00000000 +#define DDRSS2_PHY_978_DATA 0x00000000 +#define DDRSS2_PHY_979_DATA 0x00000000 +#define DDRSS2_PHY_980_DATA 0x00000000 +#define DDRSS2_PHY_981_DATA 0x00000000 +#define DDRSS2_PHY_982_DATA 0x00000000 +#define DDRSS2_PHY_983_DATA 0x00000000 +#define DDRSS2_PHY_984_DATA 0x00000000 +#define DDRSS2_PHY_985_DATA 0x00000000 +#define DDRSS2_PHY_986_DATA 0x00000000 +#define DDRSS2_PHY_987_DATA 0x00000000 +#define DDRSS2_PHY_988_DATA 0x00000000 +#define DDRSS2_PHY_989_DATA 0x00000000 +#define DDRSS2_PHY_990_DATA 0x00000000 +#define DDRSS2_PHY_991_DATA 0x00000000 +#define DDRSS2_PHY_992_DATA 0x00000000 +#define DDRSS2_PHY_993_DATA 0x00000000 +#define DDRSS2_PHY_994_DATA 0x00000000 +#define DDRSS2_PHY_995_DATA 0x00000000 +#define DDRSS2_PHY_996_DATA 0x00000000 +#define DDRSS2_PHY_997_DATA 0x00000000 +#define DDRSS2_PHY_998_DATA 0x00000000 +#define DDRSS2_PHY_999_DATA 0x00000000 +#define DDRSS2_PHY_1000_DATA 0x00000000 +#define DDRSS2_PHY_1001_DATA 0x00000000 +#define DDRSS2_PHY_1002_DATA 0x00000000 +#define DDRSS2_PHY_1003_DATA 0x00000000 +#define DDRSS2_PHY_1004_DATA 0x00000000 +#define DDRSS2_PHY_1005_DATA 0x00000000 +#define DDRSS2_PHY_1006_DATA 0x00000000 +#define DDRSS2_PHY_1007_DATA 0x00000000 +#define DDRSS2_PHY_1008_DATA 0x00000000 +#define DDRSS2_PHY_1009_DATA 0x00000000 +#define DDRSS2_PHY_1010_DATA 0x00000000 +#define DDRSS2_PHY_1011_DATA 0x00000000 +#define DDRSS2_PHY_1012_DATA 0x00000000 +#define DDRSS2_PHY_1013_DATA 0x00000000 +#define DDRSS2_PHY_1014_DATA 0x00000000 +#define DDRSS2_PHY_1015_DATA 0x00000000 +#define DDRSS2_PHY_1016_DATA 0x00000000 +#define DDRSS2_PHY_1017_DATA 0x00000000 +#define DDRSS2_PHY_1018_DATA 0x00000000 +#define DDRSS2_PHY_1019_DATA 0x00000000 +#define DDRSS2_PHY_1020_DATA 0x00000000 +#define DDRSS2_PHY_1021_DATA 0x00000000 +#define DDRSS2_PHY_1022_DATA 0x00000000 +#define DDRSS2_PHY_1023_DATA 0x00000000 +#define DDRSS2_PHY_1024_DATA 0x00000000 +#define DDRSS2_PHY_1025_DATA 0x00000000 +#define DDRSS2_PHY_1026_DATA 0x00000000 +#define DDRSS2_PHY_1027_DATA 0x00000000 +#define DDRSS2_PHY_1028_DATA 0x00000000 +#define DDRSS2_PHY_1029_DATA 0x00000100 +#define DDRSS2_PHY_1030_DATA 0x00000200 +#define DDRSS2_PHY_1031_DATA 0x00000000 +#define DDRSS2_PHY_1032_DATA 0x00000000 +#define DDRSS2_PHY_1033_DATA 0x00000000 +#define DDRSS2_PHY_1034_DATA 0x00000000 +#define DDRSS2_PHY_1035_DATA 0x00400000 +#define DDRSS2_PHY_1036_DATA 0x00000080 +#define DDRSS2_PHY_1037_DATA 0x00DCBA98 +#define DDRSS2_PHY_1038_DATA 0x03000000 +#define DDRSS2_PHY_1039_DATA 0x00200000 +#define DDRSS2_PHY_1040_DATA 0x00000000 +#define DDRSS2_PHY_1041_DATA 0x00000000 +#define DDRSS2_PHY_1042_DATA 0x00000000 +#define DDRSS2_PHY_1043_DATA 0x00000000 +#define DDRSS2_PHY_1044_DATA 0x00000000 +#define DDRSS2_PHY_1045_DATA 0x0000002A +#define DDRSS2_PHY_1046_DATA 0x00000015 +#define DDRSS2_PHY_1047_DATA 0x00000015 +#define DDRSS2_PHY_1048_DATA 0x0000002A +#define DDRSS2_PHY_1049_DATA 0x00000033 +#define DDRSS2_PHY_1050_DATA 0x0000000C +#define DDRSS2_PHY_1051_DATA 0x0000000C +#define DDRSS2_PHY_1052_DATA 0x00000033 +#define DDRSS2_PHY_1053_DATA 0x00543210 +#define DDRSS2_PHY_1054_DATA 0x003F0000 +#define DDRSS2_PHY_1055_DATA 0x000F3F3F +#define DDRSS2_PHY_1056_DATA 0x20202003 +#define DDRSS2_PHY_1057_DATA 0x00202020 +#define DDRSS2_PHY_1058_DATA 0x20008008 +#define DDRSS2_PHY_1059_DATA 0x00000810 +#define DDRSS2_PHY_1060_DATA 0x00000F00 +#define DDRSS2_PHY_1061_DATA 0x00000000 +#define DDRSS2_PHY_1062_DATA 0x00000000 +#define DDRSS2_PHY_1063_DATA 0x00000000 +#define DDRSS2_PHY_1064_DATA 0x000305CC +#define DDRSS2_PHY_1065_DATA 0x00030000 +#define DDRSS2_PHY_1066_DATA 0x00000300 +#define DDRSS2_PHY_1067_DATA 0x00000300 +#define DDRSS2_PHY_1068_DATA 0x00000300 +#define DDRSS2_PHY_1069_DATA 0x00000300 +#define DDRSS2_PHY_1070_DATA 0x00000300 +#define DDRSS2_PHY_1071_DATA 0x42080010 +#define DDRSS2_PHY_1072_DATA 0x0000803E +#define DDRSS2_PHY_1073_DATA 0x00000001 +#define DDRSS2_PHY_1074_DATA 0x01000102 +#define DDRSS2_PHY_1075_DATA 0x00008000 +#define DDRSS2_PHY_1076_DATA 0x00000000 +#define DDRSS2_PHY_1077_DATA 0x00000000 +#define DDRSS2_PHY_1078_DATA 0x00000000 +#define DDRSS2_PHY_1079_DATA 0x00000000 +#define DDRSS2_PHY_1080_DATA 0x00000000 +#define DDRSS2_PHY_1081_DATA 0x00000000 +#define DDRSS2_PHY_1082_DATA 0x00000000 +#define DDRSS2_PHY_1083_DATA 0x00000000 +#define DDRSS2_PHY_1084_DATA 0x00000000 +#define DDRSS2_PHY_1085_DATA 0x00000000 +#define DDRSS2_PHY_1086_DATA 0x00000000 +#define DDRSS2_PHY_1087_DATA 0x00000000 +#define DDRSS2_PHY_1088_DATA 0x00000000 +#define DDRSS2_PHY_1089_DATA 0x00000000 +#define DDRSS2_PHY_1090_DATA 0x00000000 +#define DDRSS2_PHY_1091_DATA 0x00000000 +#define DDRSS2_PHY_1092_DATA 0x00000000 +#define DDRSS2_PHY_1093_DATA 0x00000000 +#define DDRSS2_PHY_1094_DATA 0x00000000 +#define DDRSS2_PHY_1095_DATA 0x00000000 +#define DDRSS2_PHY_1096_DATA 0x00000000 +#define DDRSS2_PHY_1097_DATA 0x00000000 +#define DDRSS2_PHY_1098_DATA 0x00000000 +#define DDRSS2_PHY_1099_DATA 0x00000000 +#define DDRSS2_PHY_1100_DATA 0x00000000 +#define DDRSS2_PHY_1101_DATA 0x00000000 +#define DDRSS2_PHY_1102_DATA 0x00000000 +#define DDRSS2_PHY_1103_DATA 0x00000000 +#define DDRSS2_PHY_1104_DATA 0x00000000 +#define DDRSS2_PHY_1105_DATA 0x00000000 +#define DDRSS2_PHY_1106_DATA 0x00000000 +#define DDRSS2_PHY_1107_DATA 0x00000000 +#define DDRSS2_PHY_1108_DATA 0x00000000 +#define DDRSS2_PHY_1109_DATA 0x00000000 +#define DDRSS2_PHY_1110_DATA 0x00000000 +#define DDRSS2_PHY_1111_DATA 0x00000000 +#define DDRSS2_PHY_1112_DATA 0x00000000 +#define DDRSS2_PHY_1113_DATA 0x00000000 +#define DDRSS2_PHY_1114_DATA 0x00000000 +#define DDRSS2_PHY_1115_DATA 0x00000000 +#define DDRSS2_PHY_1116_DATA 0x00000000 +#define DDRSS2_PHY_1117_DATA 0x00000000 +#define DDRSS2_PHY_1118_DATA 0x00000000 +#define DDRSS2_PHY_1119_DATA 0x00000000 +#define DDRSS2_PHY_1120_DATA 0x00000000 +#define DDRSS2_PHY_1121_DATA 0x00000000 +#define DDRSS2_PHY_1122_DATA 0x00000000 +#define DDRSS2_PHY_1123_DATA 0x00000000 +#define DDRSS2_PHY_1124_DATA 0x00000000 +#define DDRSS2_PHY_1125_DATA 0x00000000 +#define DDRSS2_PHY_1126_DATA 0x00000000 +#define DDRSS2_PHY_1127_DATA 0x00000000 +#define DDRSS2_PHY_1128_DATA 0x00000000 +#define DDRSS2_PHY_1129_DATA 0x00000000 +#define DDRSS2_PHY_1130_DATA 0x00000000 +#define DDRSS2_PHY_1131_DATA 0x00000000 +#define DDRSS2_PHY_1132_DATA 0x00000000 +#define DDRSS2_PHY_1133_DATA 0x00000000 +#define DDRSS2_PHY_1134_DATA 0x00000000 +#define DDRSS2_PHY_1135_DATA 0x00000000 +#define DDRSS2_PHY_1136_DATA 0x00000000 +#define DDRSS2_PHY_1137_DATA 0x00000000 +#define DDRSS2_PHY_1138_DATA 0x00000000 +#define DDRSS2_PHY_1139_DATA 0x00000000 +#define DDRSS2_PHY_1140_DATA 0x00000000 +#define DDRSS2_PHY_1141_DATA 0x00000000 +#define DDRSS2_PHY_1142_DATA 0x00000000 +#define DDRSS2_PHY_1143_DATA 0x00000000 +#define DDRSS2_PHY_1144_DATA 0x00000000 +#define DDRSS2_PHY_1145_DATA 0x00000000 +#define DDRSS2_PHY_1146_DATA 0x00000000 +#define DDRSS2_PHY_1147_DATA 0x00000000 +#define DDRSS2_PHY_1148_DATA 0x00000000 +#define DDRSS2_PHY_1149_DATA 0x00000000 +#define DDRSS2_PHY_1150_DATA 0x00000000 +#define DDRSS2_PHY_1151_DATA 0x00000000 +#define DDRSS2_PHY_1152_DATA 0x00000000 +#define DDRSS2_PHY_1153_DATA 0x00000000 +#define DDRSS2_PHY_1154_DATA 0x00000000 +#define DDRSS2_PHY_1155_DATA 0x00000000 +#define DDRSS2_PHY_1156_DATA 0x00000000 +#define DDRSS2_PHY_1157_DATA 0x00000000 +#define DDRSS2_PHY_1158_DATA 0x00000000 +#define DDRSS2_PHY_1159_DATA 0x00000000 +#define DDRSS2_PHY_1160_DATA 0x00000000 +#define DDRSS2_PHY_1161_DATA 0x00000000 +#define DDRSS2_PHY_1162_DATA 0x00000000 +#define DDRSS2_PHY_1163_DATA 0x00000000 +#define DDRSS2_PHY_1164_DATA 0x00000000 +#define DDRSS2_PHY_1165_DATA 0x00000000 +#define DDRSS2_PHY_1166_DATA 0x00000000 +#define DDRSS2_PHY_1167_DATA 0x00000000 +#define DDRSS2_PHY_1168_DATA 0x00000000 +#define DDRSS2_PHY_1169_DATA 0x00000000 +#define DDRSS2_PHY_1170_DATA 0x00000000 +#define DDRSS2_PHY_1171_DATA 0x00000000 +#define DDRSS2_PHY_1172_DATA 0x00000000 +#define DDRSS2_PHY_1173_DATA 0x00000000 +#define DDRSS2_PHY_1174_DATA 0x00000000 +#define DDRSS2_PHY_1175_DATA 0x00000000 +#define DDRSS2_PHY_1176_DATA 0x00000000 +#define DDRSS2_PHY_1177_DATA 0x00000000 +#define DDRSS2_PHY_1178_DATA 0x00000000 +#define DDRSS2_PHY_1179_DATA 0x00000000 +#define DDRSS2_PHY_1180_DATA 0x00000000 +#define DDRSS2_PHY_1181_DATA 0x00000000 +#define DDRSS2_PHY_1182_DATA 0x00000000 +#define DDRSS2_PHY_1183_DATA 0x00000000 +#define DDRSS2_PHY_1184_DATA 0x00000000 +#define DDRSS2_PHY_1185_DATA 0x00000000 +#define DDRSS2_PHY_1186_DATA 0x00000000 +#define DDRSS2_PHY_1187_DATA 0x00000000 +#define DDRSS2_PHY_1188_DATA 0x00000000 +#define DDRSS2_PHY_1189_DATA 0x00000000 +#define DDRSS2_PHY_1190_DATA 0x00000000 +#define DDRSS2_PHY_1191_DATA 0x00000000 +#define DDRSS2_PHY_1192_DATA 0x00000000 +#define DDRSS2_PHY_1193_DATA 0x00000000 +#define DDRSS2_PHY_1194_DATA 0x00000000 +#define DDRSS2_PHY_1195_DATA 0x00000000 +#define DDRSS2_PHY_1196_DATA 0x00000000 +#define DDRSS2_PHY_1197_DATA 0x00000000 +#define DDRSS2_PHY_1198_DATA 0x00000000 +#define DDRSS2_PHY_1199_DATA 0x00000000 +#define DDRSS2_PHY_1200_DATA 0x00000000 +#define DDRSS2_PHY_1201_DATA 0x00000000 +#define DDRSS2_PHY_1202_DATA 0x00000000 +#define DDRSS2_PHY_1203_DATA 0x00000000 +#define DDRSS2_PHY_1204_DATA 0x00000000 +#define DDRSS2_PHY_1205_DATA 0x00000000 +#define DDRSS2_PHY_1206_DATA 0x00000000 +#define DDRSS2_PHY_1207_DATA 0x00000000 +#define DDRSS2_PHY_1208_DATA 0x00000000 +#define DDRSS2_PHY_1209_DATA 0x00000000 +#define DDRSS2_PHY_1210_DATA 0x00000000 +#define DDRSS2_PHY_1211_DATA 0x00000000 +#define DDRSS2_PHY_1212_DATA 0x00000000 +#define DDRSS2_PHY_1213_DATA 0x00000000 +#define DDRSS2_PHY_1214_DATA 0x00000000 +#define DDRSS2_PHY_1215_DATA 0x00000000 +#define DDRSS2_PHY_1216_DATA 0x00000000 +#define DDRSS2_PHY_1217_DATA 0x00000000 +#define DDRSS2_PHY_1218_DATA 0x00000000 +#define DDRSS2_PHY_1219_DATA 0x00000000 +#define DDRSS2_PHY_1220_DATA 0x00000000 +#define DDRSS2_PHY_1221_DATA 0x00000000 +#define DDRSS2_PHY_1222_DATA 0x00000000 +#define DDRSS2_PHY_1223_DATA 0x00000000 +#define DDRSS2_PHY_1224_DATA 0x00000000 +#define DDRSS2_PHY_1225_DATA 0x00000000 +#define DDRSS2_PHY_1226_DATA 0x00000000 +#define DDRSS2_PHY_1227_DATA 0x00000000 +#define DDRSS2_PHY_1228_DATA 0x00000000 +#define DDRSS2_PHY_1229_DATA 0x00000000 +#define DDRSS2_PHY_1230_DATA 0x00000000 +#define DDRSS2_PHY_1231_DATA 0x00000000 +#define DDRSS2_PHY_1232_DATA 0x00000000 +#define DDRSS2_PHY_1233_DATA 0x00000000 +#define DDRSS2_PHY_1234_DATA 0x00000000 +#define DDRSS2_PHY_1235_DATA 0x00000000 +#define DDRSS2_PHY_1236_DATA 0x00000000 +#define DDRSS2_PHY_1237_DATA 0x00000000 +#define DDRSS2_PHY_1238_DATA 0x00000000 +#define DDRSS2_PHY_1239_DATA 0x00000000 +#define DDRSS2_PHY_1240_DATA 0x00000000 +#define DDRSS2_PHY_1241_DATA 0x00000000 +#define DDRSS2_PHY_1242_DATA 0x00000000 +#define DDRSS2_PHY_1243_DATA 0x00000000 +#define DDRSS2_PHY_1244_DATA 0x00000000 +#define DDRSS2_PHY_1245_DATA 0x00000000 +#define DDRSS2_PHY_1246_DATA 0x00000000 +#define DDRSS2_PHY_1247_DATA 0x00000000 +#define DDRSS2_PHY_1248_DATA 0x00000000 +#define DDRSS2_PHY_1249_DATA 0x00000000 +#define DDRSS2_PHY_1250_DATA 0x00000000 +#define DDRSS2_PHY_1251_DATA 0x00000000 +#define DDRSS2_PHY_1252_DATA 0x00000000 +#define DDRSS2_PHY_1253_DATA 0x00000000 +#define DDRSS2_PHY_1254_DATA 0x00000000 +#define DDRSS2_PHY_1255_DATA 0x00000000 +#define DDRSS2_PHY_1256_DATA 0x00000000 +#define DDRSS2_PHY_1257_DATA 0x00000000 +#define DDRSS2_PHY_1258_DATA 0x00000000 +#define DDRSS2_PHY_1259_DATA 0x00000000 +#define DDRSS2_PHY_1260_DATA 0x00000000 +#define DDRSS2_PHY_1261_DATA 0x00000000 +#define DDRSS2_PHY_1262_DATA 0x00000000 +#define DDRSS2_PHY_1263_DATA 0x00000000 +#define DDRSS2_PHY_1264_DATA 0x00000000 +#define DDRSS2_PHY_1265_DATA 0x00000000 +#define DDRSS2_PHY_1266_DATA 0x00000000 +#define DDRSS2_PHY_1267_DATA 0x00000000 +#define DDRSS2_PHY_1268_DATA 0x00000000 +#define DDRSS2_PHY_1269_DATA 0x00000000 +#define DDRSS2_PHY_1270_DATA 0x00000000 +#define DDRSS2_PHY_1271_DATA 0x00000000 +#define DDRSS2_PHY_1272_DATA 0x00000000 +#define DDRSS2_PHY_1273_DATA 0x00000000 +#define DDRSS2_PHY_1274_DATA 0x00000000 +#define DDRSS2_PHY_1275_DATA 0x00000000 +#define DDRSS2_PHY_1276_DATA 0x00000000 +#define DDRSS2_PHY_1277_DATA 0x00000000 +#define DDRSS2_PHY_1278_DATA 0x00000000 +#define DDRSS2_PHY_1279_DATA 0x00000000 +#define DDRSS2_PHY_1280_DATA 0x00000000 +#define DDRSS2_PHY_1281_DATA 0x00010100 +#define DDRSS2_PHY_1282_DATA 0x00000000 +#define DDRSS2_PHY_1283_DATA 0x00000000 +#define DDRSS2_PHY_1284_DATA 0x00050000 +#define DDRSS2_PHY_1285_DATA 0x04000000 +#define DDRSS2_PHY_1286_DATA 0x00000055 +#define DDRSS2_PHY_1287_DATA 0x00000000 +#define DDRSS2_PHY_1288_DATA 0x00000000 +#define DDRSS2_PHY_1289_DATA 0x00000000 +#define DDRSS2_PHY_1290_DATA 0x00000000 +#define DDRSS2_PHY_1291_DATA 0x00002001 +#define DDRSS2_PHY_1292_DATA 0x0000400F +#define DDRSS2_PHY_1293_DATA 0x50020028 +#define DDRSS2_PHY_1294_DATA 0x01010000 +#define DDRSS2_PHY_1295_DATA 0x80080001 +#define DDRSS2_PHY_1296_DATA 0x10200000 +#define DDRSS2_PHY_1297_DATA 0x00000008 +#define DDRSS2_PHY_1298_DATA 0x00000000 +#define DDRSS2_PHY_1299_DATA 0x01090E00 +#define DDRSS2_PHY_1300_DATA 0x00040101 +#define DDRSS2_PHY_1301_DATA 0x0000010F +#define DDRSS2_PHY_1302_DATA 0x00000000 +#define DDRSS2_PHY_1303_DATA 0x00000064 +#define DDRSS2_PHY_1304_DATA 0x00000000 +#define DDRSS2_PHY_1305_DATA 0x01010000 +#define DDRSS2_PHY_1306_DATA 0x01080402 +#define DDRSS2_PHY_1307_DATA 0x01200F02 +#define DDRSS2_PHY_1308_DATA 0x00194280 +#define DDRSS2_PHY_1309_DATA 0x00000004 +#define DDRSS2_PHY_1310_DATA 0x00042000 +#define DDRSS2_PHY_1311_DATA 0x00000000 +#define DDRSS2_PHY_1312_DATA 0x00000000 +#define DDRSS2_PHY_1313_DATA 0x00000000 +#define DDRSS2_PHY_1314_DATA 0x00000000 +#define DDRSS2_PHY_1315_DATA 0x00000000 +#define DDRSS2_PHY_1316_DATA 0x00000000 +#define DDRSS2_PHY_1317_DATA 0x01000000 +#define DDRSS2_PHY_1318_DATA 0x00000705 +#define DDRSS2_PHY_1319_DATA 0x00000054 +#define DDRSS2_PHY_1320_DATA 0x00030820 +#define DDRSS2_PHY_1321_DATA 0x00010820 +#define DDRSS2_PHY_1322_DATA 0x00010820 +#define DDRSS2_PHY_1323_DATA 0x00010820 +#define DDRSS2_PHY_1324_DATA 0x00010820 +#define DDRSS2_PHY_1325_DATA 0x00010820 +#define DDRSS2_PHY_1326_DATA 0x00010820 +#define DDRSS2_PHY_1327_DATA 0x00010820 +#define DDRSS2_PHY_1328_DATA 0x00010820 +#define DDRSS2_PHY_1329_DATA 0x00000000 +#define DDRSS2_PHY_1330_DATA 0x00000074 +#define DDRSS2_PHY_1331_DATA 0x00000400 +#define DDRSS2_PHY_1332_DATA 0x00000108 +#define DDRSS2_PHY_1333_DATA 0x00000000 +#define DDRSS2_PHY_1334_DATA 0x00000000 +#define DDRSS2_PHY_1335_DATA 0x00000000 +#define DDRSS2_PHY_1336_DATA 0x00000000 +#define DDRSS2_PHY_1337_DATA 0x00000000 +#define DDRSS2_PHY_1338_DATA 0x03000000 +#define DDRSS2_PHY_1339_DATA 0x00000000 +#define DDRSS2_PHY_1340_DATA 0x00000000 +#define DDRSS2_PHY_1341_DATA 0x00000000 +#define DDRSS2_PHY_1342_DATA 0x04102006 +#define DDRSS2_PHY_1343_DATA 0x00041020 +#define DDRSS2_PHY_1344_DATA 0x01C98C98 +#define DDRSS2_PHY_1345_DATA 0x3F400000 +#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS2_PHY_1347_DATA 0x0000001F +#define DDRSS2_PHY_1348_DATA 0x00000000 +#define DDRSS2_PHY_1349_DATA 0x00000000 +#define DDRSS2_PHY_1350_DATA 0x00000000 +#define DDRSS2_PHY_1351_DATA 0x00010000 +#define DDRSS2_PHY_1352_DATA 0x00000000 +#define DDRSS2_PHY_1353_DATA 0x00000000 +#define DDRSS2_PHY_1354_DATA 0x00000000 +#define DDRSS2_PHY_1355_DATA 0x00000000 +#define DDRSS2_PHY_1356_DATA 0x76543210 +#define DDRSS2_PHY_1357_DATA 0x00010198 +#define DDRSS2_PHY_1358_DATA 0x00000000 +#define DDRSS2_PHY_1359_DATA 0x00000000 +#define DDRSS2_PHY_1360_DATA 0x00000000 +#define DDRSS2_PHY_1361_DATA 0x00040700 +#define DDRSS2_PHY_1362_DATA 0x00000000 +#define DDRSS2_PHY_1363_DATA 0x00000000 +#define DDRSS2_PHY_1364_DATA 0x00000000 +#define DDRSS2_PHY_1365_DATA 0x00000000 +#define DDRSS2_PHY_1366_DATA 0x00000000 +#define DDRSS2_PHY_1367_DATA 0x00000002 +#define DDRSS2_PHY_1368_DATA 0x00000000 +#define DDRSS2_PHY_1369_DATA 0x00000000 +#define DDRSS2_PHY_1370_DATA 0x00000000 +#define DDRSS2_PHY_1371_DATA 0x00000000 +#define DDRSS2_PHY_1372_DATA 0x00000000 +#define DDRSS2_PHY_1373_DATA 0x00000000 +#define DDRSS2_PHY_1374_DATA 0x00080000 +#define DDRSS2_PHY_1375_DATA 0x000007FF +#define DDRSS2_PHY_1376_DATA 0x00000000 +#define DDRSS2_PHY_1377_DATA 0x00000000 +#define DDRSS2_PHY_1378_DATA 0x00000000 +#define DDRSS2_PHY_1379_DATA 0x00000000 +#define DDRSS2_PHY_1380_DATA 0x00000000 +#define DDRSS2_PHY_1381_DATA 0x00000000 +#define DDRSS2_PHY_1382_DATA 0x000FFFFF +#define DDRSS2_PHY_1383_DATA 0x000FFFFF +#define DDRSS2_PHY_1384_DATA 0x0000FFFF +#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS2_PHY_1386_DATA 0x030FFFFF +#define DDRSS2_PHY_1387_DATA 0x01FFFFFF +#define DDRSS2_PHY_1388_DATA 0x0000FFFF +#define DDRSS2_PHY_1389_DATA 0x00000000 +#define DDRSS2_PHY_1390_DATA 0x00000000 +#define DDRSS2_PHY_1391_DATA 0x00000000 +#define DDRSS2_PHY_1392_DATA 0x00000000 +#define DDRSS2_PHY_1393_DATA 0x0001F7C0 +#define DDRSS2_PHY_1394_DATA 0x00000003 +#define DDRSS2_PHY_1395_DATA 0x00000000 +#define DDRSS2_PHY_1396_DATA 0x00001142 +#define DDRSS2_PHY_1397_DATA 0x040207AB +#define DDRSS2_PHY_1398_DATA 0x01000080 +#define DDRSS2_PHY_1399_DATA 0x03900390 +#define DDRSS2_PHY_1400_DATA 0x03900390 +#define DDRSS2_PHY_1401_DATA 0x00000390 +#define DDRSS2_PHY_1402_DATA 0x00000390 +#define DDRSS2_PHY_1403_DATA 0x00000390 +#define DDRSS2_PHY_1404_DATA 0x00000390 +#define DDRSS2_PHY_1405_DATA 0x00000005 +#define DDRSS2_PHY_1406_DATA 0x01813FCC +#define DDRSS2_PHY_1407_DATA 0x000000CC +#define DDRSS2_PHY_1408_DATA 0x0C000DFF +#define DDRSS2_PHY_1409_DATA 0x30000DFF +#define DDRSS2_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1411_DATA 0x000100F0 +#define DDRSS2_PHY_1412_DATA 0x780DFFCC +#define DDRSS2_PHY_1413_DATA 0x00007E31 +#define DDRSS2_PHY_1414_DATA 0x000CBF11 +#define DDRSS2_PHY_1415_DATA 0x01990010 +#define DDRSS2_PHY_1416_DATA 0x000CBF11 +#define DDRSS2_PHY_1417_DATA 0x01990010 +#define DDRSS2_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1419_DATA 0x00EF00F0 +#define DDRSS2_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1421_DATA 0x01FF00F0 +#define DDRSS2_PHY_1422_DATA 0x20040006 + +#define DDRSS3_CTL_00_DATA 0x00000B00 +#define DDRSS3_CTL_01_DATA 0x00000000 +#define DDRSS3_CTL_02_DATA 0x00000000 +#define DDRSS3_CTL_03_DATA 0x00000000 +#define DDRSS3_CTL_04_DATA 0x00000000 +#define DDRSS3_CTL_05_DATA 0x00000000 +#define DDRSS3_CTL_06_DATA 0x00000000 +#define DDRSS3_CTL_07_DATA 0x00002AF8 +#define DDRSS3_CTL_08_DATA 0x0001ADAF +#define DDRSS3_CTL_09_DATA 0x00000005 +#define DDRSS3_CTL_10_DATA 0x0000006E +#define DDRSS3_CTL_11_DATA 0x000681C8 +#define DDRSS3_CTL_12_DATA 0x004111C9 +#define DDRSS3_CTL_13_DATA 0x00000005 +#define DDRSS3_CTL_14_DATA 0x000010A9 +#define DDRSS3_CTL_15_DATA 0x000681C8 +#define DDRSS3_CTL_16_DATA 0x004111C9 +#define DDRSS3_CTL_17_DATA 0x00000005 +#define DDRSS3_CTL_18_DATA 0x000010A9 +#define DDRSS3_CTL_19_DATA 0x01010000 +#define DDRSS3_CTL_20_DATA 0x01011001 +#define DDRSS3_CTL_21_DATA 0x02010000 +#define DDRSS3_CTL_22_DATA 0x00020100 +#define DDRSS3_CTL_23_DATA 0x0000000B +#define DDRSS3_CTL_24_DATA 0x0000001C +#define DDRSS3_CTL_25_DATA 0x00000000 +#define DDRSS3_CTL_26_DATA 0x00000000 +#define DDRSS3_CTL_27_DATA 0x03020200 +#define DDRSS3_CTL_28_DATA 0x00005656 +#define DDRSS3_CTL_29_DATA 0x00100000 +#define DDRSS3_CTL_30_DATA 0x00000000 +#define DDRSS3_CTL_31_DATA 0x00000000 +#define DDRSS3_CTL_32_DATA 0x00000000 +#define DDRSS3_CTL_33_DATA 0x00000000 +#define DDRSS3_CTL_34_DATA 0x040C0000 +#define DDRSS3_CTL_35_DATA 0x12501250 +#define DDRSS3_CTL_36_DATA 0x00050804 +#define DDRSS3_CTL_37_DATA 0x09040008 +#define DDRSS3_CTL_38_DATA 0x15000204 +#define DDRSS3_CTL_39_DATA 0x1760008B +#define DDRSS3_CTL_40_DATA 0x1500422B +#define DDRSS3_CTL_41_DATA 0x1760008B +#define DDRSS3_CTL_42_DATA 0x2000422B +#define DDRSS3_CTL_43_DATA 0x000A0A09 +#define DDRSS3_CTL_44_DATA 0x040003C5 +#define DDRSS3_CTL_45_DATA 0x1E161104 +#define DDRSS3_CTL_46_DATA 0x1000922C +#define DDRSS3_CTL_47_DATA 0x1E161110 +#define DDRSS3_CTL_48_DATA 0x1000922C +#define DDRSS3_CTL_49_DATA 0x02030410 +#define DDRSS3_CTL_50_DATA 0x2C060500 +#define DDRSS3_CTL_51_DATA 0x08292C29 +#define DDRSS3_CTL_52_DATA 0x14000E0A +#define DDRSS3_CTL_53_DATA 0x04010A0A +#define DDRSS3_CTL_54_DATA 0x01010004 +#define DDRSS3_CTL_55_DATA 0x0454540A +#define DDRSS3_CTL_56_DATA 0x04313104 +#define DDRSS3_CTL_57_DATA 0x00003131 +#define DDRSS3_CTL_58_DATA 0x00010100 +#define DDRSS3_CTL_59_DATA 0x03010000 +#define DDRSS3_CTL_60_DATA 0x00001508 +#define DDRSS3_CTL_61_DATA 0x00000068 +#define DDRSS3_CTL_62_DATA 0x0000032B +#define DDRSS3_CTL_63_DATA 0x00001035 +#define DDRSS3_CTL_64_DATA 0x0000032B +#define DDRSS3_CTL_65_DATA 0x00001035 +#define DDRSS3_CTL_66_DATA 0x00000005 +#define DDRSS3_CTL_67_DATA 0x00050000 +#define DDRSS3_CTL_68_DATA 0x00CB0005 +#define DDRSS3_CTL_69_DATA 0x00CB0200 +#define DDRSS3_CTL_70_DATA 0x00400200 +#define DDRSS3_CTL_71_DATA 0x00120103 +#define DDRSS3_CTL_72_DATA 0x00100005 +#define DDRSS3_CTL_73_DATA 0x2F080010 +#define DDRSS3_CTL_74_DATA 0x0505012F +#define DDRSS3_CTL_75_DATA 0x0401030A +#define DDRSS3_CTL_76_DATA 0x041E100B +#define DDRSS3_CTL_77_DATA 0x100B0401 +#define DDRSS3_CTL_78_DATA 0x0001041E +#define DDRSS3_CTL_79_DATA 0x00160016 +#define DDRSS3_CTL_80_DATA 0x033B033B +#define DDRSS3_CTL_81_DATA 0x033B033B +#define DDRSS3_CTL_82_DATA 0x03050505 +#define DDRSS3_CTL_83_DATA 0x03010303 +#define DDRSS3_CTL_84_DATA 0x200B100B +#define DDRSS3_CTL_85_DATA 0x04041004 +#define DDRSS3_CTL_86_DATA 0x200B100B +#define DDRSS3_CTL_87_DATA 0x04041004 +#define DDRSS3_CTL_88_DATA 0x03010000 +#define DDRSS3_CTL_89_DATA 0x00010000 +#define DDRSS3_CTL_90_DATA 0x00000000 +#define DDRSS3_CTL_91_DATA 0x00000000 +#define DDRSS3_CTL_92_DATA 0x01000000 +#define DDRSS3_CTL_93_DATA 0x80104002 +#define DDRSS3_CTL_94_DATA 0x00000000 +#define DDRSS3_CTL_95_DATA 0x00040005 +#define DDRSS3_CTL_96_DATA 0x00000000 +#define DDRSS3_CTL_97_DATA 0x00050000 +#define DDRSS3_CTL_98_DATA 0x00000004 +#define DDRSS3_CTL_99_DATA 0x00000000 +#define DDRSS3_CTL_100_DATA 0x00040005 +#define DDRSS3_CTL_101_DATA 0x00000000 +#define DDRSS3_CTL_102_DATA 0x000018C0 +#define DDRSS3_CTL_103_DATA 0x000018C0 +#define DDRSS3_CTL_104_DATA 0x000018C0 +#define DDRSS3_CTL_105_DATA 0x000018C0 +#define DDRSS3_CTL_106_DATA 0x000018C0 +#define DDRSS3_CTL_107_DATA 0x00000000 +#define DDRSS3_CTL_108_DATA 0x000002B5 +#define DDRSS3_CTL_109_DATA 0x00040D40 +#define DDRSS3_CTL_110_DATA 0x00040D40 +#define DDRSS3_CTL_111_DATA 0x00040D40 +#define DDRSS3_CTL_112_DATA 0x00040D40 +#define DDRSS3_CTL_113_DATA 0x00040D40 +#define DDRSS3_CTL_114_DATA 0x00000000 +#define DDRSS3_CTL_115_DATA 0x00007173 +#define DDRSS3_CTL_116_DATA 0x00040D40 +#define DDRSS3_CTL_117_DATA 0x00040D40 +#define DDRSS3_CTL_118_DATA 0x00040D40 +#define DDRSS3_CTL_119_DATA 0x00040D40 +#define DDRSS3_CTL_120_DATA 0x00040D40 +#define DDRSS3_CTL_121_DATA 0x00000000 +#define DDRSS3_CTL_122_DATA 0x00007173 +#define DDRSS3_CTL_123_DATA 0x00000000 +#define DDRSS3_CTL_124_DATA 0x00000000 +#define DDRSS3_CTL_125_DATA 0x00000000 +#define DDRSS3_CTL_126_DATA 0x00000000 +#define DDRSS3_CTL_127_DATA 0x00000000 +#define DDRSS3_CTL_128_DATA 0x00000000 +#define DDRSS3_CTL_129_DATA 0x00000000 +#define DDRSS3_CTL_130_DATA 0x00000000 +#define DDRSS3_CTL_131_DATA 0x0B030500 +#define DDRSS3_CTL_132_DATA 0x00040B04 +#define DDRSS3_CTL_133_DATA 0x0A090000 +#define DDRSS3_CTL_134_DATA 0x0A090701 +#define DDRSS3_CTL_135_DATA 0x0900000E +#define DDRSS3_CTL_136_DATA 0x0907010A +#define DDRSS3_CTL_137_DATA 0x00000E0A +#define DDRSS3_CTL_138_DATA 0x07010A09 +#define DDRSS3_CTL_139_DATA 0x000E0A09 +#define DDRSS3_CTL_140_DATA 0x07000401 +#define DDRSS3_CTL_141_DATA 0x00000000 +#define DDRSS3_CTL_142_DATA 0x00000000 +#define DDRSS3_CTL_143_DATA 0x00000000 +#define DDRSS3_CTL_144_DATA 0x00000000 +#define DDRSS3_CTL_145_DATA 0x00000000 +#define DDRSS3_CTL_146_DATA 0x00000000 +#define DDRSS3_CTL_147_DATA 0x00000000 +#define DDRSS3_CTL_148_DATA 0x08080000 +#define DDRSS3_CTL_149_DATA 0x01000000 +#define DDRSS3_CTL_150_DATA 0x800000C0 +#define DDRSS3_CTL_151_DATA 0x800000C0 +#define DDRSS3_CTL_152_DATA 0x800000C0 +#define DDRSS3_CTL_153_DATA 0x00000000 +#define DDRSS3_CTL_154_DATA 0x00001500 +#define DDRSS3_CTL_155_DATA 0x00000000 +#define DDRSS3_CTL_156_DATA 0x00000001 +#define DDRSS3_CTL_157_DATA 0x00000002 +#define DDRSS3_CTL_158_DATA 0x0000100E +#define DDRSS3_CTL_159_DATA 0x00000000 +#define DDRSS3_CTL_160_DATA 0x00000000 +#define DDRSS3_CTL_161_DATA 0x00000000 +#define DDRSS3_CTL_162_DATA 0x00000000 +#define DDRSS3_CTL_163_DATA 0x00000000 +#define DDRSS3_CTL_164_DATA 0x000B0000 +#define DDRSS3_CTL_165_DATA 0x000E0006 +#define DDRSS3_CTL_166_DATA 0x000E0404 +#define DDRSS3_CTL_167_DATA 0x00D601AB +#define DDRSS3_CTL_168_DATA 0x10100216 +#define DDRSS3_CTL_169_DATA 0x01AB0216 +#define DDRSS3_CTL_170_DATA 0x021600D6 +#define DDRSS3_CTL_171_DATA 0x02161010 +#define DDRSS3_CTL_172_DATA 0x00000000 +#define DDRSS3_CTL_173_DATA 0x00000000 +#define DDRSS3_CTL_174_DATA 0x00000000 +#define DDRSS3_CTL_175_DATA 0x3FF40084 +#define DDRSS3_CTL_176_DATA 0xF3003FF4 +#define DDRSS3_CTL_177_DATA 0x0000F3F3 +#define DDRSS3_CTL_178_DATA 0x35350000 +#define DDRSS3_CTL_179_DATA 0x27270035 +#define DDRSS3_CTL_180_DATA 0x0F0F0000 +#define DDRSS3_CTL_181_DATA 0x16000000 +#define DDRSS3_CTL_182_DATA 0x00841616 +#define DDRSS3_CTL_183_DATA 0x3FF43FF4 +#define DDRSS3_CTL_184_DATA 0xF3F3F300 +#define DDRSS3_CTL_185_DATA 0x00000000 +#define DDRSS3_CTL_186_DATA 0x00353535 +#define DDRSS3_CTL_187_DATA 0x00002727 +#define DDRSS3_CTL_188_DATA 0x00000F0F +#define DDRSS3_CTL_189_DATA 0x16161600 +#define DDRSS3_CTL_190_DATA 0x00000020 +#define DDRSS3_CTL_191_DATA 0x01000000 +#define DDRSS3_CTL_192_DATA 0x00000001 +#define DDRSS3_CTL_193_DATA 0x00000000 +#define DDRSS3_CTL_194_DATA 0x01000000 +#define DDRSS3_CTL_195_DATA 0x00000001 +#define DDRSS3_CTL_196_DATA 0x00000000 +#define DDRSS3_CTL_197_DATA 0x00000000 +#define DDRSS3_CTL_198_DATA 0x00000000 +#define DDRSS3_CTL_199_DATA 0x00000000 +#define DDRSS3_CTL_200_DATA 0x00000000 +#define DDRSS3_CTL_201_DATA 0x00000000 +#define DDRSS3_CTL_202_DATA 0x00000000 +#define DDRSS3_CTL_203_DATA 0x00000000 +#define DDRSS3_CTL_204_DATA 0x00000000 +#define DDRSS3_CTL_205_DATA 0x00000000 +#define DDRSS3_CTL_206_DATA 0x02000000 +#define DDRSS3_CTL_207_DATA 0x01080101 +#define DDRSS3_CTL_208_DATA 0x00000000 +#define DDRSS3_CTL_209_DATA 0x00000000 +#define DDRSS3_CTL_210_DATA 0x00000000 +#define DDRSS3_CTL_211_DATA 0x00000000 +#define DDRSS3_CTL_212_DATA 0x00000000 +#define DDRSS3_CTL_213_DATA 0x00000000 +#define DDRSS3_CTL_214_DATA 0x00000000 +#define DDRSS3_CTL_215_DATA 0x00000000 +#define DDRSS3_CTL_216_DATA 0x00000000 +#define DDRSS3_CTL_217_DATA 0x00000000 +#define DDRSS3_CTL_218_DATA 0x00000000 +#define DDRSS3_CTL_219_DATA 0x00000000 +#define DDRSS3_CTL_220_DATA 0x00000000 +#define DDRSS3_CTL_221_DATA 0x00000000 +#define DDRSS3_CTL_222_DATA 0x00001000 +#define DDRSS3_CTL_223_DATA 0x006403E8 +#define DDRSS3_CTL_224_DATA 0x00000000 +#define DDRSS3_CTL_225_DATA 0x00000000 +#define DDRSS3_CTL_226_DATA 0x00000000 +#define DDRSS3_CTL_227_DATA 0x15110000 +#define DDRSS3_CTL_228_DATA 0x00040C18 +#define DDRSS3_CTL_229_DATA 0xF000C000 +#define DDRSS3_CTL_230_DATA 0x0000F000 +#define DDRSS3_CTL_231_DATA 0x00000000 +#define DDRSS3_CTL_232_DATA 0x00000000 +#define DDRSS3_CTL_233_DATA 0xC0000000 +#define DDRSS3_CTL_234_DATA 0xF000F000 +#define DDRSS3_CTL_235_DATA 0x00000000 +#define DDRSS3_CTL_236_DATA 0x00000000 +#define DDRSS3_CTL_237_DATA 0x00000000 +#define DDRSS3_CTL_238_DATA 0xF000C000 +#define DDRSS3_CTL_239_DATA 0x0000F000 +#define DDRSS3_CTL_240_DATA 0x00000000 +#define DDRSS3_CTL_241_DATA 0x00000000 +#define DDRSS3_CTL_242_DATA 0x00030000 +#define DDRSS3_CTL_243_DATA 0x00000000 +#define DDRSS3_CTL_244_DATA 0x00000000 +#define DDRSS3_CTL_245_DATA 0x00000000 +#define DDRSS3_CTL_246_DATA 0x00000000 +#define DDRSS3_CTL_247_DATA 0x00000000 +#define DDRSS3_CTL_248_DATA 0x00000000 +#define DDRSS3_CTL_249_DATA 0x00000000 +#define DDRSS3_CTL_250_DATA 0x00000000 +#define DDRSS3_CTL_251_DATA 0x00000000 +#define DDRSS3_CTL_252_DATA 0x00000000 +#define DDRSS3_CTL_253_DATA 0x00000000 +#define DDRSS3_CTL_254_DATA 0x00000000 +#define DDRSS3_CTL_255_DATA 0x00000000 +#define DDRSS3_CTL_256_DATA 0x00000000 +#define DDRSS3_CTL_257_DATA 0x01000200 +#define DDRSS3_CTL_258_DATA 0x00370040 +#define DDRSS3_CTL_259_DATA 0x00020008 +#define DDRSS3_CTL_260_DATA 0x00400100 +#define DDRSS3_CTL_261_DATA 0x00400855 +#define DDRSS3_CTL_262_DATA 0x01000200 +#define DDRSS3_CTL_263_DATA 0x08550040 +#define DDRSS3_CTL_264_DATA 0x00000040 +#define DDRSS3_CTL_265_DATA 0x006B0003 +#define DDRSS3_CTL_266_DATA 0x0100006B +#define DDRSS3_CTL_267_DATA 0x03030303 +#define DDRSS3_CTL_268_DATA 0x00000000 +#define DDRSS3_CTL_269_DATA 0x00000202 +#define DDRSS3_CTL_270_DATA 0x00001FFF +#define DDRSS3_CTL_271_DATA 0x3FFF2000 +#define DDRSS3_CTL_272_DATA 0x03FF0000 +#define DDRSS3_CTL_273_DATA 0x000103FF +#define DDRSS3_CTL_274_DATA 0x0FFF0B00 +#define DDRSS3_CTL_275_DATA 0x01010001 +#define DDRSS3_CTL_276_DATA 0x01010101 +#define DDRSS3_CTL_277_DATA 0x01180101 +#define DDRSS3_CTL_278_DATA 0x00030000 +#define DDRSS3_CTL_279_DATA 0x00000000 +#define DDRSS3_CTL_280_DATA 0x00000000 +#define DDRSS3_CTL_281_DATA 0x00000000 +#define DDRSS3_CTL_282_DATA 0x00000000 +#define DDRSS3_CTL_283_DATA 0x00000000 +#define DDRSS3_CTL_284_DATA 0x00000000 +#define DDRSS3_CTL_285_DATA 0x00000000 +#define DDRSS3_CTL_286_DATA 0x00040101 +#define DDRSS3_CTL_287_DATA 0x04010100 +#define DDRSS3_CTL_288_DATA 0x00000000 +#define DDRSS3_CTL_289_DATA 0x00000000 +#define DDRSS3_CTL_290_DATA 0x03030300 +#define DDRSS3_CTL_291_DATA 0x00010101 +#define DDRSS3_CTL_292_DATA 0x00000000 +#define DDRSS3_CTL_293_DATA 0x00000000 +#define DDRSS3_CTL_294_DATA 0x00000000 +#define DDRSS3_CTL_295_DATA 0x00000000 +#define DDRSS3_CTL_296_DATA 0x00000000 +#define DDRSS3_CTL_297_DATA 0xFFFFFFFF +#define DDRSS3_CTL_298_DATA 0x00000FFF +#define DDRSS3_CTL_299_DATA 0x00000000 +#define DDRSS3_CTL_300_DATA 0x00000000 +#define DDRSS3_CTL_301_DATA 0x00000000 +#define DDRSS3_CTL_302_DATA 0x00000000 +#define DDRSS3_CTL_303_DATA 0x00000000 +#define DDRSS3_CTL_304_DATA 0x00000000 +#define DDRSS3_CTL_305_DATA 0x00000000 +#define DDRSS3_CTL_306_DATA 0x00000000 +#define DDRSS3_CTL_307_DATA 0x00000000 +#define DDRSS3_CTL_308_DATA 0x00000000 +#define DDRSS3_CTL_309_DATA 0x00000000 +#define DDRSS3_CTL_310_DATA 0x00000000 +#define DDRSS3_CTL_311_DATA 0x00000000 +#define DDRSS3_CTL_312_DATA 0x00000000 +#define DDRSS3_CTL_313_DATA 0x01000000 +#define DDRSS3_CTL_314_DATA 0x00020201 +#define DDRSS3_CTL_315_DATA 0x01000101 +#define DDRSS3_CTL_316_DATA 0x01010001 +#define DDRSS3_CTL_317_DATA 0x00010101 +#define DDRSS3_CTL_318_DATA 0x050A0A03 +#define DDRSS3_CTL_319_DATA 0x10082323 +#define DDRSS3_CTL_320_DATA 0x00090310 +#define DDRSS3_CTL_321_DATA 0x0B0C030F +#define DDRSS3_CTL_322_DATA 0x0B0C0306 +#define DDRSS3_CTL_323_DATA 0x0C090006 +#define DDRSS3_CTL_324_DATA 0x0100000C +#define DDRSS3_CTL_325_DATA 0x08040801 +#define DDRSS3_CTL_326_DATA 0x00000004 +#define DDRSS3_CTL_327_DATA 0x00000000 +#define DDRSS3_CTL_328_DATA 0x00010000 +#define DDRSS3_CTL_329_DATA 0x00280D00 +#define DDRSS3_CTL_330_DATA 0x00000001 +#define DDRSS3_CTL_331_DATA 0x00030001 +#define DDRSS3_CTL_332_DATA 0x00000000 +#define DDRSS3_CTL_333_DATA 0x00000000 +#define DDRSS3_CTL_334_DATA 0x00000000 +#define DDRSS3_CTL_335_DATA 0x00000000 +#define DDRSS3_CTL_336_DATA 0x00000000 +#define DDRSS3_CTL_337_DATA 0x00000000 +#define DDRSS3_CTL_338_DATA 0x00000000 +#define DDRSS3_CTL_339_DATA 0x00000000 +#define DDRSS3_CTL_340_DATA 0x01000000 +#define DDRSS3_CTL_341_DATA 0x00000001 +#define DDRSS3_CTL_342_DATA 0x00010100 +#define DDRSS3_CTL_343_DATA 0x03030000 +#define DDRSS3_CTL_344_DATA 0x00000000 +#define DDRSS3_CTL_345_DATA 0x00000000 +#define DDRSS3_CTL_346_DATA 0x00000000 +#define DDRSS3_CTL_347_DATA 0x00000000 +#define DDRSS3_CTL_348_DATA 0x00000000 +#define DDRSS3_CTL_349_DATA 0x00000000 +#define DDRSS3_CTL_350_DATA 0x00000000 +#define DDRSS3_CTL_351_DATA 0x00000000 +#define DDRSS3_CTL_352_DATA 0x00000000 +#define DDRSS3_CTL_353_DATA 0x00000000 +#define DDRSS3_CTL_354_DATA 0x00000000 +#define DDRSS3_CTL_355_DATA 0x00000000 +#define DDRSS3_CTL_356_DATA 0x00000000 +#define DDRSS3_CTL_357_DATA 0x00000000 +#define DDRSS3_CTL_358_DATA 0x00000000 +#define DDRSS3_CTL_359_DATA 0x00000000 +#define DDRSS3_CTL_360_DATA 0x000556AA +#define DDRSS3_CTL_361_DATA 0x000AAAAA +#define DDRSS3_CTL_362_DATA 0x000AA955 +#define DDRSS3_CTL_363_DATA 0x00055555 +#define DDRSS3_CTL_364_DATA 0x000B3133 +#define DDRSS3_CTL_365_DATA 0x0004CD33 +#define DDRSS3_CTL_366_DATA 0x0004CECC +#define DDRSS3_CTL_367_DATA 0x000B32CC +#define DDRSS3_CTL_368_DATA 0x00010300 +#define DDRSS3_CTL_369_DATA 0x03000100 +#define DDRSS3_CTL_370_DATA 0x00000000 +#define DDRSS3_CTL_371_DATA 0x00000000 +#define DDRSS3_CTL_372_DATA 0x00000000 +#define DDRSS3_CTL_373_DATA 0x00000000 +#define DDRSS3_CTL_374_DATA 0x00000000 +#define DDRSS3_CTL_375_DATA 0x00000000 +#define DDRSS3_CTL_376_DATA 0x00000000 +#define DDRSS3_CTL_377_DATA 0x00010000 +#define DDRSS3_CTL_378_DATA 0x00000404 +#define DDRSS3_CTL_379_DATA 0x00000000 +#define DDRSS3_CTL_380_DATA 0x00000000 +#define DDRSS3_CTL_381_DATA 0x00000000 +#define DDRSS3_CTL_382_DATA 0x00000000 +#define DDRSS3_CTL_383_DATA 0x00000000 +#define DDRSS3_CTL_384_DATA 0x00000000 +#define DDRSS3_CTL_385_DATA 0x00000000 +#define DDRSS3_CTL_386_DATA 0x00000000 +#define DDRSS3_CTL_387_DATA 0x3A3A1B00 +#define DDRSS3_CTL_388_DATA 0x000A0000 +#define DDRSS3_CTL_389_DATA 0x000000C6 +#define DDRSS3_CTL_390_DATA 0x00000200 +#define DDRSS3_CTL_391_DATA 0x00000200 +#define DDRSS3_CTL_392_DATA 0x00000200 +#define DDRSS3_CTL_393_DATA 0x00000200 +#define DDRSS3_CTL_394_DATA 0x00000270 +#define DDRSS3_CTL_395_DATA 0x000007BC +#define DDRSS3_CTL_396_DATA 0x00000204 +#define DDRSS3_CTL_397_DATA 0x0000206A +#define DDRSS3_CTL_398_DATA 0x00000200 +#define DDRSS3_CTL_399_DATA 0x00000200 +#define DDRSS3_CTL_400_DATA 0x00000200 +#define DDRSS3_CTL_401_DATA 0x00000200 +#define DDRSS3_CTL_402_DATA 0x0000613E +#define DDRSS3_CTL_403_DATA 0x00014424 +#define DDRSS3_CTL_404_DATA 0x00000E19 +#define DDRSS3_CTL_405_DATA 0x0000206A +#define DDRSS3_CTL_406_DATA 0x00000200 +#define DDRSS3_CTL_407_DATA 0x00000200 +#define DDRSS3_CTL_408_DATA 0x00000200 +#define DDRSS3_CTL_409_DATA 0x00000200 +#define DDRSS3_CTL_410_DATA 0x0000613E +#define DDRSS3_CTL_411_DATA 0x00014424 +#define DDRSS3_CTL_412_DATA 0x02020E19 +#define DDRSS3_CTL_413_DATA 0x03030202 +#define DDRSS3_CTL_414_DATA 0x00000022 +#define DDRSS3_CTL_415_DATA 0x00000000 +#define DDRSS3_CTL_416_DATA 0x00000000 +#define DDRSS3_CTL_417_DATA 0x00001403 +#define DDRSS3_CTL_418_DATA 0x000007D0 +#define DDRSS3_CTL_419_DATA 0x00000000 +#define DDRSS3_CTL_420_DATA 0x00000000 +#define DDRSS3_CTL_421_DATA 0x00030000 +#define DDRSS3_CTL_422_DATA 0x0007001F +#define DDRSS3_CTL_423_DATA 0x001B0033 +#define DDRSS3_CTL_424_DATA 0x001B0033 +#define DDRSS3_CTL_425_DATA 0x00000000 +#define DDRSS3_CTL_426_DATA 0x00000000 +#define DDRSS3_CTL_427_DATA 0x02000000 +#define DDRSS3_CTL_428_DATA 0x01000404 +#define DDRSS3_CTL_429_DATA 0x0B220B22 +#define DDRSS3_CTL_430_DATA 0x00000105 +#define DDRSS3_CTL_431_DATA 0x00010101 +#define DDRSS3_CTL_432_DATA 0x00010101 +#define DDRSS3_CTL_433_DATA 0x00010001 +#define DDRSS3_CTL_434_DATA 0x00000101 +#define DDRSS3_CTL_435_DATA 0x02000201 +#define DDRSS3_CTL_436_DATA 0x02010000 +#define DDRSS3_CTL_437_DATA 0x00000200 +#define DDRSS3_CTL_438_DATA 0x28060000 +#define DDRSS3_CTL_439_DATA 0x00000128 +#define DDRSS3_CTL_440_DATA 0xFFFFFFFF +#define DDRSS3_CTL_441_DATA 0xFFFFFFFF +#define DDRSS3_CTL_442_DATA 0x00000000 +#define DDRSS3_CTL_443_DATA 0x00000000 +#define DDRSS3_CTL_444_DATA 0x00000000 +#define DDRSS3_CTL_445_DATA 0x00000000 +#define DDRSS3_CTL_446_DATA 0x00000000 +#define DDRSS3_CTL_447_DATA 0x00000000 +#define DDRSS3_CTL_448_DATA 0x00000000 +#define DDRSS3_CTL_449_DATA 0x00000000 +#define DDRSS3_CTL_450_DATA 0x00000000 +#define DDRSS3_CTL_451_DATA 0x00000000 +#define DDRSS3_CTL_452_DATA 0x00000000 +#define DDRSS3_CTL_453_DATA 0x00000000 +#define DDRSS3_CTL_454_DATA 0x00000000 +#define DDRSS3_CTL_455_DATA 0x00000000 +#define DDRSS3_CTL_456_DATA 0x00000000 +#define DDRSS3_CTL_457_DATA 0x00000000 +#define DDRSS3_CTL_458_DATA 0x00000000 + +#define DDRSS3_PI_00_DATA 0x00000B00 +#define DDRSS3_PI_01_DATA 0x00000000 +#define DDRSS3_PI_02_DATA 0x00000000 +#define DDRSS3_PI_03_DATA 0x00000000 +#define DDRSS3_PI_04_DATA 0x00000000 +#define DDRSS3_PI_05_DATA 0x00000101 +#define DDRSS3_PI_06_DATA 0x00640000 +#define DDRSS3_PI_07_DATA 0x00000001 +#define DDRSS3_PI_08_DATA 0x00000000 +#define DDRSS3_PI_09_DATA 0x00000000 +#define DDRSS3_PI_10_DATA 0x00000000 +#define DDRSS3_PI_11_DATA 0x00000000 +#define DDRSS3_PI_12_DATA 0x00000003 +#define DDRSS3_PI_13_DATA 0x00010001 +#define DDRSS3_PI_14_DATA 0x0800000F +#define DDRSS3_PI_15_DATA 0x00000103 +#define DDRSS3_PI_16_DATA 0x00000005 +#define DDRSS3_PI_17_DATA 0x00000000 +#define DDRSS3_PI_18_DATA 0x00000000 +#define DDRSS3_PI_19_DATA 0x00000000 +#define DDRSS3_PI_20_DATA 0x00000000 +#define DDRSS3_PI_21_DATA 0x00000000 +#define DDRSS3_PI_22_DATA 0x00000000 +#define DDRSS3_PI_23_DATA 0x00000000 +#define DDRSS3_PI_24_DATA 0x00000000 +#define DDRSS3_PI_25_DATA 0x00000000 +#define DDRSS3_PI_26_DATA 0x00010100 +#define DDRSS3_PI_27_DATA 0x00280A00 +#define DDRSS3_PI_28_DATA 0x00000000 +#define DDRSS3_PI_29_DATA 0x0F000000 +#define DDRSS3_PI_30_DATA 0x00003200 +#define DDRSS3_PI_31_DATA 0x00000000 +#define DDRSS3_PI_32_DATA 0x00000000 +#define DDRSS3_PI_33_DATA 0x01010102 +#define DDRSS3_PI_34_DATA 0x00000000 +#define DDRSS3_PI_35_DATA 0x000000AA +#define DDRSS3_PI_36_DATA 0x00000055 +#define DDRSS3_PI_37_DATA 0x000000B5 +#define DDRSS3_PI_38_DATA 0x0000004A +#define DDRSS3_PI_39_DATA 0x00000056 +#define DDRSS3_PI_40_DATA 0x000000A9 +#define DDRSS3_PI_41_DATA 0x000000A9 +#define DDRSS3_PI_42_DATA 0x000000B5 +#define DDRSS3_PI_43_DATA 0x00000000 +#define DDRSS3_PI_44_DATA 0x00000000 +#define DDRSS3_PI_45_DATA 0x000F0F00 +#define DDRSS3_PI_46_DATA 0x0000001B +#define DDRSS3_PI_47_DATA 0x000007D0 +#define DDRSS3_PI_48_DATA 0x00000300 +#define DDRSS3_PI_49_DATA 0x00000000 +#define DDRSS3_PI_50_DATA 0x00000000 +#define DDRSS3_PI_51_DATA 0x01000000 +#define DDRSS3_PI_52_DATA 0x00010101 +#define DDRSS3_PI_53_DATA 0x00000000 +#define DDRSS3_PI_54_DATA 0x00030000 +#define DDRSS3_PI_55_DATA 0x0F000000 +#define DDRSS3_PI_56_DATA 0x00000017 +#define DDRSS3_PI_57_DATA 0x00000000 +#define DDRSS3_PI_58_DATA 0x00000000 +#define DDRSS3_PI_59_DATA 0x00000000 +#define DDRSS3_PI_60_DATA 0x0A0A140A +#define DDRSS3_PI_61_DATA 0x10020201 +#define DDRSS3_PI_62_DATA 0x00020805 +#define DDRSS3_PI_63_DATA 0x01000404 +#define DDRSS3_PI_64_DATA 0x00000000 +#define DDRSS3_PI_65_DATA 0x00000000 +#define DDRSS3_PI_66_DATA 0x00000100 +#define DDRSS3_PI_67_DATA 0x0002020F +#define DDRSS3_PI_68_DATA 0x00340000 +#define DDRSS3_PI_69_DATA 0x00000000 +#define DDRSS3_PI_70_DATA 0x00000000 +#define DDRSS3_PI_71_DATA 0x0000FFFF +#define DDRSS3_PI_72_DATA 0x01000000 +#define DDRSS3_PI_73_DATA 0x00080000 +#define DDRSS3_PI_74_DATA 0x02000200 +#define DDRSS3_PI_75_DATA 0x01000100 +#define DDRSS3_PI_76_DATA 0x01000000 +#define DDRSS3_PI_77_DATA 0x02000200 +#define DDRSS3_PI_78_DATA 0x00000200 +#define DDRSS3_PI_79_DATA 0x00000000 +#define DDRSS3_PI_80_DATA 0x00000000 +#define DDRSS3_PI_81_DATA 0x00000000 +#define DDRSS3_PI_82_DATA 0x00000000 +#define DDRSS3_PI_83_DATA 0x00000000 +#define DDRSS3_PI_84_DATA 0x00000000 +#define DDRSS3_PI_85_DATA 0x00000000 +#define DDRSS3_PI_86_DATA 0x00000000 +#define DDRSS3_PI_87_DATA 0x00000000 +#define DDRSS3_PI_88_DATA 0x00000000 +#define DDRSS3_PI_89_DATA 0x00000000 +#define DDRSS3_PI_90_DATA 0x00000000 +#define DDRSS3_PI_91_DATA 0x00000400 +#define DDRSS3_PI_92_DATA 0x02010000 +#define DDRSS3_PI_93_DATA 0x00080003 +#define DDRSS3_PI_94_DATA 0x00080000 +#define DDRSS3_PI_95_DATA 0x00000001 +#define DDRSS3_PI_96_DATA 0x00000000 +#define DDRSS3_PI_97_DATA 0x0000AA00 +#define DDRSS3_PI_98_DATA 0x00000000 +#define DDRSS3_PI_99_DATA 0x00000000 +#define DDRSS3_PI_100_DATA 0x00010000 +#define DDRSS3_PI_101_DATA 0x00000000 +#define DDRSS3_PI_102_DATA 0x00000000 +#define DDRSS3_PI_103_DATA 0x00000000 +#define DDRSS3_PI_104_DATA 0x00000000 +#define DDRSS3_PI_105_DATA 0x00000000 +#define DDRSS3_PI_106_DATA 0x00000000 +#define DDRSS3_PI_107_DATA 0x00000000 +#define DDRSS3_PI_108_DATA 0x00000000 +#define DDRSS3_PI_109_DATA 0x00000000 +#define DDRSS3_PI_110_DATA 0x00000000 +#define DDRSS3_PI_111_DATA 0x00000000 +#define DDRSS3_PI_112_DATA 0x00000000 +#define DDRSS3_PI_113_DATA 0x00000000 +#define DDRSS3_PI_114_DATA 0x00000000 +#define DDRSS3_PI_115_DATA 0x00000000 +#define DDRSS3_PI_116_DATA 0x00000000 +#define DDRSS3_PI_117_DATA 0x00000000 +#define DDRSS3_PI_118_DATA 0x00000000 +#define DDRSS3_PI_119_DATA 0x00000000 +#define DDRSS3_PI_120_DATA 0x00000000 +#define DDRSS3_PI_121_DATA 0x00000000 +#define DDRSS3_PI_122_DATA 0x00000000 +#define DDRSS3_PI_123_DATA 0x00000000 +#define DDRSS3_PI_124_DATA 0x00000000 +#define DDRSS3_PI_125_DATA 0x00000008 +#define DDRSS3_PI_126_DATA 0x00000000 +#define DDRSS3_PI_127_DATA 0x00000000 +#define DDRSS3_PI_128_DATA 0x00000000 +#define DDRSS3_PI_129_DATA 0x00000000 +#define DDRSS3_PI_130_DATA 0x00000000 +#define DDRSS3_PI_131_DATA 0x00000000 +#define DDRSS3_PI_132_DATA 0x00000000 +#define DDRSS3_PI_133_DATA 0x00000000 +#define DDRSS3_PI_134_DATA 0x00000002 +#define DDRSS3_PI_135_DATA 0x00000000 +#define DDRSS3_PI_136_DATA 0x00000000 +#define DDRSS3_PI_137_DATA 0x0000000A +#define DDRSS3_PI_138_DATA 0x00000019 +#define DDRSS3_PI_139_DATA 0x00000100 +#define DDRSS3_PI_140_DATA 0x00000000 +#define DDRSS3_PI_141_DATA 0x00000000 +#define DDRSS3_PI_142_DATA 0x00000000 +#define DDRSS3_PI_143_DATA 0x00000000 +#define DDRSS3_PI_144_DATA 0x01000000 +#define DDRSS3_PI_145_DATA 0x00010003 +#define DDRSS3_PI_146_DATA 0x02000101 +#define DDRSS3_PI_147_DATA 0x01030001 +#define DDRSS3_PI_148_DATA 0x00010400 +#define DDRSS3_PI_149_DATA 0x06000105 +#define DDRSS3_PI_150_DATA 0x01070001 +#define DDRSS3_PI_151_DATA 0x00000000 +#define DDRSS3_PI_152_DATA 0x00000000 +#define DDRSS3_PI_153_DATA 0x00000000 +#define DDRSS3_PI_154_DATA 0x00010001 +#define DDRSS3_PI_155_DATA 0x00000000 +#define DDRSS3_PI_156_DATA 0x00000000 +#define DDRSS3_PI_157_DATA 0x00000000 +#define DDRSS3_PI_158_DATA 0x00000000 +#define DDRSS3_PI_159_DATA 0x00000401 +#define DDRSS3_PI_160_DATA 0x00000000 +#define DDRSS3_PI_161_DATA 0x05010000 +#define DDRSS3_PI_162_DATA 0x00000001 +#define DDRSS3_PI_163_DATA 0x2B2B0201 +#define DDRSS3_PI_164_DATA 0x00000034 +#define DDRSS3_PI_165_DATA 0x00000068 +#define DDRSS3_PI_166_DATA 0x00020068 +#define DDRSS3_PI_167_DATA 0x02000200 +#define DDRSS3_PI_168_DATA 0x50120C04 +#define DDRSS3_PI_169_DATA 0x00155012 +#define DDRSS3_PI_170_DATA 0x00000068 +#define DDRSS3_PI_171_DATA 0x0000032B +#define DDRSS3_PI_172_DATA 0x00001035 +#define DDRSS3_PI_173_DATA 0x0000032B +#define DDRSS3_PI_174_DATA 0x04001035 +#define DDRSS3_PI_175_DATA 0x01010404 +#define DDRSS3_PI_176_DATA 0x00001500 +#define DDRSS3_PI_177_DATA 0x00150015 +#define DDRSS3_PI_178_DATA 0x01000100 +#define DDRSS3_PI_179_DATA 0x00000100 +#define DDRSS3_PI_180_DATA 0x00000000 +#define DDRSS3_PI_181_DATA 0x01010101 +#define DDRSS3_PI_182_DATA 0x00000000 +#define DDRSS3_PI_183_DATA 0x00000000 +#define DDRSS3_PI_184_DATA 0x00000000 +#define DDRSS3_PI_185_DATA 0x19040000 +#define DDRSS3_PI_186_DATA 0x0E0E0219 +#define DDRSS3_PI_187_DATA 0x00040402 +#define DDRSS3_PI_188_DATA 0x000D0035 +#define DDRSS3_PI_189_DATA 0x00218049 +#define DDRSS3_PI_190_DATA 0x00218049 +#define DDRSS3_PI_191_DATA 0x01000101 +#define DDRSS3_PI_192_DATA 0x0004000E +#define DDRSS3_PI_193_DATA 0x00040216 +#define DDRSS3_PI_194_DATA 0x01000216 +#define DDRSS3_PI_195_DATA 0x000F000F +#define DDRSS3_PI_196_DATA 0x02170100 +#define DDRSS3_PI_197_DATA 0x01000217 +#define DDRSS3_PI_198_DATA 0x02170217 +#define DDRSS3_PI_199_DATA 0x2F1B3200 +#define DDRSS3_PI_200_DATA 0x01012F1B +#define DDRSS3_PI_201_DATA 0x0A070601 +#define DDRSS3_PI_202_DATA 0x1F130A0D +#define DDRSS3_PI_203_DATA 0x1F130A14 +#define DDRSS3_PI_204_DATA 0x0000C014 +#define DDRSS3_PI_205_DATA 0x00C01000 +#define DDRSS3_PI_206_DATA 0x00C01000 +#define DDRSS3_PI_207_DATA 0x00021000 +#define DDRSS3_PI_208_DATA 0x0024000E +#define DDRSS3_PI_209_DATA 0x00240216 +#define DDRSS3_PI_210_DATA 0x00110216 +#define DDRSS3_PI_211_DATA 0x32000056 +#define DDRSS3_PI_212_DATA 0x00000101 +#define DDRSS3_PI_213_DATA 0x005F0036 +#define DDRSS3_PI_214_DATA 0x03013212 +#define DDRSS3_PI_215_DATA 0x00003600 +#define DDRSS3_PI_216_DATA 0x3212005F +#define DDRSS3_PI_217_DATA 0x09000001 +#define DDRSS3_PI_218_DATA 0x06010504 +#define DDRSS3_PI_219_DATA 0x04000364 +#define DDRSS3_PI_220_DATA 0x0A032001 +#define DDRSS3_PI_221_DATA 0x2C31110A +#define DDRSS3_PI_222_DATA 0x00002918 +#define DDRSS3_PI_223_DATA 0x6000838E +#define DDRSS3_PI_224_DATA 0x1E202008 +#define DDRSS3_PI_225_DATA 0x2C311116 +#define DDRSS3_PI_226_DATA 0x00002918 +#define DDRSS3_PI_227_DATA 0x6000838E +#define DDRSS3_PI_228_DATA 0x1E202008 +#define DDRSS3_PI_229_DATA 0x0000C616 +#define DDRSS3_PI_230_DATA 0x000007BC +#define DDRSS3_PI_231_DATA 0x0000206A +#define DDRSS3_PI_232_DATA 0x00014424 +#define DDRSS3_PI_233_DATA 0x0000206A +#define DDRSS3_PI_234_DATA 0x00014424 +#define DDRSS3_PI_235_DATA 0x033B0016 +#define DDRSS3_PI_236_DATA 0x0303033B +#define DDRSS3_PI_237_DATA 0x002AF803 +#define DDRSS3_PI_238_DATA 0x0001ADAF +#define DDRSS3_PI_239_DATA 0x00000005 +#define DDRSS3_PI_240_DATA 0x0000006E +#define DDRSS3_PI_241_DATA 0x00000016 +#define DDRSS3_PI_242_DATA 0x000681C8 +#define DDRSS3_PI_243_DATA 0x0001ADAF +#define DDRSS3_PI_244_DATA 0x00000005 +#define DDRSS3_PI_245_DATA 0x000010A9 +#define DDRSS3_PI_246_DATA 0x0000033B +#define DDRSS3_PI_247_DATA 0x000681C8 +#define DDRSS3_PI_248_DATA 0x0001ADAF +#define DDRSS3_PI_249_DATA 0x00000005 +#define DDRSS3_PI_250_DATA 0x000010A9 +#define DDRSS3_PI_251_DATA 0x0100033B +#define DDRSS3_PI_252_DATA 0x00370040 +#define DDRSS3_PI_253_DATA 0x00010008 +#define DDRSS3_PI_254_DATA 0x08550040 +#define DDRSS3_PI_255_DATA 0x00010040 +#define DDRSS3_PI_256_DATA 0x08550040 +#define DDRSS3_PI_257_DATA 0x00000340 +#define DDRSS3_PI_258_DATA 0x006B006B +#define DDRSS3_PI_259_DATA 0x08040404 +#define DDRSS3_PI_260_DATA 0x00000055 +#define DDRSS3_PI_261_DATA 0x55083C5A +#define DDRSS3_PI_262_DATA 0x5A000000 +#define DDRSS3_PI_263_DATA 0x0055083C +#define DDRSS3_PI_264_DATA 0x3C5A0000 +#define DDRSS3_PI_265_DATA 0x00005508 +#define DDRSS3_PI_266_DATA 0x0C3C5A00 +#define DDRSS3_PI_267_DATA 0x080F0E0D +#define DDRSS3_PI_268_DATA 0x000B0A09 +#define DDRSS3_PI_269_DATA 0x00030201 +#define DDRSS3_PI_270_DATA 0x01000000 +#define DDRSS3_PI_271_DATA 0x04020201 +#define DDRSS3_PI_272_DATA 0x00080804 +#define DDRSS3_PI_273_DATA 0x00000000 +#define DDRSS3_PI_274_DATA 0x00000000 +#define DDRSS3_PI_275_DATA 0x35F30084 +#define DDRSS3_PI_276_DATA 0x00160000 +#define DDRSS3_PI_277_DATA 0x35F33FF4 +#define DDRSS3_PI_278_DATA 0x00160F27 +#define DDRSS3_PI_279_DATA 0x35F33FF4 +#define DDRSS3_PI_280_DATA 0x00160F27 +#define DDRSS3_PI_281_DATA 0x35F30084 +#define DDRSS3_PI_282_DATA 0x00160000 +#define DDRSS3_PI_283_DATA 0x35F33FF4 +#define DDRSS3_PI_284_DATA 0x00160F27 +#define DDRSS3_PI_285_DATA 0x35F33FF4 +#define DDRSS3_PI_286_DATA 0x00160F27 +#define DDRSS3_PI_287_DATA 0x35F30084 +#define DDRSS3_PI_288_DATA 0x00160000 +#define DDRSS3_PI_289_DATA 0x35F33FF4 +#define DDRSS3_PI_290_DATA 0x00160F27 +#define DDRSS3_PI_291_DATA 0x35F33FF4 +#define DDRSS3_PI_292_DATA 0x00160F27 +#define DDRSS3_PI_293_DATA 0x35F30084 +#define DDRSS3_PI_294_DATA 0x00160000 +#define DDRSS3_PI_295_DATA 0x35F33FF4 +#define DDRSS3_PI_296_DATA 0x00160F27 +#define DDRSS3_PI_297_DATA 0x35F33FF4 +#define DDRSS3_PI_298_DATA 0x00160F27 +#define DDRSS3_PI_299_DATA 0x00000000 + +#define DDRSS3_PHY_00_DATA 0x000004F0 +#define DDRSS3_PHY_01_DATA 0x00000000 +#define DDRSS3_PHY_02_DATA 0x00030200 +#define DDRSS3_PHY_03_DATA 0x00000000 +#define DDRSS3_PHY_04_DATA 0x00000000 +#define DDRSS3_PHY_05_DATA 0x01030000 +#define DDRSS3_PHY_06_DATA 0x00010000 +#define DDRSS3_PHY_07_DATA 0x01030004 +#define DDRSS3_PHY_08_DATA 0x01000000 +#define DDRSS3_PHY_09_DATA 0x00000000 +#define DDRSS3_PHY_10_DATA 0x00000000 +#define DDRSS3_PHY_11_DATA 0x01000001 +#define DDRSS3_PHY_12_DATA 0x00000200 +#define DDRSS3_PHY_13_DATA 0x000800C0 +#define DDRSS3_PHY_14_DATA 0x060100CC +#define DDRSS3_PHY_15_DATA 0x00030066 +#define DDRSS3_PHY_16_DATA 0x00000000 +#define DDRSS3_PHY_17_DATA 0x00000301 +#define DDRSS3_PHY_18_DATA 0x0000AAAA +#define DDRSS3_PHY_19_DATA 0x00005555 +#define DDRSS3_PHY_20_DATA 0x0000B5B5 +#define DDRSS3_PHY_21_DATA 0x00004A4A +#define DDRSS3_PHY_22_DATA 0x00005656 +#define DDRSS3_PHY_23_DATA 0x0000A9A9 +#define DDRSS3_PHY_24_DATA 0x0000A9A9 +#define DDRSS3_PHY_25_DATA 0x0000B5B5 +#define DDRSS3_PHY_26_DATA 0x00000000 +#define DDRSS3_PHY_27_DATA 0x00000000 +#define DDRSS3_PHY_28_DATA 0x2A000000 +#define DDRSS3_PHY_29_DATA 0x00000808 +#define DDRSS3_PHY_30_DATA 0x0F000000 +#define DDRSS3_PHY_31_DATA 0x00000F08 +#define DDRSS3_PHY_32_DATA 0x10400000 +#define DDRSS3_PHY_33_DATA 0x0C002006 +#define DDRSS3_PHY_34_DATA 0x00000000 +#define DDRSS3_PHY_35_DATA 0x00000000 +#define DDRSS3_PHY_36_DATA 0x55555555 +#define DDRSS3_PHY_37_DATA 0xAAAAAAAA +#define DDRSS3_PHY_38_DATA 0x55555555 +#define DDRSS3_PHY_39_DATA 0xAAAAAAAA +#define DDRSS3_PHY_40_DATA 0x00005555 +#define DDRSS3_PHY_41_DATA 0x01000100 +#define DDRSS3_PHY_42_DATA 0x00800180 +#define DDRSS3_PHY_43_DATA 0x00000001 +#define DDRSS3_PHY_44_DATA 0x00000000 +#define DDRSS3_PHY_45_DATA 0x00000000 +#define DDRSS3_PHY_46_DATA 0x00000000 +#define DDRSS3_PHY_47_DATA 0x00000000 +#define DDRSS3_PHY_48_DATA 0x00000000 +#define DDRSS3_PHY_49_DATA 0x00000000 +#define DDRSS3_PHY_50_DATA 0x00000000 +#define DDRSS3_PHY_51_DATA 0x00000000 +#define DDRSS3_PHY_52_DATA 0x00000000 +#define DDRSS3_PHY_53_DATA 0x00000000 +#define DDRSS3_PHY_54_DATA 0x00000000 +#define DDRSS3_PHY_55_DATA 0x00000000 +#define DDRSS3_PHY_56_DATA 0x00000000 +#define DDRSS3_PHY_57_DATA 0x00000000 +#define DDRSS3_PHY_58_DATA 0x00000000 +#define DDRSS3_PHY_59_DATA 0x00000000 +#define DDRSS3_PHY_60_DATA 0x00000000 +#define DDRSS3_PHY_61_DATA 0x00000000 +#define DDRSS3_PHY_62_DATA 0x00000000 +#define DDRSS3_PHY_63_DATA 0x00000000 +#define DDRSS3_PHY_64_DATA 0x00000000 +#define DDRSS3_PHY_65_DATA 0x00000000 +#define DDRSS3_PHY_66_DATA 0x00000104 +#define DDRSS3_PHY_67_DATA 0x00000120 +#define DDRSS3_PHY_68_DATA 0x00000000 +#define DDRSS3_PHY_69_DATA 0x00000000 +#define DDRSS3_PHY_70_DATA 0x00000000 +#define DDRSS3_PHY_71_DATA 0x00000000 +#define DDRSS3_PHY_72_DATA 0x00000000 +#define DDRSS3_PHY_73_DATA 0x00000000 +#define DDRSS3_PHY_74_DATA 0x00000000 +#define DDRSS3_PHY_75_DATA 0x00000001 +#define DDRSS3_PHY_76_DATA 0x07FF0000 +#define DDRSS3_PHY_77_DATA 0x0080081F +#define DDRSS3_PHY_78_DATA 0x00081020 +#define DDRSS3_PHY_79_DATA 0x04010000 +#define DDRSS3_PHY_80_DATA 0x00000000 +#define DDRSS3_PHY_81_DATA 0x00000000 +#define DDRSS3_PHY_82_DATA 0x00000000 +#define DDRSS3_PHY_83_DATA 0x00000100 +#define DDRSS3_PHY_84_DATA 0x01CC0C01 +#define DDRSS3_PHY_85_DATA 0x1003CC0C +#define DDRSS3_PHY_86_DATA 0x20000140 +#define DDRSS3_PHY_87_DATA 0x07FF0200 +#define DDRSS3_PHY_88_DATA 0x0000DD01 +#define DDRSS3_PHY_89_DATA 0x10100303 +#define DDRSS3_PHY_90_DATA 0x10101010 +#define DDRSS3_PHY_91_DATA 0x10101010 +#define DDRSS3_PHY_92_DATA 0x00021010 +#define DDRSS3_PHY_93_DATA 0x00100010 +#define DDRSS3_PHY_94_DATA 0x00100010 +#define DDRSS3_PHY_95_DATA 0x00100010 +#define DDRSS3_PHY_96_DATA 0x00100010 +#define DDRSS3_PHY_97_DATA 0x00050010 +#define DDRSS3_PHY_98_DATA 0x51517041 +#define DDRSS3_PHY_99_DATA 0x31C06001 +#define DDRSS3_PHY_100_DATA 0x07AB01AB +#define DDRSS3_PHY_101_DATA 0x00C0C001 +#define DDRSS3_PHY_102_DATA 0x0E0D0101 +#define DDRSS3_PHY_103_DATA 0x10001000 +#define DDRSS3_PHY_104_DATA 0x0C083E42 +#define DDRSS3_PHY_105_DATA 0x0F0C3701 +#define DDRSS3_PHY_106_DATA 0x01000140 +#define DDRSS3_PHY_107_DATA 0x0C000420 +#define DDRSS3_PHY_108_DATA 0x00000198 +#define DDRSS3_PHY_109_DATA 0x0A0000D0 +#define DDRSS3_PHY_110_DATA 0x00030200 +#define DDRSS3_PHY_111_DATA 0x02800000 +#define DDRSS3_PHY_112_DATA 0x80800000 +#define DDRSS3_PHY_113_DATA 0x000E2010 +#define DDRSS3_PHY_114_DATA 0x76543210 +#define DDRSS3_PHY_115_DATA 0x00000008 +#define DDRSS3_PHY_116_DATA 0x02800280 +#define DDRSS3_PHY_117_DATA 0x02800280 +#define DDRSS3_PHY_118_DATA 0x02800280 +#define DDRSS3_PHY_119_DATA 0x02800280 +#define DDRSS3_PHY_120_DATA 0x00000280 +#define DDRSS3_PHY_121_DATA 0x0000A000 +#define DDRSS3_PHY_122_DATA 0x00A000A0 +#define DDRSS3_PHY_123_DATA 0x00A000A0 +#define DDRSS3_PHY_124_DATA 0x00A000A0 +#define DDRSS3_PHY_125_DATA 0x00A000A0 +#define DDRSS3_PHY_126_DATA 0x00A000A0 +#define DDRSS3_PHY_127_DATA 0x00A000A0 +#define DDRSS3_PHY_128_DATA 0x00A000A0 +#define DDRSS3_PHY_129_DATA 0x00A000A0 +#define DDRSS3_PHY_130_DATA 0x01C200A0 +#define DDRSS3_PHY_131_DATA 0x01A00005 +#define DDRSS3_PHY_132_DATA 0x00000000 +#define DDRSS3_PHY_133_DATA 0x00000000 +#define DDRSS3_PHY_134_DATA 0x00080200 +#define DDRSS3_PHY_135_DATA 0x00000000 +#define DDRSS3_PHY_136_DATA 0x20202000 +#define DDRSS3_PHY_137_DATA 0x20202020 +#define DDRSS3_PHY_138_DATA 0xF0F02020 +#define DDRSS3_PHY_139_DATA 0x00000000 +#define DDRSS3_PHY_140_DATA 0x00000000 +#define DDRSS3_PHY_141_DATA 0x00000000 +#define DDRSS3_PHY_142_DATA 0x00000000 +#define DDRSS3_PHY_143_DATA 0x00000000 +#define DDRSS3_PHY_144_DATA 0x00000000 +#define DDRSS3_PHY_145_DATA 0x00000000 +#define DDRSS3_PHY_146_DATA 0x00000000 +#define DDRSS3_PHY_147_DATA 0x00000000 +#define DDRSS3_PHY_148_DATA 0x00000000 +#define DDRSS3_PHY_149_DATA 0x00000000 +#define DDRSS3_PHY_150_DATA 0x00000000 +#define DDRSS3_PHY_151_DATA 0x00000000 +#define DDRSS3_PHY_152_DATA 0x00000000 +#define DDRSS3_PHY_153_DATA 0x00000000 +#define DDRSS3_PHY_154_DATA 0x00000000 +#define DDRSS3_PHY_155_DATA 0x00000000 +#define DDRSS3_PHY_156_DATA 0x00000000 +#define DDRSS3_PHY_157_DATA 0x00000000 +#define DDRSS3_PHY_158_DATA 0x00000000 +#define DDRSS3_PHY_159_DATA 0x00000000 +#define DDRSS3_PHY_160_DATA 0x00000000 +#define DDRSS3_PHY_161_DATA 0x00000000 +#define DDRSS3_PHY_162_DATA 0x00000000 +#define DDRSS3_PHY_163_DATA 0x00000000 +#define DDRSS3_PHY_164_DATA 0x00000000 +#define DDRSS3_PHY_165_DATA 0x00000000 +#define DDRSS3_PHY_166_DATA 0x00000000 +#define DDRSS3_PHY_167_DATA 0x00000000 +#define DDRSS3_PHY_168_DATA 0x00000000 +#define DDRSS3_PHY_169_DATA 0x00000000 +#define DDRSS3_PHY_170_DATA 0x00000000 +#define DDRSS3_PHY_171_DATA 0x00000000 +#define DDRSS3_PHY_172_DATA 0x00000000 +#define DDRSS3_PHY_173_DATA 0x00000000 +#define DDRSS3_PHY_174_DATA 0x00000000 +#define DDRSS3_PHY_175_DATA 0x00000000 +#define DDRSS3_PHY_176_DATA 0x00000000 +#define DDRSS3_PHY_177_DATA 0x00000000 +#define DDRSS3_PHY_178_DATA 0x00000000 +#define DDRSS3_PHY_179_DATA 0x00000000 +#define DDRSS3_PHY_180_DATA 0x00000000 +#define DDRSS3_PHY_181_DATA 0x00000000 +#define DDRSS3_PHY_182_DATA 0x00000000 +#define DDRSS3_PHY_183_DATA 0x00000000 +#define DDRSS3_PHY_184_DATA 0x00000000 +#define DDRSS3_PHY_185_DATA 0x00000000 +#define DDRSS3_PHY_186_DATA 0x00000000 +#define DDRSS3_PHY_187_DATA 0x00000000 +#define DDRSS3_PHY_188_DATA 0x00000000 +#define DDRSS3_PHY_189_DATA 0x00000000 +#define DDRSS3_PHY_190_DATA 0x00000000 +#define DDRSS3_PHY_191_DATA 0x00000000 +#define DDRSS3_PHY_192_DATA 0x00000000 +#define DDRSS3_PHY_193_DATA 0x00000000 +#define DDRSS3_PHY_194_DATA 0x00000000 +#define DDRSS3_PHY_195_DATA 0x00000000 +#define DDRSS3_PHY_196_DATA 0x00000000 +#define DDRSS3_PHY_197_DATA 0x00000000 +#define DDRSS3_PHY_198_DATA 0x00000000 +#define DDRSS3_PHY_199_DATA 0x00000000 +#define DDRSS3_PHY_200_DATA 0x00000000 +#define DDRSS3_PHY_201_DATA 0x00000000 +#define DDRSS3_PHY_202_DATA 0x00000000 +#define DDRSS3_PHY_203_DATA 0x00000000 +#define DDRSS3_PHY_204_DATA 0x00000000 +#define DDRSS3_PHY_205_DATA 0x00000000 +#define DDRSS3_PHY_206_DATA 0x00000000 +#define DDRSS3_PHY_207_DATA 0x00000000 +#define DDRSS3_PHY_208_DATA 0x00000000 +#define DDRSS3_PHY_209_DATA 0x00000000 +#define DDRSS3_PHY_210_DATA 0x00000000 +#define DDRSS3_PHY_211_DATA 0x00000000 +#define DDRSS3_PHY_212_DATA 0x00000000 +#define DDRSS3_PHY_213_DATA 0x00000000 +#define DDRSS3_PHY_214_DATA 0x00000000 +#define DDRSS3_PHY_215_DATA 0x00000000 +#define DDRSS3_PHY_216_DATA 0x00000000 +#define DDRSS3_PHY_217_DATA 0x00000000 +#define DDRSS3_PHY_218_DATA 0x00000000 +#define DDRSS3_PHY_219_DATA 0x00000000 +#define DDRSS3_PHY_220_DATA 0x00000000 +#define DDRSS3_PHY_221_DATA 0x00000000 +#define DDRSS3_PHY_222_DATA 0x00000000 +#define DDRSS3_PHY_223_DATA 0x00000000 +#define DDRSS3_PHY_224_DATA 0x00000000 +#define DDRSS3_PHY_225_DATA 0x00000000 +#define DDRSS3_PHY_226_DATA 0x00000000 +#define DDRSS3_PHY_227_DATA 0x00000000 +#define DDRSS3_PHY_228_DATA 0x00000000 +#define DDRSS3_PHY_229_DATA 0x00000000 +#define DDRSS3_PHY_230_DATA 0x00000000 +#define DDRSS3_PHY_231_DATA 0x00000000 +#define DDRSS3_PHY_232_DATA 0x00000000 +#define DDRSS3_PHY_233_DATA 0x00000000 +#define DDRSS3_PHY_234_DATA 0x00000000 +#define DDRSS3_PHY_235_DATA 0x00000000 +#define DDRSS3_PHY_236_DATA 0x00000000 +#define DDRSS3_PHY_237_DATA 0x00000000 +#define DDRSS3_PHY_238_DATA 0x00000000 +#define DDRSS3_PHY_239_DATA 0x00000000 +#define DDRSS3_PHY_240_DATA 0x00000000 +#define DDRSS3_PHY_241_DATA 0x00000000 +#define DDRSS3_PHY_242_DATA 0x00000000 +#define DDRSS3_PHY_243_DATA 0x00000000 +#define DDRSS3_PHY_244_DATA 0x00000000 +#define DDRSS3_PHY_245_DATA 0x00000000 +#define DDRSS3_PHY_246_DATA 0x00000000 +#define DDRSS3_PHY_247_DATA 0x00000000 +#define DDRSS3_PHY_248_DATA 0x00000000 +#define DDRSS3_PHY_249_DATA 0x00000000 +#define DDRSS3_PHY_250_DATA 0x00000000 +#define DDRSS3_PHY_251_DATA 0x00000000 +#define DDRSS3_PHY_252_DATA 0x00000000 +#define DDRSS3_PHY_253_DATA 0x00000000 +#define DDRSS3_PHY_254_DATA 0x00000000 +#define DDRSS3_PHY_255_DATA 0x00000000 +#define DDRSS3_PHY_256_DATA 0x000004F0 +#define DDRSS3_PHY_257_DATA 0x00000000 +#define DDRSS3_PHY_258_DATA 0x00030200 +#define DDRSS3_PHY_259_DATA 0x00000000 +#define DDRSS3_PHY_260_DATA 0x00000000 +#define DDRSS3_PHY_261_DATA 0x01030000 +#define DDRSS3_PHY_262_DATA 0x00010000 +#define DDRSS3_PHY_263_DATA 0x01030004 +#define DDRSS3_PHY_264_DATA 0x01000000 +#define DDRSS3_PHY_265_DATA 0x00000000 +#define DDRSS3_PHY_266_DATA 0x00000000 +#define DDRSS3_PHY_267_DATA 0x01000001 +#define DDRSS3_PHY_268_DATA 0x00000200 +#define DDRSS3_PHY_269_DATA 0x000800C0 +#define DDRSS3_PHY_270_DATA 0x060100CC +#define DDRSS3_PHY_271_DATA 0x00030066 +#define DDRSS3_PHY_272_DATA 0x00000000 +#define DDRSS3_PHY_273_DATA 0x00000301 +#define DDRSS3_PHY_274_DATA 0x0000AAAA +#define DDRSS3_PHY_275_DATA 0x00005555 +#define DDRSS3_PHY_276_DATA 0x0000B5B5 +#define DDRSS3_PHY_277_DATA 0x00004A4A +#define DDRSS3_PHY_278_DATA 0x00005656 +#define DDRSS3_PHY_279_DATA 0x0000A9A9 +#define DDRSS3_PHY_280_DATA 0x0000A9A9 +#define DDRSS3_PHY_281_DATA 0x0000B5B5 +#define DDRSS3_PHY_282_DATA 0x00000000 +#define DDRSS3_PHY_283_DATA 0x00000000 +#define DDRSS3_PHY_284_DATA 0x2A000000 +#define DDRSS3_PHY_285_DATA 0x00000808 +#define DDRSS3_PHY_286_DATA 0x0F000000 +#define DDRSS3_PHY_287_DATA 0x00000F08 +#define DDRSS3_PHY_288_DATA 0x10400000 +#define DDRSS3_PHY_289_DATA 0x0C002006 +#define DDRSS3_PHY_290_DATA 0x00000000 +#define DDRSS3_PHY_291_DATA 0x00000000 +#define DDRSS3_PHY_292_DATA 0x55555555 +#define DDRSS3_PHY_293_DATA 0xAAAAAAAA +#define DDRSS3_PHY_294_DATA 0x55555555 +#define DDRSS3_PHY_295_DATA 0xAAAAAAAA +#define DDRSS3_PHY_296_DATA 0x00005555 +#define DDRSS3_PHY_297_DATA 0x01000100 +#define DDRSS3_PHY_298_DATA 0x00800180 +#define DDRSS3_PHY_299_DATA 0x00000000 +#define DDRSS3_PHY_300_DATA 0x00000000 +#define DDRSS3_PHY_301_DATA 0x00000000 +#define DDRSS3_PHY_302_DATA 0x00000000 +#define DDRSS3_PHY_303_DATA 0x00000000 +#define DDRSS3_PHY_304_DATA 0x00000000 +#define DDRSS3_PHY_305_DATA 0x00000000 +#define DDRSS3_PHY_306_DATA 0x00000000 +#define DDRSS3_PHY_307_DATA 0x00000000 +#define DDRSS3_PHY_308_DATA 0x00000000 +#define DDRSS3_PHY_309_DATA 0x00000000 +#define DDRSS3_PHY_310_DATA 0x00000000 +#define DDRSS3_PHY_311_DATA 0x00000000 +#define DDRSS3_PHY_312_DATA 0x00000000 +#define DDRSS3_PHY_313_DATA 0x00000000 +#define DDRSS3_PHY_314_DATA 0x00000000 +#define DDRSS3_PHY_315_DATA 0x00000000 +#define DDRSS3_PHY_316_DATA 0x00000000 +#define DDRSS3_PHY_317_DATA 0x00000000 +#define DDRSS3_PHY_318_DATA 0x00000000 +#define DDRSS3_PHY_319_DATA 0x00000000 +#define DDRSS3_PHY_320_DATA 0x00000000 +#define DDRSS3_PHY_321_DATA 0x00000000 +#define DDRSS3_PHY_322_DATA 0x00000104 +#define DDRSS3_PHY_323_DATA 0x00000120 +#define DDRSS3_PHY_324_DATA 0x00000000 +#define DDRSS3_PHY_325_DATA 0x00000000 +#define DDRSS3_PHY_326_DATA 0x00000000 +#define DDRSS3_PHY_327_DATA 0x00000000 +#define DDRSS3_PHY_328_DATA 0x00000000 +#define DDRSS3_PHY_329_DATA 0x00000000 +#define DDRSS3_PHY_330_DATA 0x00000000 +#define DDRSS3_PHY_331_DATA 0x00000001 +#define DDRSS3_PHY_332_DATA 0x07FF0000 +#define DDRSS3_PHY_333_DATA 0x0080081F +#define DDRSS3_PHY_334_DATA 0x00081020 +#define DDRSS3_PHY_335_DATA 0x04010000 +#define DDRSS3_PHY_336_DATA 0x00000000 +#define DDRSS3_PHY_337_DATA 0x00000000 +#define DDRSS3_PHY_338_DATA 0x00000000 +#define DDRSS3_PHY_339_DATA 0x00000100 +#define DDRSS3_PHY_340_DATA 0x01CC0C01 +#define DDRSS3_PHY_341_DATA 0x1003CC0C +#define DDRSS3_PHY_342_DATA 0x20000140 +#define DDRSS3_PHY_343_DATA 0x07FF0200 +#define DDRSS3_PHY_344_DATA 0x0000DD01 +#define DDRSS3_PHY_345_DATA 0x10100303 +#define DDRSS3_PHY_346_DATA 0x10101010 +#define DDRSS3_PHY_347_DATA 0x10101010 +#define DDRSS3_PHY_348_DATA 0x00021010 +#define DDRSS3_PHY_349_DATA 0x00100010 +#define DDRSS3_PHY_350_DATA 0x00100010 +#define DDRSS3_PHY_351_DATA 0x00100010 +#define DDRSS3_PHY_352_DATA 0x00100010 +#define DDRSS3_PHY_353_DATA 0x00050010 +#define DDRSS3_PHY_354_DATA 0x51517041 +#define DDRSS3_PHY_355_DATA 0x31C06001 +#define DDRSS3_PHY_356_DATA 0x07AB01AB +#define DDRSS3_PHY_357_DATA 0x00C0C001 +#define DDRSS3_PHY_358_DATA 0x0E0D0101 +#define DDRSS3_PHY_359_DATA 0x10001000 +#define DDRSS3_PHY_360_DATA 0x0C083E42 +#define DDRSS3_PHY_361_DATA 0x0F0C3701 +#define DDRSS3_PHY_362_DATA 0x01000140 +#define DDRSS3_PHY_363_DATA 0x0C000420 +#define DDRSS3_PHY_364_DATA 0x00000198 +#define DDRSS3_PHY_365_DATA 0x0A0000D0 +#define DDRSS3_PHY_366_DATA 0x00030200 +#define DDRSS3_PHY_367_DATA 0x02800000 +#define DDRSS3_PHY_368_DATA 0x80800000 +#define DDRSS3_PHY_369_DATA 0x000E2010 +#define DDRSS3_PHY_370_DATA 0x76543210 +#define DDRSS3_PHY_371_DATA 0x00000008 +#define DDRSS3_PHY_372_DATA 0x02800280 +#define DDRSS3_PHY_373_DATA 0x02800280 +#define DDRSS3_PHY_374_DATA 0x02800280 +#define DDRSS3_PHY_375_DATA 0x02800280 +#define DDRSS3_PHY_376_DATA 0x00000280 +#define DDRSS3_PHY_377_DATA 0x0000A000 +#define DDRSS3_PHY_378_DATA 0x00A000A0 +#define DDRSS3_PHY_379_DATA 0x00A000A0 +#define DDRSS3_PHY_380_DATA 0x00A000A0 +#define DDRSS3_PHY_381_DATA 0x00A000A0 +#define DDRSS3_PHY_382_DATA 0x00A000A0 +#define DDRSS3_PHY_383_DATA 0x00A000A0 +#define DDRSS3_PHY_384_DATA 0x00A000A0 +#define DDRSS3_PHY_385_DATA 0x00A000A0 +#define DDRSS3_PHY_386_DATA 0x01C200A0 +#define DDRSS3_PHY_387_DATA 0x01A00005 +#define DDRSS3_PHY_388_DATA 0x00000000 +#define DDRSS3_PHY_389_DATA 0x00000000 +#define DDRSS3_PHY_390_DATA 0x00080200 +#define DDRSS3_PHY_391_DATA 0x00000000 +#define DDRSS3_PHY_392_DATA 0x20202000 +#define DDRSS3_PHY_393_DATA 0x20202020 +#define DDRSS3_PHY_394_DATA 0xF0F02020 +#define DDRSS3_PHY_395_DATA 0x00000000 +#define DDRSS3_PHY_396_DATA 0x00000000 +#define DDRSS3_PHY_397_DATA 0x00000000 +#define DDRSS3_PHY_398_DATA 0x00000000 +#define DDRSS3_PHY_399_DATA 0x00000000 +#define DDRSS3_PHY_400_DATA 0x00000000 +#define DDRSS3_PHY_401_DATA 0x00000000 +#define DDRSS3_PHY_402_DATA 0x00000000 +#define DDRSS3_PHY_403_DATA 0x00000000 +#define DDRSS3_PHY_404_DATA 0x00000000 +#define DDRSS3_PHY_405_DATA 0x00000000 +#define DDRSS3_PHY_406_DATA 0x00000000 +#define DDRSS3_PHY_407_DATA 0x00000000 +#define DDRSS3_PHY_408_DATA 0x00000000 +#define DDRSS3_PHY_409_DATA 0x00000000 +#define DDRSS3_PHY_410_DATA 0x00000000 +#define DDRSS3_PHY_411_DATA 0x00000000 +#define DDRSS3_PHY_412_DATA 0x00000000 +#define DDRSS3_PHY_413_DATA 0x00000000 +#define DDRSS3_PHY_414_DATA 0x00000000 +#define DDRSS3_PHY_415_DATA 0x00000000 +#define DDRSS3_PHY_416_DATA 0x00000000 +#define DDRSS3_PHY_417_DATA 0x00000000 +#define DDRSS3_PHY_418_DATA 0x00000000 +#define DDRSS3_PHY_419_DATA 0x00000000 +#define DDRSS3_PHY_420_DATA 0x00000000 +#define DDRSS3_PHY_421_DATA 0x00000000 +#define DDRSS3_PHY_422_DATA 0x00000000 +#define DDRSS3_PHY_423_DATA 0x00000000 +#define DDRSS3_PHY_424_DATA 0x00000000 +#define DDRSS3_PHY_425_DATA 0x00000000 +#define DDRSS3_PHY_426_DATA 0x00000000 +#define DDRSS3_PHY_427_DATA 0x00000000 +#define DDRSS3_PHY_428_DATA 0x00000000 +#define DDRSS3_PHY_429_DATA 0x00000000 +#define DDRSS3_PHY_430_DATA 0x00000000 +#define DDRSS3_PHY_431_DATA 0x00000000 +#define DDRSS3_PHY_432_DATA 0x00000000 +#define DDRSS3_PHY_433_DATA 0x00000000 +#define DDRSS3_PHY_434_DATA 0x00000000 +#define DDRSS3_PHY_435_DATA 0x00000000 +#define DDRSS3_PHY_436_DATA 0x00000000 +#define DDRSS3_PHY_437_DATA 0x00000000 +#define DDRSS3_PHY_438_DATA 0x00000000 +#define DDRSS3_PHY_439_DATA 0x00000000 +#define DDRSS3_PHY_440_DATA 0x00000000 +#define DDRSS3_PHY_441_DATA 0x00000000 +#define DDRSS3_PHY_442_DATA 0x00000000 +#define DDRSS3_PHY_443_DATA 0x00000000 +#define DDRSS3_PHY_444_DATA 0x00000000 +#define DDRSS3_PHY_445_DATA 0x00000000 +#define DDRSS3_PHY_446_DATA 0x00000000 +#define DDRSS3_PHY_447_DATA 0x00000000 +#define DDRSS3_PHY_448_DATA 0x00000000 +#define DDRSS3_PHY_449_DATA 0x00000000 +#define DDRSS3_PHY_450_DATA 0x00000000 +#define DDRSS3_PHY_451_DATA 0x00000000 +#define DDRSS3_PHY_452_DATA 0x00000000 +#define DDRSS3_PHY_453_DATA 0x00000000 +#define DDRSS3_PHY_454_DATA 0x00000000 +#define DDRSS3_PHY_455_DATA 0x00000000 +#define DDRSS3_PHY_456_DATA 0x00000000 +#define DDRSS3_PHY_457_DATA 0x00000000 +#define DDRSS3_PHY_458_DATA 0x00000000 +#define DDRSS3_PHY_459_DATA 0x00000000 +#define DDRSS3_PHY_460_DATA 0x00000000 +#define DDRSS3_PHY_461_DATA 0x00000000 +#define DDRSS3_PHY_462_DATA 0x00000000 +#define DDRSS3_PHY_463_DATA 0x00000000 +#define DDRSS3_PHY_464_DATA 0x00000000 +#define DDRSS3_PHY_465_DATA 0x00000000 +#define DDRSS3_PHY_466_DATA 0x00000000 +#define DDRSS3_PHY_467_DATA 0x00000000 +#define DDRSS3_PHY_468_DATA 0x00000000 +#define DDRSS3_PHY_469_DATA 0x00000000 +#define DDRSS3_PHY_470_DATA 0x00000000 +#define DDRSS3_PHY_471_DATA 0x00000000 +#define DDRSS3_PHY_472_DATA 0x00000000 +#define DDRSS3_PHY_473_DATA 0x00000000 +#define DDRSS3_PHY_474_DATA 0x00000000 +#define DDRSS3_PHY_475_DATA 0x00000000 +#define DDRSS3_PHY_476_DATA 0x00000000 +#define DDRSS3_PHY_477_DATA 0x00000000 +#define DDRSS3_PHY_478_DATA 0x00000000 +#define DDRSS3_PHY_479_DATA 0x00000000 +#define DDRSS3_PHY_480_DATA 0x00000000 +#define DDRSS3_PHY_481_DATA 0x00000000 +#define DDRSS3_PHY_482_DATA 0x00000000 +#define DDRSS3_PHY_483_DATA 0x00000000 +#define DDRSS3_PHY_484_DATA 0x00000000 +#define DDRSS3_PHY_485_DATA 0x00000000 +#define DDRSS3_PHY_486_DATA 0x00000000 +#define DDRSS3_PHY_487_DATA 0x00000000 +#define DDRSS3_PHY_488_DATA 0x00000000 +#define DDRSS3_PHY_489_DATA 0x00000000 +#define DDRSS3_PHY_490_DATA 0x00000000 +#define DDRSS3_PHY_491_DATA 0x00000000 +#define DDRSS3_PHY_492_DATA 0x00000000 +#define DDRSS3_PHY_493_DATA 0x00000000 +#define DDRSS3_PHY_494_DATA 0x00000000 +#define DDRSS3_PHY_495_DATA 0x00000000 +#define DDRSS3_PHY_496_DATA 0x00000000 +#define DDRSS3_PHY_497_DATA 0x00000000 +#define DDRSS3_PHY_498_DATA 0x00000000 +#define DDRSS3_PHY_499_DATA 0x00000000 +#define DDRSS3_PHY_500_DATA 0x00000000 +#define DDRSS3_PHY_501_DATA 0x00000000 +#define DDRSS3_PHY_502_DATA 0x00000000 +#define DDRSS3_PHY_503_DATA 0x00000000 +#define DDRSS3_PHY_504_DATA 0x00000000 +#define DDRSS3_PHY_505_DATA 0x00000000 +#define DDRSS3_PHY_506_DATA 0x00000000 +#define DDRSS3_PHY_507_DATA 0x00000000 +#define DDRSS3_PHY_508_DATA 0x00000000 +#define DDRSS3_PHY_509_DATA 0x00000000 +#define DDRSS3_PHY_510_DATA 0x00000000 +#define DDRSS3_PHY_511_DATA 0x00000000 +#define DDRSS3_PHY_512_DATA 0x000004F0 +#define DDRSS3_PHY_513_DATA 0x00000000 +#define DDRSS3_PHY_514_DATA 0x00030200 +#define DDRSS3_PHY_515_DATA 0x00000000 +#define DDRSS3_PHY_516_DATA 0x00000000 +#define DDRSS3_PHY_517_DATA 0x01030000 +#define DDRSS3_PHY_518_DATA 0x00010000 +#define DDRSS3_PHY_519_DATA 0x01030004 +#define DDRSS3_PHY_520_DATA 0x01000000 +#define DDRSS3_PHY_521_DATA 0x00000000 +#define DDRSS3_PHY_522_DATA 0x00000000 +#define DDRSS3_PHY_523_DATA 0x01000001 +#define DDRSS3_PHY_524_DATA 0x00000200 +#define DDRSS3_PHY_525_DATA 0x000800C0 +#define DDRSS3_PHY_526_DATA 0x060100CC +#define DDRSS3_PHY_527_DATA 0x00030066 +#define DDRSS3_PHY_528_DATA 0x00000000 +#define DDRSS3_PHY_529_DATA 0x00000301 +#define DDRSS3_PHY_530_DATA 0x0000AAAA +#define DDRSS3_PHY_531_DATA 0x00005555 +#define DDRSS3_PHY_532_DATA 0x0000B5B5 +#define DDRSS3_PHY_533_DATA 0x00004A4A +#define DDRSS3_PHY_534_DATA 0x00005656 +#define DDRSS3_PHY_535_DATA 0x0000A9A9 +#define DDRSS3_PHY_536_DATA 0x0000A9A9 +#define DDRSS3_PHY_537_DATA 0x0000B5B5 +#define DDRSS3_PHY_538_DATA 0x00000000 +#define DDRSS3_PHY_539_DATA 0x00000000 +#define DDRSS3_PHY_540_DATA 0x2A000000 +#define DDRSS3_PHY_541_DATA 0x00000808 +#define DDRSS3_PHY_542_DATA 0x0F000000 +#define DDRSS3_PHY_543_DATA 0x00000F08 +#define DDRSS3_PHY_544_DATA 0x10400000 +#define DDRSS3_PHY_545_DATA 0x0C002006 +#define DDRSS3_PHY_546_DATA 0x00000000 +#define DDRSS3_PHY_547_DATA 0x00000000 +#define DDRSS3_PHY_548_DATA 0x55555555 +#define DDRSS3_PHY_549_DATA 0xAAAAAAAA +#define DDRSS3_PHY_550_DATA 0x55555555 +#define DDRSS3_PHY_551_DATA 0xAAAAAAAA +#define DDRSS3_PHY_552_DATA 0x00005555 +#define DDRSS3_PHY_553_DATA 0x01000100 +#define DDRSS3_PHY_554_DATA 0x00800180 +#define DDRSS3_PHY_555_DATA 0x00000001 +#define DDRSS3_PHY_556_DATA 0x00000000 +#define DDRSS3_PHY_557_DATA 0x00000000 +#define DDRSS3_PHY_558_DATA 0x00000000 +#define DDRSS3_PHY_559_DATA 0x00000000 +#define DDRSS3_PHY_560_DATA 0x00000000 +#define DDRSS3_PHY_561_DATA 0x00000000 +#define DDRSS3_PHY_562_DATA 0x00000000 +#define DDRSS3_PHY_563_DATA 0x00000000 +#define DDRSS3_PHY_564_DATA 0x00000000 +#define DDRSS3_PHY_565_DATA 0x00000000 +#define DDRSS3_PHY_566_DATA 0x00000000 +#define DDRSS3_PHY_567_DATA 0x00000000 +#define DDRSS3_PHY_568_DATA 0x00000000 +#define DDRSS3_PHY_569_DATA 0x00000000 +#define DDRSS3_PHY_570_DATA 0x00000000 +#define DDRSS3_PHY_571_DATA 0x00000000 +#define DDRSS3_PHY_572_DATA 0x00000000 +#define DDRSS3_PHY_573_DATA 0x00000000 +#define DDRSS3_PHY_574_DATA 0x00000000 +#define DDRSS3_PHY_575_DATA 0x00000000 +#define DDRSS3_PHY_576_DATA 0x00000000 +#define DDRSS3_PHY_577_DATA 0x00000000 +#define DDRSS3_PHY_578_DATA 0x00000104 +#define DDRSS3_PHY_579_DATA 0x00000120 +#define DDRSS3_PHY_580_DATA 0x00000000 +#define DDRSS3_PHY_581_DATA 0x00000000 +#define DDRSS3_PHY_582_DATA 0x00000000 +#define DDRSS3_PHY_583_DATA 0x00000000 +#define DDRSS3_PHY_584_DATA 0x00000000 +#define DDRSS3_PHY_585_DATA 0x00000000 +#define DDRSS3_PHY_586_DATA 0x00000000 +#define DDRSS3_PHY_587_DATA 0x00000001 +#define DDRSS3_PHY_588_DATA 0x07FF0000 +#define DDRSS3_PHY_589_DATA 0x0080081F +#define DDRSS3_PHY_590_DATA 0x00081020 +#define DDRSS3_PHY_591_DATA 0x04010000 +#define DDRSS3_PHY_592_DATA 0x00000000 +#define DDRSS3_PHY_593_DATA 0x00000000 +#define DDRSS3_PHY_594_DATA 0x00000000 +#define DDRSS3_PHY_595_DATA 0x00000100 +#define DDRSS3_PHY_596_DATA 0x01CC0C01 +#define DDRSS3_PHY_597_DATA 0x1003CC0C +#define DDRSS3_PHY_598_DATA 0x20000140 +#define DDRSS3_PHY_599_DATA 0x07FF0200 +#define DDRSS3_PHY_600_DATA 0x0000DD01 +#define DDRSS3_PHY_601_DATA 0x10100303 +#define DDRSS3_PHY_602_DATA 0x10101010 +#define DDRSS3_PHY_603_DATA 0x10101010 +#define DDRSS3_PHY_604_DATA 0x00021010 +#define DDRSS3_PHY_605_DATA 0x00100010 +#define DDRSS3_PHY_606_DATA 0x00100010 +#define DDRSS3_PHY_607_DATA 0x00100010 +#define DDRSS3_PHY_608_DATA 0x00100010 +#define DDRSS3_PHY_609_DATA 0x00050010 +#define DDRSS3_PHY_610_DATA 0x51517041 +#define DDRSS3_PHY_611_DATA 0x31C06001 +#define DDRSS3_PHY_612_DATA 0x07AB01AB +#define DDRSS3_PHY_613_DATA 0x00C0C001 +#define DDRSS3_PHY_614_DATA 0x0E0D0101 +#define DDRSS3_PHY_615_DATA 0x10001000 +#define DDRSS3_PHY_616_DATA 0x0C083E42 +#define DDRSS3_PHY_617_DATA 0x0F0C3701 +#define DDRSS3_PHY_618_DATA 0x01000140 +#define DDRSS3_PHY_619_DATA 0x0C000420 +#define DDRSS3_PHY_620_DATA 0x00000198 +#define DDRSS3_PHY_621_DATA 0x0A0000D0 +#define DDRSS3_PHY_622_DATA 0x00030200 +#define DDRSS3_PHY_623_DATA 0x02800000 +#define DDRSS3_PHY_624_DATA 0x80800000 +#define DDRSS3_PHY_625_DATA 0x000E2010 +#define DDRSS3_PHY_626_DATA 0x76543210 +#define DDRSS3_PHY_627_DATA 0x00000008 +#define DDRSS3_PHY_628_DATA 0x02800280 +#define DDRSS3_PHY_629_DATA 0x02800280 +#define DDRSS3_PHY_630_DATA 0x02800280 +#define DDRSS3_PHY_631_DATA 0x02800280 +#define DDRSS3_PHY_632_DATA 0x00000280 +#define DDRSS3_PHY_633_DATA 0x0000A000 +#define DDRSS3_PHY_634_DATA 0x00A000A0 +#define DDRSS3_PHY_635_DATA 0x00A000A0 +#define DDRSS3_PHY_636_DATA 0x00A000A0 +#define DDRSS3_PHY_637_DATA 0x00A000A0 +#define DDRSS3_PHY_638_DATA 0x00A000A0 +#define DDRSS3_PHY_639_DATA 0x00A000A0 +#define DDRSS3_PHY_640_DATA 0x00A000A0 +#define DDRSS3_PHY_641_DATA 0x00A000A0 +#define DDRSS3_PHY_642_DATA 0x01C200A0 +#define DDRSS3_PHY_643_DATA 0x01A00005 +#define DDRSS3_PHY_644_DATA 0x00000000 +#define DDRSS3_PHY_645_DATA 0x00000000 +#define DDRSS3_PHY_646_DATA 0x00080200 +#define DDRSS3_PHY_647_DATA 0x00000000 +#define DDRSS3_PHY_648_DATA 0x20202000 +#define DDRSS3_PHY_649_DATA 0x20202020 +#define DDRSS3_PHY_650_DATA 0xF0F02020 +#define DDRSS3_PHY_651_DATA 0x00000000 +#define DDRSS3_PHY_652_DATA 0x00000000 +#define DDRSS3_PHY_653_DATA 0x00000000 +#define DDRSS3_PHY_654_DATA 0x00000000 +#define DDRSS3_PHY_655_DATA 0x00000000 +#define DDRSS3_PHY_656_DATA 0x00000000 +#define DDRSS3_PHY_657_DATA 0x00000000 +#define DDRSS3_PHY_658_DATA 0x00000000 +#define DDRSS3_PHY_659_DATA 0x00000000 +#define DDRSS3_PHY_660_DATA 0x00000000 +#define DDRSS3_PHY_661_DATA 0x00000000 +#define DDRSS3_PHY_662_DATA 0x00000000 +#define DDRSS3_PHY_663_DATA 0x00000000 +#define DDRSS3_PHY_664_DATA 0x00000000 +#define DDRSS3_PHY_665_DATA 0x00000000 +#define DDRSS3_PHY_666_DATA 0x00000000 +#define DDRSS3_PHY_667_DATA 0x00000000 +#define DDRSS3_PHY_668_DATA 0x00000000 +#define DDRSS3_PHY_669_DATA 0x00000000 +#define DDRSS3_PHY_670_DATA 0x00000000 +#define DDRSS3_PHY_671_DATA 0x00000000 +#define DDRSS3_PHY_672_DATA 0x00000000 +#define DDRSS3_PHY_673_DATA 0x00000000 +#define DDRSS3_PHY_674_DATA 0x00000000 +#define DDRSS3_PHY_675_DATA 0x00000000 +#define DDRSS3_PHY_676_DATA 0x00000000 +#define DDRSS3_PHY_677_DATA 0x00000000 +#define DDRSS3_PHY_678_DATA 0x00000000 +#define DDRSS3_PHY_679_DATA 0x00000000 +#define DDRSS3_PHY_680_DATA 0x00000000 +#define DDRSS3_PHY_681_DATA 0x00000000 +#define DDRSS3_PHY_682_DATA 0x00000000 +#define DDRSS3_PHY_683_DATA 0x00000000 +#define DDRSS3_PHY_684_DATA 0x00000000 +#define DDRSS3_PHY_685_DATA 0x00000000 +#define DDRSS3_PHY_686_DATA 0x00000000 +#define DDRSS3_PHY_687_DATA 0x00000000 +#define DDRSS3_PHY_688_DATA 0x00000000 +#define DDRSS3_PHY_689_DATA 0x00000000 +#define DDRSS3_PHY_690_DATA 0x00000000 +#define DDRSS3_PHY_691_DATA 0x00000000 +#define DDRSS3_PHY_692_DATA 0x00000000 +#define DDRSS3_PHY_693_DATA 0x00000000 +#define DDRSS3_PHY_694_DATA 0x00000000 +#define DDRSS3_PHY_695_DATA 0x00000000 +#define DDRSS3_PHY_696_DATA 0x00000000 +#define DDRSS3_PHY_697_DATA 0x00000000 +#define DDRSS3_PHY_698_DATA 0x00000000 +#define DDRSS3_PHY_699_DATA 0x00000000 +#define DDRSS3_PHY_700_DATA 0x00000000 +#define DDRSS3_PHY_701_DATA 0x00000000 +#define DDRSS3_PHY_702_DATA 0x00000000 +#define DDRSS3_PHY_703_DATA 0x00000000 +#define DDRSS3_PHY_704_DATA 0x00000000 +#define DDRSS3_PHY_705_DATA 0x00000000 +#define DDRSS3_PHY_706_DATA 0x00000000 +#define DDRSS3_PHY_707_DATA 0x00000000 +#define DDRSS3_PHY_708_DATA 0x00000000 +#define DDRSS3_PHY_709_DATA 0x00000000 +#define DDRSS3_PHY_710_DATA 0x00000000 +#define DDRSS3_PHY_711_DATA 0x00000000 +#define DDRSS3_PHY_712_DATA 0x00000000 +#define DDRSS3_PHY_713_DATA 0x00000000 +#define DDRSS3_PHY_714_DATA 0x00000000 +#define DDRSS3_PHY_715_DATA 0x00000000 +#define DDRSS3_PHY_716_DATA 0x00000000 +#define DDRSS3_PHY_717_DATA 0x00000000 +#define DDRSS3_PHY_718_DATA 0x00000000 +#define DDRSS3_PHY_719_DATA 0x00000000 +#define DDRSS3_PHY_720_DATA 0x00000000 +#define DDRSS3_PHY_721_DATA 0x00000000 +#define DDRSS3_PHY_722_DATA 0x00000000 +#define DDRSS3_PHY_723_DATA 0x00000000 +#define DDRSS3_PHY_724_DATA 0x00000000 +#define DDRSS3_PHY_725_DATA 0x00000000 +#define DDRSS3_PHY_726_DATA 0x00000000 +#define DDRSS3_PHY_727_DATA 0x00000000 +#define DDRSS3_PHY_728_DATA 0x00000000 +#define DDRSS3_PHY_729_DATA 0x00000000 +#define DDRSS3_PHY_730_DATA 0x00000000 +#define DDRSS3_PHY_731_DATA 0x00000000 +#define DDRSS3_PHY_732_DATA 0x00000000 +#define DDRSS3_PHY_733_DATA 0x00000000 +#define DDRSS3_PHY_734_DATA 0x00000000 +#define DDRSS3_PHY_735_DATA 0x00000000 +#define DDRSS3_PHY_736_DATA 0x00000000 +#define DDRSS3_PHY_737_DATA 0x00000000 +#define DDRSS3_PHY_738_DATA 0x00000000 +#define DDRSS3_PHY_739_DATA 0x00000000 +#define DDRSS3_PHY_740_DATA 0x00000000 +#define DDRSS3_PHY_741_DATA 0x00000000 +#define DDRSS3_PHY_742_DATA 0x00000000 +#define DDRSS3_PHY_743_DATA 0x00000000 +#define DDRSS3_PHY_744_DATA 0x00000000 +#define DDRSS3_PHY_745_DATA 0x00000000 +#define DDRSS3_PHY_746_DATA 0x00000000 +#define DDRSS3_PHY_747_DATA 0x00000000 +#define DDRSS3_PHY_748_DATA 0x00000000 +#define DDRSS3_PHY_749_DATA 0x00000000 +#define DDRSS3_PHY_750_DATA 0x00000000 +#define DDRSS3_PHY_751_DATA 0x00000000 +#define DDRSS3_PHY_752_DATA 0x00000000 +#define DDRSS3_PHY_753_DATA 0x00000000 +#define DDRSS3_PHY_754_DATA 0x00000000 +#define DDRSS3_PHY_755_DATA 0x00000000 +#define DDRSS3_PHY_756_DATA 0x00000000 +#define DDRSS3_PHY_757_DATA 0x00000000 +#define DDRSS3_PHY_758_DATA 0x00000000 +#define DDRSS3_PHY_759_DATA 0x00000000 +#define DDRSS3_PHY_760_DATA 0x00000000 +#define DDRSS3_PHY_761_DATA 0x00000000 +#define DDRSS3_PHY_762_DATA 0x00000000 +#define DDRSS3_PHY_763_DATA 0x00000000 +#define DDRSS3_PHY_764_DATA 0x00000000 +#define DDRSS3_PHY_765_DATA 0x00000000 +#define DDRSS3_PHY_766_DATA 0x00000000 +#define DDRSS3_PHY_767_DATA 0x00000000 +#define DDRSS3_PHY_768_DATA 0x000004F0 +#define DDRSS3_PHY_769_DATA 0x00000000 +#define DDRSS3_PHY_770_DATA 0x00030200 +#define DDRSS3_PHY_771_DATA 0x00000000 +#define DDRSS3_PHY_772_DATA 0x00000000 +#define DDRSS3_PHY_773_DATA 0x01030000 +#define DDRSS3_PHY_774_DATA 0x00010000 +#define DDRSS3_PHY_775_DATA 0x01030004 +#define DDRSS3_PHY_776_DATA 0x01000000 +#define DDRSS3_PHY_777_DATA 0x00000000 +#define DDRSS3_PHY_778_DATA 0x00000000 +#define DDRSS3_PHY_779_DATA 0x01000001 +#define DDRSS3_PHY_780_DATA 0x00000200 +#define DDRSS3_PHY_781_DATA 0x000800C0 +#define DDRSS3_PHY_782_DATA 0x060100CC +#define DDRSS3_PHY_783_DATA 0x00030066 +#define DDRSS3_PHY_784_DATA 0x00000000 +#define DDRSS3_PHY_785_DATA 0x00000301 +#define DDRSS3_PHY_786_DATA 0x0000AAAA +#define DDRSS3_PHY_787_DATA 0x00005555 +#define DDRSS3_PHY_788_DATA 0x0000B5B5 +#define DDRSS3_PHY_789_DATA 0x00004A4A +#define DDRSS3_PHY_790_DATA 0x00005656 +#define DDRSS3_PHY_791_DATA 0x0000A9A9 +#define DDRSS3_PHY_792_DATA 0x0000A9A9 +#define DDRSS3_PHY_793_DATA 0x0000B5B5 +#define DDRSS3_PHY_794_DATA 0x00000000 +#define DDRSS3_PHY_795_DATA 0x00000000 +#define DDRSS3_PHY_796_DATA 0x2A000000 +#define DDRSS3_PHY_797_DATA 0x00000808 +#define DDRSS3_PHY_798_DATA 0x0F000000 +#define DDRSS3_PHY_799_DATA 0x00000F08 +#define DDRSS3_PHY_800_DATA 0x10400000 +#define DDRSS3_PHY_801_DATA 0x0C002006 +#define DDRSS3_PHY_802_DATA 0x00000000 +#define DDRSS3_PHY_803_DATA 0x00000000 +#define DDRSS3_PHY_804_DATA 0x55555555 +#define DDRSS3_PHY_805_DATA 0xAAAAAAAA +#define DDRSS3_PHY_806_DATA 0x55555555 +#define DDRSS3_PHY_807_DATA 0xAAAAAAAA +#define DDRSS3_PHY_808_DATA 0x00005555 +#define DDRSS3_PHY_809_DATA 0x01000100 +#define DDRSS3_PHY_810_DATA 0x00800180 +#define DDRSS3_PHY_811_DATA 0x00000000 +#define DDRSS3_PHY_812_DATA 0x00000000 +#define DDRSS3_PHY_813_DATA 0x00000000 +#define DDRSS3_PHY_814_DATA 0x00000000 +#define DDRSS3_PHY_815_DATA 0x00000000 +#define DDRSS3_PHY_816_DATA 0x00000000 +#define DDRSS3_PHY_817_DATA 0x00000000 +#define DDRSS3_PHY_818_DATA 0x00000000 +#define DDRSS3_PHY_819_DATA 0x00000000 +#define DDRSS3_PHY_820_DATA 0x00000000 +#define DDRSS3_PHY_821_DATA 0x00000000 +#define DDRSS3_PHY_822_DATA 0x00000000 +#define DDRSS3_PHY_823_DATA 0x00000000 +#define DDRSS3_PHY_824_DATA 0x00000000 +#define DDRSS3_PHY_825_DATA 0x00000000 +#define DDRSS3_PHY_826_DATA 0x00000000 +#define DDRSS3_PHY_827_DATA 0x00000000 +#define DDRSS3_PHY_828_DATA 0x00000000 +#define DDRSS3_PHY_829_DATA 0x00000000 +#define DDRSS3_PHY_830_DATA 0x00000000 +#define DDRSS3_PHY_831_DATA 0x00000000 +#define DDRSS3_PHY_832_DATA 0x00000000 +#define DDRSS3_PHY_833_DATA 0x00000000 +#define DDRSS3_PHY_834_DATA 0x00000104 +#define DDRSS3_PHY_835_DATA 0x00000120 +#define DDRSS3_PHY_836_DATA 0x00000000 +#define DDRSS3_PHY_837_DATA 0x00000000 +#define DDRSS3_PHY_838_DATA 0x00000000 +#define DDRSS3_PHY_839_DATA 0x00000000 +#define DDRSS3_PHY_840_DATA 0x00000000 +#define DDRSS3_PHY_841_DATA 0x00000000 +#define DDRSS3_PHY_842_DATA 0x00000000 +#define DDRSS3_PHY_843_DATA 0x00000001 +#define DDRSS3_PHY_844_DATA 0x07FF0000 +#define DDRSS3_PHY_845_DATA 0x0080081F +#define DDRSS3_PHY_846_DATA 0x00081020 +#define DDRSS3_PHY_847_DATA 0x04010000 +#define DDRSS3_PHY_848_DATA 0x00000000 +#define DDRSS3_PHY_849_DATA 0x00000000 +#define DDRSS3_PHY_850_DATA 0x00000000 +#define DDRSS3_PHY_851_DATA 0x00000100 +#define DDRSS3_PHY_852_DATA 0x01CC0C01 +#define DDRSS3_PHY_853_DATA 0x1003CC0C +#define DDRSS3_PHY_854_DATA 0x20000140 +#define DDRSS3_PHY_855_DATA 0x07FF0200 +#define DDRSS3_PHY_856_DATA 0x0000DD01 +#define DDRSS3_PHY_857_DATA 0x10100303 +#define DDRSS3_PHY_858_DATA 0x10101010 +#define DDRSS3_PHY_859_DATA 0x10101010 +#define DDRSS3_PHY_860_DATA 0x00021010 +#define DDRSS3_PHY_861_DATA 0x00100010 +#define DDRSS3_PHY_862_DATA 0x00100010 +#define DDRSS3_PHY_863_DATA 0x00100010 +#define DDRSS3_PHY_864_DATA 0x00100010 +#define DDRSS3_PHY_865_DATA 0x00050010 +#define DDRSS3_PHY_866_DATA 0x51517041 +#define DDRSS3_PHY_867_DATA 0x31C06001 +#define DDRSS3_PHY_868_DATA 0x07AB01AB +#define DDRSS3_PHY_869_DATA 0x00C0C001 +#define DDRSS3_PHY_870_DATA 0x0E0D0101 +#define DDRSS3_PHY_871_DATA 0x10001000 +#define DDRSS3_PHY_872_DATA 0x0C083E42 +#define DDRSS3_PHY_873_DATA 0x0F0C3701 +#define DDRSS3_PHY_874_DATA 0x01000140 +#define DDRSS3_PHY_875_DATA 0x0C000420 +#define DDRSS3_PHY_876_DATA 0x00000198 +#define DDRSS3_PHY_877_DATA 0x0A0000D0 +#define DDRSS3_PHY_878_DATA 0x00030200 +#define DDRSS3_PHY_879_DATA 0x02800000 +#define DDRSS3_PHY_880_DATA 0x80800000 +#define DDRSS3_PHY_881_DATA 0x000E2010 +#define DDRSS3_PHY_882_DATA 0x76543210 +#define DDRSS3_PHY_883_DATA 0x00000008 +#define DDRSS3_PHY_884_DATA 0x02800280 +#define DDRSS3_PHY_885_DATA 0x02800280 +#define DDRSS3_PHY_886_DATA 0x02800280 +#define DDRSS3_PHY_887_DATA 0x02800280 +#define DDRSS3_PHY_888_DATA 0x00000280 +#define DDRSS3_PHY_889_DATA 0x0000A000 +#define DDRSS3_PHY_890_DATA 0x00A000A0 +#define DDRSS3_PHY_891_DATA 0x00A000A0 +#define DDRSS3_PHY_892_DATA 0x00A000A0 +#define DDRSS3_PHY_893_DATA 0x00A000A0 +#define DDRSS3_PHY_894_DATA 0x00A000A0 +#define DDRSS3_PHY_895_DATA 0x00A000A0 +#define DDRSS3_PHY_896_DATA 0x00A000A0 +#define DDRSS3_PHY_897_DATA 0x00A000A0 +#define DDRSS3_PHY_898_DATA 0x01C200A0 +#define DDRSS3_PHY_899_DATA 0x01A00005 +#define DDRSS3_PHY_900_DATA 0x00000000 +#define DDRSS3_PHY_901_DATA 0x00000000 +#define DDRSS3_PHY_902_DATA 0x00080200 +#define DDRSS3_PHY_903_DATA 0x00000000 +#define DDRSS3_PHY_904_DATA 0x20202000 +#define DDRSS3_PHY_905_DATA 0x20202020 +#define DDRSS3_PHY_906_DATA 0xF0F02020 +#define DDRSS3_PHY_907_DATA 0x00000000 +#define DDRSS3_PHY_908_DATA 0x00000000 +#define DDRSS3_PHY_909_DATA 0x00000000 +#define DDRSS3_PHY_910_DATA 0x00000000 +#define DDRSS3_PHY_911_DATA 0x00000000 +#define DDRSS3_PHY_912_DATA 0x00000000 +#define DDRSS3_PHY_913_DATA 0x00000000 +#define DDRSS3_PHY_914_DATA 0x00000000 +#define DDRSS3_PHY_915_DATA 0x00000000 +#define DDRSS3_PHY_916_DATA 0x00000000 +#define DDRSS3_PHY_917_DATA 0x00000000 +#define DDRSS3_PHY_918_DATA 0x00000000 +#define DDRSS3_PHY_919_DATA 0x00000000 +#define DDRSS3_PHY_920_DATA 0x00000000 +#define DDRSS3_PHY_921_DATA 0x00000000 +#define DDRSS3_PHY_922_DATA 0x00000000 +#define DDRSS3_PHY_923_DATA 0x00000000 +#define DDRSS3_PHY_924_DATA 0x00000000 +#define DDRSS3_PHY_925_DATA 0x00000000 +#define DDRSS3_PHY_926_DATA 0x00000000 +#define DDRSS3_PHY_927_DATA 0x00000000 +#define DDRSS3_PHY_928_DATA 0x00000000 +#define DDRSS3_PHY_929_DATA 0x00000000 +#define DDRSS3_PHY_930_DATA 0x00000000 +#define DDRSS3_PHY_931_DATA 0x00000000 +#define DDRSS3_PHY_932_DATA 0x00000000 +#define DDRSS3_PHY_933_DATA 0x00000000 +#define DDRSS3_PHY_934_DATA 0x00000000 +#define DDRSS3_PHY_935_DATA 0x00000000 +#define DDRSS3_PHY_936_DATA 0x00000000 +#define DDRSS3_PHY_937_DATA 0x00000000 +#define DDRSS3_PHY_938_DATA 0x00000000 +#define DDRSS3_PHY_939_DATA 0x00000000 +#define DDRSS3_PHY_940_DATA 0x00000000 +#define DDRSS3_PHY_941_DATA 0x00000000 +#define DDRSS3_PHY_942_DATA 0x00000000 +#define DDRSS3_PHY_943_DATA 0x00000000 +#define DDRSS3_PHY_944_DATA 0x00000000 +#define DDRSS3_PHY_945_DATA 0x00000000 +#define DDRSS3_PHY_946_DATA 0x00000000 +#define DDRSS3_PHY_947_DATA 0x00000000 +#define DDRSS3_PHY_948_DATA 0x00000000 +#define DDRSS3_PHY_949_DATA 0x00000000 +#define DDRSS3_PHY_950_DATA 0x00000000 +#define DDRSS3_PHY_951_DATA 0x00000000 +#define DDRSS3_PHY_952_DATA 0x00000000 +#define DDRSS3_PHY_953_DATA 0x00000000 +#define DDRSS3_PHY_954_DATA 0x00000000 +#define DDRSS3_PHY_955_DATA 0x00000000 +#define DDRSS3_PHY_956_DATA 0x00000000 +#define DDRSS3_PHY_957_DATA 0x00000000 +#define DDRSS3_PHY_958_DATA 0x00000000 +#define DDRSS3_PHY_959_DATA 0x00000000 +#define DDRSS3_PHY_960_DATA 0x00000000 +#define DDRSS3_PHY_961_DATA 0x00000000 +#define DDRSS3_PHY_962_DATA 0x00000000 +#define DDRSS3_PHY_963_DATA 0x00000000 +#define DDRSS3_PHY_964_DATA 0x00000000 +#define DDRSS3_PHY_965_DATA 0x00000000 +#define DDRSS3_PHY_966_DATA 0x00000000 +#define DDRSS3_PHY_967_DATA 0x00000000 +#define DDRSS3_PHY_968_DATA 0x00000000 +#define DDRSS3_PHY_969_DATA 0x00000000 +#define DDRSS3_PHY_970_DATA 0x00000000 +#define DDRSS3_PHY_971_DATA 0x00000000 +#define DDRSS3_PHY_972_DATA 0x00000000 +#define DDRSS3_PHY_973_DATA 0x00000000 +#define DDRSS3_PHY_974_DATA 0x00000000 +#define DDRSS3_PHY_975_DATA 0x00000000 +#define DDRSS3_PHY_976_DATA 0x00000000 +#define DDRSS3_PHY_977_DATA 0x00000000 +#define DDRSS3_PHY_978_DATA 0x00000000 +#define DDRSS3_PHY_979_DATA 0x00000000 +#define DDRSS3_PHY_980_DATA 0x00000000 +#define DDRSS3_PHY_981_DATA 0x00000000 +#define DDRSS3_PHY_982_DATA 0x00000000 +#define DDRSS3_PHY_983_DATA 0x00000000 +#define DDRSS3_PHY_984_DATA 0x00000000 +#define DDRSS3_PHY_985_DATA 0x00000000 +#define DDRSS3_PHY_986_DATA 0x00000000 +#define DDRSS3_PHY_987_DATA 0x00000000 +#define DDRSS3_PHY_988_DATA 0x00000000 +#define DDRSS3_PHY_989_DATA 0x00000000 +#define DDRSS3_PHY_990_DATA 0x00000000 +#define DDRSS3_PHY_991_DATA 0x00000000 +#define DDRSS3_PHY_992_DATA 0x00000000 +#define DDRSS3_PHY_993_DATA 0x00000000 +#define DDRSS3_PHY_994_DATA 0x00000000 +#define DDRSS3_PHY_995_DATA 0x00000000 +#define DDRSS3_PHY_996_DATA 0x00000000 +#define DDRSS3_PHY_997_DATA 0x00000000 +#define DDRSS3_PHY_998_DATA 0x00000000 +#define DDRSS3_PHY_999_DATA 0x00000000 +#define DDRSS3_PHY_1000_DATA 0x00000000 +#define DDRSS3_PHY_1001_DATA 0x00000000 +#define DDRSS3_PHY_1002_DATA 0x00000000 +#define DDRSS3_PHY_1003_DATA 0x00000000 +#define DDRSS3_PHY_1004_DATA 0x00000000 +#define DDRSS3_PHY_1005_DATA 0x00000000 +#define DDRSS3_PHY_1006_DATA 0x00000000 +#define DDRSS3_PHY_1007_DATA 0x00000000 +#define DDRSS3_PHY_1008_DATA 0x00000000 +#define DDRSS3_PHY_1009_DATA 0x00000000 +#define DDRSS3_PHY_1010_DATA 0x00000000 +#define DDRSS3_PHY_1011_DATA 0x00000000 +#define DDRSS3_PHY_1012_DATA 0x00000000 +#define DDRSS3_PHY_1013_DATA 0x00000000 +#define DDRSS3_PHY_1014_DATA 0x00000000 +#define DDRSS3_PHY_1015_DATA 0x00000000 +#define DDRSS3_PHY_1016_DATA 0x00000000 +#define DDRSS3_PHY_1017_DATA 0x00000000 +#define DDRSS3_PHY_1018_DATA 0x00000000 +#define DDRSS3_PHY_1019_DATA 0x00000000 +#define DDRSS3_PHY_1020_DATA 0x00000000 +#define DDRSS3_PHY_1021_DATA 0x00000000 +#define DDRSS3_PHY_1022_DATA 0x00000000 +#define DDRSS3_PHY_1023_DATA 0x00000000 +#define DDRSS3_PHY_1024_DATA 0x00000000 +#define DDRSS3_PHY_1025_DATA 0x00000000 +#define DDRSS3_PHY_1026_DATA 0x00000000 +#define DDRSS3_PHY_1027_DATA 0x00000000 +#define DDRSS3_PHY_1028_DATA 0x00000000 +#define DDRSS3_PHY_1029_DATA 0x00000100 +#define DDRSS3_PHY_1030_DATA 0x00000200 +#define DDRSS3_PHY_1031_DATA 0x00000000 +#define DDRSS3_PHY_1032_DATA 0x00000000 +#define DDRSS3_PHY_1033_DATA 0x00000000 +#define DDRSS3_PHY_1034_DATA 0x00000000 +#define DDRSS3_PHY_1035_DATA 0x00400000 +#define DDRSS3_PHY_1036_DATA 0x00000080 +#define DDRSS3_PHY_1037_DATA 0x00DCBA98 +#define DDRSS3_PHY_1038_DATA 0x03000000 +#define DDRSS3_PHY_1039_DATA 0x00200000 +#define DDRSS3_PHY_1040_DATA 0x00000000 +#define DDRSS3_PHY_1041_DATA 0x00000000 +#define DDRSS3_PHY_1042_DATA 0x00000000 +#define DDRSS3_PHY_1043_DATA 0x00000000 +#define DDRSS3_PHY_1044_DATA 0x00000000 +#define DDRSS3_PHY_1045_DATA 0x0000002A +#define DDRSS3_PHY_1046_DATA 0x00000015 +#define DDRSS3_PHY_1047_DATA 0x00000015 +#define DDRSS3_PHY_1048_DATA 0x0000002A +#define DDRSS3_PHY_1049_DATA 0x00000033 +#define DDRSS3_PHY_1050_DATA 0x0000000C +#define DDRSS3_PHY_1051_DATA 0x0000000C +#define DDRSS3_PHY_1052_DATA 0x00000033 +#define DDRSS3_PHY_1053_DATA 0x00543210 +#define DDRSS3_PHY_1054_DATA 0x003F0000 +#define DDRSS3_PHY_1055_DATA 0x000F3F3F +#define DDRSS3_PHY_1056_DATA 0x20202003 +#define DDRSS3_PHY_1057_DATA 0x00202020 +#define DDRSS3_PHY_1058_DATA 0x20008008 +#define DDRSS3_PHY_1059_DATA 0x00000810 +#define DDRSS3_PHY_1060_DATA 0x00000F00 +#define DDRSS3_PHY_1061_DATA 0x00000000 +#define DDRSS3_PHY_1062_DATA 0x00000000 +#define DDRSS3_PHY_1063_DATA 0x00000000 +#define DDRSS3_PHY_1064_DATA 0x000305CC +#define DDRSS3_PHY_1065_DATA 0x00030000 +#define DDRSS3_PHY_1066_DATA 0x00000300 +#define DDRSS3_PHY_1067_DATA 0x00000300 +#define DDRSS3_PHY_1068_DATA 0x00000300 +#define DDRSS3_PHY_1069_DATA 0x00000300 +#define DDRSS3_PHY_1070_DATA 0x00000300 +#define DDRSS3_PHY_1071_DATA 0x42080010 +#define DDRSS3_PHY_1072_DATA 0x0000803E +#define DDRSS3_PHY_1073_DATA 0x00000001 +#define DDRSS3_PHY_1074_DATA 0x01000102 +#define DDRSS3_PHY_1075_DATA 0x00008000 +#define DDRSS3_PHY_1076_DATA 0x00000000 +#define DDRSS3_PHY_1077_DATA 0x00000000 +#define DDRSS3_PHY_1078_DATA 0x00000000 +#define DDRSS3_PHY_1079_DATA 0x00000000 +#define DDRSS3_PHY_1080_DATA 0x00000000 +#define DDRSS3_PHY_1081_DATA 0x00000000 +#define DDRSS3_PHY_1082_DATA 0x00000000 +#define DDRSS3_PHY_1083_DATA 0x00000000 +#define DDRSS3_PHY_1084_DATA 0x00000000 +#define DDRSS3_PHY_1085_DATA 0x00000000 +#define DDRSS3_PHY_1086_DATA 0x00000000 +#define DDRSS3_PHY_1087_DATA 0x00000000 +#define DDRSS3_PHY_1088_DATA 0x00000000 +#define DDRSS3_PHY_1089_DATA 0x00000000 +#define DDRSS3_PHY_1090_DATA 0x00000000 +#define DDRSS3_PHY_1091_DATA 0x00000000 +#define DDRSS3_PHY_1092_DATA 0x00000000 +#define DDRSS3_PHY_1093_DATA 0x00000000 +#define DDRSS3_PHY_1094_DATA 0x00000000 +#define DDRSS3_PHY_1095_DATA 0x00000000 +#define DDRSS3_PHY_1096_DATA 0x00000000 +#define DDRSS3_PHY_1097_DATA 0x00000000 +#define DDRSS3_PHY_1098_DATA 0x00000000 +#define DDRSS3_PHY_1099_DATA 0x00000000 +#define DDRSS3_PHY_1100_DATA 0x00000000 +#define DDRSS3_PHY_1101_DATA 0x00000000 +#define DDRSS3_PHY_1102_DATA 0x00000000 +#define DDRSS3_PHY_1103_DATA 0x00000000 +#define DDRSS3_PHY_1104_DATA 0x00000000 +#define DDRSS3_PHY_1105_DATA 0x00000000 +#define DDRSS3_PHY_1106_DATA 0x00000000 +#define DDRSS3_PHY_1107_DATA 0x00000000 +#define DDRSS3_PHY_1108_DATA 0x00000000 +#define DDRSS3_PHY_1109_DATA 0x00000000 +#define DDRSS3_PHY_1110_DATA 0x00000000 +#define DDRSS3_PHY_1111_DATA 0x00000000 +#define DDRSS3_PHY_1112_DATA 0x00000000 +#define DDRSS3_PHY_1113_DATA 0x00000000 +#define DDRSS3_PHY_1114_DATA 0x00000000 +#define DDRSS3_PHY_1115_DATA 0x00000000 +#define DDRSS3_PHY_1116_DATA 0x00000000 +#define DDRSS3_PHY_1117_DATA 0x00000000 +#define DDRSS3_PHY_1118_DATA 0x00000000 +#define DDRSS3_PHY_1119_DATA 0x00000000 +#define DDRSS3_PHY_1120_DATA 0x00000000 +#define DDRSS3_PHY_1121_DATA 0x00000000 +#define DDRSS3_PHY_1122_DATA 0x00000000 +#define DDRSS3_PHY_1123_DATA 0x00000000 +#define DDRSS3_PHY_1124_DATA 0x00000000 +#define DDRSS3_PHY_1125_DATA 0x00000000 +#define DDRSS3_PHY_1126_DATA 0x00000000 +#define DDRSS3_PHY_1127_DATA 0x00000000 +#define DDRSS3_PHY_1128_DATA 0x00000000 +#define DDRSS3_PHY_1129_DATA 0x00000000 +#define DDRSS3_PHY_1130_DATA 0x00000000 +#define DDRSS3_PHY_1131_DATA 0x00000000 +#define DDRSS3_PHY_1132_DATA 0x00000000 +#define DDRSS3_PHY_1133_DATA 0x00000000 +#define DDRSS3_PHY_1134_DATA 0x00000000 +#define DDRSS3_PHY_1135_DATA 0x00000000 +#define DDRSS3_PHY_1136_DATA 0x00000000 +#define DDRSS3_PHY_1137_DATA 0x00000000 +#define DDRSS3_PHY_1138_DATA 0x00000000 +#define DDRSS3_PHY_1139_DATA 0x00000000 +#define DDRSS3_PHY_1140_DATA 0x00000000 +#define DDRSS3_PHY_1141_DATA 0x00000000 +#define DDRSS3_PHY_1142_DATA 0x00000000 +#define DDRSS3_PHY_1143_DATA 0x00000000 +#define DDRSS3_PHY_1144_DATA 0x00000000 +#define DDRSS3_PHY_1145_DATA 0x00000000 +#define DDRSS3_PHY_1146_DATA 0x00000000 +#define DDRSS3_PHY_1147_DATA 0x00000000 +#define DDRSS3_PHY_1148_DATA 0x00000000 +#define DDRSS3_PHY_1149_DATA 0x00000000 +#define DDRSS3_PHY_1150_DATA 0x00000000 +#define DDRSS3_PHY_1151_DATA 0x00000000 +#define DDRSS3_PHY_1152_DATA 0x00000000 +#define DDRSS3_PHY_1153_DATA 0x00000000 +#define DDRSS3_PHY_1154_DATA 0x00000000 +#define DDRSS3_PHY_1155_DATA 0x00000000 +#define DDRSS3_PHY_1156_DATA 0x00000000 +#define DDRSS3_PHY_1157_DATA 0x00000000 +#define DDRSS3_PHY_1158_DATA 0x00000000 +#define DDRSS3_PHY_1159_DATA 0x00000000 +#define DDRSS3_PHY_1160_DATA 0x00000000 +#define DDRSS3_PHY_1161_DATA 0x00000000 +#define DDRSS3_PHY_1162_DATA 0x00000000 +#define DDRSS3_PHY_1163_DATA 0x00000000 +#define DDRSS3_PHY_1164_DATA 0x00000000 +#define DDRSS3_PHY_1165_DATA 0x00000000 +#define DDRSS3_PHY_1166_DATA 0x00000000 +#define DDRSS3_PHY_1167_DATA 0x00000000 +#define DDRSS3_PHY_1168_DATA 0x00000000 +#define DDRSS3_PHY_1169_DATA 0x00000000 +#define DDRSS3_PHY_1170_DATA 0x00000000 +#define DDRSS3_PHY_1171_DATA 0x00000000 +#define DDRSS3_PHY_1172_DATA 0x00000000 +#define DDRSS3_PHY_1173_DATA 0x00000000 +#define DDRSS3_PHY_1174_DATA 0x00000000 +#define DDRSS3_PHY_1175_DATA 0x00000000 +#define DDRSS3_PHY_1176_DATA 0x00000000 +#define DDRSS3_PHY_1177_DATA 0x00000000 +#define DDRSS3_PHY_1178_DATA 0x00000000 +#define DDRSS3_PHY_1179_DATA 0x00000000 +#define DDRSS3_PHY_1180_DATA 0x00000000 +#define DDRSS3_PHY_1181_DATA 0x00000000 +#define DDRSS3_PHY_1182_DATA 0x00000000 +#define DDRSS3_PHY_1183_DATA 0x00000000 +#define DDRSS3_PHY_1184_DATA 0x00000000 +#define DDRSS3_PHY_1185_DATA 0x00000000 +#define DDRSS3_PHY_1186_DATA 0x00000000 +#define DDRSS3_PHY_1187_DATA 0x00000000 +#define DDRSS3_PHY_1188_DATA 0x00000000 +#define DDRSS3_PHY_1189_DATA 0x00000000 +#define DDRSS3_PHY_1190_DATA 0x00000000 +#define DDRSS3_PHY_1191_DATA 0x00000000 +#define DDRSS3_PHY_1192_DATA 0x00000000 +#define DDRSS3_PHY_1193_DATA 0x00000000 +#define DDRSS3_PHY_1194_DATA 0x00000000 +#define DDRSS3_PHY_1195_DATA 0x00000000 +#define DDRSS3_PHY_1196_DATA 0x00000000 +#define DDRSS3_PHY_1197_DATA 0x00000000 +#define DDRSS3_PHY_1198_DATA 0x00000000 +#define DDRSS3_PHY_1199_DATA 0x00000000 +#define DDRSS3_PHY_1200_DATA 0x00000000 +#define DDRSS3_PHY_1201_DATA 0x00000000 +#define DDRSS3_PHY_1202_DATA 0x00000000 +#define DDRSS3_PHY_1203_DATA 0x00000000 +#define DDRSS3_PHY_1204_DATA 0x00000000 +#define DDRSS3_PHY_1205_DATA 0x00000000 +#define DDRSS3_PHY_1206_DATA 0x00000000 +#define DDRSS3_PHY_1207_DATA 0x00000000 +#define DDRSS3_PHY_1208_DATA 0x00000000 +#define DDRSS3_PHY_1209_DATA 0x00000000 +#define DDRSS3_PHY_1210_DATA 0x00000000 +#define DDRSS3_PHY_1211_DATA 0x00000000 +#define DDRSS3_PHY_1212_DATA 0x00000000 +#define DDRSS3_PHY_1213_DATA 0x00000000 +#define DDRSS3_PHY_1214_DATA 0x00000000 +#define DDRSS3_PHY_1215_DATA 0x00000000 +#define DDRSS3_PHY_1216_DATA 0x00000000 +#define DDRSS3_PHY_1217_DATA 0x00000000 +#define DDRSS3_PHY_1218_DATA 0x00000000 +#define DDRSS3_PHY_1219_DATA 0x00000000 +#define DDRSS3_PHY_1220_DATA 0x00000000 +#define DDRSS3_PHY_1221_DATA 0x00000000 +#define DDRSS3_PHY_1222_DATA 0x00000000 +#define DDRSS3_PHY_1223_DATA 0x00000000 +#define DDRSS3_PHY_1224_DATA 0x00000000 +#define DDRSS3_PHY_1225_DATA 0x00000000 +#define DDRSS3_PHY_1226_DATA 0x00000000 +#define DDRSS3_PHY_1227_DATA 0x00000000 +#define DDRSS3_PHY_1228_DATA 0x00000000 +#define DDRSS3_PHY_1229_DATA 0x00000000 +#define DDRSS3_PHY_1230_DATA 0x00000000 +#define DDRSS3_PHY_1231_DATA 0x00000000 +#define DDRSS3_PHY_1232_DATA 0x00000000 +#define DDRSS3_PHY_1233_DATA 0x00000000 +#define DDRSS3_PHY_1234_DATA 0x00000000 +#define DDRSS3_PHY_1235_DATA 0x00000000 +#define DDRSS3_PHY_1236_DATA 0x00000000 +#define DDRSS3_PHY_1237_DATA 0x00000000 +#define DDRSS3_PHY_1238_DATA 0x00000000 +#define DDRSS3_PHY_1239_DATA 0x00000000 +#define DDRSS3_PHY_1240_DATA 0x00000000 +#define DDRSS3_PHY_1241_DATA 0x00000000 +#define DDRSS3_PHY_1242_DATA 0x00000000 +#define DDRSS3_PHY_1243_DATA 0x00000000 +#define DDRSS3_PHY_1244_DATA 0x00000000 +#define DDRSS3_PHY_1245_DATA 0x00000000 +#define DDRSS3_PHY_1246_DATA 0x00000000 +#define DDRSS3_PHY_1247_DATA 0x00000000 +#define DDRSS3_PHY_1248_DATA 0x00000000 +#define DDRSS3_PHY_1249_DATA 0x00000000 +#define DDRSS3_PHY_1250_DATA 0x00000000 +#define DDRSS3_PHY_1251_DATA 0x00000000 +#define DDRSS3_PHY_1252_DATA 0x00000000 +#define DDRSS3_PHY_1253_DATA 0x00000000 +#define DDRSS3_PHY_1254_DATA 0x00000000 +#define DDRSS3_PHY_1255_DATA 0x00000000 +#define DDRSS3_PHY_1256_DATA 0x00000000 +#define DDRSS3_PHY_1257_DATA 0x00000000 +#define DDRSS3_PHY_1258_DATA 0x00000000 +#define DDRSS3_PHY_1259_DATA 0x00000000 +#define DDRSS3_PHY_1260_DATA 0x00000000 +#define DDRSS3_PHY_1261_DATA 0x00000000 +#define DDRSS3_PHY_1262_DATA 0x00000000 +#define DDRSS3_PHY_1263_DATA 0x00000000 +#define DDRSS3_PHY_1264_DATA 0x00000000 +#define DDRSS3_PHY_1265_DATA 0x00000000 +#define DDRSS3_PHY_1266_DATA 0x00000000 +#define DDRSS3_PHY_1267_DATA 0x00000000 +#define DDRSS3_PHY_1268_DATA 0x00000000 +#define DDRSS3_PHY_1269_DATA 0x00000000 +#define DDRSS3_PHY_1270_DATA 0x00000000 +#define DDRSS3_PHY_1271_DATA 0x00000000 +#define DDRSS3_PHY_1272_DATA 0x00000000 +#define DDRSS3_PHY_1273_DATA 0x00000000 +#define DDRSS3_PHY_1274_DATA 0x00000000 +#define DDRSS3_PHY_1275_DATA 0x00000000 +#define DDRSS3_PHY_1276_DATA 0x00000000 +#define DDRSS3_PHY_1277_DATA 0x00000000 +#define DDRSS3_PHY_1278_DATA 0x00000000 +#define DDRSS3_PHY_1279_DATA 0x00000000 +#define DDRSS3_PHY_1280_DATA 0x00000000 +#define DDRSS3_PHY_1281_DATA 0x00010100 +#define DDRSS3_PHY_1282_DATA 0x00000000 +#define DDRSS3_PHY_1283_DATA 0x00000000 +#define DDRSS3_PHY_1284_DATA 0x00050000 +#define DDRSS3_PHY_1285_DATA 0x04000000 +#define DDRSS3_PHY_1286_DATA 0x00000055 +#define DDRSS3_PHY_1287_DATA 0x00000000 +#define DDRSS3_PHY_1288_DATA 0x00000000 +#define DDRSS3_PHY_1289_DATA 0x00000000 +#define DDRSS3_PHY_1290_DATA 0x00000000 +#define DDRSS3_PHY_1291_DATA 0x00002001 +#define DDRSS3_PHY_1292_DATA 0x0000400F +#define DDRSS3_PHY_1293_DATA 0x50020028 +#define DDRSS3_PHY_1294_DATA 0x01010000 +#define DDRSS3_PHY_1295_DATA 0x80080001 +#define DDRSS3_PHY_1296_DATA 0x10200000 +#define DDRSS3_PHY_1297_DATA 0x00000008 +#define DDRSS3_PHY_1298_DATA 0x00000000 +#define DDRSS3_PHY_1299_DATA 0x01090E00 +#define DDRSS3_PHY_1300_DATA 0x00040101 +#define DDRSS3_PHY_1301_DATA 0x0000010F +#define DDRSS3_PHY_1302_DATA 0x00000000 +#define DDRSS3_PHY_1303_DATA 0x00000064 +#define DDRSS3_PHY_1304_DATA 0x00000000 +#define DDRSS3_PHY_1305_DATA 0x01010000 +#define DDRSS3_PHY_1306_DATA 0x01080402 +#define DDRSS3_PHY_1307_DATA 0x01200F02 +#define DDRSS3_PHY_1308_DATA 0x00194280 +#define DDRSS3_PHY_1309_DATA 0x00000004 +#define DDRSS3_PHY_1310_DATA 0x00042000 +#define DDRSS3_PHY_1311_DATA 0x00000000 +#define DDRSS3_PHY_1312_DATA 0x00000000 +#define DDRSS3_PHY_1313_DATA 0x00000000 +#define DDRSS3_PHY_1314_DATA 0x00000000 +#define DDRSS3_PHY_1315_DATA 0x00000000 +#define DDRSS3_PHY_1316_DATA 0x00000000 +#define DDRSS3_PHY_1317_DATA 0x01000000 +#define DDRSS3_PHY_1318_DATA 0x00000705 +#define DDRSS3_PHY_1319_DATA 0x00000054 +#define DDRSS3_PHY_1320_DATA 0x00030820 +#define DDRSS3_PHY_1321_DATA 0x00010820 +#define DDRSS3_PHY_1322_DATA 0x00010820 +#define DDRSS3_PHY_1323_DATA 0x00010820 +#define DDRSS3_PHY_1324_DATA 0x00010820 +#define DDRSS3_PHY_1325_DATA 0x00010820 +#define DDRSS3_PHY_1326_DATA 0x00010820 +#define DDRSS3_PHY_1327_DATA 0x00010820 +#define DDRSS3_PHY_1328_DATA 0x00010820 +#define DDRSS3_PHY_1329_DATA 0x00000000 +#define DDRSS3_PHY_1330_DATA 0x00000074 +#define DDRSS3_PHY_1331_DATA 0x00000400 +#define DDRSS3_PHY_1332_DATA 0x00000108 +#define DDRSS3_PHY_1333_DATA 0x00000000 +#define DDRSS3_PHY_1334_DATA 0x00000000 +#define DDRSS3_PHY_1335_DATA 0x00000000 +#define DDRSS3_PHY_1336_DATA 0x00000000 +#define DDRSS3_PHY_1337_DATA 0x00000000 +#define DDRSS3_PHY_1338_DATA 0x03000000 +#define DDRSS3_PHY_1339_DATA 0x00000000 +#define DDRSS3_PHY_1340_DATA 0x00000000 +#define DDRSS3_PHY_1341_DATA 0x00000000 +#define DDRSS3_PHY_1342_DATA 0x04102006 +#define DDRSS3_PHY_1343_DATA 0x00041020 +#define DDRSS3_PHY_1344_DATA 0x01C98C98 +#define DDRSS3_PHY_1345_DATA 0x3F400000 +#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS3_PHY_1347_DATA 0x0000001F +#define DDRSS3_PHY_1348_DATA 0x00000000 +#define DDRSS3_PHY_1349_DATA 0x00000000 +#define DDRSS3_PHY_1350_DATA 0x00000000 +#define DDRSS3_PHY_1351_DATA 0x00010000 +#define DDRSS3_PHY_1352_DATA 0x00000000 +#define DDRSS3_PHY_1353_DATA 0x00000000 +#define DDRSS3_PHY_1354_DATA 0x00000000 +#define DDRSS3_PHY_1355_DATA 0x00000000 +#define DDRSS3_PHY_1356_DATA 0x76543210 +#define DDRSS3_PHY_1357_DATA 0x00010198 +#define DDRSS3_PHY_1358_DATA 0x00000000 +#define DDRSS3_PHY_1359_DATA 0x00000000 +#define DDRSS3_PHY_1360_DATA 0x00000000 +#define DDRSS3_PHY_1361_DATA 0x00040700 +#define DDRSS3_PHY_1362_DATA 0x00000000 +#define DDRSS3_PHY_1363_DATA 0x00000000 +#define DDRSS3_PHY_1364_DATA 0x00000000 +#define DDRSS3_PHY_1365_DATA 0x00000000 +#define DDRSS3_PHY_1366_DATA 0x00000000 +#define DDRSS3_PHY_1367_DATA 0x00000002 +#define DDRSS3_PHY_1368_DATA 0x00000000 +#define DDRSS3_PHY_1369_DATA 0x00000000 +#define DDRSS3_PHY_1370_DATA 0x00000000 +#define DDRSS3_PHY_1371_DATA 0x00000000 +#define DDRSS3_PHY_1372_DATA 0x00000000 +#define DDRSS3_PHY_1373_DATA 0x00000000 +#define DDRSS3_PHY_1374_DATA 0x00080000 +#define DDRSS3_PHY_1375_DATA 0x000007FF +#define DDRSS3_PHY_1376_DATA 0x00000000 +#define DDRSS3_PHY_1377_DATA 0x00000000 +#define DDRSS3_PHY_1378_DATA 0x00000000 +#define DDRSS3_PHY_1379_DATA 0x00000000 +#define DDRSS3_PHY_1380_DATA 0x00000000 +#define DDRSS3_PHY_1381_DATA 0x00000000 +#define DDRSS3_PHY_1382_DATA 0x000FFFFF +#define DDRSS3_PHY_1383_DATA 0x000FFFFF +#define DDRSS3_PHY_1384_DATA 0x0000FFFF +#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS3_PHY_1386_DATA 0x030FFFFF +#define DDRSS3_PHY_1387_DATA 0x01FFFFFF +#define DDRSS3_PHY_1388_DATA 0x0000FFFF +#define DDRSS3_PHY_1389_DATA 0x00000000 +#define DDRSS3_PHY_1390_DATA 0x00000000 +#define DDRSS3_PHY_1391_DATA 0x00000000 +#define DDRSS3_PHY_1392_DATA 0x00000000 +#define DDRSS3_PHY_1393_DATA 0x0001F7C0 +#define DDRSS3_PHY_1394_DATA 0x00000003 +#define DDRSS3_PHY_1395_DATA 0x00000000 +#define DDRSS3_PHY_1396_DATA 0x00001142 +#define DDRSS3_PHY_1397_DATA 0x040207AB +#define DDRSS3_PHY_1398_DATA 0x01000080 +#define DDRSS3_PHY_1399_DATA 0x03900390 +#define DDRSS3_PHY_1400_DATA 0x03900390 +#define DDRSS3_PHY_1401_DATA 0x00000390 +#define DDRSS3_PHY_1402_DATA 0x00000390 +#define DDRSS3_PHY_1403_DATA 0x00000390 +#define DDRSS3_PHY_1404_DATA 0x00000390 +#define DDRSS3_PHY_1405_DATA 0x00000005 +#define DDRSS3_PHY_1406_DATA 0x01813FCC +#define DDRSS3_PHY_1407_DATA 0x000000CC +#define DDRSS3_PHY_1408_DATA 0x0C000DFF +#define DDRSS3_PHY_1409_DATA 0x30000DFF +#define DDRSS3_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1411_DATA 0x000100F0 +#define DDRSS3_PHY_1412_DATA 0x780DFFCC +#define DDRSS3_PHY_1413_DATA 0x00007E31 +#define DDRSS3_PHY_1414_DATA 0x000CBF11 +#define DDRSS3_PHY_1415_DATA 0x01990010 +#define DDRSS3_PHY_1416_DATA 0x000CBF11 +#define DDRSS3_PHY_1417_DATA 0x01990010 +#define DDRSS3_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1419_DATA 0x00EF00F0 +#define DDRSS3_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1421_DATA 0x01FF00F0 +#define DDRSS3_PHY_1422_DATA 0x20040006 diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts index e8362647c5d..036d3d9d250 100644 --- a/arch/arm/dts/k3-am69-r5-sk.dts +++ b/arch/arm/dts/k3-am69-r5-sk.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-am69-sk.dts" -#include "k3-j784s4-ddr-evm-lp4-4266.dtsi" +#include "k3-am69-ddr-sk-lp4-4266.dtsi" #include "k3-j784s4-ddr.dtsi" #include "k3-am69-sk-u-boot.dtsi" #include "k3-j784s4-r5.dtsi" From 54fb646ca42444f0756a6f1f4ecff7d027a70a96 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 3 Nov 2025 12:40:34 +0530 Subject: [PATCH 27/65] arm: dts: k3-j742s2: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for J742S2 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar Signed-off-by: Neha Malcom Francis --- arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi | 4872 +----------------- 1 file changed, 263 insertions(+), 4609 deletions(-) diff --git a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi index a64d19b05f3..2cd21efbf93 100644 --- a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi @@ -1,10 +1,23 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.0 - */ + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 15:02:20 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -12,9 +25,18 @@ #define MULTI_DDR_CFG_INTRLV_GRAN 0 #define MULTI_DDR_CFG_INTRLV_SIZE 11 #define MULTI_DDR_CFG_ECC_ENABLE 0 -#define MULTI_DDR_CFG_HYBRID_SELECT 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 2 #define MULTI_DDR_CFG_EMIFS_ACTIVE 3 +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000003 +#define DDR_REG1_SIZE_LSB 0x80000000 + + #define DDRSS0_CTL_00_DATA 0x00000B00 #define DDRSS0_CTL_01_DATA 0x00000000 #define DDRSS0_CTL_02_DATA 0x00000000 @@ -35,7 +57,7 @@ #define DDRSS0_CTL_17_DATA 0x00000005 #define DDRSS0_CTL_18_DATA 0x000010A9 #define DDRSS0_CTL_19_DATA 0x01010000 -#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_20_DATA 0x01011001 #define DDRSS0_CTL_21_DATA 0x02010000 #define DDRSS0_CTL_22_DATA 0x00020100 #define DDRSS0_CTL_23_DATA 0x0000000B @@ -50,7 +72,7 @@ #define DDRSS0_CTL_32_DATA 0x00000000 #define DDRSS0_CTL_33_DATA 0x00000000 #define DDRSS0_CTL_34_DATA 0x040C0000 -#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_35_DATA 0x12501250 #define DDRSS0_CTL_36_DATA 0x00050804 #define DDRSS0_CTL_37_DATA 0x09040008 #define DDRSS0_CTL_38_DATA 0x15000204 @@ -59,33 +81,33 @@ #define DDRSS0_CTL_41_DATA 0x1760008B #define DDRSS0_CTL_42_DATA 0x2000422B #define DDRSS0_CTL_43_DATA 0x000A0A09 -#define DDRSS0_CTL_44_DATA 0x0400078A +#define DDRSS0_CTL_44_DATA 0x040003C5 #define DDRSS0_CTL_45_DATA 0x1E161104 -#define DDRSS0_CTL_46_DATA 0x10012458 +#define DDRSS0_CTL_46_DATA 0x1000922C #define DDRSS0_CTL_47_DATA 0x1E161110 -#define DDRSS0_CTL_48_DATA 0x10012458 +#define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 -#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_50_DATA 0x2C060500 #define DDRSS0_CTL_51_DATA 0x08292C29 #define DDRSS0_CTL_52_DATA 0x14000E0A #define DDRSS0_CTL_53_DATA 0x04010A0A #define DDRSS0_CTL_54_DATA 0x01010004 -#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_55_DATA 0x0454540A #define DDRSS0_CTL_56_DATA 0x04313104 #define DDRSS0_CTL_57_DATA 0x00003131 #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x000000CE +#define DDRSS0_CTL_61_DATA 0x00000068 #define DDRSS0_CTL_62_DATA 0x0000032B -#define DDRSS0_CTL_63_DATA 0x00002073 +#define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B -#define DDRSS0_CTL_65_DATA 0x00002073 +#define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 -#define DDRSS0_CTL_68_DATA 0x00CB0012 -#define DDRSS0_CTL_69_DATA 0x00CB0408 -#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 #define DDRSS0_CTL_71_DATA 0x00120103 #define DDRSS0_CTL_72_DATA 0x00100005 #define DDRSS0_CTL_73_DATA 0x2F080010 @@ -117,27 +139,27 @@ #define DDRSS0_CTL_99_DATA 0x00000000 #define DDRSS0_CTL_100_DATA 0x00040005 #define DDRSS0_CTL_101_DATA 0x00000000 -#define DDRSS0_CTL_102_DATA 0x00003380 -#define DDRSS0_CTL_103_DATA 0x00003380 -#define DDRSS0_CTL_104_DATA 0x00003380 -#define DDRSS0_CTL_105_DATA 0x00003380 -#define DDRSS0_CTL_106_DATA 0x00003380 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 #define DDRSS0_CTL_107_DATA 0x00000000 -#define DDRSS0_CTL_108_DATA 0x000005A2 -#define DDRSS0_CTL_109_DATA 0x00081CC0 -#define DDRSS0_CTL_110_DATA 0x00081CC0 -#define DDRSS0_CTL_111_DATA 0x00081CC0 -#define DDRSS0_CTL_112_DATA 0x00081CC0 -#define DDRSS0_CTL_113_DATA 0x00081CC0 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 #define DDRSS0_CTL_114_DATA 0x00000000 -#define DDRSS0_CTL_115_DATA 0x0000E325 -#define DDRSS0_CTL_116_DATA 0x00081CC0 -#define DDRSS0_CTL_117_DATA 0x00081CC0 -#define DDRSS0_CTL_118_DATA 0x00081CC0 -#define DDRSS0_CTL_119_DATA 0x00081CC0 -#define DDRSS0_CTL_120_DATA 0x00081CC0 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 #define DDRSS0_CTL_121_DATA 0x00000000 -#define DDRSS0_CTL_122_DATA 0x0000E325 +#define DDRSS0_CTL_122_DATA 0x00007173 #define DDRSS0_CTL_123_DATA 0x00000000 #define DDRSS0_CTL_124_DATA 0x00000000 #define DDRSS0_CTL_125_DATA 0x00000000 @@ -191,22 +213,22 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 #define DDRSS0_CTL_178_DATA 0x35000000 #define DDRSS0_CTL_179_DATA 0x27270035 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 #define DDRSS0_CTL_185_DATA 0x00000000 #define DDRSS0_CTL_186_DATA 0x00353500 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 #define DDRSS0_CTL_190_DATA 0x00000020 -#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_191_DATA 0x01000000 #define DDRSS0_CTL_192_DATA 0x00000001 #define DDRSS0_CTL_193_DATA 0x00000000 #define DDRSS0_CTL_194_DATA 0x01000000 @@ -306,14 +328,14 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00010101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 #define DDRSS0_CTL_295_DATA 0x00000000 #define DDRSS0_CTL_296_DATA 0x00000000 -#define DDRSS0_CTL_297_DATA 0x00000000 -#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF #define DDRSS0_CTL_299_DATA 0x00000000 #define DDRSS0_CTL_300_DATA 0x00000000 #define DDRSS0_CTL_301_DATA 0x00000000 @@ -334,7 +356,7 @@ #define DDRSS0_CTL_316_DATA 0x01010001 #define DDRSS0_CTL_317_DATA 0x00010101 #define DDRSS0_CTL_318_DATA 0x050A0A03 -#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_319_DATA 0x10082323 #define DDRSS0_CTL_320_DATA 0x00090310 #define DDRSS0_CTL_321_DATA 0x0B0C030F #define DDRSS0_CTL_322_DATA 0x0B0C0306 @@ -404,30 +426,30 @@ #define DDRSS0_CTL_386_DATA 0x00000000 #define DDRSS0_CTL_387_DATA 0x3A3A1B00 #define DDRSS0_CTL_388_DATA 0x000A0000 -#define DDRSS0_CTL_389_DATA 0x0000019C +#define DDRSS0_CTL_389_DATA 0x000000C6 #define DDRSS0_CTL_390_DATA 0x00000200 #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x000004D4 -#define DDRSS0_CTL_395_DATA 0x00001018 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 -#define DDRSS0_CTL_397_DATA 0x000040E6 +#define DDRSS0_CTL_397_DATA 0x0000206A #define DDRSS0_CTL_398_DATA 0x00000200 #define DDRSS0_CTL_399_DATA 0x00000200 #define DDRSS0_CTL_400_DATA 0x00000200 #define DDRSS0_CTL_401_DATA 0x00000200 -#define DDRSS0_CTL_402_DATA 0x0000C2B2 -#define DDRSS0_CTL_403_DATA 0x000288FC -#define DDRSS0_CTL_404_DATA 0x00000E15 -#define DDRSS0_CTL_405_DATA 0x000040E6 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 #define DDRSS0_CTL_408_DATA 0x00000200 #define DDRSS0_CTL_409_DATA 0x00000200 -#define DDRSS0_CTL_410_DATA 0x0000C2B2 -#define DDRSS0_CTL_411_DATA 0x000288FC -#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 #define DDRSS0_CTL_415_DATA 0x00000000 @@ -444,7 +466,7 @@ #define DDRSS0_CTL_426_DATA 0x00000000 #define DDRSS0_CTL_427_DATA 0x02000000 #define DDRSS0_CTL_428_DATA 0x01000404 -#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_429_DATA 0x0B220B22 #define DDRSS0_CTL_430_DATA 0x00000105 #define DDRSS0_CTL_431_DATA 0x00010101 #define DDRSS0_CTL_432_DATA 0x00010101 @@ -487,8 +509,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -536,18 +558,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 #define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_67_DATA 0x0002020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -636,37 +658,37 @@ #define DDRSS0_PI_158_DATA 0x00000000 #define DDRSS0_PI_159_DATA 0x00000401 #define DDRSS0_PI_160_DATA 0x00000000 -#define DDRSS0_PI_161_DATA 0x00010000 -#define DDRSS0_PI_162_DATA 0x00000000 -#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 #define DDRSS0_PI_164_DATA 0x00000034 -#define DDRSS0_PI_165_DATA 0x00000064 -#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 #define DDRSS0_PI_167_DATA 0x02000200 -#define DDRSS0_PI_168_DATA 0x48120C04 -#define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x000000CE +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 #define DDRSS0_PI_171_DATA 0x0000032B -#define DDRSS0_PI_172_DATA 0x00002073 +#define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B -#define DDRSS0_PI_174_DATA 0x04002073 +#define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 -#define DDRSS0_PI_185_DATA 0x15040000 -#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 #define DDRSS0_PI_187_DATA 0x00040402 #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -674,8 +696,8 @@ #define DDRSS0_PI_196_DATA 0x02170100 #define DDRSS0_PI_197_DATA 0x01000217 #define DDRSS0_PI_198_DATA 0x02170217 -#define DDRSS0_PI_199_DATA 0x32103200 -#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B #define DDRSS0_PI_201_DATA 0x0A070601 #define DDRSS0_PI_202_DATA 0x1F130A0D #define DDRSS0_PI_203_DATA 0x1F130A14 @@ -687,29 +709,29 @@ #define DDRSS0_PI_209_DATA 0x00240216 #define DDRSS0_PI_210_DATA 0x00110216 #define DDRSS0_PI_211_DATA 0x32000056 -#define DDRSS0_PI_212_DATA 0x00000301 -#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 -#define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 -#define DDRSS0_PI_218_DATA 0x04010504 -#define DDRSS0_PI_219_DATA 0x040006C9 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A #define DDRSS0_PI_222_DATA 0x00002918 -#define DDRSS0_PI_223_DATA 0x6001071C +#define DDRSS0_PI_223_DATA 0x6000838E #define DDRSS0_PI_224_DATA 0x1E202008 #define DDRSS0_PI_225_DATA 0x2C311116 #define DDRSS0_PI_226_DATA 0x00002918 -#define DDRSS0_PI_227_DATA 0x6001071C +#define DDRSS0_PI_227_DATA 0x6000838E #define DDRSS0_PI_228_DATA 0x1E202008 -#define DDRSS0_PI_229_DATA 0x00019C16 -#define DDRSS0_PI_230_DATA 0x00001018 -#define DDRSS0_PI_231_DATA 0x000040E6 -#define DDRSS0_PI_232_DATA 0x000288FC -#define DDRSS0_PI_233_DATA 0x000040E6 -#define DDRSS0_PI_234_DATA 0x000288FC +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 #define DDRSS0_PI_235_DATA 0x033B0016 #define DDRSS0_PI_236_DATA 0x0303033B #define DDRSS0_PI_237_DATA 0x002AF803 @@ -750,29 +772,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00F30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x35333FF4 +#define DDRSS0_PI_277_DATA 0x35F33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x35333FF4 +#define DDRSS0_PI_279_DATA 0x35F33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00F30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x35333FF4 +#define DDRSS0_PI_283_DATA 0x35F33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x35333FF4 +#define DDRSS0_PI_285_DATA 0x35F33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00F30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x35333FF4 +#define DDRSS0_PI_289_DATA 0x35F33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x35333FF4 +#define DDRSS0_PI_291_DATA 0x35F33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00F30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x35333FF4 +#define DDRSS0_PI_295_DATA 0x35F33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x35333FF4 +#define DDRSS0_PI_297_DATA 0x35F33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -788,7 +810,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -807,7 +829,7 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F +#define DDRSS0_PHY_31_DATA 0x00000F08 #define DDRSS0_PHY_32_DATA 0x10400000 #define DDRSS0_PHY_33_DATA 0x0C002006 #define DDRSS0_PHY_34_DATA 0x00000000 @@ -876,9 +898,9 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 -#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 #define DDRSS0_PHY_103_DATA 0x10001000 #define DDRSS0_PHY_104_DATA 0x0C083E42 #define DDRSS0_PHY_105_DATA 0x0F0C3701 @@ -1044,7 +1066,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1063,7 +1085,7 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F +#define DDRSS0_PHY_287_DATA 0x00000F08 #define DDRSS0_PHY_288_DATA 0x10400000 #define DDRSS0_PHY_289_DATA 0x0C002006 #define DDRSS0_PHY_290_DATA 0x00000000 @@ -1132,9 +1154,9 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 -#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 #define DDRSS0_PHY_359_DATA 0x10001000 #define DDRSS0_PHY_360_DATA 0x0C083E42 #define DDRSS0_PHY_361_DATA 0x0F0C3701 @@ -1300,7 +1322,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1319,7 +1341,7 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F +#define DDRSS0_PHY_543_DATA 0x00000F08 #define DDRSS0_PHY_544_DATA 0x10400000 #define DDRSS0_PHY_545_DATA 0x0C002006 #define DDRSS0_PHY_546_DATA 0x00000000 @@ -1388,9 +1410,9 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 -#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 #define DDRSS0_PHY_615_DATA 0x10001000 #define DDRSS0_PHY_616_DATA 0x0C083E42 #define DDRSS0_PHY_617_DATA 0x0F0C3701 @@ -1556,7 +1578,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1575,7 +1597,7 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F +#define DDRSS0_PHY_799_DATA 0x00000F08 #define DDRSS0_PHY_800_DATA 0x10400000 #define DDRSS0_PHY_801_DATA 0x0C002006 #define DDRSS0_PHY_802_DATA 0x00000000 @@ -1644,9 +1666,9 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 -#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 #define DDRSS0_PHY_871_DATA 0x10001000 #define DDRSS0_PHY_872_DATA 0x0C083E42 #define DDRSS0_PHY_873_DATA 0x0F0C3701 @@ -1831,7 +1853,7 @@ #define DDRSS0_PHY_1052_DATA 0x00000033 #define DDRSS0_PHY_1053_DATA 0x00543210 #define DDRSS0_PHY_1054_DATA 0x003F0000 -#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1055_DATA 0x000F3F3F #define DDRSS0_PHY_1056_DATA 0x20202003 #define DDRSS0_PHY_1057_DATA 0x00202020 #define DDRSS0_PHY_1058_DATA 0x20008008 @@ -2079,7 +2101,7 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 @@ -2173,7 +2195,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2220,7 +2242,7 @@ #define DDRSS1_CTL_17_DATA 0x00000005 #define DDRSS1_CTL_18_DATA 0x000010A9 #define DDRSS1_CTL_19_DATA 0x01010000 -#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_20_DATA 0x01011001 #define DDRSS1_CTL_21_DATA 0x02010000 #define DDRSS1_CTL_22_DATA 0x00020100 #define DDRSS1_CTL_23_DATA 0x0000000B @@ -2235,7 +2257,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_35_DATA 0x12501250 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2244,33 +2266,33 @@ #define DDRSS1_CTL_41_DATA 0x1760008B #define DDRSS1_CTL_42_DATA 0x2000422B #define DDRSS1_CTL_43_DATA 0x000A0A09 -#define DDRSS1_CTL_44_DATA 0x0400078A +#define DDRSS1_CTL_44_DATA 0x040003C5 #define DDRSS1_CTL_45_DATA 0x1E161104 -#define DDRSS1_CTL_46_DATA 0x10012458 +#define DDRSS1_CTL_46_DATA 0x1000922C #define DDRSS1_CTL_47_DATA 0x1E161110 -#define DDRSS1_CTL_48_DATA 0x10012458 +#define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 -#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_50_DATA 0x2C060500 #define DDRSS1_CTL_51_DATA 0x08292C29 #define DDRSS1_CTL_52_DATA 0x14000E0A #define DDRSS1_CTL_53_DATA 0x04010A0A #define DDRSS1_CTL_54_DATA 0x01010004 -#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_55_DATA 0x0454540A #define DDRSS1_CTL_56_DATA 0x04313104 #define DDRSS1_CTL_57_DATA 0x00003131 #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x000000CE +#define DDRSS1_CTL_61_DATA 0x00000068 #define DDRSS1_CTL_62_DATA 0x0000032B -#define DDRSS1_CTL_63_DATA 0x00002073 +#define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B -#define DDRSS1_CTL_65_DATA 0x00002073 +#define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 -#define DDRSS1_CTL_68_DATA 0x00CB0012 -#define DDRSS1_CTL_69_DATA 0x00CB0408 -#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 #define DDRSS1_CTL_71_DATA 0x00120103 #define DDRSS1_CTL_72_DATA 0x00100005 #define DDRSS1_CTL_73_DATA 0x2F080010 @@ -2302,27 +2324,27 @@ #define DDRSS1_CTL_99_DATA 0x00000000 #define DDRSS1_CTL_100_DATA 0x00040005 #define DDRSS1_CTL_101_DATA 0x00000000 -#define DDRSS1_CTL_102_DATA 0x00003380 -#define DDRSS1_CTL_103_DATA 0x00003380 -#define DDRSS1_CTL_104_DATA 0x00003380 -#define DDRSS1_CTL_105_DATA 0x00003380 -#define DDRSS1_CTL_106_DATA 0x00003380 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 #define DDRSS1_CTL_107_DATA 0x00000000 -#define DDRSS1_CTL_108_DATA 0x000005A2 -#define DDRSS1_CTL_109_DATA 0x00081CC0 -#define DDRSS1_CTL_110_DATA 0x00081CC0 -#define DDRSS1_CTL_111_DATA 0x00081CC0 -#define DDRSS1_CTL_112_DATA 0x00081CC0 -#define DDRSS1_CTL_113_DATA 0x00081CC0 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 #define DDRSS1_CTL_114_DATA 0x00000000 -#define DDRSS1_CTL_115_DATA 0x0000E325 -#define DDRSS1_CTL_116_DATA 0x00081CC0 -#define DDRSS1_CTL_117_DATA 0x00081CC0 -#define DDRSS1_CTL_118_DATA 0x00081CC0 -#define DDRSS1_CTL_119_DATA 0x00081CC0 -#define DDRSS1_CTL_120_DATA 0x00081CC0 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 #define DDRSS1_CTL_121_DATA 0x00000000 -#define DDRSS1_CTL_122_DATA 0x0000E325 +#define DDRSS1_CTL_122_DATA 0x00007173 #define DDRSS1_CTL_123_DATA 0x00000000 #define DDRSS1_CTL_124_DATA 0x00000000 #define DDRSS1_CTL_125_DATA 0x00000000 @@ -2376,22 +2398,22 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 #define DDRSS1_CTL_178_DATA 0x35000000 #define DDRSS1_CTL_179_DATA 0x27270035 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 #define DDRSS1_CTL_185_DATA 0x00000000 #define DDRSS1_CTL_186_DATA 0x00353500 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 #define DDRSS1_CTL_190_DATA 0x00000020 -#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_191_DATA 0x01000000 #define DDRSS1_CTL_192_DATA 0x00000001 #define DDRSS1_CTL_193_DATA 0x00000000 #define DDRSS1_CTL_194_DATA 0x01000000 @@ -2491,14 +2513,14 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00010101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 #define DDRSS1_CTL_295_DATA 0x00000000 #define DDRSS1_CTL_296_DATA 0x00000000 -#define DDRSS1_CTL_297_DATA 0x00000000 -#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF #define DDRSS1_CTL_299_DATA 0x00000000 #define DDRSS1_CTL_300_DATA 0x00000000 #define DDRSS1_CTL_301_DATA 0x00000000 @@ -2519,7 +2541,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_319_DATA 0x10082323 #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2589,30 +2611,30 @@ #define DDRSS1_CTL_386_DATA 0x00000000 #define DDRSS1_CTL_387_DATA 0x3A3A1B00 #define DDRSS1_CTL_388_DATA 0x000A0000 -#define DDRSS1_CTL_389_DATA 0x0000019C +#define DDRSS1_CTL_389_DATA 0x000000C6 #define DDRSS1_CTL_390_DATA 0x00000200 #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x000004D4 -#define DDRSS1_CTL_395_DATA 0x00001018 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 -#define DDRSS1_CTL_397_DATA 0x000040E6 +#define DDRSS1_CTL_397_DATA 0x0000206A #define DDRSS1_CTL_398_DATA 0x00000200 #define DDRSS1_CTL_399_DATA 0x00000200 #define DDRSS1_CTL_400_DATA 0x00000200 #define DDRSS1_CTL_401_DATA 0x00000200 -#define DDRSS1_CTL_402_DATA 0x0000C2B2 -#define DDRSS1_CTL_403_DATA 0x000288FC -#define DDRSS1_CTL_404_DATA 0x00000E15 -#define DDRSS1_CTL_405_DATA 0x000040E6 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 #define DDRSS1_CTL_408_DATA 0x00000200 #define DDRSS1_CTL_409_DATA 0x00000200 -#define DDRSS1_CTL_410_DATA 0x0000C2B2 -#define DDRSS1_CTL_411_DATA 0x000288FC -#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2629,7 +2651,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_429_DATA 0x0B220B22 #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2672,8 +2694,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2721,18 +2743,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2821,37 +2843,37 @@ #define DDRSS1_PI_158_DATA 0x00000000 #define DDRSS1_PI_159_DATA 0x00000401 #define DDRSS1_PI_160_DATA 0x00000000 -#define DDRSS1_PI_161_DATA 0x00010000 -#define DDRSS1_PI_162_DATA 0x00000000 -#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000064 -#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x48120C04 -#define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x000000CE +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 #define DDRSS1_PI_171_DATA 0x0000032B -#define DDRSS1_PI_172_DATA 0x00002073 +#define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B -#define DDRSS1_PI_174_DATA 0x04002073 +#define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x15040000 -#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2859,8 +2881,8 @@ #define DDRSS1_PI_196_DATA 0x02170100 #define DDRSS1_PI_197_DATA 0x01000217 #define DDRSS1_PI_198_DATA 0x02170217 -#define DDRSS1_PI_199_DATA 0x32103200 -#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B #define DDRSS1_PI_201_DATA 0x0A070601 #define DDRSS1_PI_202_DATA 0x1F130A0D #define DDRSS1_PI_203_DATA 0x1F130A14 @@ -2872,29 +2894,29 @@ #define DDRSS1_PI_209_DATA 0x00240216 #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 -#define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 -#define DDRSS1_PI_218_DATA 0x04010504 -#define DDRSS1_PI_219_DATA 0x040006C9 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A #define DDRSS1_PI_222_DATA 0x00002918 -#define DDRSS1_PI_223_DATA 0x6001071C +#define DDRSS1_PI_223_DATA 0x6000838E #define DDRSS1_PI_224_DATA 0x1E202008 #define DDRSS1_PI_225_DATA 0x2C311116 #define DDRSS1_PI_226_DATA 0x00002918 -#define DDRSS1_PI_227_DATA 0x6001071C +#define DDRSS1_PI_227_DATA 0x6000838E #define DDRSS1_PI_228_DATA 0x1E202008 -#define DDRSS1_PI_229_DATA 0x00019C16 -#define DDRSS1_PI_230_DATA 0x00001018 -#define DDRSS1_PI_231_DATA 0x000040E6 -#define DDRSS1_PI_232_DATA 0x000288FC -#define DDRSS1_PI_233_DATA 0x000040E6 -#define DDRSS1_PI_234_DATA 0x000288FC +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 #define DDRSS1_PI_235_DATA 0x033B0016 #define DDRSS1_PI_236_DATA 0x0303033B #define DDRSS1_PI_237_DATA 0x002AF803 @@ -2935,29 +2957,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00F30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x35333FF4 +#define DDRSS1_PI_277_DATA 0x35F33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x35333FF4 +#define DDRSS1_PI_279_DATA 0x35F33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00F30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x35333FF4 +#define DDRSS1_PI_283_DATA 0x35F33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x35333FF4 +#define DDRSS1_PI_285_DATA 0x35F33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00F30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x35333FF4 +#define DDRSS1_PI_289_DATA 0x35F33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x35333FF4 +#define DDRSS1_PI_291_DATA 0x35F33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00F30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x35333FF4 +#define DDRSS1_PI_295_DATA 0x35F33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x35333FF4 +#define DDRSS1_PI_297_DATA 0x35F33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2973,7 +2995,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2992,7 +3014,7 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F +#define DDRSS1_PHY_31_DATA 0x00000F08 #define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 @@ -3061,9 +3083,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3229,7 +3251,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3248,7 +3270,7 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F +#define DDRSS1_PHY_287_DATA 0x00000F08 #define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 @@ -3317,9 +3339,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3485,7 +3507,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3504,7 +3526,7 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F +#define DDRSS1_PHY_543_DATA 0x00000F08 #define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 @@ -3573,9 +3595,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3741,7 +3763,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3760,7 +3782,7 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F +#define DDRSS1_PHY_799_DATA 0x00000F08 #define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 @@ -3829,9 +3851,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -4016,7 +4038,7 @@ #define DDRSS1_PHY_1052_DATA 0x00000033 #define DDRSS1_PHY_1053_DATA 0x00543210 #define DDRSS1_PHY_1054_DATA 0x003F0000 -#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1055_DATA 0x000F3F3F #define DDRSS1_PHY_1056_DATA 0x20202003 #define DDRSS1_PHY_1057_DATA 0x00202020 #define DDRSS1_PHY_1058_DATA 0x20008008 @@ -4264,7 +4286,7 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 @@ -4358,7 +4380,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 @@ -4385,4372 +4407,4 @@ #define DDRSS1_PHY_1421_DATA 0x01FF00F0 #define DDRSS1_PHY_1422_DATA 0x20040006 -#define DDRSS2_CTL_00_DATA 0x00000B00 -#define DDRSS2_CTL_01_DATA 0x00000000 -#define DDRSS2_CTL_02_DATA 0x00000000 -#define DDRSS2_CTL_03_DATA 0x00000000 -#define DDRSS2_CTL_04_DATA 0x00000000 -#define DDRSS2_CTL_05_DATA 0x00000000 -#define DDRSS2_CTL_06_DATA 0x00000000 -#define DDRSS2_CTL_07_DATA 0x00002AF8 -#define DDRSS2_CTL_08_DATA 0x0001ADAF -#define DDRSS2_CTL_09_DATA 0x00000005 -#define DDRSS2_CTL_10_DATA 0x0000006E -#define DDRSS2_CTL_11_DATA 0x000681C8 -#define DDRSS2_CTL_12_DATA 0x004111C9 -#define DDRSS2_CTL_13_DATA 0x00000005 -#define DDRSS2_CTL_14_DATA 0x000010A9 -#define DDRSS2_CTL_15_DATA 0x000681C8 -#define DDRSS2_CTL_16_DATA 0x004111C9 -#define DDRSS2_CTL_17_DATA 0x00000005 -#define DDRSS2_CTL_18_DATA 0x000010A9 -#define DDRSS2_CTL_19_DATA 0x01010000 -#define DDRSS2_CTL_20_DATA 0x02011001 -#define DDRSS2_CTL_21_DATA 0x02010000 -#define DDRSS2_CTL_22_DATA 0x00020100 -#define DDRSS2_CTL_23_DATA 0x0000000B -#define DDRSS2_CTL_24_DATA 0x0000001C -#define DDRSS2_CTL_25_DATA 0x00000000 -#define DDRSS2_CTL_26_DATA 0x00000000 -#define DDRSS2_CTL_27_DATA 0x03020200 -#define DDRSS2_CTL_28_DATA 0x00005656 -#define DDRSS2_CTL_29_DATA 0x00100000 -#define DDRSS2_CTL_30_DATA 0x00000000 -#define DDRSS2_CTL_31_DATA 0x00000000 -#define DDRSS2_CTL_32_DATA 0x00000000 -#define DDRSS2_CTL_33_DATA 0x00000000 -#define DDRSS2_CTL_34_DATA 0x040C0000 -#define DDRSS2_CTL_35_DATA 0x12481248 -#define DDRSS2_CTL_36_DATA 0x00050804 -#define DDRSS2_CTL_37_DATA 0x09040008 -#define DDRSS2_CTL_38_DATA 0x15000204 -#define DDRSS2_CTL_39_DATA 0x1760008B -#define DDRSS2_CTL_40_DATA 0x1500422B -#define DDRSS2_CTL_41_DATA 0x1760008B -#define DDRSS2_CTL_42_DATA 0x2000422B -#define DDRSS2_CTL_43_DATA 0x000A0A09 -#define DDRSS2_CTL_44_DATA 0x0400078A -#define DDRSS2_CTL_45_DATA 0x1E161104 -#define DDRSS2_CTL_46_DATA 0x10012458 -#define DDRSS2_CTL_47_DATA 0x1E161110 -#define DDRSS2_CTL_48_DATA 0x10012458 -#define DDRSS2_CTL_49_DATA 0x02030410 -#define DDRSS2_CTL_50_DATA 0x2C040500 -#define DDRSS2_CTL_51_DATA 0x08292C29 -#define DDRSS2_CTL_52_DATA 0x14000E0A -#define DDRSS2_CTL_53_DATA 0x04010A0A -#define DDRSS2_CTL_54_DATA 0x01010004 -#define DDRSS2_CTL_55_DATA 0x04545408 -#define DDRSS2_CTL_56_DATA 0x04313104 -#define DDRSS2_CTL_57_DATA 0x00003131 -#define DDRSS2_CTL_58_DATA 0x00010100 -#define DDRSS2_CTL_59_DATA 0x03010000 -#define DDRSS2_CTL_60_DATA 0x00001508 -#define DDRSS2_CTL_61_DATA 0x000000CE -#define DDRSS2_CTL_62_DATA 0x0000032B -#define DDRSS2_CTL_63_DATA 0x00002073 -#define DDRSS2_CTL_64_DATA 0x0000032B -#define DDRSS2_CTL_65_DATA 0x00002073 -#define DDRSS2_CTL_66_DATA 0x00000005 -#define DDRSS2_CTL_67_DATA 0x00050000 -#define DDRSS2_CTL_68_DATA 0x00CB0012 -#define DDRSS2_CTL_69_DATA 0x00CB0408 -#define DDRSS2_CTL_70_DATA 0x00400408 -#define DDRSS2_CTL_71_DATA 0x00120103 -#define DDRSS2_CTL_72_DATA 0x00100005 -#define DDRSS2_CTL_73_DATA 0x2F080010 -#define DDRSS2_CTL_74_DATA 0x0505012F -#define DDRSS2_CTL_75_DATA 0x0401030A -#define DDRSS2_CTL_76_DATA 0x041E100B -#define DDRSS2_CTL_77_DATA 0x100B0401 -#define DDRSS2_CTL_78_DATA 0x0001041E -#define DDRSS2_CTL_79_DATA 0x00160016 -#define DDRSS2_CTL_80_DATA 0x033B033B -#define DDRSS2_CTL_81_DATA 0x033B033B -#define DDRSS2_CTL_82_DATA 0x03050505 -#define DDRSS2_CTL_83_DATA 0x03010303 -#define DDRSS2_CTL_84_DATA 0x200B100B -#define DDRSS2_CTL_85_DATA 0x04041004 -#define DDRSS2_CTL_86_DATA 0x200B100B -#define DDRSS2_CTL_87_DATA 0x04041004 -#define DDRSS2_CTL_88_DATA 0x03010000 -#define DDRSS2_CTL_89_DATA 0x00010000 -#define DDRSS2_CTL_90_DATA 0x00000000 -#define DDRSS2_CTL_91_DATA 0x00000000 -#define DDRSS2_CTL_92_DATA 0x01000000 -#define DDRSS2_CTL_93_DATA 0x80104002 -#define DDRSS2_CTL_94_DATA 0x00000000 -#define DDRSS2_CTL_95_DATA 0x00040005 -#define DDRSS2_CTL_96_DATA 0x00000000 -#define DDRSS2_CTL_97_DATA 0x00050000 -#define DDRSS2_CTL_98_DATA 0x00000004 -#define DDRSS2_CTL_99_DATA 0x00000000 -#define DDRSS2_CTL_100_DATA 0x00040005 -#define DDRSS2_CTL_101_DATA 0x00000000 -#define DDRSS2_CTL_102_DATA 0x00003380 -#define DDRSS2_CTL_103_DATA 0x00003380 -#define DDRSS2_CTL_104_DATA 0x00003380 -#define DDRSS2_CTL_105_DATA 0x00003380 -#define DDRSS2_CTL_106_DATA 0x00003380 -#define DDRSS2_CTL_107_DATA 0x00000000 -#define DDRSS2_CTL_108_DATA 0x000005A2 -#define DDRSS2_CTL_109_DATA 0x00081CC0 -#define DDRSS2_CTL_110_DATA 0x00081CC0 -#define DDRSS2_CTL_111_DATA 0x00081CC0 -#define DDRSS2_CTL_112_DATA 0x00081CC0 -#define DDRSS2_CTL_113_DATA 0x00081CC0 -#define DDRSS2_CTL_114_DATA 0x00000000 -#define DDRSS2_CTL_115_DATA 0x0000E325 -#define DDRSS2_CTL_116_DATA 0x00081CC0 -#define DDRSS2_CTL_117_DATA 0x00081CC0 -#define DDRSS2_CTL_118_DATA 0x00081CC0 -#define DDRSS2_CTL_119_DATA 0x00081CC0 -#define DDRSS2_CTL_120_DATA 0x00081CC0 -#define DDRSS2_CTL_121_DATA 0x00000000 -#define DDRSS2_CTL_122_DATA 0x0000E325 -#define DDRSS2_CTL_123_DATA 0x00000000 -#define DDRSS2_CTL_124_DATA 0x00000000 -#define DDRSS2_CTL_125_DATA 0x00000000 -#define DDRSS2_CTL_126_DATA 0x00000000 -#define DDRSS2_CTL_127_DATA 0x00000000 -#define DDRSS2_CTL_128_DATA 0x00000000 -#define DDRSS2_CTL_129_DATA 0x00000000 -#define DDRSS2_CTL_130_DATA 0x00000000 -#define DDRSS2_CTL_131_DATA 0x0B030500 -#define DDRSS2_CTL_132_DATA 0x00040B04 -#define DDRSS2_CTL_133_DATA 0x0A090000 -#define DDRSS2_CTL_134_DATA 0x0A090701 -#define DDRSS2_CTL_135_DATA 0x0900000E -#define DDRSS2_CTL_136_DATA 0x0907010A -#define DDRSS2_CTL_137_DATA 0x00000E0A -#define DDRSS2_CTL_138_DATA 0x07010A09 -#define DDRSS2_CTL_139_DATA 0x000E0A09 -#define DDRSS2_CTL_140_DATA 0x07000401 -#define DDRSS2_CTL_141_DATA 0x00000000 -#define DDRSS2_CTL_142_DATA 0x00000000 -#define DDRSS2_CTL_143_DATA 0x00000000 -#define DDRSS2_CTL_144_DATA 0x00000000 -#define DDRSS2_CTL_145_DATA 0x00000000 -#define DDRSS2_CTL_146_DATA 0x00000000 -#define DDRSS2_CTL_147_DATA 0x00000000 -#define DDRSS2_CTL_148_DATA 0x08080000 -#define DDRSS2_CTL_149_DATA 0x01000000 -#define DDRSS2_CTL_150_DATA 0x800000C0 -#define DDRSS2_CTL_151_DATA 0x800000C0 -#define DDRSS2_CTL_152_DATA 0x800000C0 -#define DDRSS2_CTL_153_DATA 0x00000000 -#define DDRSS2_CTL_154_DATA 0x00001500 -#define DDRSS2_CTL_155_DATA 0x00000000 -#define DDRSS2_CTL_156_DATA 0x00000001 -#define DDRSS2_CTL_157_DATA 0x00000002 -#define DDRSS2_CTL_158_DATA 0x0000100E -#define DDRSS2_CTL_159_DATA 0x00000000 -#define DDRSS2_CTL_160_DATA 0x00000000 -#define DDRSS2_CTL_161_DATA 0x00000000 -#define DDRSS2_CTL_162_DATA 0x00000000 -#define DDRSS2_CTL_163_DATA 0x00000000 -#define DDRSS2_CTL_164_DATA 0x000B0000 -#define DDRSS2_CTL_165_DATA 0x000E0006 -#define DDRSS2_CTL_166_DATA 0x000E0404 -#define DDRSS2_CTL_167_DATA 0x00D601AB -#define DDRSS2_CTL_168_DATA 0x10100216 -#define DDRSS2_CTL_169_DATA 0x01AB0216 -#define DDRSS2_CTL_170_DATA 0x021600D6 -#define DDRSS2_CTL_171_DATA 0x02161010 -#define DDRSS2_CTL_172_DATA 0x00000000 -#define DDRSS2_CTL_173_DATA 0x00000000 -#define DDRSS2_CTL_174_DATA 0x00000000 -#define DDRSS2_CTL_175_DATA 0x3FF40084 -#define DDRSS2_CTL_176_DATA 0x33003FF4 -#define DDRSS2_CTL_177_DATA 0x00003333 -#define DDRSS2_CTL_178_DATA 0x35000000 -#define DDRSS2_CTL_179_DATA 0x27270035 -#define DDRSS2_CTL_180_DATA 0x0F0F0000 -#define DDRSS2_CTL_181_DATA 0x16000000 -#define DDRSS2_CTL_182_DATA 0x00841616 -#define DDRSS2_CTL_183_DATA 0x3FF43FF4 -#define DDRSS2_CTL_184_DATA 0x33333300 -#define DDRSS2_CTL_185_DATA 0x00000000 -#define DDRSS2_CTL_186_DATA 0x00353500 -#define DDRSS2_CTL_187_DATA 0x00002727 -#define DDRSS2_CTL_188_DATA 0x00000F0F -#define DDRSS2_CTL_189_DATA 0x16161600 -#define DDRSS2_CTL_190_DATA 0x00000020 -#define DDRSS2_CTL_191_DATA 0x00000000 -#define DDRSS2_CTL_192_DATA 0x00000001 -#define DDRSS2_CTL_193_DATA 0x00000000 -#define DDRSS2_CTL_194_DATA 0x01000000 -#define DDRSS2_CTL_195_DATA 0x00000001 -#define DDRSS2_CTL_196_DATA 0x00000000 -#define DDRSS2_CTL_197_DATA 0x00000000 -#define DDRSS2_CTL_198_DATA 0x00000000 -#define DDRSS2_CTL_199_DATA 0x00000000 -#define DDRSS2_CTL_200_DATA 0x00000000 -#define DDRSS2_CTL_201_DATA 0x00000000 -#define DDRSS2_CTL_202_DATA 0x00000000 -#define DDRSS2_CTL_203_DATA 0x00000000 -#define DDRSS2_CTL_204_DATA 0x00000000 -#define DDRSS2_CTL_205_DATA 0x00000000 -#define DDRSS2_CTL_206_DATA 0x02000000 -#define DDRSS2_CTL_207_DATA 0x01080101 -#define DDRSS2_CTL_208_DATA 0x00000000 -#define DDRSS2_CTL_209_DATA 0x00000000 -#define DDRSS2_CTL_210_DATA 0x00000000 -#define DDRSS2_CTL_211_DATA 0x00000000 -#define DDRSS2_CTL_212_DATA 0x00000000 -#define DDRSS2_CTL_213_DATA 0x00000000 -#define DDRSS2_CTL_214_DATA 0x00000000 -#define DDRSS2_CTL_215_DATA 0x00000000 -#define DDRSS2_CTL_216_DATA 0x00000000 -#define DDRSS2_CTL_217_DATA 0x00000000 -#define DDRSS2_CTL_218_DATA 0x00000000 -#define DDRSS2_CTL_219_DATA 0x00000000 -#define DDRSS2_CTL_220_DATA 0x00000000 -#define DDRSS2_CTL_221_DATA 0x00000000 -#define DDRSS2_CTL_222_DATA 0x00001000 -#define DDRSS2_CTL_223_DATA 0x006403E8 -#define DDRSS2_CTL_224_DATA 0x00000000 -#define DDRSS2_CTL_225_DATA 0x00000000 -#define DDRSS2_CTL_226_DATA 0x00000000 -#define DDRSS2_CTL_227_DATA 0x15110000 -#define DDRSS2_CTL_228_DATA 0x00040C18 -#define DDRSS2_CTL_229_DATA 0xF000C000 -#define DDRSS2_CTL_230_DATA 0x0000F000 -#define DDRSS2_CTL_231_DATA 0x00000000 -#define DDRSS2_CTL_232_DATA 0x00000000 -#define DDRSS2_CTL_233_DATA 0xC0000000 -#define DDRSS2_CTL_234_DATA 0xF000F000 -#define DDRSS2_CTL_235_DATA 0x00000000 -#define DDRSS2_CTL_236_DATA 0x00000000 -#define DDRSS2_CTL_237_DATA 0x00000000 -#define DDRSS2_CTL_238_DATA 0xF000C000 -#define DDRSS2_CTL_239_DATA 0x0000F000 -#define DDRSS2_CTL_240_DATA 0x00000000 -#define DDRSS2_CTL_241_DATA 0x00000000 -#define DDRSS2_CTL_242_DATA 0x00030000 -#define DDRSS2_CTL_243_DATA 0x00000000 -#define DDRSS2_CTL_244_DATA 0x00000000 -#define DDRSS2_CTL_245_DATA 0x00000000 -#define DDRSS2_CTL_246_DATA 0x00000000 -#define DDRSS2_CTL_247_DATA 0x00000000 -#define DDRSS2_CTL_248_DATA 0x00000000 -#define DDRSS2_CTL_249_DATA 0x00000000 -#define DDRSS2_CTL_250_DATA 0x00000000 -#define DDRSS2_CTL_251_DATA 0x00000000 -#define DDRSS2_CTL_252_DATA 0x00000000 -#define DDRSS2_CTL_253_DATA 0x00000000 -#define DDRSS2_CTL_254_DATA 0x00000000 -#define DDRSS2_CTL_255_DATA 0x00000000 -#define DDRSS2_CTL_256_DATA 0x00000000 -#define DDRSS2_CTL_257_DATA 0x01000200 -#define DDRSS2_CTL_258_DATA 0x00370040 -#define DDRSS2_CTL_259_DATA 0x00020008 -#define DDRSS2_CTL_260_DATA 0x00400100 -#define DDRSS2_CTL_261_DATA 0x00400855 -#define DDRSS2_CTL_262_DATA 0x01000200 -#define DDRSS2_CTL_263_DATA 0x08550040 -#define DDRSS2_CTL_264_DATA 0x00000040 -#define DDRSS2_CTL_265_DATA 0x006B0003 -#define DDRSS2_CTL_266_DATA 0x0100006B -#define DDRSS2_CTL_267_DATA 0x03030303 -#define DDRSS2_CTL_268_DATA 0x00000000 -#define DDRSS2_CTL_269_DATA 0x00000202 -#define DDRSS2_CTL_270_DATA 0x00001FFF -#define DDRSS2_CTL_271_DATA 0x3FFF2000 -#define DDRSS2_CTL_272_DATA 0x03FF0000 -#define DDRSS2_CTL_273_DATA 0x000103FF -#define DDRSS2_CTL_274_DATA 0x0FFF0B00 -#define DDRSS2_CTL_275_DATA 0x01010001 -#define DDRSS2_CTL_276_DATA 0x01010101 -#define DDRSS2_CTL_277_DATA 0x01180101 -#define DDRSS2_CTL_278_DATA 0x00030000 -#define DDRSS2_CTL_279_DATA 0x00000000 -#define DDRSS2_CTL_280_DATA 0x00000000 -#define DDRSS2_CTL_281_DATA 0x00000000 -#define DDRSS2_CTL_282_DATA 0x00000000 -#define DDRSS2_CTL_283_DATA 0x00000000 -#define DDRSS2_CTL_284_DATA 0x00000000 -#define DDRSS2_CTL_285_DATA 0x00000000 -#define DDRSS2_CTL_286_DATA 0x00040101 -#define DDRSS2_CTL_287_DATA 0x04010100 -#define DDRSS2_CTL_288_DATA 0x00000000 -#define DDRSS2_CTL_289_DATA 0x00000000 -#define DDRSS2_CTL_290_DATA 0x03030300 -#define DDRSS2_CTL_291_DATA 0x00000001 -#define DDRSS2_CTL_292_DATA 0x00000000 -#define DDRSS2_CTL_293_DATA 0x00000000 -#define DDRSS2_CTL_294_DATA 0x00000000 -#define DDRSS2_CTL_295_DATA 0x00000000 -#define DDRSS2_CTL_296_DATA 0x00000000 -#define DDRSS2_CTL_297_DATA 0x00000000 -#define DDRSS2_CTL_298_DATA 0x00000000 -#define DDRSS2_CTL_299_DATA 0x00000000 -#define DDRSS2_CTL_300_DATA 0x00000000 -#define DDRSS2_CTL_301_DATA 0x00000000 -#define DDRSS2_CTL_302_DATA 0x00000000 -#define DDRSS2_CTL_303_DATA 0x00000000 -#define DDRSS2_CTL_304_DATA 0x00000000 -#define DDRSS2_CTL_305_DATA 0x00000000 -#define DDRSS2_CTL_306_DATA 0x00000000 -#define DDRSS2_CTL_307_DATA 0x00000000 -#define DDRSS2_CTL_308_DATA 0x00000000 -#define DDRSS2_CTL_309_DATA 0x00000000 -#define DDRSS2_CTL_310_DATA 0x00000000 -#define DDRSS2_CTL_311_DATA 0x00000000 -#define DDRSS2_CTL_312_DATA 0x00000000 -#define DDRSS2_CTL_313_DATA 0x01000000 -#define DDRSS2_CTL_314_DATA 0x00020201 -#define DDRSS2_CTL_315_DATA 0x01000101 -#define DDRSS2_CTL_316_DATA 0x01010001 -#define DDRSS2_CTL_317_DATA 0x00010101 -#define DDRSS2_CTL_318_DATA 0x050A0A03 -#define DDRSS2_CTL_319_DATA 0x10081F1F -#define DDRSS2_CTL_320_DATA 0x00090310 -#define DDRSS2_CTL_321_DATA 0x0B0C030F -#define DDRSS2_CTL_322_DATA 0x0B0C0306 -#define DDRSS2_CTL_323_DATA 0x0C090006 -#define DDRSS2_CTL_324_DATA 0x0100000C -#define DDRSS2_CTL_325_DATA 0x08040801 -#define DDRSS2_CTL_326_DATA 0x00000004 -#define DDRSS2_CTL_327_DATA 0x00000000 -#define DDRSS2_CTL_328_DATA 0x00010000 -#define DDRSS2_CTL_329_DATA 0x00280D00 -#define DDRSS2_CTL_330_DATA 0x00000001 -#define DDRSS2_CTL_331_DATA 0x00030001 -#define DDRSS2_CTL_332_DATA 0x00000000 -#define DDRSS2_CTL_333_DATA 0x00000000 -#define DDRSS2_CTL_334_DATA 0x00000000 -#define DDRSS2_CTL_335_DATA 0x00000000 -#define DDRSS2_CTL_336_DATA 0x00000000 -#define DDRSS2_CTL_337_DATA 0x00000000 -#define DDRSS2_CTL_338_DATA 0x00000000 -#define DDRSS2_CTL_339_DATA 0x00000000 -#define DDRSS2_CTL_340_DATA 0x01000000 -#define DDRSS2_CTL_341_DATA 0x00000001 -#define DDRSS2_CTL_342_DATA 0x00010100 -#define DDRSS2_CTL_343_DATA 0x03030000 -#define DDRSS2_CTL_344_DATA 0x00000000 -#define DDRSS2_CTL_345_DATA 0x00000000 -#define DDRSS2_CTL_346_DATA 0x00000000 -#define DDRSS2_CTL_347_DATA 0x00000000 -#define DDRSS2_CTL_348_DATA 0x00000000 -#define DDRSS2_CTL_349_DATA 0x00000000 -#define DDRSS2_CTL_350_DATA 0x00000000 -#define DDRSS2_CTL_351_DATA 0x00000000 -#define DDRSS2_CTL_352_DATA 0x00000000 -#define DDRSS2_CTL_353_DATA 0x00000000 -#define DDRSS2_CTL_354_DATA 0x00000000 -#define DDRSS2_CTL_355_DATA 0x00000000 -#define DDRSS2_CTL_356_DATA 0x00000000 -#define DDRSS2_CTL_357_DATA 0x00000000 -#define DDRSS2_CTL_358_DATA 0x00000000 -#define DDRSS2_CTL_359_DATA 0x00000000 -#define DDRSS2_CTL_360_DATA 0x000556AA -#define DDRSS2_CTL_361_DATA 0x000AAAAA -#define DDRSS2_CTL_362_DATA 0x000AA955 -#define DDRSS2_CTL_363_DATA 0x00055555 -#define DDRSS2_CTL_364_DATA 0x000B3133 -#define DDRSS2_CTL_365_DATA 0x0004CD33 -#define DDRSS2_CTL_366_DATA 0x0004CECC -#define DDRSS2_CTL_367_DATA 0x000B32CC -#define DDRSS2_CTL_368_DATA 0x00010300 -#define DDRSS2_CTL_369_DATA 0x03000100 -#define DDRSS2_CTL_370_DATA 0x00000000 -#define DDRSS2_CTL_371_DATA 0x00000000 -#define DDRSS2_CTL_372_DATA 0x00000000 -#define DDRSS2_CTL_373_DATA 0x00000000 -#define DDRSS2_CTL_374_DATA 0x00000000 -#define DDRSS2_CTL_375_DATA 0x00000000 -#define DDRSS2_CTL_376_DATA 0x00000000 -#define DDRSS2_CTL_377_DATA 0x00010000 -#define DDRSS2_CTL_378_DATA 0x00000404 -#define DDRSS2_CTL_379_DATA 0x00000000 -#define DDRSS2_CTL_380_DATA 0x00000000 -#define DDRSS2_CTL_381_DATA 0x00000000 -#define DDRSS2_CTL_382_DATA 0x00000000 -#define DDRSS2_CTL_383_DATA 0x00000000 -#define DDRSS2_CTL_384_DATA 0x00000000 -#define DDRSS2_CTL_385_DATA 0x00000000 -#define DDRSS2_CTL_386_DATA 0x00000000 -#define DDRSS2_CTL_387_DATA 0x3A3A1B00 -#define DDRSS2_CTL_388_DATA 0x000A0000 -#define DDRSS2_CTL_389_DATA 0x0000019C -#define DDRSS2_CTL_390_DATA 0x00000200 -#define DDRSS2_CTL_391_DATA 0x00000200 -#define DDRSS2_CTL_392_DATA 0x00000200 -#define DDRSS2_CTL_393_DATA 0x00000200 -#define DDRSS2_CTL_394_DATA 0x000004D4 -#define DDRSS2_CTL_395_DATA 0x00001018 -#define DDRSS2_CTL_396_DATA 0x00000204 -#define DDRSS2_CTL_397_DATA 0x000040E6 -#define DDRSS2_CTL_398_DATA 0x00000200 -#define DDRSS2_CTL_399_DATA 0x00000200 -#define DDRSS2_CTL_400_DATA 0x00000200 -#define DDRSS2_CTL_401_DATA 0x00000200 -#define DDRSS2_CTL_402_DATA 0x0000C2B2 -#define DDRSS2_CTL_403_DATA 0x000288FC -#define DDRSS2_CTL_404_DATA 0x00000E15 -#define DDRSS2_CTL_405_DATA 0x000040E6 -#define DDRSS2_CTL_406_DATA 0x00000200 -#define DDRSS2_CTL_407_DATA 0x00000200 -#define DDRSS2_CTL_408_DATA 0x00000200 -#define DDRSS2_CTL_409_DATA 0x00000200 -#define DDRSS2_CTL_410_DATA 0x0000C2B2 -#define DDRSS2_CTL_411_DATA 0x000288FC -#define DDRSS2_CTL_412_DATA 0x02020E15 -#define DDRSS2_CTL_413_DATA 0x03030202 -#define DDRSS2_CTL_414_DATA 0x00000022 -#define DDRSS2_CTL_415_DATA 0x00000000 -#define DDRSS2_CTL_416_DATA 0x00000000 -#define DDRSS2_CTL_417_DATA 0x00001403 -#define DDRSS2_CTL_418_DATA 0x000007D0 -#define DDRSS2_CTL_419_DATA 0x00000000 -#define DDRSS2_CTL_420_DATA 0x00000000 -#define DDRSS2_CTL_421_DATA 0x00030000 -#define DDRSS2_CTL_422_DATA 0x0007001F -#define DDRSS2_CTL_423_DATA 0x001B0033 -#define DDRSS2_CTL_424_DATA 0x001B0033 -#define DDRSS2_CTL_425_DATA 0x00000000 -#define DDRSS2_CTL_426_DATA 0x00000000 -#define DDRSS2_CTL_427_DATA 0x02000000 -#define DDRSS2_CTL_428_DATA 0x01000404 -#define DDRSS2_CTL_429_DATA 0x0B1E0B1E -#define DDRSS2_CTL_430_DATA 0x00000105 -#define DDRSS2_CTL_431_DATA 0x00010101 -#define DDRSS2_CTL_432_DATA 0x00010101 -#define DDRSS2_CTL_433_DATA 0x00010001 -#define DDRSS2_CTL_434_DATA 0x00000101 -#define DDRSS2_CTL_435_DATA 0x02000201 -#define DDRSS2_CTL_436_DATA 0x02010000 -#define DDRSS2_CTL_437_DATA 0x00000200 -#define DDRSS2_CTL_438_DATA 0x28060000 -#define DDRSS2_CTL_439_DATA 0x00000128 -#define DDRSS2_CTL_440_DATA 0xFFFFFFFF -#define DDRSS2_CTL_441_DATA 0xFFFFFFFF -#define DDRSS2_CTL_442_DATA 0x00000000 -#define DDRSS2_CTL_443_DATA 0x00000000 -#define DDRSS2_CTL_444_DATA 0x00000000 -#define DDRSS2_CTL_445_DATA 0x00000000 -#define DDRSS2_CTL_446_DATA 0x00000000 -#define DDRSS2_CTL_447_DATA 0x00000000 -#define DDRSS2_CTL_448_DATA 0x00000000 -#define DDRSS2_CTL_449_DATA 0x00000000 -#define DDRSS2_CTL_450_DATA 0x00000000 -#define DDRSS2_CTL_451_DATA 0x00000000 -#define DDRSS2_CTL_452_DATA 0x00000000 -#define DDRSS2_CTL_453_DATA 0x00000000 -#define DDRSS2_CTL_454_DATA 0x00000000 -#define DDRSS2_CTL_455_DATA 0x00000000 -#define DDRSS2_CTL_456_DATA 0x00000000 -#define DDRSS2_CTL_457_DATA 0x00000000 -#define DDRSS2_CTL_458_DATA 0x00000000 -#define DDRSS2_PI_00_DATA 0x00000B00 -#define DDRSS2_PI_01_DATA 0x00000000 -#define DDRSS2_PI_02_DATA 0x00000000 -#define DDRSS2_PI_03_DATA 0x00000000 -#define DDRSS2_PI_04_DATA 0x00000000 -#define DDRSS2_PI_05_DATA 0x00000101 -#define DDRSS2_PI_06_DATA 0x00640000 -#define DDRSS2_PI_07_DATA 0x00000001 -#define DDRSS2_PI_08_DATA 0x00000000 -#define DDRSS2_PI_09_DATA 0x00000000 -#define DDRSS2_PI_10_DATA 0x00000000 -#define DDRSS2_PI_11_DATA 0x00000000 -#define DDRSS2_PI_12_DATA 0x00000007 -#define DDRSS2_PI_13_DATA 0x00010002 -#define DDRSS2_PI_14_DATA 0x0800000F -#define DDRSS2_PI_15_DATA 0x00000103 -#define DDRSS2_PI_16_DATA 0x00000005 -#define DDRSS2_PI_17_DATA 0x00000000 -#define DDRSS2_PI_18_DATA 0x00000000 -#define DDRSS2_PI_19_DATA 0x00000000 -#define DDRSS2_PI_20_DATA 0x00000000 -#define DDRSS2_PI_21_DATA 0x00000000 -#define DDRSS2_PI_22_DATA 0x00000000 -#define DDRSS2_PI_23_DATA 0x00000000 -#define DDRSS2_PI_24_DATA 0x00000000 -#define DDRSS2_PI_25_DATA 0x00000000 -#define DDRSS2_PI_26_DATA 0x00010100 -#define DDRSS2_PI_27_DATA 0x00280A00 -#define DDRSS2_PI_28_DATA 0x00000000 -#define DDRSS2_PI_29_DATA 0x0F000000 -#define DDRSS2_PI_30_DATA 0x00003200 -#define DDRSS2_PI_31_DATA 0x00000000 -#define DDRSS2_PI_32_DATA 0x00000000 -#define DDRSS2_PI_33_DATA 0x01010102 -#define DDRSS2_PI_34_DATA 0x00000000 -#define DDRSS2_PI_35_DATA 0x000000AA -#define DDRSS2_PI_36_DATA 0x00000055 -#define DDRSS2_PI_37_DATA 0x000000B5 -#define DDRSS2_PI_38_DATA 0x0000004A -#define DDRSS2_PI_39_DATA 0x00000056 -#define DDRSS2_PI_40_DATA 0x000000A9 -#define DDRSS2_PI_41_DATA 0x000000A9 -#define DDRSS2_PI_42_DATA 0x000000B5 -#define DDRSS2_PI_43_DATA 0x00000000 -#define DDRSS2_PI_44_DATA 0x00000000 -#define DDRSS2_PI_45_DATA 0x000F0F00 -#define DDRSS2_PI_46_DATA 0x0000001B -#define DDRSS2_PI_47_DATA 0x000007D0 -#define DDRSS2_PI_48_DATA 0x00000300 -#define DDRSS2_PI_49_DATA 0x00000000 -#define DDRSS2_PI_50_DATA 0x00000000 -#define DDRSS2_PI_51_DATA 0x01000000 -#define DDRSS2_PI_52_DATA 0x00010101 -#define DDRSS2_PI_53_DATA 0x00000000 -#define DDRSS2_PI_54_DATA 0x00030000 -#define DDRSS2_PI_55_DATA 0x0F000000 -#define DDRSS2_PI_56_DATA 0x00000017 -#define DDRSS2_PI_57_DATA 0x00000000 -#define DDRSS2_PI_58_DATA 0x00000000 -#define DDRSS2_PI_59_DATA 0x00000000 -#define DDRSS2_PI_60_DATA 0x0A0A140A -#define DDRSS2_PI_61_DATA 0x10020101 -#define DDRSS2_PI_62_DATA 0x00020805 -#define DDRSS2_PI_63_DATA 0x01000404 -#define DDRSS2_PI_64_DATA 0x00000000 -#define DDRSS2_PI_65_DATA 0x00000000 -#define DDRSS2_PI_66_DATA 0x00000100 -#define DDRSS2_PI_67_DATA 0x0001010F -#define DDRSS2_PI_68_DATA 0x00340000 -#define DDRSS2_PI_69_DATA 0x00000000 -#define DDRSS2_PI_70_DATA 0x00000000 -#define DDRSS2_PI_71_DATA 0x0000FFFF -#define DDRSS2_PI_72_DATA 0x00000000 -#define DDRSS2_PI_73_DATA 0x00080000 -#define DDRSS2_PI_74_DATA 0x02000200 -#define DDRSS2_PI_75_DATA 0x01000100 -#define DDRSS2_PI_76_DATA 0x01000000 -#define DDRSS2_PI_77_DATA 0x02000200 -#define DDRSS2_PI_78_DATA 0x00000200 -#define DDRSS2_PI_79_DATA 0x00000000 -#define DDRSS2_PI_80_DATA 0x00000000 -#define DDRSS2_PI_81_DATA 0x00000000 -#define DDRSS2_PI_82_DATA 0x00000000 -#define DDRSS2_PI_83_DATA 0x00000000 -#define DDRSS2_PI_84_DATA 0x00000000 -#define DDRSS2_PI_85_DATA 0x00000000 -#define DDRSS2_PI_86_DATA 0x00000000 -#define DDRSS2_PI_87_DATA 0x00000000 -#define DDRSS2_PI_88_DATA 0x00000000 -#define DDRSS2_PI_89_DATA 0x00000000 -#define DDRSS2_PI_90_DATA 0x00000000 -#define DDRSS2_PI_91_DATA 0x00000400 -#define DDRSS2_PI_92_DATA 0x02010000 -#define DDRSS2_PI_93_DATA 0x00080003 -#define DDRSS2_PI_94_DATA 0x00080000 -#define DDRSS2_PI_95_DATA 0x00000001 -#define DDRSS2_PI_96_DATA 0x00000000 -#define DDRSS2_PI_97_DATA 0x0000AA00 -#define DDRSS2_PI_98_DATA 0x00000000 -#define DDRSS2_PI_99_DATA 0x00000000 -#define DDRSS2_PI_100_DATA 0x00010000 -#define DDRSS2_PI_101_DATA 0x00000000 -#define DDRSS2_PI_102_DATA 0x00000000 -#define DDRSS2_PI_103_DATA 0x00000000 -#define DDRSS2_PI_104_DATA 0x00000000 -#define DDRSS2_PI_105_DATA 0x00000000 -#define DDRSS2_PI_106_DATA 0x00000000 -#define DDRSS2_PI_107_DATA 0x00000000 -#define DDRSS2_PI_108_DATA 0x00000000 -#define DDRSS2_PI_109_DATA 0x00000000 -#define DDRSS2_PI_110_DATA 0x00000000 -#define DDRSS2_PI_111_DATA 0x00000000 -#define DDRSS2_PI_112_DATA 0x00000000 -#define DDRSS2_PI_113_DATA 0x00000000 -#define DDRSS2_PI_114_DATA 0x00000000 -#define DDRSS2_PI_115_DATA 0x00000000 -#define DDRSS2_PI_116_DATA 0x00000000 -#define DDRSS2_PI_117_DATA 0x00000000 -#define DDRSS2_PI_118_DATA 0x00000000 -#define DDRSS2_PI_119_DATA 0x00000000 -#define DDRSS2_PI_120_DATA 0x00000000 -#define DDRSS2_PI_121_DATA 0x00000000 -#define DDRSS2_PI_122_DATA 0x00000000 -#define DDRSS2_PI_123_DATA 0x00000000 -#define DDRSS2_PI_124_DATA 0x00000000 -#define DDRSS2_PI_125_DATA 0x00000008 -#define DDRSS2_PI_126_DATA 0x00000000 -#define DDRSS2_PI_127_DATA 0x00000000 -#define DDRSS2_PI_128_DATA 0x00000000 -#define DDRSS2_PI_129_DATA 0x00000000 -#define DDRSS2_PI_130_DATA 0x00000000 -#define DDRSS2_PI_131_DATA 0x00000000 -#define DDRSS2_PI_132_DATA 0x00000000 -#define DDRSS2_PI_133_DATA 0x00000000 -#define DDRSS2_PI_134_DATA 0x00000002 -#define DDRSS2_PI_135_DATA 0x00000000 -#define DDRSS2_PI_136_DATA 0x00000000 -#define DDRSS2_PI_137_DATA 0x0000000A -#define DDRSS2_PI_138_DATA 0x00000019 -#define DDRSS2_PI_139_DATA 0x00000100 -#define DDRSS2_PI_140_DATA 0x00000000 -#define DDRSS2_PI_141_DATA 0x00000000 -#define DDRSS2_PI_142_DATA 0x00000000 -#define DDRSS2_PI_143_DATA 0x00000000 -#define DDRSS2_PI_144_DATA 0x01000000 -#define DDRSS2_PI_145_DATA 0x00010003 -#define DDRSS2_PI_146_DATA 0x02000101 -#define DDRSS2_PI_147_DATA 0x01030001 -#define DDRSS2_PI_148_DATA 0x00010400 -#define DDRSS2_PI_149_DATA 0x06000105 -#define DDRSS2_PI_150_DATA 0x01070001 -#define DDRSS2_PI_151_DATA 0x00000000 -#define DDRSS2_PI_152_DATA 0x00000000 -#define DDRSS2_PI_153_DATA 0x00000000 -#define DDRSS2_PI_154_DATA 0x00010001 -#define DDRSS2_PI_155_DATA 0x00000000 -#define DDRSS2_PI_156_DATA 0x00000000 -#define DDRSS2_PI_157_DATA 0x00000000 -#define DDRSS2_PI_158_DATA 0x00000000 -#define DDRSS2_PI_159_DATA 0x00000401 -#define DDRSS2_PI_160_DATA 0x00000000 -#define DDRSS2_PI_161_DATA 0x00010000 -#define DDRSS2_PI_162_DATA 0x00000000 -#define DDRSS2_PI_163_DATA 0x2B2B0200 -#define DDRSS2_PI_164_DATA 0x00000034 -#define DDRSS2_PI_165_DATA 0x00000064 -#define DDRSS2_PI_166_DATA 0x00020064 -#define DDRSS2_PI_167_DATA 0x02000200 -#define DDRSS2_PI_168_DATA 0x48120C04 -#define DDRSS2_PI_169_DATA 0x00154812 -#define DDRSS2_PI_170_DATA 0x000000CE -#define DDRSS2_PI_171_DATA 0x0000032B -#define DDRSS2_PI_172_DATA 0x00002073 -#define DDRSS2_PI_173_DATA 0x0000032B -#define DDRSS2_PI_174_DATA 0x04002073 -#define DDRSS2_PI_175_DATA 0x01010404 -#define DDRSS2_PI_176_DATA 0x00001501 -#define DDRSS2_PI_177_DATA 0x00150015 -#define DDRSS2_PI_178_DATA 0x01000100 -#define DDRSS2_PI_179_DATA 0x00000100 -#define DDRSS2_PI_180_DATA 0x00000000 -#define DDRSS2_PI_181_DATA 0x01010101 -#define DDRSS2_PI_182_DATA 0x00000101 -#define DDRSS2_PI_183_DATA 0x00000000 -#define DDRSS2_PI_184_DATA 0x00000000 -#define DDRSS2_PI_185_DATA 0x15040000 -#define DDRSS2_PI_186_DATA 0x0E0E0215 -#define DDRSS2_PI_187_DATA 0x00040402 -#define DDRSS2_PI_188_DATA 0x000D0035 -#define DDRSS2_PI_189_DATA 0x00218049 -#define DDRSS2_PI_190_DATA 0x00218049 -#define DDRSS2_PI_191_DATA 0x01010101 -#define DDRSS2_PI_192_DATA 0x0004000E -#define DDRSS2_PI_193_DATA 0x00040216 -#define DDRSS2_PI_194_DATA 0x01000216 -#define DDRSS2_PI_195_DATA 0x000F000F -#define DDRSS2_PI_196_DATA 0x02170100 -#define DDRSS2_PI_197_DATA 0x01000217 -#define DDRSS2_PI_198_DATA 0x02170217 -#define DDRSS2_PI_199_DATA 0x32103200 -#define DDRSS2_PI_200_DATA 0x01013210 -#define DDRSS2_PI_201_DATA 0x0A070601 -#define DDRSS2_PI_202_DATA 0x1F130A0D -#define DDRSS2_PI_203_DATA 0x1F130A14 -#define DDRSS2_PI_204_DATA 0x0000C014 -#define DDRSS2_PI_205_DATA 0x00C01000 -#define DDRSS2_PI_206_DATA 0x00C01000 -#define DDRSS2_PI_207_DATA 0x00021000 -#define DDRSS2_PI_208_DATA 0x0024000E -#define DDRSS2_PI_209_DATA 0x00240216 -#define DDRSS2_PI_210_DATA 0x00110216 -#define DDRSS2_PI_211_DATA 0x32000056 -#define DDRSS2_PI_212_DATA 0x00000301 -#define DDRSS2_PI_213_DATA 0x005B0036 -#define DDRSS2_PI_214_DATA 0x03013212 -#define DDRSS2_PI_215_DATA 0x00003600 -#define DDRSS2_PI_216_DATA 0x3212005B -#define DDRSS2_PI_217_DATA 0x09000301 -#define DDRSS2_PI_218_DATA 0x04010504 -#define DDRSS2_PI_219_DATA 0x040006C9 -#define DDRSS2_PI_220_DATA 0x0A032001 -#define DDRSS2_PI_221_DATA 0x2C31110A -#define DDRSS2_PI_222_DATA 0x00002918 -#define DDRSS2_PI_223_DATA 0x6001071C -#define DDRSS2_PI_224_DATA 0x1E202008 -#define DDRSS2_PI_225_DATA 0x2C311116 -#define DDRSS2_PI_226_DATA 0x00002918 -#define DDRSS2_PI_227_DATA 0x6001071C -#define DDRSS2_PI_228_DATA 0x1E202008 -#define DDRSS2_PI_229_DATA 0x00019C16 -#define DDRSS2_PI_230_DATA 0x00001018 -#define DDRSS2_PI_231_DATA 0x000040E6 -#define DDRSS2_PI_232_DATA 0x000288FC -#define DDRSS2_PI_233_DATA 0x000040E6 -#define DDRSS2_PI_234_DATA 0x000288FC -#define DDRSS2_PI_235_DATA 0x033B0016 -#define DDRSS2_PI_236_DATA 0x0303033B -#define DDRSS2_PI_237_DATA 0x002AF803 -#define DDRSS2_PI_238_DATA 0x0001ADAF -#define DDRSS2_PI_239_DATA 0x00000005 -#define DDRSS2_PI_240_DATA 0x0000006E -#define DDRSS2_PI_241_DATA 0x00000016 -#define DDRSS2_PI_242_DATA 0x000681C8 -#define DDRSS2_PI_243_DATA 0x0001ADAF -#define DDRSS2_PI_244_DATA 0x00000005 -#define DDRSS2_PI_245_DATA 0x000010A9 -#define DDRSS2_PI_246_DATA 0x0000033B -#define DDRSS2_PI_247_DATA 0x000681C8 -#define DDRSS2_PI_248_DATA 0x0001ADAF -#define DDRSS2_PI_249_DATA 0x00000005 -#define DDRSS2_PI_250_DATA 0x000010A9 -#define DDRSS2_PI_251_DATA 0x0100033B -#define DDRSS2_PI_252_DATA 0x00370040 -#define DDRSS2_PI_253_DATA 0x00010008 -#define DDRSS2_PI_254_DATA 0x08550040 -#define DDRSS2_PI_255_DATA 0x00010040 -#define DDRSS2_PI_256_DATA 0x08550040 -#define DDRSS2_PI_257_DATA 0x00000340 -#define DDRSS2_PI_258_DATA 0x006B006B -#define DDRSS2_PI_259_DATA 0x08040404 -#define DDRSS2_PI_260_DATA 0x00000055 -#define DDRSS2_PI_261_DATA 0x55083C5A -#define DDRSS2_PI_262_DATA 0x5A000000 -#define DDRSS2_PI_263_DATA 0x0055083C -#define DDRSS2_PI_264_DATA 0x3C5A0000 -#define DDRSS2_PI_265_DATA 0x00005508 -#define DDRSS2_PI_266_DATA 0x0C3C5A00 -#define DDRSS2_PI_267_DATA 0x080F0E0D -#define DDRSS2_PI_268_DATA 0x000B0A09 -#define DDRSS2_PI_269_DATA 0x00030201 -#define DDRSS2_PI_270_DATA 0x01000000 -#define DDRSS2_PI_271_DATA 0x04020201 -#define DDRSS2_PI_272_DATA 0x00080804 -#define DDRSS2_PI_273_DATA 0x00000000 -#define DDRSS2_PI_274_DATA 0x00000000 -#define DDRSS2_PI_275_DATA 0x00330084 -#define DDRSS2_PI_276_DATA 0x00160000 -#define DDRSS2_PI_277_DATA 0x35333FF4 -#define DDRSS2_PI_278_DATA 0x00160F27 -#define DDRSS2_PI_279_DATA 0x35333FF4 -#define DDRSS2_PI_280_DATA 0x00160F27 -#define DDRSS2_PI_281_DATA 0x00330084 -#define DDRSS2_PI_282_DATA 0x00160000 -#define DDRSS2_PI_283_DATA 0x35333FF4 -#define DDRSS2_PI_284_DATA 0x00160F27 -#define DDRSS2_PI_285_DATA 0x35333FF4 -#define DDRSS2_PI_286_DATA 0x00160F27 -#define DDRSS2_PI_287_DATA 0x00330084 -#define DDRSS2_PI_288_DATA 0x00160000 -#define DDRSS2_PI_289_DATA 0x35333FF4 -#define DDRSS2_PI_290_DATA 0x00160F27 -#define DDRSS2_PI_291_DATA 0x35333FF4 -#define DDRSS2_PI_292_DATA 0x00160F27 -#define DDRSS2_PI_293_DATA 0x00330084 -#define DDRSS2_PI_294_DATA 0x00160000 -#define DDRSS2_PI_295_DATA 0x35333FF4 -#define DDRSS2_PI_296_DATA 0x00160F27 -#define DDRSS2_PI_297_DATA 0x35333FF4 -#define DDRSS2_PI_298_DATA 0x00160F27 -#define DDRSS2_PI_299_DATA 0x00000000 - -#define DDRSS2_PHY_00_DATA 0x000004F0 -#define DDRSS2_PHY_01_DATA 0x00000000 -#define DDRSS2_PHY_02_DATA 0x00030200 -#define DDRSS2_PHY_03_DATA 0x00000000 -#define DDRSS2_PHY_04_DATA 0x00000000 -#define DDRSS2_PHY_05_DATA 0x01030000 -#define DDRSS2_PHY_06_DATA 0x00010000 -#define DDRSS2_PHY_07_DATA 0x01030004 -#define DDRSS2_PHY_08_DATA 0x01000000 -#define DDRSS2_PHY_09_DATA 0x00000000 -#define DDRSS2_PHY_10_DATA 0x00000000 -#define DDRSS2_PHY_11_DATA 0x01000001 -#define DDRSS2_PHY_12_DATA 0x00000100 -#define DDRSS2_PHY_13_DATA 0x000800C0 -#define DDRSS2_PHY_14_DATA 0x060100CC -#define DDRSS2_PHY_15_DATA 0x00030066 -#define DDRSS2_PHY_16_DATA 0x00000000 -#define DDRSS2_PHY_17_DATA 0x00000301 -#define DDRSS2_PHY_18_DATA 0x0000AAAA -#define DDRSS2_PHY_19_DATA 0x00005555 -#define DDRSS2_PHY_20_DATA 0x0000B5B5 -#define DDRSS2_PHY_21_DATA 0x00004A4A -#define DDRSS2_PHY_22_DATA 0x00005656 -#define DDRSS2_PHY_23_DATA 0x0000A9A9 -#define DDRSS2_PHY_24_DATA 0x0000A9A9 -#define DDRSS2_PHY_25_DATA 0x0000B5B5 -#define DDRSS2_PHY_26_DATA 0x00000000 -#define DDRSS2_PHY_27_DATA 0x00000000 -#define DDRSS2_PHY_28_DATA 0x2A000000 -#define DDRSS2_PHY_29_DATA 0x00000808 -#define DDRSS2_PHY_30_DATA 0x0F000000 -#define DDRSS2_PHY_31_DATA 0x00000F0F -#define DDRSS2_PHY_32_DATA 0x10400000 -#define DDRSS2_PHY_33_DATA 0x0C002006 -#define DDRSS2_PHY_34_DATA 0x00000000 -#define DDRSS2_PHY_35_DATA 0x00000000 -#define DDRSS2_PHY_36_DATA 0x55555555 -#define DDRSS2_PHY_37_DATA 0xAAAAAAAA -#define DDRSS2_PHY_38_DATA 0x55555555 -#define DDRSS2_PHY_39_DATA 0xAAAAAAAA -#define DDRSS2_PHY_40_DATA 0x00005555 -#define DDRSS2_PHY_41_DATA 0x01000100 -#define DDRSS2_PHY_42_DATA 0x00800180 -#define DDRSS2_PHY_43_DATA 0x00000001 -#define DDRSS2_PHY_44_DATA 0x00000000 -#define DDRSS2_PHY_45_DATA 0x00000000 -#define DDRSS2_PHY_46_DATA 0x00000000 -#define DDRSS2_PHY_47_DATA 0x00000000 -#define DDRSS2_PHY_48_DATA 0x00000000 -#define DDRSS2_PHY_49_DATA 0x00000000 -#define DDRSS2_PHY_50_DATA 0x00000000 -#define DDRSS2_PHY_51_DATA 0x00000000 -#define DDRSS2_PHY_52_DATA 0x00000000 -#define DDRSS2_PHY_53_DATA 0x00000000 -#define DDRSS2_PHY_54_DATA 0x00000000 -#define DDRSS2_PHY_55_DATA 0x00000000 -#define DDRSS2_PHY_56_DATA 0x00000000 -#define DDRSS2_PHY_57_DATA 0x00000000 -#define DDRSS2_PHY_58_DATA 0x00000000 -#define DDRSS2_PHY_59_DATA 0x00000000 -#define DDRSS2_PHY_60_DATA 0x00000000 -#define DDRSS2_PHY_61_DATA 0x00000000 -#define DDRSS2_PHY_62_DATA 0x00000000 -#define DDRSS2_PHY_63_DATA 0x00000000 -#define DDRSS2_PHY_64_DATA 0x00000000 -#define DDRSS2_PHY_65_DATA 0x00000000 -#define DDRSS2_PHY_66_DATA 0x00000104 -#define DDRSS2_PHY_67_DATA 0x00000120 -#define DDRSS2_PHY_68_DATA 0x00000000 -#define DDRSS2_PHY_69_DATA 0x00000000 -#define DDRSS2_PHY_70_DATA 0x00000000 -#define DDRSS2_PHY_71_DATA 0x00000000 -#define DDRSS2_PHY_72_DATA 0x00000000 -#define DDRSS2_PHY_73_DATA 0x00000000 -#define DDRSS2_PHY_74_DATA 0x00000000 -#define DDRSS2_PHY_75_DATA 0x00000001 -#define DDRSS2_PHY_76_DATA 0x07FF0000 -#define DDRSS2_PHY_77_DATA 0x0080081F -#define DDRSS2_PHY_78_DATA 0x00081020 -#define DDRSS2_PHY_79_DATA 0x04010000 -#define DDRSS2_PHY_80_DATA 0x00000000 -#define DDRSS2_PHY_81_DATA 0x00000000 -#define DDRSS2_PHY_82_DATA 0x00000000 -#define DDRSS2_PHY_83_DATA 0x00000100 -#define DDRSS2_PHY_84_DATA 0x01CC0C01 -#define DDRSS2_PHY_85_DATA 0x1003CC0C -#define DDRSS2_PHY_86_DATA 0x20000140 -#define DDRSS2_PHY_87_DATA 0x07FF0200 -#define DDRSS2_PHY_88_DATA 0x0000DD01 -#define DDRSS2_PHY_89_DATA 0x10100303 -#define DDRSS2_PHY_90_DATA 0x10101010 -#define DDRSS2_PHY_91_DATA 0x10101010 -#define DDRSS2_PHY_92_DATA 0x00021010 -#define DDRSS2_PHY_93_DATA 0x00100010 -#define DDRSS2_PHY_94_DATA 0x00100010 -#define DDRSS2_PHY_95_DATA 0x00100010 -#define DDRSS2_PHY_96_DATA 0x00100010 -#define DDRSS2_PHY_97_DATA 0x00050010 -#define DDRSS2_PHY_98_DATA 0x51517041 -#define DDRSS2_PHY_99_DATA 0x31C06001 -#define DDRSS2_PHY_100_DATA 0x07AB0340 -#define DDRSS2_PHY_101_DATA 0x00C0C001 -#define DDRSS2_PHY_102_DATA 0x0E0D0001 -#define DDRSS2_PHY_103_DATA 0x10001000 -#define DDRSS2_PHY_104_DATA 0x0C083E42 -#define DDRSS2_PHY_105_DATA 0x0F0C3701 -#define DDRSS2_PHY_106_DATA 0x01000140 -#define DDRSS2_PHY_107_DATA 0x0C000420 -#define DDRSS2_PHY_108_DATA 0x00000198 -#define DDRSS2_PHY_109_DATA 0x0A0000D0 -#define DDRSS2_PHY_110_DATA 0x00030200 -#define DDRSS2_PHY_111_DATA 0x02800000 -#define DDRSS2_PHY_112_DATA 0x80800000 -#define DDRSS2_PHY_113_DATA 0x000E2010 -#define DDRSS2_PHY_114_DATA 0x76543210 -#define DDRSS2_PHY_115_DATA 0x00000008 -#define DDRSS2_PHY_116_DATA 0x02800280 -#define DDRSS2_PHY_117_DATA 0x02800280 -#define DDRSS2_PHY_118_DATA 0x02800280 -#define DDRSS2_PHY_119_DATA 0x02800280 -#define DDRSS2_PHY_120_DATA 0x00000280 -#define DDRSS2_PHY_121_DATA 0x0000A000 -#define DDRSS2_PHY_122_DATA 0x00A000A0 -#define DDRSS2_PHY_123_DATA 0x00A000A0 -#define DDRSS2_PHY_124_DATA 0x00A000A0 -#define DDRSS2_PHY_125_DATA 0x00A000A0 -#define DDRSS2_PHY_126_DATA 0x00A000A0 -#define DDRSS2_PHY_127_DATA 0x00A000A0 -#define DDRSS2_PHY_128_DATA 0x00A000A0 -#define DDRSS2_PHY_129_DATA 0x00A000A0 -#define DDRSS2_PHY_130_DATA 0x01C200A0 -#define DDRSS2_PHY_131_DATA 0x01A00005 -#define DDRSS2_PHY_132_DATA 0x00000000 -#define DDRSS2_PHY_133_DATA 0x00000000 -#define DDRSS2_PHY_134_DATA 0x00080200 -#define DDRSS2_PHY_135_DATA 0x00000000 -#define DDRSS2_PHY_136_DATA 0x20202000 -#define DDRSS2_PHY_137_DATA 0x20202020 -#define DDRSS2_PHY_138_DATA 0xF0F02020 -#define DDRSS2_PHY_139_DATA 0x00000000 -#define DDRSS2_PHY_140_DATA 0x00000000 -#define DDRSS2_PHY_141_DATA 0x00000000 -#define DDRSS2_PHY_142_DATA 0x00000000 -#define DDRSS2_PHY_143_DATA 0x00000000 -#define DDRSS2_PHY_144_DATA 0x00000000 -#define DDRSS2_PHY_145_DATA 0x00000000 -#define DDRSS2_PHY_146_DATA 0x00000000 -#define DDRSS2_PHY_147_DATA 0x00000000 -#define DDRSS2_PHY_148_DATA 0x00000000 -#define DDRSS2_PHY_149_DATA 0x00000000 -#define DDRSS2_PHY_150_DATA 0x00000000 -#define DDRSS2_PHY_151_DATA 0x00000000 -#define DDRSS2_PHY_152_DATA 0x00000000 -#define DDRSS2_PHY_153_DATA 0x00000000 -#define DDRSS2_PHY_154_DATA 0x00000000 -#define DDRSS2_PHY_155_DATA 0x00000000 -#define DDRSS2_PHY_156_DATA 0x00000000 -#define DDRSS2_PHY_157_DATA 0x00000000 -#define DDRSS2_PHY_158_DATA 0x00000000 -#define DDRSS2_PHY_159_DATA 0x00000000 -#define DDRSS2_PHY_160_DATA 0x00000000 -#define DDRSS2_PHY_161_DATA 0x00000000 -#define DDRSS2_PHY_162_DATA 0x00000000 -#define DDRSS2_PHY_163_DATA 0x00000000 -#define DDRSS2_PHY_164_DATA 0x00000000 -#define DDRSS2_PHY_165_DATA 0x00000000 -#define DDRSS2_PHY_166_DATA 0x00000000 -#define DDRSS2_PHY_167_DATA 0x00000000 -#define DDRSS2_PHY_168_DATA 0x00000000 -#define DDRSS2_PHY_169_DATA 0x00000000 -#define DDRSS2_PHY_170_DATA 0x00000000 -#define DDRSS2_PHY_171_DATA 0x00000000 -#define DDRSS2_PHY_172_DATA 0x00000000 -#define DDRSS2_PHY_173_DATA 0x00000000 -#define DDRSS2_PHY_174_DATA 0x00000000 -#define DDRSS2_PHY_175_DATA 0x00000000 -#define DDRSS2_PHY_176_DATA 0x00000000 -#define DDRSS2_PHY_177_DATA 0x00000000 -#define DDRSS2_PHY_178_DATA 0x00000000 -#define DDRSS2_PHY_179_DATA 0x00000000 -#define DDRSS2_PHY_180_DATA 0x00000000 -#define DDRSS2_PHY_181_DATA 0x00000000 -#define DDRSS2_PHY_182_DATA 0x00000000 -#define DDRSS2_PHY_183_DATA 0x00000000 -#define DDRSS2_PHY_184_DATA 0x00000000 -#define DDRSS2_PHY_185_DATA 0x00000000 -#define DDRSS2_PHY_186_DATA 0x00000000 -#define DDRSS2_PHY_187_DATA 0x00000000 -#define DDRSS2_PHY_188_DATA 0x00000000 -#define DDRSS2_PHY_189_DATA 0x00000000 -#define DDRSS2_PHY_190_DATA 0x00000000 -#define DDRSS2_PHY_191_DATA 0x00000000 -#define DDRSS2_PHY_192_DATA 0x00000000 -#define DDRSS2_PHY_193_DATA 0x00000000 -#define DDRSS2_PHY_194_DATA 0x00000000 -#define DDRSS2_PHY_195_DATA 0x00000000 -#define DDRSS2_PHY_196_DATA 0x00000000 -#define DDRSS2_PHY_197_DATA 0x00000000 -#define DDRSS2_PHY_198_DATA 0x00000000 -#define DDRSS2_PHY_199_DATA 0x00000000 -#define DDRSS2_PHY_200_DATA 0x00000000 -#define DDRSS2_PHY_201_DATA 0x00000000 -#define DDRSS2_PHY_202_DATA 0x00000000 -#define DDRSS2_PHY_203_DATA 0x00000000 -#define DDRSS2_PHY_204_DATA 0x00000000 -#define DDRSS2_PHY_205_DATA 0x00000000 -#define DDRSS2_PHY_206_DATA 0x00000000 -#define DDRSS2_PHY_207_DATA 0x00000000 -#define DDRSS2_PHY_208_DATA 0x00000000 -#define DDRSS2_PHY_209_DATA 0x00000000 -#define DDRSS2_PHY_210_DATA 0x00000000 -#define DDRSS2_PHY_211_DATA 0x00000000 -#define DDRSS2_PHY_212_DATA 0x00000000 -#define DDRSS2_PHY_213_DATA 0x00000000 -#define DDRSS2_PHY_214_DATA 0x00000000 -#define DDRSS2_PHY_215_DATA 0x00000000 -#define DDRSS2_PHY_216_DATA 0x00000000 -#define DDRSS2_PHY_217_DATA 0x00000000 -#define DDRSS2_PHY_218_DATA 0x00000000 -#define DDRSS2_PHY_219_DATA 0x00000000 -#define DDRSS2_PHY_220_DATA 0x00000000 -#define DDRSS2_PHY_221_DATA 0x00000000 -#define DDRSS2_PHY_222_DATA 0x00000000 -#define DDRSS2_PHY_223_DATA 0x00000000 -#define DDRSS2_PHY_224_DATA 0x00000000 -#define DDRSS2_PHY_225_DATA 0x00000000 -#define DDRSS2_PHY_226_DATA 0x00000000 -#define DDRSS2_PHY_227_DATA 0x00000000 -#define DDRSS2_PHY_228_DATA 0x00000000 -#define DDRSS2_PHY_229_DATA 0x00000000 -#define DDRSS2_PHY_230_DATA 0x00000000 -#define DDRSS2_PHY_231_DATA 0x00000000 -#define DDRSS2_PHY_232_DATA 0x00000000 -#define DDRSS2_PHY_233_DATA 0x00000000 -#define DDRSS2_PHY_234_DATA 0x00000000 -#define DDRSS2_PHY_235_DATA 0x00000000 -#define DDRSS2_PHY_236_DATA 0x00000000 -#define DDRSS2_PHY_237_DATA 0x00000000 -#define DDRSS2_PHY_238_DATA 0x00000000 -#define DDRSS2_PHY_239_DATA 0x00000000 -#define DDRSS2_PHY_240_DATA 0x00000000 -#define DDRSS2_PHY_241_DATA 0x00000000 -#define DDRSS2_PHY_242_DATA 0x00000000 -#define DDRSS2_PHY_243_DATA 0x00000000 -#define DDRSS2_PHY_244_DATA 0x00000000 -#define DDRSS2_PHY_245_DATA 0x00000000 -#define DDRSS2_PHY_246_DATA 0x00000000 -#define DDRSS2_PHY_247_DATA 0x00000000 -#define DDRSS2_PHY_248_DATA 0x00000000 -#define DDRSS2_PHY_249_DATA 0x00000000 -#define DDRSS2_PHY_250_DATA 0x00000000 -#define DDRSS2_PHY_251_DATA 0x00000000 -#define DDRSS2_PHY_252_DATA 0x00000000 -#define DDRSS2_PHY_253_DATA 0x00000000 -#define DDRSS2_PHY_254_DATA 0x00000000 -#define DDRSS2_PHY_255_DATA 0x00000000 -#define DDRSS2_PHY_256_DATA 0x000004F0 -#define DDRSS2_PHY_257_DATA 0x00000000 -#define DDRSS2_PHY_258_DATA 0x00030200 -#define DDRSS2_PHY_259_DATA 0x00000000 -#define DDRSS2_PHY_260_DATA 0x00000000 -#define DDRSS2_PHY_261_DATA 0x01030000 -#define DDRSS2_PHY_262_DATA 0x00010000 -#define DDRSS2_PHY_263_DATA 0x01030004 -#define DDRSS2_PHY_264_DATA 0x01000000 -#define DDRSS2_PHY_265_DATA 0x00000000 -#define DDRSS2_PHY_266_DATA 0x00000000 -#define DDRSS2_PHY_267_DATA 0x01000001 -#define DDRSS2_PHY_268_DATA 0x00000100 -#define DDRSS2_PHY_269_DATA 0x000800C0 -#define DDRSS2_PHY_270_DATA 0x060100CC -#define DDRSS2_PHY_271_DATA 0x00030066 -#define DDRSS2_PHY_272_DATA 0x00000000 -#define DDRSS2_PHY_273_DATA 0x00000301 -#define DDRSS2_PHY_274_DATA 0x0000AAAA -#define DDRSS2_PHY_275_DATA 0x00005555 -#define DDRSS2_PHY_276_DATA 0x0000B5B5 -#define DDRSS2_PHY_277_DATA 0x00004A4A -#define DDRSS2_PHY_278_DATA 0x00005656 -#define DDRSS2_PHY_279_DATA 0x0000A9A9 -#define DDRSS2_PHY_280_DATA 0x0000A9A9 -#define DDRSS2_PHY_281_DATA 0x0000B5B5 -#define DDRSS2_PHY_282_DATA 0x00000000 -#define DDRSS2_PHY_283_DATA 0x00000000 -#define DDRSS2_PHY_284_DATA 0x2A000000 -#define DDRSS2_PHY_285_DATA 0x00000808 -#define DDRSS2_PHY_286_DATA 0x0F000000 -#define DDRSS2_PHY_287_DATA 0x00000F0F -#define DDRSS2_PHY_288_DATA 0x10400000 -#define DDRSS2_PHY_289_DATA 0x0C002006 -#define DDRSS2_PHY_290_DATA 0x00000000 -#define DDRSS2_PHY_291_DATA 0x00000000 -#define DDRSS2_PHY_292_DATA 0x55555555 -#define DDRSS2_PHY_293_DATA 0xAAAAAAAA -#define DDRSS2_PHY_294_DATA 0x55555555 -#define DDRSS2_PHY_295_DATA 0xAAAAAAAA -#define DDRSS2_PHY_296_DATA 0x00005555 -#define DDRSS2_PHY_297_DATA 0x01000100 -#define DDRSS2_PHY_298_DATA 0x00800180 -#define DDRSS2_PHY_299_DATA 0x00000000 -#define DDRSS2_PHY_300_DATA 0x00000000 -#define DDRSS2_PHY_301_DATA 0x00000000 -#define DDRSS2_PHY_302_DATA 0x00000000 -#define DDRSS2_PHY_303_DATA 0x00000000 -#define DDRSS2_PHY_304_DATA 0x00000000 -#define DDRSS2_PHY_305_DATA 0x00000000 -#define DDRSS2_PHY_306_DATA 0x00000000 -#define DDRSS2_PHY_307_DATA 0x00000000 -#define DDRSS2_PHY_308_DATA 0x00000000 -#define DDRSS2_PHY_309_DATA 0x00000000 -#define DDRSS2_PHY_310_DATA 0x00000000 -#define DDRSS2_PHY_311_DATA 0x00000000 -#define DDRSS2_PHY_312_DATA 0x00000000 -#define DDRSS2_PHY_313_DATA 0x00000000 -#define DDRSS2_PHY_314_DATA 0x00000000 -#define DDRSS2_PHY_315_DATA 0x00000000 -#define DDRSS2_PHY_316_DATA 0x00000000 -#define DDRSS2_PHY_317_DATA 0x00000000 -#define DDRSS2_PHY_318_DATA 0x00000000 -#define DDRSS2_PHY_319_DATA 0x00000000 -#define DDRSS2_PHY_320_DATA 0x00000000 -#define DDRSS2_PHY_321_DATA 0x00000000 -#define DDRSS2_PHY_322_DATA 0x00000104 -#define DDRSS2_PHY_323_DATA 0x00000120 -#define DDRSS2_PHY_324_DATA 0x00000000 -#define DDRSS2_PHY_325_DATA 0x00000000 -#define DDRSS2_PHY_326_DATA 0x00000000 -#define DDRSS2_PHY_327_DATA 0x00000000 -#define DDRSS2_PHY_328_DATA 0x00000000 -#define DDRSS2_PHY_329_DATA 0x00000000 -#define DDRSS2_PHY_330_DATA 0x00000000 -#define DDRSS2_PHY_331_DATA 0x00000001 -#define DDRSS2_PHY_332_DATA 0x07FF0000 -#define DDRSS2_PHY_333_DATA 0x0080081F -#define DDRSS2_PHY_334_DATA 0x00081020 -#define DDRSS2_PHY_335_DATA 0x04010000 -#define DDRSS2_PHY_336_DATA 0x00000000 -#define DDRSS2_PHY_337_DATA 0x00000000 -#define DDRSS2_PHY_338_DATA 0x00000000 -#define DDRSS2_PHY_339_DATA 0x00000100 -#define DDRSS2_PHY_340_DATA 0x01CC0C01 -#define DDRSS2_PHY_341_DATA 0x1003CC0C -#define DDRSS2_PHY_342_DATA 0x20000140 -#define DDRSS2_PHY_343_DATA 0x07FF0200 -#define DDRSS2_PHY_344_DATA 0x0000DD01 -#define DDRSS2_PHY_345_DATA 0x10100303 -#define DDRSS2_PHY_346_DATA 0x10101010 -#define DDRSS2_PHY_347_DATA 0x10101010 -#define DDRSS2_PHY_348_DATA 0x00021010 -#define DDRSS2_PHY_349_DATA 0x00100010 -#define DDRSS2_PHY_350_DATA 0x00100010 -#define DDRSS2_PHY_351_DATA 0x00100010 -#define DDRSS2_PHY_352_DATA 0x00100010 -#define DDRSS2_PHY_353_DATA 0x00050010 -#define DDRSS2_PHY_354_DATA 0x51517041 -#define DDRSS2_PHY_355_DATA 0x31C06001 -#define DDRSS2_PHY_356_DATA 0x07AB0340 -#define DDRSS2_PHY_357_DATA 0x00C0C001 -#define DDRSS2_PHY_358_DATA 0x0E0D0001 -#define DDRSS2_PHY_359_DATA 0x10001000 -#define DDRSS2_PHY_360_DATA 0x0C083E42 -#define DDRSS2_PHY_361_DATA 0x0F0C3701 -#define DDRSS2_PHY_362_DATA 0x01000140 -#define DDRSS2_PHY_363_DATA 0x0C000420 -#define DDRSS2_PHY_364_DATA 0x00000198 -#define DDRSS2_PHY_365_DATA 0x0A0000D0 -#define DDRSS2_PHY_366_DATA 0x00030200 -#define DDRSS2_PHY_367_DATA 0x02800000 -#define DDRSS2_PHY_368_DATA 0x80800000 -#define DDRSS2_PHY_369_DATA 0x000E2010 -#define DDRSS2_PHY_370_DATA 0x76543210 -#define DDRSS2_PHY_371_DATA 0x00000008 -#define DDRSS2_PHY_372_DATA 0x02800280 -#define DDRSS2_PHY_373_DATA 0x02800280 -#define DDRSS2_PHY_374_DATA 0x02800280 -#define DDRSS2_PHY_375_DATA 0x02800280 -#define DDRSS2_PHY_376_DATA 0x00000280 -#define DDRSS2_PHY_377_DATA 0x0000A000 -#define DDRSS2_PHY_378_DATA 0x00A000A0 -#define DDRSS2_PHY_379_DATA 0x00A000A0 -#define DDRSS2_PHY_380_DATA 0x00A000A0 -#define DDRSS2_PHY_381_DATA 0x00A000A0 -#define DDRSS2_PHY_382_DATA 0x00A000A0 -#define DDRSS2_PHY_383_DATA 0x00A000A0 -#define DDRSS2_PHY_384_DATA 0x00A000A0 -#define DDRSS2_PHY_385_DATA 0x00A000A0 -#define DDRSS2_PHY_386_DATA 0x01C200A0 -#define DDRSS2_PHY_387_DATA 0x01A00005 -#define DDRSS2_PHY_388_DATA 0x00000000 -#define DDRSS2_PHY_389_DATA 0x00000000 -#define DDRSS2_PHY_390_DATA 0x00080200 -#define DDRSS2_PHY_391_DATA 0x00000000 -#define DDRSS2_PHY_392_DATA 0x20202000 -#define DDRSS2_PHY_393_DATA 0x20202020 -#define DDRSS2_PHY_394_DATA 0xF0F02020 -#define DDRSS2_PHY_395_DATA 0x00000000 -#define DDRSS2_PHY_396_DATA 0x00000000 -#define DDRSS2_PHY_397_DATA 0x00000000 -#define DDRSS2_PHY_398_DATA 0x00000000 -#define DDRSS2_PHY_399_DATA 0x00000000 -#define DDRSS2_PHY_400_DATA 0x00000000 -#define DDRSS2_PHY_401_DATA 0x00000000 -#define DDRSS2_PHY_402_DATA 0x00000000 -#define DDRSS2_PHY_403_DATA 0x00000000 -#define DDRSS2_PHY_404_DATA 0x00000000 -#define DDRSS2_PHY_405_DATA 0x00000000 -#define DDRSS2_PHY_406_DATA 0x00000000 -#define DDRSS2_PHY_407_DATA 0x00000000 -#define DDRSS2_PHY_408_DATA 0x00000000 -#define DDRSS2_PHY_409_DATA 0x00000000 -#define DDRSS2_PHY_410_DATA 0x00000000 -#define DDRSS2_PHY_411_DATA 0x00000000 -#define DDRSS2_PHY_412_DATA 0x00000000 -#define DDRSS2_PHY_413_DATA 0x00000000 -#define DDRSS2_PHY_414_DATA 0x00000000 -#define DDRSS2_PHY_415_DATA 0x00000000 -#define DDRSS2_PHY_416_DATA 0x00000000 -#define DDRSS2_PHY_417_DATA 0x00000000 -#define DDRSS2_PHY_418_DATA 0x00000000 -#define DDRSS2_PHY_419_DATA 0x00000000 -#define DDRSS2_PHY_420_DATA 0x00000000 -#define DDRSS2_PHY_421_DATA 0x00000000 -#define DDRSS2_PHY_422_DATA 0x00000000 -#define DDRSS2_PHY_423_DATA 0x00000000 -#define DDRSS2_PHY_424_DATA 0x00000000 -#define DDRSS2_PHY_425_DATA 0x00000000 -#define DDRSS2_PHY_426_DATA 0x00000000 -#define DDRSS2_PHY_427_DATA 0x00000000 -#define DDRSS2_PHY_428_DATA 0x00000000 -#define DDRSS2_PHY_429_DATA 0x00000000 -#define DDRSS2_PHY_430_DATA 0x00000000 -#define DDRSS2_PHY_431_DATA 0x00000000 -#define DDRSS2_PHY_432_DATA 0x00000000 -#define DDRSS2_PHY_433_DATA 0x00000000 -#define DDRSS2_PHY_434_DATA 0x00000000 -#define DDRSS2_PHY_435_DATA 0x00000000 -#define DDRSS2_PHY_436_DATA 0x00000000 -#define DDRSS2_PHY_437_DATA 0x00000000 -#define DDRSS2_PHY_438_DATA 0x00000000 -#define DDRSS2_PHY_439_DATA 0x00000000 -#define DDRSS2_PHY_440_DATA 0x00000000 -#define DDRSS2_PHY_441_DATA 0x00000000 -#define DDRSS2_PHY_442_DATA 0x00000000 -#define DDRSS2_PHY_443_DATA 0x00000000 -#define DDRSS2_PHY_444_DATA 0x00000000 -#define DDRSS2_PHY_445_DATA 0x00000000 -#define DDRSS2_PHY_446_DATA 0x00000000 -#define DDRSS2_PHY_447_DATA 0x00000000 -#define DDRSS2_PHY_448_DATA 0x00000000 -#define DDRSS2_PHY_449_DATA 0x00000000 -#define DDRSS2_PHY_450_DATA 0x00000000 -#define DDRSS2_PHY_451_DATA 0x00000000 -#define DDRSS2_PHY_452_DATA 0x00000000 -#define DDRSS2_PHY_453_DATA 0x00000000 -#define DDRSS2_PHY_454_DATA 0x00000000 -#define DDRSS2_PHY_455_DATA 0x00000000 -#define DDRSS2_PHY_456_DATA 0x00000000 -#define DDRSS2_PHY_457_DATA 0x00000000 -#define DDRSS2_PHY_458_DATA 0x00000000 -#define DDRSS2_PHY_459_DATA 0x00000000 -#define DDRSS2_PHY_460_DATA 0x00000000 -#define DDRSS2_PHY_461_DATA 0x00000000 -#define DDRSS2_PHY_462_DATA 0x00000000 -#define DDRSS2_PHY_463_DATA 0x00000000 -#define DDRSS2_PHY_464_DATA 0x00000000 -#define DDRSS2_PHY_465_DATA 0x00000000 -#define DDRSS2_PHY_466_DATA 0x00000000 -#define DDRSS2_PHY_467_DATA 0x00000000 -#define DDRSS2_PHY_468_DATA 0x00000000 -#define DDRSS2_PHY_469_DATA 0x00000000 -#define DDRSS2_PHY_470_DATA 0x00000000 -#define DDRSS2_PHY_471_DATA 0x00000000 -#define DDRSS2_PHY_472_DATA 0x00000000 -#define DDRSS2_PHY_473_DATA 0x00000000 -#define DDRSS2_PHY_474_DATA 0x00000000 -#define DDRSS2_PHY_475_DATA 0x00000000 -#define DDRSS2_PHY_476_DATA 0x00000000 -#define DDRSS2_PHY_477_DATA 0x00000000 -#define DDRSS2_PHY_478_DATA 0x00000000 -#define DDRSS2_PHY_479_DATA 0x00000000 -#define DDRSS2_PHY_480_DATA 0x00000000 -#define DDRSS2_PHY_481_DATA 0x00000000 -#define DDRSS2_PHY_482_DATA 0x00000000 -#define DDRSS2_PHY_483_DATA 0x00000000 -#define DDRSS2_PHY_484_DATA 0x00000000 -#define DDRSS2_PHY_485_DATA 0x00000000 -#define DDRSS2_PHY_486_DATA 0x00000000 -#define DDRSS2_PHY_487_DATA 0x00000000 -#define DDRSS2_PHY_488_DATA 0x00000000 -#define DDRSS2_PHY_489_DATA 0x00000000 -#define DDRSS2_PHY_490_DATA 0x00000000 -#define DDRSS2_PHY_491_DATA 0x00000000 -#define DDRSS2_PHY_492_DATA 0x00000000 -#define DDRSS2_PHY_493_DATA 0x00000000 -#define DDRSS2_PHY_494_DATA 0x00000000 -#define DDRSS2_PHY_495_DATA 0x00000000 -#define DDRSS2_PHY_496_DATA 0x00000000 -#define DDRSS2_PHY_497_DATA 0x00000000 -#define DDRSS2_PHY_498_DATA 0x00000000 -#define DDRSS2_PHY_499_DATA 0x00000000 -#define DDRSS2_PHY_500_DATA 0x00000000 -#define DDRSS2_PHY_501_DATA 0x00000000 -#define DDRSS2_PHY_502_DATA 0x00000000 -#define DDRSS2_PHY_503_DATA 0x00000000 -#define DDRSS2_PHY_504_DATA 0x00000000 -#define DDRSS2_PHY_505_DATA 0x00000000 -#define DDRSS2_PHY_506_DATA 0x00000000 -#define DDRSS2_PHY_507_DATA 0x00000000 -#define DDRSS2_PHY_508_DATA 0x00000000 -#define DDRSS2_PHY_509_DATA 0x00000000 -#define DDRSS2_PHY_510_DATA 0x00000000 -#define DDRSS2_PHY_511_DATA 0x00000000 -#define DDRSS2_PHY_512_DATA 0x000004F0 -#define DDRSS2_PHY_513_DATA 0x00000000 -#define DDRSS2_PHY_514_DATA 0x00030200 -#define DDRSS2_PHY_515_DATA 0x00000000 -#define DDRSS2_PHY_516_DATA 0x00000000 -#define DDRSS2_PHY_517_DATA 0x01030000 -#define DDRSS2_PHY_518_DATA 0x00010000 -#define DDRSS2_PHY_519_DATA 0x01030004 -#define DDRSS2_PHY_520_DATA 0x01000000 -#define DDRSS2_PHY_521_DATA 0x00000000 -#define DDRSS2_PHY_522_DATA 0x00000000 -#define DDRSS2_PHY_523_DATA 0x01000001 -#define DDRSS2_PHY_524_DATA 0x00000100 -#define DDRSS2_PHY_525_DATA 0x000800C0 -#define DDRSS2_PHY_526_DATA 0x060100CC -#define DDRSS2_PHY_527_DATA 0x00030066 -#define DDRSS2_PHY_528_DATA 0x00000000 -#define DDRSS2_PHY_529_DATA 0x00000301 -#define DDRSS2_PHY_530_DATA 0x0000AAAA -#define DDRSS2_PHY_531_DATA 0x00005555 -#define DDRSS2_PHY_532_DATA 0x0000B5B5 -#define DDRSS2_PHY_533_DATA 0x00004A4A -#define DDRSS2_PHY_534_DATA 0x00005656 -#define DDRSS2_PHY_535_DATA 0x0000A9A9 -#define DDRSS2_PHY_536_DATA 0x0000A9A9 -#define DDRSS2_PHY_537_DATA 0x0000B5B5 -#define DDRSS2_PHY_538_DATA 0x00000000 -#define DDRSS2_PHY_539_DATA 0x00000000 -#define DDRSS2_PHY_540_DATA 0x2A000000 -#define DDRSS2_PHY_541_DATA 0x00000808 -#define DDRSS2_PHY_542_DATA 0x0F000000 -#define DDRSS2_PHY_543_DATA 0x00000F0F -#define DDRSS2_PHY_544_DATA 0x10400000 -#define DDRSS2_PHY_545_DATA 0x0C002006 -#define DDRSS2_PHY_546_DATA 0x00000000 -#define DDRSS2_PHY_547_DATA 0x00000000 -#define DDRSS2_PHY_548_DATA 0x55555555 -#define DDRSS2_PHY_549_DATA 0xAAAAAAAA -#define DDRSS2_PHY_550_DATA 0x55555555 -#define DDRSS2_PHY_551_DATA 0xAAAAAAAA -#define DDRSS2_PHY_552_DATA 0x00005555 -#define DDRSS2_PHY_553_DATA 0x01000100 -#define DDRSS2_PHY_554_DATA 0x00800180 -#define DDRSS2_PHY_555_DATA 0x00000001 -#define DDRSS2_PHY_556_DATA 0x00000000 -#define DDRSS2_PHY_557_DATA 0x00000000 -#define DDRSS2_PHY_558_DATA 0x00000000 -#define DDRSS2_PHY_559_DATA 0x00000000 -#define DDRSS2_PHY_560_DATA 0x00000000 -#define DDRSS2_PHY_561_DATA 0x00000000 -#define DDRSS2_PHY_562_DATA 0x00000000 -#define DDRSS2_PHY_563_DATA 0x00000000 -#define DDRSS2_PHY_564_DATA 0x00000000 -#define DDRSS2_PHY_565_DATA 0x00000000 -#define DDRSS2_PHY_566_DATA 0x00000000 -#define DDRSS2_PHY_567_DATA 0x00000000 -#define DDRSS2_PHY_568_DATA 0x00000000 -#define DDRSS2_PHY_569_DATA 0x00000000 -#define DDRSS2_PHY_570_DATA 0x00000000 -#define DDRSS2_PHY_571_DATA 0x00000000 -#define DDRSS2_PHY_572_DATA 0x00000000 -#define DDRSS2_PHY_573_DATA 0x00000000 -#define DDRSS2_PHY_574_DATA 0x00000000 -#define DDRSS2_PHY_575_DATA 0x00000000 -#define DDRSS2_PHY_576_DATA 0x00000000 -#define DDRSS2_PHY_577_DATA 0x00000000 -#define DDRSS2_PHY_578_DATA 0x00000104 -#define DDRSS2_PHY_579_DATA 0x00000120 -#define DDRSS2_PHY_580_DATA 0x00000000 -#define DDRSS2_PHY_581_DATA 0x00000000 -#define DDRSS2_PHY_582_DATA 0x00000000 -#define DDRSS2_PHY_583_DATA 0x00000000 -#define DDRSS2_PHY_584_DATA 0x00000000 -#define DDRSS2_PHY_585_DATA 0x00000000 -#define DDRSS2_PHY_586_DATA 0x00000000 -#define DDRSS2_PHY_587_DATA 0x00000001 -#define DDRSS2_PHY_588_DATA 0x07FF0000 -#define DDRSS2_PHY_589_DATA 0x0080081F -#define DDRSS2_PHY_590_DATA 0x00081020 -#define DDRSS2_PHY_591_DATA 0x04010000 -#define DDRSS2_PHY_592_DATA 0x00000000 -#define DDRSS2_PHY_593_DATA 0x00000000 -#define DDRSS2_PHY_594_DATA 0x00000000 -#define DDRSS2_PHY_595_DATA 0x00000100 -#define DDRSS2_PHY_596_DATA 0x01CC0C01 -#define DDRSS2_PHY_597_DATA 0x1003CC0C -#define DDRSS2_PHY_598_DATA 0x20000140 -#define DDRSS2_PHY_599_DATA 0x07FF0200 -#define DDRSS2_PHY_600_DATA 0x0000DD01 -#define DDRSS2_PHY_601_DATA 0x10100303 -#define DDRSS2_PHY_602_DATA 0x10101010 -#define DDRSS2_PHY_603_DATA 0x10101010 -#define DDRSS2_PHY_604_DATA 0x00021010 -#define DDRSS2_PHY_605_DATA 0x00100010 -#define DDRSS2_PHY_606_DATA 0x00100010 -#define DDRSS2_PHY_607_DATA 0x00100010 -#define DDRSS2_PHY_608_DATA 0x00100010 -#define DDRSS2_PHY_609_DATA 0x00050010 -#define DDRSS2_PHY_610_DATA 0x51517041 -#define DDRSS2_PHY_611_DATA 0x31C06001 -#define DDRSS2_PHY_612_DATA 0x07AB0340 -#define DDRSS2_PHY_613_DATA 0x00C0C001 -#define DDRSS2_PHY_614_DATA 0x0E0D0001 -#define DDRSS2_PHY_615_DATA 0x10001000 -#define DDRSS2_PHY_616_DATA 0x0C083E42 -#define DDRSS2_PHY_617_DATA 0x0F0C3701 -#define DDRSS2_PHY_618_DATA 0x01000140 -#define DDRSS2_PHY_619_DATA 0x0C000420 -#define DDRSS2_PHY_620_DATA 0x00000198 -#define DDRSS2_PHY_621_DATA 0x0A0000D0 -#define DDRSS2_PHY_622_DATA 0x00030200 -#define DDRSS2_PHY_623_DATA 0x02800000 -#define DDRSS2_PHY_624_DATA 0x80800000 -#define DDRSS2_PHY_625_DATA 0x000E2010 -#define DDRSS2_PHY_626_DATA 0x76543210 -#define DDRSS2_PHY_627_DATA 0x00000008 -#define DDRSS2_PHY_628_DATA 0x02800280 -#define DDRSS2_PHY_629_DATA 0x02800280 -#define DDRSS2_PHY_630_DATA 0x02800280 -#define DDRSS2_PHY_631_DATA 0x02800280 -#define DDRSS2_PHY_632_DATA 0x00000280 -#define DDRSS2_PHY_633_DATA 0x0000A000 -#define DDRSS2_PHY_634_DATA 0x00A000A0 -#define DDRSS2_PHY_635_DATA 0x00A000A0 -#define DDRSS2_PHY_636_DATA 0x00A000A0 -#define DDRSS2_PHY_637_DATA 0x00A000A0 -#define DDRSS2_PHY_638_DATA 0x00A000A0 -#define DDRSS2_PHY_639_DATA 0x00A000A0 -#define DDRSS2_PHY_640_DATA 0x00A000A0 -#define DDRSS2_PHY_641_DATA 0x00A000A0 -#define DDRSS2_PHY_642_DATA 0x01C200A0 -#define DDRSS2_PHY_643_DATA 0x01A00005 -#define DDRSS2_PHY_644_DATA 0x00000000 -#define DDRSS2_PHY_645_DATA 0x00000000 -#define DDRSS2_PHY_646_DATA 0x00080200 -#define DDRSS2_PHY_647_DATA 0x00000000 -#define DDRSS2_PHY_648_DATA 0x20202000 -#define DDRSS2_PHY_649_DATA 0x20202020 -#define DDRSS2_PHY_650_DATA 0xF0F02020 -#define DDRSS2_PHY_651_DATA 0x00000000 -#define DDRSS2_PHY_652_DATA 0x00000000 -#define DDRSS2_PHY_653_DATA 0x00000000 -#define DDRSS2_PHY_654_DATA 0x00000000 -#define DDRSS2_PHY_655_DATA 0x00000000 -#define DDRSS2_PHY_656_DATA 0x00000000 -#define DDRSS2_PHY_657_DATA 0x00000000 -#define DDRSS2_PHY_658_DATA 0x00000000 -#define DDRSS2_PHY_659_DATA 0x00000000 -#define DDRSS2_PHY_660_DATA 0x00000000 -#define DDRSS2_PHY_661_DATA 0x00000000 -#define DDRSS2_PHY_662_DATA 0x00000000 -#define DDRSS2_PHY_663_DATA 0x00000000 -#define DDRSS2_PHY_664_DATA 0x00000000 -#define DDRSS2_PHY_665_DATA 0x00000000 -#define DDRSS2_PHY_666_DATA 0x00000000 -#define DDRSS2_PHY_667_DATA 0x00000000 -#define DDRSS2_PHY_668_DATA 0x00000000 -#define DDRSS2_PHY_669_DATA 0x00000000 -#define DDRSS2_PHY_670_DATA 0x00000000 -#define DDRSS2_PHY_671_DATA 0x00000000 -#define DDRSS2_PHY_672_DATA 0x00000000 -#define DDRSS2_PHY_673_DATA 0x00000000 -#define DDRSS2_PHY_674_DATA 0x00000000 -#define DDRSS2_PHY_675_DATA 0x00000000 -#define DDRSS2_PHY_676_DATA 0x00000000 -#define DDRSS2_PHY_677_DATA 0x00000000 -#define DDRSS2_PHY_678_DATA 0x00000000 -#define DDRSS2_PHY_679_DATA 0x00000000 -#define DDRSS2_PHY_680_DATA 0x00000000 -#define DDRSS2_PHY_681_DATA 0x00000000 -#define DDRSS2_PHY_682_DATA 0x00000000 -#define DDRSS2_PHY_683_DATA 0x00000000 -#define DDRSS2_PHY_684_DATA 0x00000000 -#define DDRSS2_PHY_685_DATA 0x00000000 -#define DDRSS2_PHY_686_DATA 0x00000000 -#define DDRSS2_PHY_687_DATA 0x00000000 -#define DDRSS2_PHY_688_DATA 0x00000000 -#define DDRSS2_PHY_689_DATA 0x00000000 -#define DDRSS2_PHY_690_DATA 0x00000000 -#define DDRSS2_PHY_691_DATA 0x00000000 -#define DDRSS2_PHY_692_DATA 0x00000000 -#define DDRSS2_PHY_693_DATA 0x00000000 -#define DDRSS2_PHY_694_DATA 0x00000000 -#define DDRSS2_PHY_695_DATA 0x00000000 -#define DDRSS2_PHY_696_DATA 0x00000000 -#define DDRSS2_PHY_697_DATA 0x00000000 -#define DDRSS2_PHY_698_DATA 0x00000000 -#define DDRSS2_PHY_699_DATA 0x00000000 -#define DDRSS2_PHY_700_DATA 0x00000000 -#define DDRSS2_PHY_701_DATA 0x00000000 -#define DDRSS2_PHY_702_DATA 0x00000000 -#define DDRSS2_PHY_703_DATA 0x00000000 -#define DDRSS2_PHY_704_DATA 0x00000000 -#define DDRSS2_PHY_705_DATA 0x00000000 -#define DDRSS2_PHY_706_DATA 0x00000000 -#define DDRSS2_PHY_707_DATA 0x00000000 -#define DDRSS2_PHY_708_DATA 0x00000000 -#define DDRSS2_PHY_709_DATA 0x00000000 -#define DDRSS2_PHY_710_DATA 0x00000000 -#define DDRSS2_PHY_711_DATA 0x00000000 -#define DDRSS2_PHY_712_DATA 0x00000000 -#define DDRSS2_PHY_713_DATA 0x00000000 -#define DDRSS2_PHY_714_DATA 0x00000000 -#define DDRSS2_PHY_715_DATA 0x00000000 -#define DDRSS2_PHY_716_DATA 0x00000000 -#define DDRSS2_PHY_717_DATA 0x00000000 -#define DDRSS2_PHY_718_DATA 0x00000000 -#define DDRSS2_PHY_719_DATA 0x00000000 -#define DDRSS2_PHY_720_DATA 0x00000000 -#define DDRSS2_PHY_721_DATA 0x00000000 -#define DDRSS2_PHY_722_DATA 0x00000000 -#define DDRSS2_PHY_723_DATA 0x00000000 -#define DDRSS2_PHY_724_DATA 0x00000000 -#define DDRSS2_PHY_725_DATA 0x00000000 -#define DDRSS2_PHY_726_DATA 0x00000000 -#define DDRSS2_PHY_727_DATA 0x00000000 -#define DDRSS2_PHY_728_DATA 0x00000000 -#define DDRSS2_PHY_729_DATA 0x00000000 -#define DDRSS2_PHY_730_DATA 0x00000000 -#define DDRSS2_PHY_731_DATA 0x00000000 -#define DDRSS2_PHY_732_DATA 0x00000000 -#define DDRSS2_PHY_733_DATA 0x00000000 -#define DDRSS2_PHY_734_DATA 0x00000000 -#define DDRSS2_PHY_735_DATA 0x00000000 -#define DDRSS2_PHY_736_DATA 0x00000000 -#define DDRSS2_PHY_737_DATA 0x00000000 -#define DDRSS2_PHY_738_DATA 0x00000000 -#define DDRSS2_PHY_739_DATA 0x00000000 -#define DDRSS2_PHY_740_DATA 0x00000000 -#define DDRSS2_PHY_741_DATA 0x00000000 -#define DDRSS2_PHY_742_DATA 0x00000000 -#define DDRSS2_PHY_743_DATA 0x00000000 -#define DDRSS2_PHY_744_DATA 0x00000000 -#define DDRSS2_PHY_745_DATA 0x00000000 -#define DDRSS2_PHY_746_DATA 0x00000000 -#define DDRSS2_PHY_747_DATA 0x00000000 -#define DDRSS2_PHY_748_DATA 0x00000000 -#define DDRSS2_PHY_749_DATA 0x00000000 -#define DDRSS2_PHY_750_DATA 0x00000000 -#define DDRSS2_PHY_751_DATA 0x00000000 -#define DDRSS2_PHY_752_DATA 0x00000000 -#define DDRSS2_PHY_753_DATA 0x00000000 -#define DDRSS2_PHY_754_DATA 0x00000000 -#define DDRSS2_PHY_755_DATA 0x00000000 -#define DDRSS2_PHY_756_DATA 0x00000000 -#define DDRSS2_PHY_757_DATA 0x00000000 -#define DDRSS2_PHY_758_DATA 0x00000000 -#define DDRSS2_PHY_759_DATA 0x00000000 -#define DDRSS2_PHY_760_DATA 0x00000000 -#define DDRSS2_PHY_761_DATA 0x00000000 -#define DDRSS2_PHY_762_DATA 0x00000000 -#define DDRSS2_PHY_763_DATA 0x00000000 -#define DDRSS2_PHY_764_DATA 0x00000000 -#define DDRSS2_PHY_765_DATA 0x00000000 -#define DDRSS2_PHY_766_DATA 0x00000000 -#define DDRSS2_PHY_767_DATA 0x00000000 -#define DDRSS2_PHY_768_DATA 0x000004F0 -#define DDRSS2_PHY_769_DATA 0x00000000 -#define DDRSS2_PHY_770_DATA 0x00030200 -#define DDRSS2_PHY_771_DATA 0x00000000 -#define DDRSS2_PHY_772_DATA 0x00000000 -#define DDRSS2_PHY_773_DATA 0x01030000 -#define DDRSS2_PHY_774_DATA 0x00010000 -#define DDRSS2_PHY_775_DATA 0x01030004 -#define DDRSS2_PHY_776_DATA 0x01000000 -#define DDRSS2_PHY_777_DATA 0x00000000 -#define DDRSS2_PHY_778_DATA 0x00000000 -#define DDRSS2_PHY_779_DATA 0x01000001 -#define DDRSS2_PHY_780_DATA 0x00000100 -#define DDRSS2_PHY_781_DATA 0x000800C0 -#define DDRSS2_PHY_782_DATA 0x060100CC -#define DDRSS2_PHY_783_DATA 0x00030066 -#define DDRSS2_PHY_784_DATA 0x00000000 -#define DDRSS2_PHY_785_DATA 0x00000301 -#define DDRSS2_PHY_786_DATA 0x0000AAAA -#define DDRSS2_PHY_787_DATA 0x00005555 -#define DDRSS2_PHY_788_DATA 0x0000B5B5 -#define DDRSS2_PHY_789_DATA 0x00004A4A -#define DDRSS2_PHY_790_DATA 0x00005656 -#define DDRSS2_PHY_791_DATA 0x0000A9A9 -#define DDRSS2_PHY_792_DATA 0x0000A9A9 -#define DDRSS2_PHY_793_DATA 0x0000B5B5 -#define DDRSS2_PHY_794_DATA 0x00000000 -#define DDRSS2_PHY_795_DATA 0x00000000 -#define DDRSS2_PHY_796_DATA 0x2A000000 -#define DDRSS2_PHY_797_DATA 0x00000808 -#define DDRSS2_PHY_798_DATA 0x0F000000 -#define DDRSS2_PHY_799_DATA 0x00000F0F -#define DDRSS2_PHY_800_DATA 0x10400000 -#define DDRSS2_PHY_801_DATA 0x0C002006 -#define DDRSS2_PHY_802_DATA 0x00000000 -#define DDRSS2_PHY_803_DATA 0x00000000 -#define DDRSS2_PHY_804_DATA 0x55555555 -#define DDRSS2_PHY_805_DATA 0xAAAAAAAA -#define DDRSS2_PHY_806_DATA 0x55555555 -#define DDRSS2_PHY_807_DATA 0xAAAAAAAA -#define DDRSS2_PHY_808_DATA 0x00005555 -#define DDRSS2_PHY_809_DATA 0x01000100 -#define DDRSS2_PHY_810_DATA 0x00800180 -#define DDRSS2_PHY_811_DATA 0x00000000 -#define DDRSS2_PHY_812_DATA 0x00000000 -#define DDRSS2_PHY_813_DATA 0x00000000 -#define DDRSS2_PHY_814_DATA 0x00000000 -#define DDRSS2_PHY_815_DATA 0x00000000 -#define DDRSS2_PHY_816_DATA 0x00000000 -#define DDRSS2_PHY_817_DATA 0x00000000 -#define DDRSS2_PHY_818_DATA 0x00000000 -#define DDRSS2_PHY_819_DATA 0x00000000 -#define DDRSS2_PHY_820_DATA 0x00000000 -#define DDRSS2_PHY_821_DATA 0x00000000 -#define DDRSS2_PHY_822_DATA 0x00000000 -#define DDRSS2_PHY_823_DATA 0x00000000 -#define DDRSS2_PHY_824_DATA 0x00000000 -#define DDRSS2_PHY_825_DATA 0x00000000 -#define DDRSS2_PHY_826_DATA 0x00000000 -#define DDRSS2_PHY_827_DATA 0x00000000 -#define DDRSS2_PHY_828_DATA 0x00000000 -#define DDRSS2_PHY_829_DATA 0x00000000 -#define DDRSS2_PHY_830_DATA 0x00000000 -#define DDRSS2_PHY_831_DATA 0x00000000 -#define DDRSS2_PHY_832_DATA 0x00000000 -#define DDRSS2_PHY_833_DATA 0x00000000 -#define DDRSS2_PHY_834_DATA 0x00000104 -#define DDRSS2_PHY_835_DATA 0x00000120 -#define DDRSS2_PHY_836_DATA 0x00000000 -#define DDRSS2_PHY_837_DATA 0x00000000 -#define DDRSS2_PHY_838_DATA 0x00000000 -#define DDRSS2_PHY_839_DATA 0x00000000 -#define DDRSS2_PHY_840_DATA 0x00000000 -#define DDRSS2_PHY_841_DATA 0x00000000 -#define DDRSS2_PHY_842_DATA 0x00000000 -#define DDRSS2_PHY_843_DATA 0x00000001 -#define DDRSS2_PHY_844_DATA 0x07FF0000 -#define DDRSS2_PHY_845_DATA 0x0080081F -#define DDRSS2_PHY_846_DATA 0x00081020 -#define DDRSS2_PHY_847_DATA 0x04010000 -#define DDRSS2_PHY_848_DATA 0x00000000 -#define DDRSS2_PHY_849_DATA 0x00000000 -#define DDRSS2_PHY_850_DATA 0x00000000 -#define DDRSS2_PHY_851_DATA 0x00000100 -#define DDRSS2_PHY_852_DATA 0x01CC0C01 -#define DDRSS2_PHY_853_DATA 0x1003CC0C -#define DDRSS2_PHY_854_DATA 0x20000140 -#define DDRSS2_PHY_855_DATA 0x07FF0200 -#define DDRSS2_PHY_856_DATA 0x0000DD01 -#define DDRSS2_PHY_857_DATA 0x10100303 -#define DDRSS2_PHY_858_DATA 0x10101010 -#define DDRSS2_PHY_859_DATA 0x10101010 -#define DDRSS2_PHY_860_DATA 0x00021010 -#define DDRSS2_PHY_861_DATA 0x00100010 -#define DDRSS2_PHY_862_DATA 0x00100010 -#define DDRSS2_PHY_863_DATA 0x00100010 -#define DDRSS2_PHY_864_DATA 0x00100010 -#define DDRSS2_PHY_865_DATA 0x00050010 -#define DDRSS2_PHY_866_DATA 0x51517041 -#define DDRSS2_PHY_867_DATA 0x31C06001 -#define DDRSS2_PHY_868_DATA 0x07AB0340 -#define DDRSS2_PHY_869_DATA 0x00C0C001 -#define DDRSS2_PHY_870_DATA 0x0E0D0001 -#define DDRSS2_PHY_871_DATA 0x10001000 -#define DDRSS2_PHY_872_DATA 0x0C083E42 -#define DDRSS2_PHY_873_DATA 0x0F0C3701 -#define DDRSS2_PHY_874_DATA 0x01000140 -#define DDRSS2_PHY_875_DATA 0x0C000420 -#define DDRSS2_PHY_876_DATA 0x00000198 -#define DDRSS2_PHY_877_DATA 0x0A0000D0 -#define DDRSS2_PHY_878_DATA 0x00030200 -#define DDRSS2_PHY_879_DATA 0x02800000 -#define DDRSS2_PHY_880_DATA 0x80800000 -#define DDRSS2_PHY_881_DATA 0x000E2010 -#define DDRSS2_PHY_882_DATA 0x76543210 -#define DDRSS2_PHY_883_DATA 0x00000008 -#define DDRSS2_PHY_884_DATA 0x02800280 -#define DDRSS2_PHY_885_DATA 0x02800280 -#define DDRSS2_PHY_886_DATA 0x02800280 -#define DDRSS2_PHY_887_DATA 0x02800280 -#define DDRSS2_PHY_888_DATA 0x00000280 -#define DDRSS2_PHY_889_DATA 0x0000A000 -#define DDRSS2_PHY_890_DATA 0x00A000A0 -#define DDRSS2_PHY_891_DATA 0x00A000A0 -#define DDRSS2_PHY_892_DATA 0x00A000A0 -#define DDRSS2_PHY_893_DATA 0x00A000A0 -#define DDRSS2_PHY_894_DATA 0x00A000A0 -#define DDRSS2_PHY_895_DATA 0x00A000A0 -#define DDRSS2_PHY_896_DATA 0x00A000A0 -#define DDRSS2_PHY_897_DATA 0x00A000A0 -#define DDRSS2_PHY_898_DATA 0x01C200A0 -#define DDRSS2_PHY_899_DATA 0x01A00005 -#define DDRSS2_PHY_900_DATA 0x00000000 -#define DDRSS2_PHY_901_DATA 0x00000000 -#define DDRSS2_PHY_902_DATA 0x00080200 -#define DDRSS2_PHY_903_DATA 0x00000000 -#define DDRSS2_PHY_904_DATA 0x20202000 -#define DDRSS2_PHY_905_DATA 0x20202020 -#define DDRSS2_PHY_906_DATA 0xF0F02020 -#define DDRSS2_PHY_907_DATA 0x00000000 -#define DDRSS2_PHY_908_DATA 0x00000000 -#define DDRSS2_PHY_909_DATA 0x00000000 -#define DDRSS2_PHY_910_DATA 0x00000000 -#define DDRSS2_PHY_911_DATA 0x00000000 -#define DDRSS2_PHY_912_DATA 0x00000000 -#define DDRSS2_PHY_913_DATA 0x00000000 -#define DDRSS2_PHY_914_DATA 0x00000000 -#define DDRSS2_PHY_915_DATA 0x00000000 -#define DDRSS2_PHY_916_DATA 0x00000000 -#define DDRSS2_PHY_917_DATA 0x00000000 -#define DDRSS2_PHY_918_DATA 0x00000000 -#define DDRSS2_PHY_919_DATA 0x00000000 -#define DDRSS2_PHY_920_DATA 0x00000000 -#define DDRSS2_PHY_921_DATA 0x00000000 -#define DDRSS2_PHY_922_DATA 0x00000000 -#define DDRSS2_PHY_923_DATA 0x00000000 -#define DDRSS2_PHY_924_DATA 0x00000000 -#define DDRSS2_PHY_925_DATA 0x00000000 -#define DDRSS2_PHY_926_DATA 0x00000000 -#define DDRSS2_PHY_927_DATA 0x00000000 -#define DDRSS2_PHY_928_DATA 0x00000000 -#define DDRSS2_PHY_929_DATA 0x00000000 -#define DDRSS2_PHY_930_DATA 0x00000000 -#define DDRSS2_PHY_931_DATA 0x00000000 -#define DDRSS2_PHY_932_DATA 0x00000000 -#define DDRSS2_PHY_933_DATA 0x00000000 -#define DDRSS2_PHY_934_DATA 0x00000000 -#define DDRSS2_PHY_935_DATA 0x00000000 -#define DDRSS2_PHY_936_DATA 0x00000000 -#define DDRSS2_PHY_937_DATA 0x00000000 -#define DDRSS2_PHY_938_DATA 0x00000000 -#define DDRSS2_PHY_939_DATA 0x00000000 -#define DDRSS2_PHY_940_DATA 0x00000000 -#define DDRSS2_PHY_941_DATA 0x00000000 -#define DDRSS2_PHY_942_DATA 0x00000000 -#define DDRSS2_PHY_943_DATA 0x00000000 -#define DDRSS2_PHY_944_DATA 0x00000000 -#define DDRSS2_PHY_945_DATA 0x00000000 -#define DDRSS2_PHY_946_DATA 0x00000000 -#define DDRSS2_PHY_947_DATA 0x00000000 -#define DDRSS2_PHY_948_DATA 0x00000000 -#define DDRSS2_PHY_949_DATA 0x00000000 -#define DDRSS2_PHY_950_DATA 0x00000000 -#define DDRSS2_PHY_951_DATA 0x00000000 -#define DDRSS2_PHY_952_DATA 0x00000000 -#define DDRSS2_PHY_953_DATA 0x00000000 -#define DDRSS2_PHY_954_DATA 0x00000000 -#define DDRSS2_PHY_955_DATA 0x00000000 -#define DDRSS2_PHY_956_DATA 0x00000000 -#define DDRSS2_PHY_957_DATA 0x00000000 -#define DDRSS2_PHY_958_DATA 0x00000000 -#define DDRSS2_PHY_959_DATA 0x00000000 -#define DDRSS2_PHY_960_DATA 0x00000000 -#define DDRSS2_PHY_961_DATA 0x00000000 -#define DDRSS2_PHY_962_DATA 0x00000000 -#define DDRSS2_PHY_963_DATA 0x00000000 -#define DDRSS2_PHY_964_DATA 0x00000000 -#define DDRSS2_PHY_965_DATA 0x00000000 -#define DDRSS2_PHY_966_DATA 0x00000000 -#define DDRSS2_PHY_967_DATA 0x00000000 -#define DDRSS2_PHY_968_DATA 0x00000000 -#define DDRSS2_PHY_969_DATA 0x00000000 -#define DDRSS2_PHY_970_DATA 0x00000000 -#define DDRSS2_PHY_971_DATA 0x00000000 -#define DDRSS2_PHY_972_DATA 0x00000000 -#define DDRSS2_PHY_973_DATA 0x00000000 -#define DDRSS2_PHY_974_DATA 0x00000000 -#define DDRSS2_PHY_975_DATA 0x00000000 -#define DDRSS2_PHY_976_DATA 0x00000000 -#define DDRSS2_PHY_977_DATA 0x00000000 -#define DDRSS2_PHY_978_DATA 0x00000000 -#define DDRSS2_PHY_979_DATA 0x00000000 -#define DDRSS2_PHY_980_DATA 0x00000000 -#define DDRSS2_PHY_981_DATA 0x00000000 -#define DDRSS2_PHY_982_DATA 0x00000000 -#define DDRSS2_PHY_983_DATA 0x00000000 -#define DDRSS2_PHY_984_DATA 0x00000000 -#define DDRSS2_PHY_985_DATA 0x00000000 -#define DDRSS2_PHY_986_DATA 0x00000000 -#define DDRSS2_PHY_987_DATA 0x00000000 -#define DDRSS2_PHY_988_DATA 0x00000000 -#define DDRSS2_PHY_989_DATA 0x00000000 -#define DDRSS2_PHY_990_DATA 0x00000000 -#define DDRSS2_PHY_991_DATA 0x00000000 -#define DDRSS2_PHY_992_DATA 0x00000000 -#define DDRSS2_PHY_993_DATA 0x00000000 -#define DDRSS2_PHY_994_DATA 0x00000000 -#define DDRSS2_PHY_995_DATA 0x00000000 -#define DDRSS2_PHY_996_DATA 0x00000000 -#define DDRSS2_PHY_997_DATA 0x00000000 -#define DDRSS2_PHY_998_DATA 0x00000000 -#define DDRSS2_PHY_999_DATA 0x00000000 -#define DDRSS2_PHY_1000_DATA 0x00000000 -#define DDRSS2_PHY_1001_DATA 0x00000000 -#define DDRSS2_PHY_1002_DATA 0x00000000 -#define DDRSS2_PHY_1003_DATA 0x00000000 -#define DDRSS2_PHY_1004_DATA 0x00000000 -#define DDRSS2_PHY_1005_DATA 0x00000000 -#define DDRSS2_PHY_1006_DATA 0x00000000 -#define DDRSS2_PHY_1007_DATA 0x00000000 -#define DDRSS2_PHY_1008_DATA 0x00000000 -#define DDRSS2_PHY_1009_DATA 0x00000000 -#define DDRSS2_PHY_1010_DATA 0x00000000 -#define DDRSS2_PHY_1011_DATA 0x00000000 -#define DDRSS2_PHY_1012_DATA 0x00000000 -#define DDRSS2_PHY_1013_DATA 0x00000000 -#define DDRSS2_PHY_1014_DATA 0x00000000 -#define DDRSS2_PHY_1015_DATA 0x00000000 -#define DDRSS2_PHY_1016_DATA 0x00000000 -#define DDRSS2_PHY_1017_DATA 0x00000000 -#define DDRSS2_PHY_1018_DATA 0x00000000 -#define DDRSS2_PHY_1019_DATA 0x00000000 -#define DDRSS2_PHY_1020_DATA 0x00000000 -#define DDRSS2_PHY_1021_DATA 0x00000000 -#define DDRSS2_PHY_1022_DATA 0x00000000 -#define DDRSS2_PHY_1023_DATA 0x00000000 -#define DDRSS2_PHY_1024_DATA 0x00000000 -#define DDRSS2_PHY_1025_DATA 0x00000000 -#define DDRSS2_PHY_1026_DATA 0x00000000 -#define DDRSS2_PHY_1027_DATA 0x00000000 -#define DDRSS2_PHY_1028_DATA 0x00000000 -#define DDRSS2_PHY_1029_DATA 0x00000100 -#define DDRSS2_PHY_1030_DATA 0x00000200 -#define DDRSS2_PHY_1031_DATA 0x00000000 -#define DDRSS2_PHY_1032_DATA 0x00000000 -#define DDRSS2_PHY_1033_DATA 0x00000000 -#define DDRSS2_PHY_1034_DATA 0x00000000 -#define DDRSS2_PHY_1035_DATA 0x00400000 -#define DDRSS2_PHY_1036_DATA 0x00000080 -#define DDRSS2_PHY_1037_DATA 0x00DCBA98 -#define DDRSS2_PHY_1038_DATA 0x03000000 -#define DDRSS2_PHY_1039_DATA 0x00200000 -#define DDRSS2_PHY_1040_DATA 0x00000000 -#define DDRSS2_PHY_1041_DATA 0x00000000 -#define DDRSS2_PHY_1042_DATA 0x00000000 -#define DDRSS2_PHY_1043_DATA 0x00000000 -#define DDRSS2_PHY_1044_DATA 0x00000000 -#define DDRSS2_PHY_1045_DATA 0x0000002A -#define DDRSS2_PHY_1046_DATA 0x00000015 -#define DDRSS2_PHY_1047_DATA 0x00000015 -#define DDRSS2_PHY_1048_DATA 0x0000002A -#define DDRSS2_PHY_1049_DATA 0x00000033 -#define DDRSS2_PHY_1050_DATA 0x0000000C -#define DDRSS2_PHY_1051_DATA 0x0000000C -#define DDRSS2_PHY_1052_DATA 0x00000033 -#define DDRSS2_PHY_1053_DATA 0x00543210 -#define DDRSS2_PHY_1054_DATA 0x003F0000 -#define DDRSS2_PHY_1055_DATA 0x000F013F -#define DDRSS2_PHY_1056_DATA 0x20202003 -#define DDRSS2_PHY_1057_DATA 0x00202020 -#define DDRSS2_PHY_1058_DATA 0x20008008 -#define DDRSS2_PHY_1059_DATA 0x00000810 -#define DDRSS2_PHY_1060_DATA 0x00000F00 -#define DDRSS2_PHY_1061_DATA 0x00000000 -#define DDRSS2_PHY_1062_DATA 0x00000000 -#define DDRSS2_PHY_1063_DATA 0x00000000 -#define DDRSS2_PHY_1064_DATA 0x000305CC -#define DDRSS2_PHY_1065_DATA 0x00030000 -#define DDRSS2_PHY_1066_DATA 0x00000300 -#define DDRSS2_PHY_1067_DATA 0x00000300 -#define DDRSS2_PHY_1068_DATA 0x00000300 -#define DDRSS2_PHY_1069_DATA 0x00000300 -#define DDRSS2_PHY_1070_DATA 0x00000300 -#define DDRSS2_PHY_1071_DATA 0x42080010 -#define DDRSS2_PHY_1072_DATA 0x0000803E -#define DDRSS2_PHY_1073_DATA 0x00000001 -#define DDRSS2_PHY_1074_DATA 0x01000102 -#define DDRSS2_PHY_1075_DATA 0x00008000 -#define DDRSS2_PHY_1076_DATA 0x00000000 -#define DDRSS2_PHY_1077_DATA 0x00000000 -#define DDRSS2_PHY_1078_DATA 0x00000000 -#define DDRSS2_PHY_1079_DATA 0x00000000 -#define DDRSS2_PHY_1080_DATA 0x00000000 -#define DDRSS2_PHY_1081_DATA 0x00000000 -#define DDRSS2_PHY_1082_DATA 0x00000000 -#define DDRSS2_PHY_1083_DATA 0x00000000 -#define DDRSS2_PHY_1084_DATA 0x00000000 -#define DDRSS2_PHY_1085_DATA 0x00000000 -#define DDRSS2_PHY_1086_DATA 0x00000000 -#define DDRSS2_PHY_1087_DATA 0x00000000 -#define DDRSS2_PHY_1088_DATA 0x00000000 -#define DDRSS2_PHY_1089_DATA 0x00000000 -#define DDRSS2_PHY_1090_DATA 0x00000000 -#define DDRSS2_PHY_1091_DATA 0x00000000 -#define DDRSS2_PHY_1092_DATA 0x00000000 -#define DDRSS2_PHY_1093_DATA 0x00000000 -#define DDRSS2_PHY_1094_DATA 0x00000000 -#define DDRSS2_PHY_1095_DATA 0x00000000 -#define DDRSS2_PHY_1096_DATA 0x00000000 -#define DDRSS2_PHY_1097_DATA 0x00000000 -#define DDRSS2_PHY_1098_DATA 0x00000000 -#define DDRSS2_PHY_1099_DATA 0x00000000 -#define DDRSS2_PHY_1100_DATA 0x00000000 -#define DDRSS2_PHY_1101_DATA 0x00000000 -#define DDRSS2_PHY_1102_DATA 0x00000000 -#define DDRSS2_PHY_1103_DATA 0x00000000 -#define DDRSS2_PHY_1104_DATA 0x00000000 -#define DDRSS2_PHY_1105_DATA 0x00000000 -#define DDRSS2_PHY_1106_DATA 0x00000000 -#define DDRSS2_PHY_1107_DATA 0x00000000 -#define DDRSS2_PHY_1108_DATA 0x00000000 -#define DDRSS2_PHY_1109_DATA 0x00000000 -#define DDRSS2_PHY_1110_DATA 0x00000000 -#define DDRSS2_PHY_1111_DATA 0x00000000 -#define DDRSS2_PHY_1112_DATA 0x00000000 -#define DDRSS2_PHY_1113_DATA 0x00000000 -#define DDRSS2_PHY_1114_DATA 0x00000000 -#define DDRSS2_PHY_1115_DATA 0x00000000 -#define DDRSS2_PHY_1116_DATA 0x00000000 -#define DDRSS2_PHY_1117_DATA 0x00000000 -#define DDRSS2_PHY_1118_DATA 0x00000000 -#define DDRSS2_PHY_1119_DATA 0x00000000 -#define DDRSS2_PHY_1120_DATA 0x00000000 -#define DDRSS2_PHY_1121_DATA 0x00000000 -#define DDRSS2_PHY_1122_DATA 0x00000000 -#define DDRSS2_PHY_1123_DATA 0x00000000 -#define DDRSS2_PHY_1124_DATA 0x00000000 -#define DDRSS2_PHY_1125_DATA 0x00000000 -#define DDRSS2_PHY_1126_DATA 0x00000000 -#define DDRSS2_PHY_1127_DATA 0x00000000 -#define DDRSS2_PHY_1128_DATA 0x00000000 -#define DDRSS2_PHY_1129_DATA 0x00000000 -#define DDRSS2_PHY_1130_DATA 0x00000000 -#define DDRSS2_PHY_1131_DATA 0x00000000 -#define DDRSS2_PHY_1132_DATA 0x00000000 -#define DDRSS2_PHY_1133_DATA 0x00000000 -#define DDRSS2_PHY_1134_DATA 0x00000000 -#define DDRSS2_PHY_1135_DATA 0x00000000 -#define DDRSS2_PHY_1136_DATA 0x00000000 -#define DDRSS2_PHY_1137_DATA 0x00000000 -#define DDRSS2_PHY_1138_DATA 0x00000000 -#define DDRSS2_PHY_1139_DATA 0x00000000 -#define DDRSS2_PHY_1140_DATA 0x00000000 -#define DDRSS2_PHY_1141_DATA 0x00000000 -#define DDRSS2_PHY_1142_DATA 0x00000000 -#define DDRSS2_PHY_1143_DATA 0x00000000 -#define DDRSS2_PHY_1144_DATA 0x00000000 -#define DDRSS2_PHY_1145_DATA 0x00000000 -#define DDRSS2_PHY_1146_DATA 0x00000000 -#define DDRSS2_PHY_1147_DATA 0x00000000 -#define DDRSS2_PHY_1148_DATA 0x00000000 -#define DDRSS2_PHY_1149_DATA 0x00000000 -#define DDRSS2_PHY_1150_DATA 0x00000000 -#define DDRSS2_PHY_1151_DATA 0x00000000 -#define DDRSS2_PHY_1152_DATA 0x00000000 -#define DDRSS2_PHY_1153_DATA 0x00000000 -#define DDRSS2_PHY_1154_DATA 0x00000000 -#define DDRSS2_PHY_1155_DATA 0x00000000 -#define DDRSS2_PHY_1156_DATA 0x00000000 -#define DDRSS2_PHY_1157_DATA 0x00000000 -#define DDRSS2_PHY_1158_DATA 0x00000000 -#define DDRSS2_PHY_1159_DATA 0x00000000 -#define DDRSS2_PHY_1160_DATA 0x00000000 -#define DDRSS2_PHY_1161_DATA 0x00000000 -#define DDRSS2_PHY_1162_DATA 0x00000000 -#define DDRSS2_PHY_1163_DATA 0x00000000 -#define DDRSS2_PHY_1164_DATA 0x00000000 -#define DDRSS2_PHY_1165_DATA 0x00000000 -#define DDRSS2_PHY_1166_DATA 0x00000000 -#define DDRSS2_PHY_1167_DATA 0x00000000 -#define DDRSS2_PHY_1168_DATA 0x00000000 -#define DDRSS2_PHY_1169_DATA 0x00000000 -#define DDRSS2_PHY_1170_DATA 0x00000000 -#define DDRSS2_PHY_1171_DATA 0x00000000 -#define DDRSS2_PHY_1172_DATA 0x00000000 -#define DDRSS2_PHY_1173_DATA 0x00000000 -#define DDRSS2_PHY_1174_DATA 0x00000000 -#define DDRSS2_PHY_1175_DATA 0x00000000 -#define DDRSS2_PHY_1176_DATA 0x00000000 -#define DDRSS2_PHY_1177_DATA 0x00000000 -#define DDRSS2_PHY_1178_DATA 0x00000000 -#define DDRSS2_PHY_1179_DATA 0x00000000 -#define DDRSS2_PHY_1180_DATA 0x00000000 -#define DDRSS2_PHY_1181_DATA 0x00000000 -#define DDRSS2_PHY_1182_DATA 0x00000000 -#define DDRSS2_PHY_1183_DATA 0x00000000 -#define DDRSS2_PHY_1184_DATA 0x00000000 -#define DDRSS2_PHY_1185_DATA 0x00000000 -#define DDRSS2_PHY_1186_DATA 0x00000000 -#define DDRSS2_PHY_1187_DATA 0x00000000 -#define DDRSS2_PHY_1188_DATA 0x00000000 -#define DDRSS2_PHY_1189_DATA 0x00000000 -#define DDRSS2_PHY_1190_DATA 0x00000000 -#define DDRSS2_PHY_1191_DATA 0x00000000 -#define DDRSS2_PHY_1192_DATA 0x00000000 -#define DDRSS2_PHY_1193_DATA 0x00000000 -#define DDRSS2_PHY_1194_DATA 0x00000000 -#define DDRSS2_PHY_1195_DATA 0x00000000 -#define DDRSS2_PHY_1196_DATA 0x00000000 -#define DDRSS2_PHY_1197_DATA 0x00000000 -#define DDRSS2_PHY_1198_DATA 0x00000000 -#define DDRSS2_PHY_1199_DATA 0x00000000 -#define DDRSS2_PHY_1200_DATA 0x00000000 -#define DDRSS2_PHY_1201_DATA 0x00000000 -#define DDRSS2_PHY_1202_DATA 0x00000000 -#define DDRSS2_PHY_1203_DATA 0x00000000 -#define DDRSS2_PHY_1204_DATA 0x00000000 -#define DDRSS2_PHY_1205_DATA 0x00000000 -#define DDRSS2_PHY_1206_DATA 0x00000000 -#define DDRSS2_PHY_1207_DATA 0x00000000 -#define DDRSS2_PHY_1208_DATA 0x00000000 -#define DDRSS2_PHY_1209_DATA 0x00000000 -#define DDRSS2_PHY_1210_DATA 0x00000000 -#define DDRSS2_PHY_1211_DATA 0x00000000 -#define DDRSS2_PHY_1212_DATA 0x00000000 -#define DDRSS2_PHY_1213_DATA 0x00000000 -#define DDRSS2_PHY_1214_DATA 0x00000000 -#define DDRSS2_PHY_1215_DATA 0x00000000 -#define DDRSS2_PHY_1216_DATA 0x00000000 -#define DDRSS2_PHY_1217_DATA 0x00000000 -#define DDRSS2_PHY_1218_DATA 0x00000000 -#define DDRSS2_PHY_1219_DATA 0x00000000 -#define DDRSS2_PHY_1220_DATA 0x00000000 -#define DDRSS2_PHY_1221_DATA 0x00000000 -#define DDRSS2_PHY_1222_DATA 0x00000000 -#define DDRSS2_PHY_1223_DATA 0x00000000 -#define DDRSS2_PHY_1224_DATA 0x00000000 -#define DDRSS2_PHY_1225_DATA 0x00000000 -#define DDRSS2_PHY_1226_DATA 0x00000000 -#define DDRSS2_PHY_1227_DATA 0x00000000 -#define DDRSS2_PHY_1228_DATA 0x00000000 -#define DDRSS2_PHY_1229_DATA 0x00000000 -#define DDRSS2_PHY_1230_DATA 0x00000000 -#define DDRSS2_PHY_1231_DATA 0x00000000 -#define DDRSS2_PHY_1232_DATA 0x00000000 -#define DDRSS2_PHY_1233_DATA 0x00000000 -#define DDRSS2_PHY_1234_DATA 0x00000000 -#define DDRSS2_PHY_1235_DATA 0x00000000 -#define DDRSS2_PHY_1236_DATA 0x00000000 -#define DDRSS2_PHY_1237_DATA 0x00000000 -#define DDRSS2_PHY_1238_DATA 0x00000000 -#define DDRSS2_PHY_1239_DATA 0x00000000 -#define DDRSS2_PHY_1240_DATA 0x00000000 -#define DDRSS2_PHY_1241_DATA 0x00000000 -#define DDRSS2_PHY_1242_DATA 0x00000000 -#define DDRSS2_PHY_1243_DATA 0x00000000 -#define DDRSS2_PHY_1244_DATA 0x00000000 -#define DDRSS2_PHY_1245_DATA 0x00000000 -#define DDRSS2_PHY_1246_DATA 0x00000000 -#define DDRSS2_PHY_1247_DATA 0x00000000 -#define DDRSS2_PHY_1248_DATA 0x00000000 -#define DDRSS2_PHY_1249_DATA 0x00000000 -#define DDRSS2_PHY_1250_DATA 0x00000000 -#define DDRSS2_PHY_1251_DATA 0x00000000 -#define DDRSS2_PHY_1252_DATA 0x00000000 -#define DDRSS2_PHY_1253_DATA 0x00000000 -#define DDRSS2_PHY_1254_DATA 0x00000000 -#define DDRSS2_PHY_1255_DATA 0x00000000 -#define DDRSS2_PHY_1256_DATA 0x00000000 -#define DDRSS2_PHY_1257_DATA 0x00000000 -#define DDRSS2_PHY_1258_DATA 0x00000000 -#define DDRSS2_PHY_1259_DATA 0x00000000 -#define DDRSS2_PHY_1260_DATA 0x00000000 -#define DDRSS2_PHY_1261_DATA 0x00000000 -#define DDRSS2_PHY_1262_DATA 0x00000000 -#define DDRSS2_PHY_1263_DATA 0x00000000 -#define DDRSS2_PHY_1264_DATA 0x00000000 -#define DDRSS2_PHY_1265_DATA 0x00000000 -#define DDRSS2_PHY_1266_DATA 0x00000000 -#define DDRSS2_PHY_1267_DATA 0x00000000 -#define DDRSS2_PHY_1268_DATA 0x00000000 -#define DDRSS2_PHY_1269_DATA 0x00000000 -#define DDRSS2_PHY_1270_DATA 0x00000000 -#define DDRSS2_PHY_1271_DATA 0x00000000 -#define DDRSS2_PHY_1272_DATA 0x00000000 -#define DDRSS2_PHY_1273_DATA 0x00000000 -#define DDRSS2_PHY_1274_DATA 0x00000000 -#define DDRSS2_PHY_1275_DATA 0x00000000 -#define DDRSS2_PHY_1276_DATA 0x00000000 -#define DDRSS2_PHY_1277_DATA 0x00000000 -#define DDRSS2_PHY_1278_DATA 0x00000000 -#define DDRSS2_PHY_1279_DATA 0x00000000 -#define DDRSS2_PHY_1280_DATA 0x00000000 -#define DDRSS2_PHY_1281_DATA 0x00010100 -#define DDRSS2_PHY_1282_DATA 0x00000000 -#define DDRSS2_PHY_1283_DATA 0x00000000 -#define DDRSS2_PHY_1284_DATA 0x00050000 -#define DDRSS2_PHY_1285_DATA 0x04000000 -#define DDRSS2_PHY_1286_DATA 0x00000055 -#define DDRSS2_PHY_1287_DATA 0x00000000 -#define DDRSS2_PHY_1288_DATA 0x00000000 -#define DDRSS2_PHY_1289_DATA 0x00000000 -#define DDRSS2_PHY_1290_DATA 0x00000000 -#define DDRSS2_PHY_1291_DATA 0x00002001 -#define DDRSS2_PHY_1292_DATA 0x0000400F -#define DDRSS2_PHY_1293_DATA 0x50020028 -#define DDRSS2_PHY_1294_DATA 0x01010000 -#define DDRSS2_PHY_1295_DATA 0x80080001 -#define DDRSS2_PHY_1296_DATA 0x10200000 -#define DDRSS2_PHY_1297_DATA 0x00000008 -#define DDRSS2_PHY_1298_DATA 0x00000000 -#define DDRSS2_PHY_1299_DATA 0x01090E00 -#define DDRSS2_PHY_1300_DATA 0x00040101 -#define DDRSS2_PHY_1301_DATA 0x0000010F -#define DDRSS2_PHY_1302_DATA 0x00000000 -#define DDRSS2_PHY_1303_DATA 0x0000FFFF -#define DDRSS2_PHY_1304_DATA 0x00000000 -#define DDRSS2_PHY_1305_DATA 0x01010000 -#define DDRSS2_PHY_1306_DATA 0x01080402 -#define DDRSS2_PHY_1307_DATA 0x01200F02 -#define DDRSS2_PHY_1308_DATA 0x00194280 -#define DDRSS2_PHY_1309_DATA 0x00000004 -#define DDRSS2_PHY_1310_DATA 0x00042000 -#define DDRSS2_PHY_1311_DATA 0x00000000 -#define DDRSS2_PHY_1312_DATA 0x00000000 -#define DDRSS2_PHY_1313_DATA 0x00000000 -#define DDRSS2_PHY_1314_DATA 0x00000000 -#define DDRSS2_PHY_1315_DATA 0x00000000 -#define DDRSS2_PHY_1316_DATA 0x00000000 -#define DDRSS2_PHY_1317_DATA 0x01000000 -#define DDRSS2_PHY_1318_DATA 0x00000705 -#define DDRSS2_PHY_1319_DATA 0x00000054 -#define DDRSS2_PHY_1320_DATA 0x00030820 -#define DDRSS2_PHY_1321_DATA 0x00010820 -#define DDRSS2_PHY_1322_DATA 0x00010820 -#define DDRSS2_PHY_1323_DATA 0x00010820 -#define DDRSS2_PHY_1324_DATA 0x00010820 -#define DDRSS2_PHY_1325_DATA 0x00010820 -#define DDRSS2_PHY_1326_DATA 0x00010820 -#define DDRSS2_PHY_1327_DATA 0x00010820 -#define DDRSS2_PHY_1328_DATA 0x00010820 -#define DDRSS2_PHY_1329_DATA 0x00000000 -#define DDRSS2_PHY_1330_DATA 0x00000074 -#define DDRSS2_PHY_1331_DATA 0x00000400 -#define DDRSS2_PHY_1332_DATA 0x00000108 -#define DDRSS2_PHY_1333_DATA 0x00000000 -#define DDRSS2_PHY_1334_DATA 0x00000000 -#define DDRSS2_PHY_1335_DATA 0x00000000 -#define DDRSS2_PHY_1336_DATA 0x00000000 -#define DDRSS2_PHY_1337_DATA 0x00000000 -#define DDRSS2_PHY_1338_DATA 0x03000000 -#define DDRSS2_PHY_1339_DATA 0x00000000 -#define DDRSS2_PHY_1340_DATA 0x00000000 -#define DDRSS2_PHY_1341_DATA 0x00000000 -#define DDRSS2_PHY_1342_DATA 0x04102006 -#define DDRSS2_PHY_1343_DATA 0x00041020 -#define DDRSS2_PHY_1344_DATA 0x01C98C98 -#define DDRSS2_PHY_1345_DATA 0x3F400000 -#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F -#define DDRSS2_PHY_1347_DATA 0x0000001F -#define DDRSS2_PHY_1348_DATA 0x00000000 -#define DDRSS2_PHY_1349_DATA 0x00000000 -#define DDRSS2_PHY_1350_DATA 0x00000000 -#define DDRSS2_PHY_1351_DATA 0x00010000 -#define DDRSS2_PHY_1352_DATA 0x00000000 -#define DDRSS2_PHY_1353_DATA 0x00000000 -#define DDRSS2_PHY_1354_DATA 0x00000000 -#define DDRSS2_PHY_1355_DATA 0x00000000 -#define DDRSS2_PHY_1356_DATA 0x76543210 -#define DDRSS2_PHY_1357_DATA 0x00010198 -#define DDRSS2_PHY_1358_DATA 0x00000000 -#define DDRSS2_PHY_1359_DATA 0x00000000 -#define DDRSS2_PHY_1360_DATA 0x00000000 -#define DDRSS2_PHY_1361_DATA 0x00040700 -#define DDRSS2_PHY_1362_DATA 0x00000000 -#define DDRSS2_PHY_1363_DATA 0x00000000 -#define DDRSS2_PHY_1364_DATA 0x00000000 -#define DDRSS2_PHY_1365_DATA 0x00000000 -#define DDRSS2_PHY_1366_DATA 0x00000000 -#define DDRSS2_PHY_1367_DATA 0x00000002 -#define DDRSS2_PHY_1368_DATA 0x00000000 -#define DDRSS2_PHY_1369_DATA 0x00000000 -#define DDRSS2_PHY_1370_DATA 0x00000000 -#define DDRSS2_PHY_1371_DATA 0x00000000 -#define DDRSS2_PHY_1372_DATA 0x00000000 -#define DDRSS2_PHY_1373_DATA 0x00000000 -#define DDRSS2_PHY_1374_DATA 0x00080000 -#define DDRSS2_PHY_1375_DATA 0x000007FF -#define DDRSS2_PHY_1376_DATA 0x00000000 -#define DDRSS2_PHY_1377_DATA 0x00000000 -#define DDRSS2_PHY_1378_DATA 0x00000000 -#define DDRSS2_PHY_1379_DATA 0x00000000 -#define DDRSS2_PHY_1380_DATA 0x00000000 -#define DDRSS2_PHY_1381_DATA 0x00000000 -#define DDRSS2_PHY_1382_DATA 0x000FFFFF -#define DDRSS2_PHY_1383_DATA 0x000FFFFF -#define DDRSS2_PHY_1384_DATA 0x0000FFFF -#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0 -#define DDRSS2_PHY_1386_DATA 0x030FFFFF -#define DDRSS2_PHY_1387_DATA 0x01FFFFFF -#define DDRSS2_PHY_1388_DATA 0x0000FFFF -#define DDRSS2_PHY_1389_DATA 0x00000000 -#define DDRSS2_PHY_1390_DATA 0x00000000 -#define DDRSS2_PHY_1391_DATA 0x00000000 -#define DDRSS2_PHY_1392_DATA 0x00000000 -#define DDRSS2_PHY_1393_DATA 0x0001F7C0 -#define DDRSS2_PHY_1394_DATA 0x00000003 -#define DDRSS2_PHY_1395_DATA 0x00000000 -#define DDRSS2_PHY_1396_DATA 0x00001142 -#define DDRSS2_PHY_1397_DATA 0x010207AB -#define DDRSS2_PHY_1398_DATA 0x01000080 -#define DDRSS2_PHY_1399_DATA 0x03900390 -#define DDRSS2_PHY_1400_DATA 0x03900390 -#define DDRSS2_PHY_1401_DATA 0x00000390 -#define DDRSS2_PHY_1402_DATA 0x00000390 -#define DDRSS2_PHY_1403_DATA 0x00000390 -#define DDRSS2_PHY_1404_DATA 0x00000390 -#define DDRSS2_PHY_1405_DATA 0x00000005 -#define DDRSS2_PHY_1406_DATA 0x01813FCC -#define DDRSS2_PHY_1407_DATA 0x000000CC -#define DDRSS2_PHY_1408_DATA 0x0C000DFF -#define DDRSS2_PHY_1409_DATA 0x30000DFF -#define DDRSS2_PHY_1410_DATA 0x3F0DFF11 -#define DDRSS2_PHY_1411_DATA 0x000100F0 -#define DDRSS2_PHY_1412_DATA 0x780DFFCC -#define DDRSS2_PHY_1413_DATA 0x00007E31 -#define DDRSS2_PHY_1414_DATA 0x000CBF11 -#define DDRSS2_PHY_1415_DATA 0x01990010 -#define DDRSS2_PHY_1416_DATA 0x000CBF11 -#define DDRSS2_PHY_1417_DATA 0x01990010 -#define DDRSS2_PHY_1418_DATA 0x3F0DFF11 -#define DDRSS2_PHY_1419_DATA 0x00EF00F0 -#define DDRSS2_PHY_1420_DATA 0x3F0DFF11 -#define DDRSS2_PHY_1421_DATA 0x01FF00F0 -#define DDRSS2_PHY_1422_DATA 0x20040006 - -#define DDRSS3_CTL_00_DATA 0x00000B00 -#define DDRSS3_CTL_01_DATA 0x00000000 -#define DDRSS3_CTL_02_DATA 0x00000000 -#define DDRSS3_CTL_03_DATA 0x00000000 -#define DDRSS3_CTL_04_DATA 0x00000000 -#define DDRSS3_CTL_05_DATA 0x00000000 -#define DDRSS3_CTL_06_DATA 0x00000000 -#define DDRSS3_CTL_07_DATA 0x00002AF8 -#define DDRSS3_CTL_08_DATA 0x0001ADAF -#define DDRSS3_CTL_09_DATA 0x00000005 -#define DDRSS3_CTL_10_DATA 0x0000006E -#define DDRSS3_CTL_11_DATA 0x000681C8 -#define DDRSS3_CTL_12_DATA 0x004111C9 -#define DDRSS3_CTL_13_DATA 0x00000005 -#define DDRSS3_CTL_14_DATA 0x000010A9 -#define DDRSS3_CTL_15_DATA 0x000681C8 -#define DDRSS3_CTL_16_DATA 0x004111C9 -#define DDRSS3_CTL_17_DATA 0x00000005 -#define DDRSS3_CTL_18_DATA 0x000010A9 -#define DDRSS3_CTL_19_DATA 0x01010000 -#define DDRSS3_CTL_20_DATA 0x02011001 -#define DDRSS3_CTL_21_DATA 0x02010000 -#define DDRSS3_CTL_22_DATA 0x00020100 -#define DDRSS3_CTL_23_DATA 0x0000000B -#define DDRSS3_CTL_24_DATA 0x0000001C -#define DDRSS3_CTL_25_DATA 0x00000000 -#define DDRSS3_CTL_26_DATA 0x00000000 -#define DDRSS3_CTL_27_DATA 0x03020200 -#define DDRSS3_CTL_28_DATA 0x00005656 -#define DDRSS3_CTL_29_DATA 0x00100000 -#define DDRSS3_CTL_30_DATA 0x00000000 -#define DDRSS3_CTL_31_DATA 0x00000000 -#define DDRSS3_CTL_32_DATA 0x00000000 -#define DDRSS3_CTL_33_DATA 0x00000000 -#define DDRSS3_CTL_34_DATA 0x040C0000 -#define DDRSS3_CTL_35_DATA 0x12481248 -#define DDRSS3_CTL_36_DATA 0x00050804 -#define DDRSS3_CTL_37_DATA 0x09040008 -#define DDRSS3_CTL_38_DATA 0x15000204 -#define DDRSS3_CTL_39_DATA 0x1760008B -#define DDRSS3_CTL_40_DATA 0x1500422B -#define DDRSS3_CTL_41_DATA 0x1760008B -#define DDRSS3_CTL_42_DATA 0x2000422B -#define DDRSS3_CTL_43_DATA 0x000A0A09 -#define DDRSS3_CTL_44_DATA 0x0400078A -#define DDRSS3_CTL_45_DATA 0x1E161104 -#define DDRSS3_CTL_46_DATA 0x10012458 -#define DDRSS3_CTL_47_DATA 0x1E161110 -#define DDRSS3_CTL_48_DATA 0x10012458 -#define DDRSS3_CTL_49_DATA 0x02030410 -#define DDRSS3_CTL_50_DATA 0x2C040500 -#define DDRSS3_CTL_51_DATA 0x08292C29 -#define DDRSS3_CTL_52_DATA 0x14000E0A -#define DDRSS3_CTL_53_DATA 0x04010A0A -#define DDRSS3_CTL_54_DATA 0x01010004 -#define DDRSS3_CTL_55_DATA 0x04545408 -#define DDRSS3_CTL_56_DATA 0x04313104 -#define DDRSS3_CTL_57_DATA 0x00003131 -#define DDRSS3_CTL_58_DATA 0x00010100 -#define DDRSS3_CTL_59_DATA 0x03010000 -#define DDRSS3_CTL_60_DATA 0x00001508 -#define DDRSS3_CTL_61_DATA 0x000000CE -#define DDRSS3_CTL_62_DATA 0x0000032B -#define DDRSS3_CTL_63_DATA 0x00002073 -#define DDRSS3_CTL_64_DATA 0x0000032B -#define DDRSS3_CTL_65_DATA 0x00002073 -#define DDRSS3_CTL_66_DATA 0x00000005 -#define DDRSS3_CTL_67_DATA 0x00050000 -#define DDRSS3_CTL_68_DATA 0x00CB0012 -#define DDRSS3_CTL_69_DATA 0x00CB0408 -#define DDRSS3_CTL_70_DATA 0x00400408 -#define DDRSS3_CTL_71_DATA 0x00120103 -#define DDRSS3_CTL_72_DATA 0x00100005 -#define DDRSS3_CTL_73_DATA 0x2F080010 -#define DDRSS3_CTL_74_DATA 0x0505012F -#define DDRSS3_CTL_75_DATA 0x0401030A -#define DDRSS3_CTL_76_DATA 0x041E100B -#define DDRSS3_CTL_77_DATA 0x100B0401 -#define DDRSS3_CTL_78_DATA 0x0001041E -#define DDRSS3_CTL_79_DATA 0x00160016 -#define DDRSS3_CTL_80_DATA 0x033B033B -#define DDRSS3_CTL_81_DATA 0x033B033B -#define DDRSS3_CTL_82_DATA 0x03050505 -#define DDRSS3_CTL_83_DATA 0x03010303 -#define DDRSS3_CTL_84_DATA 0x200B100B -#define DDRSS3_CTL_85_DATA 0x04041004 -#define DDRSS3_CTL_86_DATA 0x200B100B -#define DDRSS3_CTL_87_DATA 0x04041004 -#define DDRSS3_CTL_88_DATA 0x03010000 -#define DDRSS3_CTL_89_DATA 0x00010000 -#define DDRSS3_CTL_90_DATA 0x00000000 -#define DDRSS3_CTL_91_DATA 0x00000000 -#define DDRSS3_CTL_92_DATA 0x01000000 -#define DDRSS3_CTL_93_DATA 0x80104002 -#define DDRSS3_CTL_94_DATA 0x00000000 -#define DDRSS3_CTL_95_DATA 0x00040005 -#define DDRSS3_CTL_96_DATA 0x00000000 -#define DDRSS3_CTL_97_DATA 0x00050000 -#define DDRSS3_CTL_98_DATA 0x00000004 -#define DDRSS3_CTL_99_DATA 0x00000000 -#define DDRSS3_CTL_100_DATA 0x00040005 -#define DDRSS3_CTL_101_DATA 0x00000000 -#define DDRSS3_CTL_102_DATA 0x00003380 -#define DDRSS3_CTL_103_DATA 0x00003380 -#define DDRSS3_CTL_104_DATA 0x00003380 -#define DDRSS3_CTL_105_DATA 0x00003380 -#define DDRSS3_CTL_106_DATA 0x00003380 -#define DDRSS3_CTL_107_DATA 0x00000000 -#define DDRSS3_CTL_108_DATA 0x000005A2 -#define DDRSS3_CTL_109_DATA 0x00081CC0 -#define DDRSS3_CTL_110_DATA 0x00081CC0 -#define DDRSS3_CTL_111_DATA 0x00081CC0 -#define DDRSS3_CTL_112_DATA 0x00081CC0 -#define DDRSS3_CTL_113_DATA 0x00081CC0 -#define DDRSS3_CTL_114_DATA 0x00000000 -#define DDRSS3_CTL_115_DATA 0x0000E325 -#define DDRSS3_CTL_116_DATA 0x00081CC0 -#define DDRSS3_CTL_117_DATA 0x00081CC0 -#define DDRSS3_CTL_118_DATA 0x00081CC0 -#define DDRSS3_CTL_119_DATA 0x00081CC0 -#define DDRSS3_CTL_120_DATA 0x00081CC0 -#define DDRSS3_CTL_121_DATA 0x00000000 -#define DDRSS3_CTL_122_DATA 0x0000E325 -#define DDRSS3_CTL_123_DATA 0x00000000 -#define DDRSS3_CTL_124_DATA 0x00000000 -#define DDRSS3_CTL_125_DATA 0x00000000 -#define DDRSS3_CTL_126_DATA 0x00000000 -#define DDRSS3_CTL_127_DATA 0x00000000 -#define DDRSS3_CTL_128_DATA 0x00000000 -#define DDRSS3_CTL_129_DATA 0x00000000 -#define DDRSS3_CTL_130_DATA 0x00000000 -#define DDRSS3_CTL_131_DATA 0x0B030500 -#define DDRSS3_CTL_132_DATA 0x00040B04 -#define DDRSS3_CTL_133_DATA 0x0A090000 -#define DDRSS3_CTL_134_DATA 0x0A090701 -#define DDRSS3_CTL_135_DATA 0x0900000E -#define DDRSS3_CTL_136_DATA 0x0907010A -#define DDRSS3_CTL_137_DATA 0x00000E0A -#define DDRSS3_CTL_138_DATA 0x07010A09 -#define DDRSS3_CTL_139_DATA 0x000E0A09 -#define DDRSS3_CTL_140_DATA 0x07000401 -#define DDRSS3_CTL_141_DATA 0x00000000 -#define DDRSS3_CTL_142_DATA 0x00000000 -#define DDRSS3_CTL_143_DATA 0x00000000 -#define DDRSS3_CTL_144_DATA 0x00000000 -#define DDRSS3_CTL_145_DATA 0x00000000 -#define DDRSS3_CTL_146_DATA 0x00000000 -#define DDRSS3_CTL_147_DATA 0x00000000 -#define DDRSS3_CTL_148_DATA 0x08080000 -#define DDRSS3_CTL_149_DATA 0x01000000 -#define DDRSS3_CTL_150_DATA 0x800000C0 -#define DDRSS3_CTL_151_DATA 0x800000C0 -#define DDRSS3_CTL_152_DATA 0x800000C0 -#define DDRSS3_CTL_153_DATA 0x00000000 -#define DDRSS3_CTL_154_DATA 0x00001500 -#define DDRSS3_CTL_155_DATA 0x00000000 -#define DDRSS3_CTL_156_DATA 0x00000001 -#define DDRSS3_CTL_157_DATA 0x00000002 -#define DDRSS3_CTL_158_DATA 0x0000100E -#define DDRSS3_CTL_159_DATA 0x00000000 -#define DDRSS3_CTL_160_DATA 0x00000000 -#define DDRSS3_CTL_161_DATA 0x00000000 -#define DDRSS3_CTL_162_DATA 0x00000000 -#define DDRSS3_CTL_163_DATA 0x00000000 -#define DDRSS3_CTL_164_DATA 0x000B0000 -#define DDRSS3_CTL_165_DATA 0x000E0006 -#define DDRSS3_CTL_166_DATA 0x000E0404 -#define DDRSS3_CTL_167_DATA 0x00D601AB -#define DDRSS3_CTL_168_DATA 0x10100216 -#define DDRSS3_CTL_169_DATA 0x01AB0216 -#define DDRSS3_CTL_170_DATA 0x021600D6 -#define DDRSS3_CTL_171_DATA 0x02161010 -#define DDRSS3_CTL_172_DATA 0x00000000 -#define DDRSS3_CTL_173_DATA 0x00000000 -#define DDRSS3_CTL_174_DATA 0x00000000 -#define DDRSS3_CTL_175_DATA 0x3FF40084 -#define DDRSS3_CTL_176_DATA 0x33003FF4 -#define DDRSS3_CTL_177_DATA 0x00003333 -#define DDRSS3_CTL_178_DATA 0x35000000 -#define DDRSS3_CTL_179_DATA 0x27270035 -#define DDRSS3_CTL_180_DATA 0x0F0F0000 -#define DDRSS3_CTL_181_DATA 0x16000000 -#define DDRSS3_CTL_182_DATA 0x00841616 -#define DDRSS3_CTL_183_DATA 0x3FF43FF4 -#define DDRSS3_CTL_184_DATA 0x33333300 -#define DDRSS3_CTL_185_DATA 0x00000000 -#define DDRSS3_CTL_186_DATA 0x00353500 -#define DDRSS3_CTL_187_DATA 0x00002727 -#define DDRSS3_CTL_188_DATA 0x00000F0F -#define DDRSS3_CTL_189_DATA 0x16161600 -#define DDRSS3_CTL_190_DATA 0x00000020 -#define DDRSS3_CTL_191_DATA 0x00000000 -#define DDRSS3_CTL_192_DATA 0x00000001 -#define DDRSS3_CTL_193_DATA 0x00000000 -#define DDRSS3_CTL_194_DATA 0x01000000 -#define DDRSS3_CTL_195_DATA 0x00000001 -#define DDRSS3_CTL_196_DATA 0x00000000 -#define DDRSS3_CTL_197_DATA 0x00000000 -#define DDRSS3_CTL_198_DATA 0x00000000 -#define DDRSS3_CTL_199_DATA 0x00000000 -#define DDRSS3_CTL_200_DATA 0x00000000 -#define DDRSS3_CTL_201_DATA 0x00000000 -#define DDRSS3_CTL_202_DATA 0x00000000 -#define DDRSS3_CTL_203_DATA 0x00000000 -#define DDRSS3_CTL_204_DATA 0x00000000 -#define DDRSS3_CTL_205_DATA 0x00000000 -#define DDRSS3_CTL_206_DATA 0x02000000 -#define DDRSS3_CTL_207_DATA 0x01080101 -#define DDRSS3_CTL_208_DATA 0x00000000 -#define DDRSS3_CTL_209_DATA 0x00000000 -#define DDRSS3_CTL_210_DATA 0x00000000 -#define DDRSS3_CTL_211_DATA 0x00000000 -#define DDRSS3_CTL_212_DATA 0x00000000 -#define DDRSS3_CTL_213_DATA 0x00000000 -#define DDRSS3_CTL_214_DATA 0x00000000 -#define DDRSS3_CTL_215_DATA 0x00000000 -#define DDRSS3_CTL_216_DATA 0x00000000 -#define DDRSS3_CTL_217_DATA 0x00000000 -#define DDRSS3_CTL_218_DATA 0x00000000 -#define DDRSS3_CTL_219_DATA 0x00000000 -#define DDRSS3_CTL_220_DATA 0x00000000 -#define DDRSS3_CTL_221_DATA 0x00000000 -#define DDRSS3_CTL_222_DATA 0x00001000 -#define DDRSS3_CTL_223_DATA 0x006403E8 -#define DDRSS3_CTL_224_DATA 0x00000000 -#define DDRSS3_CTL_225_DATA 0x00000000 -#define DDRSS3_CTL_226_DATA 0x00000000 -#define DDRSS3_CTL_227_DATA 0x15110000 -#define DDRSS3_CTL_228_DATA 0x00040C18 -#define DDRSS3_CTL_229_DATA 0xF000C000 -#define DDRSS3_CTL_230_DATA 0x0000F000 -#define DDRSS3_CTL_231_DATA 0x00000000 -#define DDRSS3_CTL_232_DATA 0x00000000 -#define DDRSS3_CTL_233_DATA 0xC0000000 -#define DDRSS3_CTL_234_DATA 0xF000F000 -#define DDRSS3_CTL_235_DATA 0x00000000 -#define DDRSS3_CTL_236_DATA 0x00000000 -#define DDRSS3_CTL_237_DATA 0x00000000 -#define DDRSS3_CTL_238_DATA 0xF000C000 -#define DDRSS3_CTL_239_DATA 0x0000F000 -#define DDRSS3_CTL_240_DATA 0x00000000 -#define DDRSS3_CTL_241_DATA 0x00000000 -#define DDRSS3_CTL_242_DATA 0x00030000 -#define DDRSS3_CTL_243_DATA 0x00000000 -#define DDRSS3_CTL_244_DATA 0x00000000 -#define DDRSS3_CTL_245_DATA 0x00000000 -#define DDRSS3_CTL_246_DATA 0x00000000 -#define DDRSS3_CTL_247_DATA 0x00000000 -#define DDRSS3_CTL_248_DATA 0x00000000 -#define DDRSS3_CTL_249_DATA 0x00000000 -#define DDRSS3_CTL_250_DATA 0x00000000 -#define DDRSS3_CTL_251_DATA 0x00000000 -#define DDRSS3_CTL_252_DATA 0x00000000 -#define DDRSS3_CTL_253_DATA 0x00000000 -#define DDRSS3_CTL_254_DATA 0x00000000 -#define DDRSS3_CTL_255_DATA 0x00000000 -#define DDRSS3_CTL_256_DATA 0x00000000 -#define DDRSS3_CTL_257_DATA 0x01000200 -#define DDRSS3_CTL_258_DATA 0x00370040 -#define DDRSS3_CTL_259_DATA 0x00020008 -#define DDRSS3_CTL_260_DATA 0x00400100 -#define DDRSS3_CTL_261_DATA 0x00400855 -#define DDRSS3_CTL_262_DATA 0x01000200 -#define DDRSS3_CTL_263_DATA 0x08550040 -#define DDRSS3_CTL_264_DATA 0x00000040 -#define DDRSS3_CTL_265_DATA 0x006B0003 -#define DDRSS3_CTL_266_DATA 0x0100006B -#define DDRSS3_CTL_267_DATA 0x03030303 -#define DDRSS3_CTL_268_DATA 0x00000000 -#define DDRSS3_CTL_269_DATA 0x00000202 -#define DDRSS3_CTL_270_DATA 0x00001FFF -#define DDRSS3_CTL_271_DATA 0x3FFF2000 -#define DDRSS3_CTL_272_DATA 0x03FF0000 -#define DDRSS3_CTL_273_DATA 0x000103FF -#define DDRSS3_CTL_274_DATA 0x0FFF0B00 -#define DDRSS3_CTL_275_DATA 0x01010001 -#define DDRSS3_CTL_276_DATA 0x01010101 -#define DDRSS3_CTL_277_DATA 0x01180101 -#define DDRSS3_CTL_278_DATA 0x00030000 -#define DDRSS3_CTL_279_DATA 0x00000000 -#define DDRSS3_CTL_280_DATA 0x00000000 -#define DDRSS3_CTL_281_DATA 0x00000000 -#define DDRSS3_CTL_282_DATA 0x00000000 -#define DDRSS3_CTL_283_DATA 0x00000000 -#define DDRSS3_CTL_284_DATA 0x00000000 -#define DDRSS3_CTL_285_DATA 0x00000000 -#define DDRSS3_CTL_286_DATA 0x00040101 -#define DDRSS3_CTL_287_DATA 0x04010100 -#define DDRSS3_CTL_288_DATA 0x00000000 -#define DDRSS3_CTL_289_DATA 0x00000000 -#define DDRSS3_CTL_290_DATA 0x03030300 -#define DDRSS3_CTL_291_DATA 0x00000001 -#define DDRSS3_CTL_292_DATA 0x00000000 -#define DDRSS3_CTL_293_DATA 0x00000000 -#define DDRSS3_CTL_294_DATA 0x00000000 -#define DDRSS3_CTL_295_DATA 0x00000000 -#define DDRSS3_CTL_296_DATA 0x00000000 -#define DDRSS3_CTL_297_DATA 0x00000000 -#define DDRSS3_CTL_298_DATA 0x00000000 -#define DDRSS3_CTL_299_DATA 0x00000000 -#define DDRSS3_CTL_300_DATA 0x00000000 -#define DDRSS3_CTL_301_DATA 0x00000000 -#define DDRSS3_CTL_302_DATA 0x00000000 -#define DDRSS3_CTL_303_DATA 0x00000000 -#define DDRSS3_CTL_304_DATA 0x00000000 -#define DDRSS3_CTL_305_DATA 0x00000000 -#define DDRSS3_CTL_306_DATA 0x00000000 -#define DDRSS3_CTL_307_DATA 0x00000000 -#define DDRSS3_CTL_308_DATA 0x00000000 -#define DDRSS3_CTL_309_DATA 0x00000000 -#define DDRSS3_CTL_310_DATA 0x00000000 -#define DDRSS3_CTL_311_DATA 0x00000000 -#define DDRSS3_CTL_312_DATA 0x00000000 -#define DDRSS3_CTL_313_DATA 0x01000000 -#define DDRSS3_CTL_314_DATA 0x00020201 -#define DDRSS3_CTL_315_DATA 0x01000101 -#define DDRSS3_CTL_316_DATA 0x01010001 -#define DDRSS3_CTL_317_DATA 0x00010101 -#define DDRSS3_CTL_318_DATA 0x050A0A03 -#define DDRSS3_CTL_319_DATA 0x10081F1F -#define DDRSS3_CTL_320_DATA 0x00090310 -#define DDRSS3_CTL_321_DATA 0x0B0C030F -#define DDRSS3_CTL_322_DATA 0x0B0C0306 -#define DDRSS3_CTL_323_DATA 0x0C090006 -#define DDRSS3_CTL_324_DATA 0x0100000C -#define DDRSS3_CTL_325_DATA 0x08040801 -#define DDRSS3_CTL_326_DATA 0x00000004 -#define DDRSS3_CTL_327_DATA 0x00000000 -#define DDRSS3_CTL_328_DATA 0x00010000 -#define DDRSS3_CTL_329_DATA 0x00280D00 -#define DDRSS3_CTL_330_DATA 0x00000001 -#define DDRSS3_CTL_331_DATA 0x00030001 -#define DDRSS3_CTL_332_DATA 0x00000000 -#define DDRSS3_CTL_333_DATA 0x00000000 -#define DDRSS3_CTL_334_DATA 0x00000000 -#define DDRSS3_CTL_335_DATA 0x00000000 -#define DDRSS3_CTL_336_DATA 0x00000000 -#define DDRSS3_CTL_337_DATA 0x00000000 -#define DDRSS3_CTL_338_DATA 0x00000000 -#define DDRSS3_CTL_339_DATA 0x00000000 -#define DDRSS3_CTL_340_DATA 0x01000000 -#define DDRSS3_CTL_341_DATA 0x00000001 -#define DDRSS3_CTL_342_DATA 0x00010100 -#define DDRSS3_CTL_343_DATA 0x03030000 -#define DDRSS3_CTL_344_DATA 0x00000000 -#define DDRSS3_CTL_345_DATA 0x00000000 -#define DDRSS3_CTL_346_DATA 0x00000000 -#define DDRSS3_CTL_347_DATA 0x00000000 -#define DDRSS3_CTL_348_DATA 0x00000000 -#define DDRSS3_CTL_349_DATA 0x00000000 -#define DDRSS3_CTL_350_DATA 0x00000000 -#define DDRSS3_CTL_351_DATA 0x00000000 -#define DDRSS3_CTL_352_DATA 0x00000000 -#define DDRSS3_CTL_353_DATA 0x00000000 -#define DDRSS3_CTL_354_DATA 0x00000000 -#define DDRSS3_CTL_355_DATA 0x00000000 -#define DDRSS3_CTL_356_DATA 0x00000000 -#define DDRSS3_CTL_357_DATA 0x00000000 -#define DDRSS3_CTL_358_DATA 0x00000000 -#define DDRSS3_CTL_359_DATA 0x00000000 -#define DDRSS3_CTL_360_DATA 0x000556AA -#define DDRSS3_CTL_361_DATA 0x000AAAAA -#define DDRSS3_CTL_362_DATA 0x000AA955 -#define DDRSS3_CTL_363_DATA 0x00055555 -#define DDRSS3_CTL_364_DATA 0x000B3133 -#define DDRSS3_CTL_365_DATA 0x0004CD33 -#define DDRSS3_CTL_366_DATA 0x0004CECC -#define DDRSS3_CTL_367_DATA 0x000B32CC -#define DDRSS3_CTL_368_DATA 0x00010300 -#define DDRSS3_CTL_369_DATA 0x03000100 -#define DDRSS3_CTL_370_DATA 0x00000000 -#define DDRSS3_CTL_371_DATA 0x00000000 -#define DDRSS3_CTL_372_DATA 0x00000000 -#define DDRSS3_CTL_373_DATA 0x00000000 -#define DDRSS3_CTL_374_DATA 0x00000000 -#define DDRSS3_CTL_375_DATA 0x00000000 -#define DDRSS3_CTL_376_DATA 0x00000000 -#define DDRSS3_CTL_377_DATA 0x00010000 -#define DDRSS3_CTL_378_DATA 0x00000404 -#define DDRSS3_CTL_379_DATA 0x00000000 -#define DDRSS3_CTL_380_DATA 0x00000000 -#define DDRSS3_CTL_381_DATA 0x00000000 -#define DDRSS3_CTL_382_DATA 0x00000000 -#define DDRSS3_CTL_383_DATA 0x00000000 -#define DDRSS3_CTL_384_DATA 0x00000000 -#define DDRSS3_CTL_385_DATA 0x00000000 -#define DDRSS3_CTL_386_DATA 0x00000000 -#define DDRSS3_CTL_387_DATA 0x3A3A1B00 -#define DDRSS3_CTL_388_DATA 0x000A0000 -#define DDRSS3_CTL_389_DATA 0x0000019C -#define DDRSS3_CTL_390_DATA 0x00000200 -#define DDRSS3_CTL_391_DATA 0x00000200 -#define DDRSS3_CTL_392_DATA 0x00000200 -#define DDRSS3_CTL_393_DATA 0x00000200 -#define DDRSS3_CTL_394_DATA 0x000004D4 -#define DDRSS3_CTL_395_DATA 0x00001018 -#define DDRSS3_CTL_396_DATA 0x00000204 -#define DDRSS3_CTL_397_DATA 0x000040E6 -#define DDRSS3_CTL_398_DATA 0x00000200 -#define DDRSS3_CTL_399_DATA 0x00000200 -#define DDRSS3_CTL_400_DATA 0x00000200 -#define DDRSS3_CTL_401_DATA 0x00000200 -#define DDRSS3_CTL_402_DATA 0x0000C2B2 -#define DDRSS3_CTL_403_DATA 0x000288FC -#define DDRSS3_CTL_404_DATA 0x00000E15 -#define DDRSS3_CTL_405_DATA 0x000040E6 -#define DDRSS3_CTL_406_DATA 0x00000200 -#define DDRSS3_CTL_407_DATA 0x00000200 -#define DDRSS3_CTL_408_DATA 0x00000200 -#define DDRSS3_CTL_409_DATA 0x00000200 -#define DDRSS3_CTL_410_DATA 0x0000C2B2 -#define DDRSS3_CTL_411_DATA 0x000288FC -#define DDRSS3_CTL_412_DATA 0x02020E15 -#define DDRSS3_CTL_413_DATA 0x03030202 -#define DDRSS3_CTL_414_DATA 0x00000022 -#define DDRSS3_CTL_415_DATA 0x00000000 -#define DDRSS3_CTL_416_DATA 0x00000000 -#define DDRSS3_CTL_417_DATA 0x00001403 -#define DDRSS3_CTL_418_DATA 0x000007D0 -#define DDRSS3_CTL_419_DATA 0x00000000 -#define DDRSS3_CTL_420_DATA 0x00000000 -#define DDRSS3_CTL_421_DATA 0x00030000 -#define DDRSS3_CTL_422_DATA 0x0007001F -#define DDRSS3_CTL_423_DATA 0x001B0033 -#define DDRSS3_CTL_424_DATA 0x001B0033 -#define DDRSS3_CTL_425_DATA 0x00000000 -#define DDRSS3_CTL_426_DATA 0x00000000 -#define DDRSS3_CTL_427_DATA 0x02000000 -#define DDRSS3_CTL_428_DATA 0x01000404 -#define DDRSS3_CTL_429_DATA 0x0B1E0B1E -#define DDRSS3_CTL_430_DATA 0x00000105 -#define DDRSS3_CTL_431_DATA 0x00010101 -#define DDRSS3_CTL_432_DATA 0x00010101 -#define DDRSS3_CTL_433_DATA 0x00010001 -#define DDRSS3_CTL_434_DATA 0x00000101 -#define DDRSS3_CTL_435_DATA 0x02000201 -#define DDRSS3_CTL_436_DATA 0x02010000 -#define DDRSS3_CTL_437_DATA 0x00000200 -#define DDRSS3_CTL_438_DATA 0x28060000 -#define DDRSS3_CTL_439_DATA 0x00000128 -#define DDRSS3_CTL_440_DATA 0xFFFFFFFF -#define DDRSS3_CTL_441_DATA 0xFFFFFFFF -#define DDRSS3_CTL_442_DATA 0x00000000 -#define DDRSS3_CTL_443_DATA 0x00000000 -#define DDRSS3_CTL_444_DATA 0x00000000 -#define DDRSS3_CTL_445_DATA 0x00000000 -#define DDRSS3_CTL_446_DATA 0x00000000 -#define DDRSS3_CTL_447_DATA 0x00000000 -#define DDRSS3_CTL_448_DATA 0x00000000 -#define DDRSS3_CTL_449_DATA 0x00000000 -#define DDRSS3_CTL_450_DATA 0x00000000 -#define DDRSS3_CTL_451_DATA 0x00000000 -#define DDRSS3_CTL_452_DATA 0x00000000 -#define DDRSS3_CTL_453_DATA 0x00000000 -#define DDRSS3_CTL_454_DATA 0x00000000 -#define DDRSS3_CTL_455_DATA 0x00000000 -#define DDRSS3_CTL_456_DATA 0x00000000 -#define DDRSS3_CTL_457_DATA 0x00000000 -#define DDRSS3_CTL_458_DATA 0x00000000 - -#define DDRSS3_PI_00_DATA 0x00000B00 -#define DDRSS3_PI_01_DATA 0x00000000 -#define DDRSS3_PI_02_DATA 0x00000000 -#define DDRSS3_PI_03_DATA 0x00000000 -#define DDRSS3_PI_04_DATA 0x00000000 -#define DDRSS3_PI_05_DATA 0x00000101 -#define DDRSS3_PI_06_DATA 0x00640000 -#define DDRSS3_PI_07_DATA 0x00000001 -#define DDRSS3_PI_08_DATA 0x00000000 -#define DDRSS3_PI_09_DATA 0x00000000 -#define DDRSS3_PI_10_DATA 0x00000000 -#define DDRSS3_PI_11_DATA 0x00000000 -#define DDRSS3_PI_12_DATA 0x00000007 -#define DDRSS3_PI_13_DATA 0x00010002 -#define DDRSS3_PI_14_DATA 0x0800000F -#define DDRSS3_PI_15_DATA 0x00000103 -#define DDRSS3_PI_16_DATA 0x00000005 -#define DDRSS3_PI_17_DATA 0x00000000 -#define DDRSS3_PI_18_DATA 0x00000000 -#define DDRSS3_PI_19_DATA 0x00000000 -#define DDRSS3_PI_20_DATA 0x00000000 -#define DDRSS3_PI_21_DATA 0x00000000 -#define DDRSS3_PI_22_DATA 0x00000000 -#define DDRSS3_PI_23_DATA 0x00000000 -#define DDRSS3_PI_24_DATA 0x00000000 -#define DDRSS3_PI_25_DATA 0x00000000 -#define DDRSS3_PI_26_DATA 0x00010100 -#define DDRSS3_PI_27_DATA 0x00280A00 -#define DDRSS3_PI_28_DATA 0x00000000 -#define DDRSS3_PI_29_DATA 0x0F000000 -#define DDRSS3_PI_30_DATA 0x00003200 -#define DDRSS3_PI_31_DATA 0x00000000 -#define DDRSS3_PI_32_DATA 0x00000000 -#define DDRSS3_PI_33_DATA 0x01010102 -#define DDRSS3_PI_34_DATA 0x00000000 -#define DDRSS3_PI_35_DATA 0x000000AA -#define DDRSS3_PI_36_DATA 0x00000055 -#define DDRSS3_PI_37_DATA 0x000000B5 -#define DDRSS3_PI_38_DATA 0x0000004A -#define DDRSS3_PI_39_DATA 0x00000056 -#define DDRSS3_PI_40_DATA 0x000000A9 -#define DDRSS3_PI_41_DATA 0x000000A9 -#define DDRSS3_PI_42_DATA 0x000000B5 -#define DDRSS3_PI_43_DATA 0x00000000 -#define DDRSS3_PI_44_DATA 0x00000000 -#define DDRSS3_PI_45_DATA 0x000F0F00 -#define DDRSS3_PI_46_DATA 0x0000001B -#define DDRSS3_PI_47_DATA 0x000007D0 -#define DDRSS3_PI_48_DATA 0x00000300 -#define DDRSS3_PI_49_DATA 0x00000000 -#define DDRSS3_PI_50_DATA 0x00000000 -#define DDRSS3_PI_51_DATA 0x01000000 -#define DDRSS3_PI_52_DATA 0x00010101 -#define DDRSS3_PI_53_DATA 0x00000000 -#define DDRSS3_PI_54_DATA 0x00030000 -#define DDRSS3_PI_55_DATA 0x0F000000 -#define DDRSS3_PI_56_DATA 0x00000017 -#define DDRSS3_PI_57_DATA 0x00000000 -#define DDRSS3_PI_58_DATA 0x00000000 -#define DDRSS3_PI_59_DATA 0x00000000 -#define DDRSS3_PI_60_DATA 0x0A0A140A -#define DDRSS3_PI_61_DATA 0x10020101 -#define DDRSS3_PI_62_DATA 0x00020805 -#define DDRSS3_PI_63_DATA 0x01000404 -#define DDRSS3_PI_64_DATA 0x00000000 -#define DDRSS3_PI_65_DATA 0x00000000 -#define DDRSS3_PI_66_DATA 0x00000100 -#define DDRSS3_PI_67_DATA 0x0001010F -#define DDRSS3_PI_68_DATA 0x00340000 -#define DDRSS3_PI_69_DATA 0x00000000 -#define DDRSS3_PI_70_DATA 0x00000000 -#define DDRSS3_PI_71_DATA 0x0000FFFF -#define DDRSS3_PI_72_DATA 0x00000000 -#define DDRSS3_PI_73_DATA 0x00080000 -#define DDRSS3_PI_74_DATA 0x02000200 -#define DDRSS3_PI_75_DATA 0x01000100 -#define DDRSS3_PI_76_DATA 0x01000000 -#define DDRSS3_PI_77_DATA 0x02000200 -#define DDRSS3_PI_78_DATA 0x00000200 -#define DDRSS3_PI_79_DATA 0x00000000 -#define DDRSS3_PI_80_DATA 0x00000000 -#define DDRSS3_PI_81_DATA 0x00000000 -#define DDRSS3_PI_82_DATA 0x00000000 -#define DDRSS3_PI_83_DATA 0x00000000 -#define DDRSS3_PI_84_DATA 0x00000000 -#define DDRSS3_PI_85_DATA 0x00000000 -#define DDRSS3_PI_86_DATA 0x00000000 -#define DDRSS3_PI_87_DATA 0x00000000 -#define DDRSS3_PI_88_DATA 0x00000000 -#define DDRSS3_PI_89_DATA 0x00000000 -#define DDRSS3_PI_90_DATA 0x00000000 -#define DDRSS3_PI_91_DATA 0x00000400 -#define DDRSS3_PI_92_DATA 0x02010000 -#define DDRSS3_PI_93_DATA 0x00080003 -#define DDRSS3_PI_94_DATA 0x00080000 -#define DDRSS3_PI_95_DATA 0x00000001 -#define DDRSS3_PI_96_DATA 0x00000000 -#define DDRSS3_PI_97_DATA 0x0000AA00 -#define DDRSS3_PI_98_DATA 0x00000000 -#define DDRSS3_PI_99_DATA 0x00000000 -#define DDRSS3_PI_100_DATA 0x00010000 -#define DDRSS3_PI_101_DATA 0x00000000 -#define DDRSS3_PI_102_DATA 0x00000000 -#define DDRSS3_PI_103_DATA 0x00000000 -#define DDRSS3_PI_104_DATA 0x00000000 -#define DDRSS3_PI_105_DATA 0x00000000 -#define DDRSS3_PI_106_DATA 0x00000000 -#define DDRSS3_PI_107_DATA 0x00000000 -#define DDRSS3_PI_108_DATA 0x00000000 -#define DDRSS3_PI_109_DATA 0x00000000 -#define DDRSS3_PI_110_DATA 0x00000000 -#define DDRSS3_PI_111_DATA 0x00000000 -#define DDRSS3_PI_112_DATA 0x00000000 -#define DDRSS3_PI_113_DATA 0x00000000 -#define DDRSS3_PI_114_DATA 0x00000000 -#define DDRSS3_PI_115_DATA 0x00000000 -#define DDRSS3_PI_116_DATA 0x00000000 -#define DDRSS3_PI_117_DATA 0x00000000 -#define DDRSS3_PI_118_DATA 0x00000000 -#define DDRSS3_PI_119_DATA 0x00000000 -#define DDRSS3_PI_120_DATA 0x00000000 -#define DDRSS3_PI_121_DATA 0x00000000 -#define DDRSS3_PI_122_DATA 0x00000000 -#define DDRSS3_PI_123_DATA 0x00000000 -#define DDRSS3_PI_124_DATA 0x00000000 -#define DDRSS3_PI_125_DATA 0x00000008 -#define DDRSS3_PI_126_DATA 0x00000000 -#define DDRSS3_PI_127_DATA 0x00000000 -#define DDRSS3_PI_128_DATA 0x00000000 -#define DDRSS3_PI_129_DATA 0x00000000 -#define DDRSS3_PI_130_DATA 0x00000000 -#define DDRSS3_PI_131_DATA 0x00000000 -#define DDRSS3_PI_132_DATA 0x00000000 -#define DDRSS3_PI_133_DATA 0x00000000 -#define DDRSS3_PI_134_DATA 0x00000002 -#define DDRSS3_PI_135_DATA 0x00000000 -#define DDRSS3_PI_136_DATA 0x00000000 -#define DDRSS3_PI_137_DATA 0x0000000A -#define DDRSS3_PI_138_DATA 0x00000019 -#define DDRSS3_PI_139_DATA 0x00000100 -#define DDRSS3_PI_140_DATA 0x00000000 -#define DDRSS3_PI_141_DATA 0x00000000 -#define DDRSS3_PI_142_DATA 0x00000000 -#define DDRSS3_PI_143_DATA 0x00000000 -#define DDRSS3_PI_144_DATA 0x01000000 -#define DDRSS3_PI_145_DATA 0x00010003 -#define DDRSS3_PI_146_DATA 0x02000101 -#define DDRSS3_PI_147_DATA 0x01030001 -#define DDRSS3_PI_148_DATA 0x00010400 -#define DDRSS3_PI_149_DATA 0x06000105 -#define DDRSS3_PI_150_DATA 0x01070001 -#define DDRSS3_PI_151_DATA 0x00000000 -#define DDRSS3_PI_152_DATA 0x00000000 -#define DDRSS3_PI_153_DATA 0x00000000 -#define DDRSS3_PI_154_DATA 0x00010001 -#define DDRSS3_PI_155_DATA 0x00000000 -#define DDRSS3_PI_156_DATA 0x00000000 -#define DDRSS3_PI_157_DATA 0x00000000 -#define DDRSS3_PI_158_DATA 0x00000000 -#define DDRSS3_PI_159_DATA 0x00000401 -#define DDRSS3_PI_160_DATA 0x00000000 -#define DDRSS3_PI_161_DATA 0x00010000 -#define DDRSS3_PI_162_DATA 0x00000000 -#define DDRSS3_PI_163_DATA 0x2B2B0200 -#define DDRSS3_PI_164_DATA 0x00000034 -#define DDRSS3_PI_165_DATA 0x00000064 -#define DDRSS3_PI_166_DATA 0x00020064 -#define DDRSS3_PI_167_DATA 0x02000200 -#define DDRSS3_PI_168_DATA 0x48120C04 -#define DDRSS3_PI_169_DATA 0x00154812 -#define DDRSS3_PI_170_DATA 0x000000CE -#define DDRSS3_PI_171_DATA 0x0000032B -#define DDRSS3_PI_172_DATA 0x00002073 -#define DDRSS3_PI_173_DATA 0x0000032B -#define DDRSS3_PI_174_DATA 0x04002073 -#define DDRSS3_PI_175_DATA 0x01010404 -#define DDRSS3_PI_176_DATA 0x00001501 -#define DDRSS3_PI_177_DATA 0x00150015 -#define DDRSS3_PI_178_DATA 0x01000100 -#define DDRSS3_PI_179_DATA 0x00000100 -#define DDRSS3_PI_180_DATA 0x00000000 -#define DDRSS3_PI_181_DATA 0x01010101 -#define DDRSS3_PI_182_DATA 0x00000101 -#define DDRSS3_PI_183_DATA 0x00000000 -#define DDRSS3_PI_184_DATA 0x00000000 -#define DDRSS3_PI_185_DATA 0x15040000 -#define DDRSS3_PI_186_DATA 0x0E0E0215 -#define DDRSS3_PI_187_DATA 0x00040402 -#define DDRSS3_PI_188_DATA 0x000D0035 -#define DDRSS3_PI_189_DATA 0x00218049 -#define DDRSS3_PI_190_DATA 0x00218049 -#define DDRSS3_PI_191_DATA 0x01010101 -#define DDRSS3_PI_192_DATA 0x0004000E -#define DDRSS3_PI_193_DATA 0x00040216 -#define DDRSS3_PI_194_DATA 0x01000216 -#define DDRSS3_PI_195_DATA 0x000F000F -#define DDRSS3_PI_196_DATA 0x02170100 -#define DDRSS3_PI_197_DATA 0x01000217 -#define DDRSS3_PI_198_DATA 0x02170217 -#define DDRSS3_PI_199_DATA 0x32103200 -#define DDRSS3_PI_200_DATA 0x01013210 -#define DDRSS3_PI_201_DATA 0x0A070601 -#define DDRSS3_PI_202_DATA 0x1F130A0D -#define DDRSS3_PI_203_DATA 0x1F130A14 -#define DDRSS3_PI_204_DATA 0x0000C014 -#define DDRSS3_PI_205_DATA 0x00C01000 -#define DDRSS3_PI_206_DATA 0x00C01000 -#define DDRSS3_PI_207_DATA 0x00021000 -#define DDRSS3_PI_208_DATA 0x0024000E -#define DDRSS3_PI_209_DATA 0x00240216 -#define DDRSS3_PI_210_DATA 0x00110216 -#define DDRSS3_PI_211_DATA 0x32000056 -#define DDRSS3_PI_212_DATA 0x00000301 -#define DDRSS3_PI_213_DATA 0x005B0036 -#define DDRSS3_PI_214_DATA 0x03013212 -#define DDRSS3_PI_215_DATA 0x00003600 -#define DDRSS3_PI_216_DATA 0x3212005B -#define DDRSS3_PI_217_DATA 0x09000301 -#define DDRSS3_PI_218_DATA 0x04010504 -#define DDRSS3_PI_219_DATA 0x040006C9 -#define DDRSS3_PI_220_DATA 0x0A032001 -#define DDRSS3_PI_221_DATA 0x2C31110A -#define DDRSS3_PI_222_DATA 0x00002918 -#define DDRSS3_PI_223_DATA 0x6001071C -#define DDRSS3_PI_224_DATA 0x1E202008 -#define DDRSS3_PI_225_DATA 0x2C311116 -#define DDRSS3_PI_226_DATA 0x00002918 -#define DDRSS3_PI_227_DATA 0x6001071C -#define DDRSS3_PI_228_DATA 0x1E202008 -#define DDRSS3_PI_229_DATA 0x00019C16 -#define DDRSS3_PI_230_DATA 0x00001018 -#define DDRSS3_PI_231_DATA 0x000040E6 -#define DDRSS3_PI_232_DATA 0x000288FC -#define DDRSS3_PI_233_DATA 0x000040E6 -#define DDRSS3_PI_234_DATA 0x000288FC -#define DDRSS3_PI_235_DATA 0x033B0016 -#define DDRSS3_PI_236_DATA 0x0303033B -#define DDRSS3_PI_237_DATA 0x002AF803 -#define DDRSS3_PI_238_DATA 0x0001ADAF -#define DDRSS3_PI_239_DATA 0x00000005 -#define DDRSS3_PI_240_DATA 0x0000006E -#define DDRSS3_PI_241_DATA 0x00000016 -#define DDRSS3_PI_242_DATA 0x000681C8 -#define DDRSS3_PI_243_DATA 0x0001ADAF -#define DDRSS3_PI_244_DATA 0x00000005 -#define DDRSS3_PI_245_DATA 0x000010A9 -#define DDRSS3_PI_246_DATA 0x0000033B -#define DDRSS3_PI_247_DATA 0x000681C8 -#define DDRSS3_PI_248_DATA 0x0001ADAF -#define DDRSS3_PI_249_DATA 0x00000005 -#define DDRSS3_PI_250_DATA 0x000010A9 -#define DDRSS3_PI_251_DATA 0x0100033B -#define DDRSS3_PI_252_DATA 0x00370040 -#define DDRSS3_PI_253_DATA 0x00010008 -#define DDRSS3_PI_254_DATA 0x08550040 -#define DDRSS3_PI_255_DATA 0x00010040 -#define DDRSS3_PI_256_DATA 0x08550040 -#define DDRSS3_PI_257_DATA 0x00000340 -#define DDRSS3_PI_258_DATA 0x006B006B -#define DDRSS3_PI_259_DATA 0x08040404 -#define DDRSS3_PI_260_DATA 0x00000055 -#define DDRSS3_PI_261_DATA 0x55083C5A -#define DDRSS3_PI_262_DATA 0x5A000000 -#define DDRSS3_PI_263_DATA 0x0055083C -#define DDRSS3_PI_264_DATA 0x3C5A0000 -#define DDRSS3_PI_265_DATA 0x00005508 -#define DDRSS3_PI_266_DATA 0x0C3C5A00 -#define DDRSS3_PI_267_DATA 0x080F0E0D -#define DDRSS3_PI_268_DATA 0x000B0A09 -#define DDRSS3_PI_269_DATA 0x00030201 -#define DDRSS3_PI_270_DATA 0x01000000 -#define DDRSS3_PI_271_DATA 0x04020201 -#define DDRSS3_PI_272_DATA 0x00080804 -#define DDRSS3_PI_273_DATA 0x00000000 -#define DDRSS3_PI_274_DATA 0x00000000 -#define DDRSS3_PI_275_DATA 0x00330084 -#define DDRSS3_PI_276_DATA 0x00160000 -#define DDRSS3_PI_277_DATA 0x35333FF4 -#define DDRSS3_PI_278_DATA 0x00160F27 -#define DDRSS3_PI_279_DATA 0x35333FF4 -#define DDRSS3_PI_280_DATA 0x00160F27 -#define DDRSS3_PI_281_DATA 0x00330084 -#define DDRSS3_PI_282_DATA 0x00160000 -#define DDRSS3_PI_283_DATA 0x35333FF4 -#define DDRSS3_PI_284_DATA 0x00160F27 -#define DDRSS3_PI_285_DATA 0x35333FF4 -#define DDRSS3_PI_286_DATA 0x00160F27 -#define DDRSS3_PI_287_DATA 0x00330084 -#define DDRSS3_PI_288_DATA 0x00160000 -#define DDRSS3_PI_289_DATA 0x35333FF4 -#define DDRSS3_PI_290_DATA 0x00160F27 -#define DDRSS3_PI_291_DATA 0x35333FF4 -#define DDRSS3_PI_292_DATA 0x00160F27 -#define DDRSS3_PI_293_DATA 0x00330084 -#define DDRSS3_PI_294_DATA 0x00160000 -#define DDRSS3_PI_295_DATA 0x35333FF4 -#define DDRSS3_PI_296_DATA 0x00160F27 -#define DDRSS3_PI_297_DATA 0x35333FF4 -#define DDRSS3_PI_298_DATA 0x00160F27 -#define DDRSS3_PI_299_DATA 0x00000000 - -#define DDRSS3_PHY_00_DATA 0x000004F0 -#define DDRSS3_PHY_01_DATA 0x00000000 -#define DDRSS3_PHY_02_DATA 0x00030200 -#define DDRSS3_PHY_03_DATA 0x00000000 -#define DDRSS3_PHY_04_DATA 0x00000000 -#define DDRSS3_PHY_05_DATA 0x01030000 -#define DDRSS3_PHY_06_DATA 0x00010000 -#define DDRSS3_PHY_07_DATA 0x01030004 -#define DDRSS3_PHY_08_DATA 0x01000000 -#define DDRSS3_PHY_09_DATA 0x00000000 -#define DDRSS3_PHY_10_DATA 0x00000000 -#define DDRSS3_PHY_11_DATA 0x01000001 -#define DDRSS3_PHY_12_DATA 0x00000100 -#define DDRSS3_PHY_13_DATA 0x000800C0 -#define DDRSS3_PHY_14_DATA 0x060100CC -#define DDRSS3_PHY_15_DATA 0x00030066 -#define DDRSS3_PHY_16_DATA 0x00000000 -#define DDRSS3_PHY_17_DATA 0x00000301 -#define DDRSS3_PHY_18_DATA 0x0000AAAA -#define DDRSS3_PHY_19_DATA 0x00005555 -#define DDRSS3_PHY_20_DATA 0x0000B5B5 -#define DDRSS3_PHY_21_DATA 0x00004A4A -#define DDRSS3_PHY_22_DATA 0x00005656 -#define DDRSS3_PHY_23_DATA 0x0000A9A9 -#define DDRSS3_PHY_24_DATA 0x0000A9A9 -#define DDRSS3_PHY_25_DATA 0x0000B5B5 -#define DDRSS3_PHY_26_DATA 0x00000000 -#define DDRSS3_PHY_27_DATA 0x00000000 -#define DDRSS3_PHY_28_DATA 0x2A000000 -#define DDRSS3_PHY_29_DATA 0x00000808 -#define DDRSS3_PHY_30_DATA 0x0F000000 -#define DDRSS3_PHY_31_DATA 0x00000F0F -#define DDRSS3_PHY_32_DATA 0x10400000 -#define DDRSS3_PHY_33_DATA 0x0C002006 -#define DDRSS3_PHY_34_DATA 0x00000000 -#define DDRSS3_PHY_35_DATA 0x00000000 -#define DDRSS3_PHY_36_DATA 0x55555555 -#define DDRSS3_PHY_37_DATA 0xAAAAAAAA -#define DDRSS3_PHY_38_DATA 0x55555555 -#define DDRSS3_PHY_39_DATA 0xAAAAAAAA -#define DDRSS3_PHY_40_DATA 0x00005555 -#define DDRSS3_PHY_41_DATA 0x01000100 -#define DDRSS3_PHY_42_DATA 0x00800180 -#define DDRSS3_PHY_43_DATA 0x00000001 -#define DDRSS3_PHY_44_DATA 0x00000000 -#define DDRSS3_PHY_45_DATA 0x00000000 -#define DDRSS3_PHY_46_DATA 0x00000000 -#define DDRSS3_PHY_47_DATA 0x00000000 -#define DDRSS3_PHY_48_DATA 0x00000000 -#define DDRSS3_PHY_49_DATA 0x00000000 -#define DDRSS3_PHY_50_DATA 0x00000000 -#define DDRSS3_PHY_51_DATA 0x00000000 -#define DDRSS3_PHY_52_DATA 0x00000000 -#define DDRSS3_PHY_53_DATA 0x00000000 -#define DDRSS3_PHY_54_DATA 0x00000000 -#define DDRSS3_PHY_55_DATA 0x00000000 -#define DDRSS3_PHY_56_DATA 0x00000000 -#define DDRSS3_PHY_57_DATA 0x00000000 -#define DDRSS3_PHY_58_DATA 0x00000000 -#define DDRSS3_PHY_59_DATA 0x00000000 -#define DDRSS3_PHY_60_DATA 0x00000000 -#define DDRSS3_PHY_61_DATA 0x00000000 -#define DDRSS3_PHY_62_DATA 0x00000000 -#define DDRSS3_PHY_63_DATA 0x00000000 -#define DDRSS3_PHY_64_DATA 0x00000000 -#define DDRSS3_PHY_65_DATA 0x00000000 -#define DDRSS3_PHY_66_DATA 0x00000104 -#define DDRSS3_PHY_67_DATA 0x00000120 -#define DDRSS3_PHY_68_DATA 0x00000000 -#define DDRSS3_PHY_69_DATA 0x00000000 -#define DDRSS3_PHY_70_DATA 0x00000000 -#define DDRSS3_PHY_71_DATA 0x00000000 -#define DDRSS3_PHY_72_DATA 0x00000000 -#define DDRSS3_PHY_73_DATA 0x00000000 -#define DDRSS3_PHY_74_DATA 0x00000000 -#define DDRSS3_PHY_75_DATA 0x00000001 -#define DDRSS3_PHY_76_DATA 0x07FF0000 -#define DDRSS3_PHY_77_DATA 0x0080081F -#define DDRSS3_PHY_78_DATA 0x00081020 -#define DDRSS3_PHY_79_DATA 0x04010000 -#define DDRSS3_PHY_80_DATA 0x00000000 -#define DDRSS3_PHY_81_DATA 0x00000000 -#define DDRSS3_PHY_82_DATA 0x00000000 -#define DDRSS3_PHY_83_DATA 0x00000100 -#define DDRSS3_PHY_84_DATA 0x01CC0C01 -#define DDRSS3_PHY_85_DATA 0x1003CC0C -#define DDRSS3_PHY_86_DATA 0x20000140 -#define DDRSS3_PHY_87_DATA 0x07FF0200 -#define DDRSS3_PHY_88_DATA 0x0000DD01 -#define DDRSS3_PHY_89_DATA 0x10100303 -#define DDRSS3_PHY_90_DATA 0x10101010 -#define DDRSS3_PHY_91_DATA 0x10101010 -#define DDRSS3_PHY_92_DATA 0x00021010 -#define DDRSS3_PHY_93_DATA 0x00100010 -#define DDRSS3_PHY_94_DATA 0x00100010 -#define DDRSS3_PHY_95_DATA 0x00100010 -#define DDRSS3_PHY_96_DATA 0x00100010 -#define DDRSS3_PHY_97_DATA 0x00050010 -#define DDRSS3_PHY_98_DATA 0x51517041 -#define DDRSS3_PHY_99_DATA 0x31C06001 -#define DDRSS3_PHY_100_DATA 0x07AB0340 -#define DDRSS3_PHY_101_DATA 0x00C0C001 -#define DDRSS3_PHY_102_DATA 0x0E0D0001 -#define DDRSS3_PHY_103_DATA 0x10001000 -#define DDRSS3_PHY_104_DATA 0x0C083E42 -#define DDRSS3_PHY_105_DATA 0x0F0C3701 -#define DDRSS3_PHY_106_DATA 0x01000140 -#define DDRSS3_PHY_107_DATA 0x0C000420 -#define DDRSS3_PHY_108_DATA 0x00000198 -#define DDRSS3_PHY_109_DATA 0x0A0000D0 -#define DDRSS3_PHY_110_DATA 0x00030200 -#define DDRSS3_PHY_111_DATA 0x02800000 -#define DDRSS3_PHY_112_DATA 0x80800000 -#define DDRSS3_PHY_113_DATA 0x000E2010 -#define DDRSS3_PHY_114_DATA 0x76543210 -#define DDRSS3_PHY_115_DATA 0x00000008 -#define DDRSS3_PHY_116_DATA 0x02800280 -#define DDRSS3_PHY_117_DATA 0x02800280 -#define DDRSS3_PHY_118_DATA 0x02800280 -#define DDRSS3_PHY_119_DATA 0x02800280 -#define DDRSS3_PHY_120_DATA 0x00000280 -#define DDRSS3_PHY_121_DATA 0x0000A000 -#define DDRSS3_PHY_122_DATA 0x00A000A0 -#define DDRSS3_PHY_123_DATA 0x00A000A0 -#define DDRSS3_PHY_124_DATA 0x00A000A0 -#define DDRSS3_PHY_125_DATA 0x00A000A0 -#define DDRSS3_PHY_126_DATA 0x00A000A0 -#define DDRSS3_PHY_127_DATA 0x00A000A0 -#define DDRSS3_PHY_128_DATA 0x00A000A0 -#define DDRSS3_PHY_129_DATA 0x00A000A0 -#define DDRSS3_PHY_130_DATA 0x01C200A0 -#define DDRSS3_PHY_131_DATA 0x01A00005 -#define DDRSS3_PHY_132_DATA 0x00000000 -#define DDRSS3_PHY_133_DATA 0x00000000 -#define DDRSS3_PHY_134_DATA 0x00080200 -#define DDRSS3_PHY_135_DATA 0x00000000 -#define DDRSS3_PHY_136_DATA 0x20202000 -#define DDRSS3_PHY_137_DATA 0x20202020 -#define DDRSS3_PHY_138_DATA 0xF0F02020 -#define DDRSS3_PHY_139_DATA 0x00000000 -#define DDRSS3_PHY_140_DATA 0x00000000 -#define DDRSS3_PHY_141_DATA 0x00000000 -#define DDRSS3_PHY_142_DATA 0x00000000 -#define DDRSS3_PHY_143_DATA 0x00000000 -#define DDRSS3_PHY_144_DATA 0x00000000 -#define DDRSS3_PHY_145_DATA 0x00000000 -#define DDRSS3_PHY_146_DATA 0x00000000 -#define DDRSS3_PHY_147_DATA 0x00000000 -#define DDRSS3_PHY_148_DATA 0x00000000 -#define DDRSS3_PHY_149_DATA 0x00000000 -#define DDRSS3_PHY_150_DATA 0x00000000 -#define DDRSS3_PHY_151_DATA 0x00000000 -#define DDRSS3_PHY_152_DATA 0x00000000 -#define DDRSS3_PHY_153_DATA 0x00000000 -#define DDRSS3_PHY_154_DATA 0x00000000 -#define DDRSS3_PHY_155_DATA 0x00000000 -#define DDRSS3_PHY_156_DATA 0x00000000 -#define DDRSS3_PHY_157_DATA 0x00000000 -#define DDRSS3_PHY_158_DATA 0x00000000 -#define DDRSS3_PHY_159_DATA 0x00000000 -#define DDRSS3_PHY_160_DATA 0x00000000 -#define DDRSS3_PHY_161_DATA 0x00000000 -#define DDRSS3_PHY_162_DATA 0x00000000 -#define DDRSS3_PHY_163_DATA 0x00000000 -#define DDRSS3_PHY_164_DATA 0x00000000 -#define DDRSS3_PHY_165_DATA 0x00000000 -#define DDRSS3_PHY_166_DATA 0x00000000 -#define DDRSS3_PHY_167_DATA 0x00000000 -#define DDRSS3_PHY_168_DATA 0x00000000 -#define DDRSS3_PHY_169_DATA 0x00000000 -#define DDRSS3_PHY_170_DATA 0x00000000 -#define DDRSS3_PHY_171_DATA 0x00000000 -#define DDRSS3_PHY_172_DATA 0x00000000 -#define DDRSS3_PHY_173_DATA 0x00000000 -#define DDRSS3_PHY_174_DATA 0x00000000 -#define DDRSS3_PHY_175_DATA 0x00000000 -#define DDRSS3_PHY_176_DATA 0x00000000 -#define DDRSS3_PHY_177_DATA 0x00000000 -#define DDRSS3_PHY_178_DATA 0x00000000 -#define DDRSS3_PHY_179_DATA 0x00000000 -#define DDRSS3_PHY_180_DATA 0x00000000 -#define DDRSS3_PHY_181_DATA 0x00000000 -#define DDRSS3_PHY_182_DATA 0x00000000 -#define DDRSS3_PHY_183_DATA 0x00000000 -#define DDRSS3_PHY_184_DATA 0x00000000 -#define DDRSS3_PHY_185_DATA 0x00000000 -#define DDRSS3_PHY_186_DATA 0x00000000 -#define DDRSS3_PHY_187_DATA 0x00000000 -#define DDRSS3_PHY_188_DATA 0x00000000 -#define DDRSS3_PHY_189_DATA 0x00000000 -#define DDRSS3_PHY_190_DATA 0x00000000 -#define DDRSS3_PHY_191_DATA 0x00000000 -#define DDRSS3_PHY_192_DATA 0x00000000 -#define DDRSS3_PHY_193_DATA 0x00000000 -#define DDRSS3_PHY_194_DATA 0x00000000 -#define DDRSS3_PHY_195_DATA 0x00000000 -#define DDRSS3_PHY_196_DATA 0x00000000 -#define DDRSS3_PHY_197_DATA 0x00000000 -#define DDRSS3_PHY_198_DATA 0x00000000 -#define DDRSS3_PHY_199_DATA 0x00000000 -#define DDRSS3_PHY_200_DATA 0x00000000 -#define DDRSS3_PHY_201_DATA 0x00000000 -#define DDRSS3_PHY_202_DATA 0x00000000 -#define DDRSS3_PHY_203_DATA 0x00000000 -#define DDRSS3_PHY_204_DATA 0x00000000 -#define DDRSS3_PHY_205_DATA 0x00000000 -#define DDRSS3_PHY_206_DATA 0x00000000 -#define DDRSS3_PHY_207_DATA 0x00000000 -#define DDRSS3_PHY_208_DATA 0x00000000 -#define DDRSS3_PHY_209_DATA 0x00000000 -#define DDRSS3_PHY_210_DATA 0x00000000 -#define DDRSS3_PHY_211_DATA 0x00000000 -#define DDRSS3_PHY_212_DATA 0x00000000 -#define DDRSS3_PHY_213_DATA 0x00000000 -#define DDRSS3_PHY_214_DATA 0x00000000 -#define DDRSS3_PHY_215_DATA 0x00000000 -#define DDRSS3_PHY_216_DATA 0x00000000 -#define DDRSS3_PHY_217_DATA 0x00000000 -#define DDRSS3_PHY_218_DATA 0x00000000 -#define DDRSS3_PHY_219_DATA 0x00000000 -#define DDRSS3_PHY_220_DATA 0x00000000 -#define DDRSS3_PHY_221_DATA 0x00000000 -#define DDRSS3_PHY_222_DATA 0x00000000 -#define DDRSS3_PHY_223_DATA 0x00000000 -#define DDRSS3_PHY_224_DATA 0x00000000 -#define DDRSS3_PHY_225_DATA 0x00000000 -#define DDRSS3_PHY_226_DATA 0x00000000 -#define DDRSS3_PHY_227_DATA 0x00000000 -#define DDRSS3_PHY_228_DATA 0x00000000 -#define DDRSS3_PHY_229_DATA 0x00000000 -#define DDRSS3_PHY_230_DATA 0x00000000 -#define DDRSS3_PHY_231_DATA 0x00000000 -#define DDRSS3_PHY_232_DATA 0x00000000 -#define DDRSS3_PHY_233_DATA 0x00000000 -#define DDRSS3_PHY_234_DATA 0x00000000 -#define DDRSS3_PHY_235_DATA 0x00000000 -#define DDRSS3_PHY_236_DATA 0x00000000 -#define DDRSS3_PHY_237_DATA 0x00000000 -#define DDRSS3_PHY_238_DATA 0x00000000 -#define DDRSS3_PHY_239_DATA 0x00000000 -#define DDRSS3_PHY_240_DATA 0x00000000 -#define DDRSS3_PHY_241_DATA 0x00000000 -#define DDRSS3_PHY_242_DATA 0x00000000 -#define DDRSS3_PHY_243_DATA 0x00000000 -#define DDRSS3_PHY_244_DATA 0x00000000 -#define DDRSS3_PHY_245_DATA 0x00000000 -#define DDRSS3_PHY_246_DATA 0x00000000 -#define DDRSS3_PHY_247_DATA 0x00000000 -#define DDRSS3_PHY_248_DATA 0x00000000 -#define DDRSS3_PHY_249_DATA 0x00000000 -#define DDRSS3_PHY_250_DATA 0x00000000 -#define DDRSS3_PHY_251_DATA 0x00000000 -#define DDRSS3_PHY_252_DATA 0x00000000 -#define DDRSS3_PHY_253_DATA 0x00000000 -#define DDRSS3_PHY_254_DATA 0x00000000 -#define DDRSS3_PHY_255_DATA 0x00000000 -#define DDRSS3_PHY_256_DATA 0x000004F0 -#define DDRSS3_PHY_257_DATA 0x00000000 -#define DDRSS3_PHY_258_DATA 0x00030200 -#define DDRSS3_PHY_259_DATA 0x00000000 -#define DDRSS3_PHY_260_DATA 0x00000000 -#define DDRSS3_PHY_261_DATA 0x01030000 -#define DDRSS3_PHY_262_DATA 0x00010000 -#define DDRSS3_PHY_263_DATA 0x01030004 -#define DDRSS3_PHY_264_DATA 0x01000000 -#define DDRSS3_PHY_265_DATA 0x00000000 -#define DDRSS3_PHY_266_DATA 0x00000000 -#define DDRSS3_PHY_267_DATA 0x01000001 -#define DDRSS3_PHY_268_DATA 0x00000100 -#define DDRSS3_PHY_269_DATA 0x000800C0 -#define DDRSS3_PHY_270_DATA 0x060100CC -#define DDRSS3_PHY_271_DATA 0x00030066 -#define DDRSS3_PHY_272_DATA 0x00000000 -#define DDRSS3_PHY_273_DATA 0x00000301 -#define DDRSS3_PHY_274_DATA 0x0000AAAA -#define DDRSS3_PHY_275_DATA 0x00005555 -#define DDRSS3_PHY_276_DATA 0x0000B5B5 -#define DDRSS3_PHY_277_DATA 0x00004A4A -#define DDRSS3_PHY_278_DATA 0x00005656 -#define DDRSS3_PHY_279_DATA 0x0000A9A9 -#define DDRSS3_PHY_280_DATA 0x0000A9A9 -#define DDRSS3_PHY_281_DATA 0x0000B5B5 -#define DDRSS3_PHY_282_DATA 0x00000000 -#define DDRSS3_PHY_283_DATA 0x00000000 -#define DDRSS3_PHY_284_DATA 0x2A000000 -#define DDRSS3_PHY_285_DATA 0x00000808 -#define DDRSS3_PHY_286_DATA 0x0F000000 -#define DDRSS3_PHY_287_DATA 0x00000F0F -#define DDRSS3_PHY_288_DATA 0x10400000 -#define DDRSS3_PHY_289_DATA 0x0C002006 -#define DDRSS3_PHY_290_DATA 0x00000000 -#define DDRSS3_PHY_291_DATA 0x00000000 -#define DDRSS3_PHY_292_DATA 0x55555555 -#define DDRSS3_PHY_293_DATA 0xAAAAAAAA -#define DDRSS3_PHY_294_DATA 0x55555555 -#define DDRSS3_PHY_295_DATA 0xAAAAAAAA -#define DDRSS3_PHY_296_DATA 0x00005555 -#define DDRSS3_PHY_297_DATA 0x01000100 -#define DDRSS3_PHY_298_DATA 0x00800180 -#define DDRSS3_PHY_299_DATA 0x00000000 -#define DDRSS3_PHY_300_DATA 0x00000000 -#define DDRSS3_PHY_301_DATA 0x00000000 -#define DDRSS3_PHY_302_DATA 0x00000000 -#define DDRSS3_PHY_303_DATA 0x00000000 -#define DDRSS3_PHY_304_DATA 0x00000000 -#define DDRSS3_PHY_305_DATA 0x00000000 -#define DDRSS3_PHY_306_DATA 0x00000000 -#define DDRSS3_PHY_307_DATA 0x00000000 -#define DDRSS3_PHY_308_DATA 0x00000000 -#define DDRSS3_PHY_309_DATA 0x00000000 -#define DDRSS3_PHY_310_DATA 0x00000000 -#define DDRSS3_PHY_311_DATA 0x00000000 -#define DDRSS3_PHY_312_DATA 0x00000000 -#define DDRSS3_PHY_313_DATA 0x00000000 -#define DDRSS3_PHY_314_DATA 0x00000000 -#define DDRSS3_PHY_315_DATA 0x00000000 -#define DDRSS3_PHY_316_DATA 0x00000000 -#define DDRSS3_PHY_317_DATA 0x00000000 -#define DDRSS3_PHY_318_DATA 0x00000000 -#define DDRSS3_PHY_319_DATA 0x00000000 -#define DDRSS3_PHY_320_DATA 0x00000000 -#define DDRSS3_PHY_321_DATA 0x00000000 -#define DDRSS3_PHY_322_DATA 0x00000104 -#define DDRSS3_PHY_323_DATA 0x00000120 -#define DDRSS3_PHY_324_DATA 0x00000000 -#define DDRSS3_PHY_325_DATA 0x00000000 -#define DDRSS3_PHY_326_DATA 0x00000000 -#define DDRSS3_PHY_327_DATA 0x00000000 -#define DDRSS3_PHY_328_DATA 0x00000000 -#define DDRSS3_PHY_329_DATA 0x00000000 -#define DDRSS3_PHY_330_DATA 0x00000000 -#define DDRSS3_PHY_331_DATA 0x00000001 -#define DDRSS3_PHY_332_DATA 0x07FF0000 -#define DDRSS3_PHY_333_DATA 0x0080081F -#define DDRSS3_PHY_334_DATA 0x00081020 -#define DDRSS3_PHY_335_DATA 0x04010000 -#define DDRSS3_PHY_336_DATA 0x00000000 -#define DDRSS3_PHY_337_DATA 0x00000000 -#define DDRSS3_PHY_338_DATA 0x00000000 -#define DDRSS3_PHY_339_DATA 0x00000100 -#define DDRSS3_PHY_340_DATA 0x01CC0C01 -#define DDRSS3_PHY_341_DATA 0x1003CC0C -#define DDRSS3_PHY_342_DATA 0x20000140 -#define DDRSS3_PHY_343_DATA 0x07FF0200 -#define DDRSS3_PHY_344_DATA 0x0000DD01 -#define DDRSS3_PHY_345_DATA 0x10100303 -#define DDRSS3_PHY_346_DATA 0x10101010 -#define DDRSS3_PHY_347_DATA 0x10101010 -#define DDRSS3_PHY_348_DATA 0x00021010 -#define DDRSS3_PHY_349_DATA 0x00100010 -#define DDRSS3_PHY_350_DATA 0x00100010 -#define DDRSS3_PHY_351_DATA 0x00100010 -#define DDRSS3_PHY_352_DATA 0x00100010 -#define DDRSS3_PHY_353_DATA 0x00050010 -#define DDRSS3_PHY_354_DATA 0x51517041 -#define DDRSS3_PHY_355_DATA 0x31C06001 -#define DDRSS3_PHY_356_DATA 0x07AB0340 -#define DDRSS3_PHY_357_DATA 0x00C0C001 -#define DDRSS3_PHY_358_DATA 0x0E0D0001 -#define DDRSS3_PHY_359_DATA 0x10001000 -#define DDRSS3_PHY_360_DATA 0x0C083E42 -#define DDRSS3_PHY_361_DATA 0x0F0C3701 -#define DDRSS3_PHY_362_DATA 0x01000140 -#define DDRSS3_PHY_363_DATA 0x0C000420 -#define DDRSS3_PHY_364_DATA 0x00000198 -#define DDRSS3_PHY_365_DATA 0x0A0000D0 -#define DDRSS3_PHY_366_DATA 0x00030200 -#define DDRSS3_PHY_367_DATA 0x02800000 -#define DDRSS3_PHY_368_DATA 0x80800000 -#define DDRSS3_PHY_369_DATA 0x000E2010 -#define DDRSS3_PHY_370_DATA 0x76543210 -#define DDRSS3_PHY_371_DATA 0x00000008 -#define DDRSS3_PHY_372_DATA 0x02800280 -#define DDRSS3_PHY_373_DATA 0x02800280 -#define DDRSS3_PHY_374_DATA 0x02800280 -#define DDRSS3_PHY_375_DATA 0x02800280 -#define DDRSS3_PHY_376_DATA 0x00000280 -#define DDRSS3_PHY_377_DATA 0x0000A000 -#define DDRSS3_PHY_378_DATA 0x00A000A0 -#define DDRSS3_PHY_379_DATA 0x00A000A0 -#define DDRSS3_PHY_380_DATA 0x00A000A0 -#define DDRSS3_PHY_381_DATA 0x00A000A0 -#define DDRSS3_PHY_382_DATA 0x00A000A0 -#define DDRSS3_PHY_383_DATA 0x00A000A0 -#define DDRSS3_PHY_384_DATA 0x00A000A0 -#define DDRSS3_PHY_385_DATA 0x00A000A0 -#define DDRSS3_PHY_386_DATA 0x01C200A0 -#define DDRSS3_PHY_387_DATA 0x01A00005 -#define DDRSS3_PHY_388_DATA 0x00000000 -#define DDRSS3_PHY_389_DATA 0x00000000 -#define DDRSS3_PHY_390_DATA 0x00080200 -#define DDRSS3_PHY_391_DATA 0x00000000 -#define DDRSS3_PHY_392_DATA 0x20202000 -#define DDRSS3_PHY_393_DATA 0x20202020 -#define DDRSS3_PHY_394_DATA 0xF0F02020 -#define DDRSS3_PHY_395_DATA 0x00000000 -#define DDRSS3_PHY_396_DATA 0x00000000 -#define DDRSS3_PHY_397_DATA 0x00000000 -#define DDRSS3_PHY_398_DATA 0x00000000 -#define DDRSS3_PHY_399_DATA 0x00000000 -#define DDRSS3_PHY_400_DATA 0x00000000 -#define DDRSS3_PHY_401_DATA 0x00000000 -#define DDRSS3_PHY_402_DATA 0x00000000 -#define DDRSS3_PHY_403_DATA 0x00000000 -#define DDRSS3_PHY_404_DATA 0x00000000 -#define DDRSS3_PHY_405_DATA 0x00000000 -#define DDRSS3_PHY_406_DATA 0x00000000 -#define DDRSS3_PHY_407_DATA 0x00000000 -#define DDRSS3_PHY_408_DATA 0x00000000 -#define DDRSS3_PHY_409_DATA 0x00000000 -#define DDRSS3_PHY_410_DATA 0x00000000 -#define DDRSS3_PHY_411_DATA 0x00000000 -#define DDRSS3_PHY_412_DATA 0x00000000 -#define DDRSS3_PHY_413_DATA 0x00000000 -#define DDRSS3_PHY_414_DATA 0x00000000 -#define DDRSS3_PHY_415_DATA 0x00000000 -#define DDRSS3_PHY_416_DATA 0x00000000 -#define DDRSS3_PHY_417_DATA 0x00000000 -#define DDRSS3_PHY_418_DATA 0x00000000 -#define DDRSS3_PHY_419_DATA 0x00000000 -#define DDRSS3_PHY_420_DATA 0x00000000 -#define DDRSS3_PHY_421_DATA 0x00000000 -#define DDRSS3_PHY_422_DATA 0x00000000 -#define DDRSS3_PHY_423_DATA 0x00000000 -#define DDRSS3_PHY_424_DATA 0x00000000 -#define DDRSS3_PHY_425_DATA 0x00000000 -#define DDRSS3_PHY_426_DATA 0x00000000 -#define DDRSS3_PHY_427_DATA 0x00000000 -#define DDRSS3_PHY_428_DATA 0x00000000 -#define DDRSS3_PHY_429_DATA 0x00000000 -#define DDRSS3_PHY_430_DATA 0x00000000 -#define DDRSS3_PHY_431_DATA 0x00000000 -#define DDRSS3_PHY_432_DATA 0x00000000 -#define DDRSS3_PHY_433_DATA 0x00000000 -#define DDRSS3_PHY_434_DATA 0x00000000 -#define DDRSS3_PHY_435_DATA 0x00000000 -#define DDRSS3_PHY_436_DATA 0x00000000 -#define DDRSS3_PHY_437_DATA 0x00000000 -#define DDRSS3_PHY_438_DATA 0x00000000 -#define DDRSS3_PHY_439_DATA 0x00000000 -#define DDRSS3_PHY_440_DATA 0x00000000 -#define DDRSS3_PHY_441_DATA 0x00000000 -#define DDRSS3_PHY_442_DATA 0x00000000 -#define DDRSS3_PHY_443_DATA 0x00000000 -#define DDRSS3_PHY_444_DATA 0x00000000 -#define DDRSS3_PHY_445_DATA 0x00000000 -#define DDRSS3_PHY_446_DATA 0x00000000 -#define DDRSS3_PHY_447_DATA 0x00000000 -#define DDRSS3_PHY_448_DATA 0x00000000 -#define DDRSS3_PHY_449_DATA 0x00000000 -#define DDRSS3_PHY_450_DATA 0x00000000 -#define DDRSS3_PHY_451_DATA 0x00000000 -#define DDRSS3_PHY_452_DATA 0x00000000 -#define DDRSS3_PHY_453_DATA 0x00000000 -#define DDRSS3_PHY_454_DATA 0x00000000 -#define DDRSS3_PHY_455_DATA 0x00000000 -#define DDRSS3_PHY_456_DATA 0x00000000 -#define DDRSS3_PHY_457_DATA 0x00000000 -#define DDRSS3_PHY_458_DATA 0x00000000 -#define DDRSS3_PHY_459_DATA 0x00000000 -#define DDRSS3_PHY_460_DATA 0x00000000 -#define DDRSS3_PHY_461_DATA 0x00000000 -#define DDRSS3_PHY_462_DATA 0x00000000 -#define DDRSS3_PHY_463_DATA 0x00000000 -#define DDRSS3_PHY_464_DATA 0x00000000 -#define DDRSS3_PHY_465_DATA 0x00000000 -#define DDRSS3_PHY_466_DATA 0x00000000 -#define DDRSS3_PHY_467_DATA 0x00000000 -#define DDRSS3_PHY_468_DATA 0x00000000 -#define DDRSS3_PHY_469_DATA 0x00000000 -#define DDRSS3_PHY_470_DATA 0x00000000 -#define DDRSS3_PHY_471_DATA 0x00000000 -#define DDRSS3_PHY_472_DATA 0x00000000 -#define DDRSS3_PHY_473_DATA 0x00000000 -#define DDRSS3_PHY_474_DATA 0x00000000 -#define DDRSS3_PHY_475_DATA 0x00000000 -#define DDRSS3_PHY_476_DATA 0x00000000 -#define DDRSS3_PHY_477_DATA 0x00000000 -#define DDRSS3_PHY_478_DATA 0x00000000 -#define DDRSS3_PHY_479_DATA 0x00000000 -#define DDRSS3_PHY_480_DATA 0x00000000 -#define DDRSS3_PHY_481_DATA 0x00000000 -#define DDRSS3_PHY_482_DATA 0x00000000 -#define DDRSS3_PHY_483_DATA 0x00000000 -#define DDRSS3_PHY_484_DATA 0x00000000 -#define DDRSS3_PHY_485_DATA 0x00000000 -#define DDRSS3_PHY_486_DATA 0x00000000 -#define DDRSS3_PHY_487_DATA 0x00000000 -#define DDRSS3_PHY_488_DATA 0x00000000 -#define DDRSS3_PHY_489_DATA 0x00000000 -#define DDRSS3_PHY_490_DATA 0x00000000 -#define DDRSS3_PHY_491_DATA 0x00000000 -#define DDRSS3_PHY_492_DATA 0x00000000 -#define DDRSS3_PHY_493_DATA 0x00000000 -#define DDRSS3_PHY_494_DATA 0x00000000 -#define DDRSS3_PHY_495_DATA 0x00000000 -#define DDRSS3_PHY_496_DATA 0x00000000 -#define DDRSS3_PHY_497_DATA 0x00000000 -#define DDRSS3_PHY_498_DATA 0x00000000 -#define DDRSS3_PHY_499_DATA 0x00000000 -#define DDRSS3_PHY_500_DATA 0x00000000 -#define DDRSS3_PHY_501_DATA 0x00000000 -#define DDRSS3_PHY_502_DATA 0x00000000 -#define DDRSS3_PHY_503_DATA 0x00000000 -#define DDRSS3_PHY_504_DATA 0x00000000 -#define DDRSS3_PHY_505_DATA 0x00000000 -#define DDRSS3_PHY_506_DATA 0x00000000 -#define DDRSS3_PHY_507_DATA 0x00000000 -#define DDRSS3_PHY_508_DATA 0x00000000 -#define DDRSS3_PHY_509_DATA 0x00000000 -#define DDRSS3_PHY_510_DATA 0x00000000 -#define DDRSS3_PHY_511_DATA 0x00000000 -#define DDRSS3_PHY_512_DATA 0x000004F0 -#define DDRSS3_PHY_513_DATA 0x00000000 -#define DDRSS3_PHY_514_DATA 0x00030200 -#define DDRSS3_PHY_515_DATA 0x00000000 -#define DDRSS3_PHY_516_DATA 0x00000000 -#define DDRSS3_PHY_517_DATA 0x01030000 -#define DDRSS3_PHY_518_DATA 0x00010000 -#define DDRSS3_PHY_519_DATA 0x01030004 -#define DDRSS3_PHY_520_DATA 0x01000000 -#define DDRSS3_PHY_521_DATA 0x00000000 -#define DDRSS3_PHY_522_DATA 0x00000000 -#define DDRSS3_PHY_523_DATA 0x01000001 -#define DDRSS3_PHY_524_DATA 0x00000100 -#define DDRSS3_PHY_525_DATA 0x000800C0 -#define DDRSS3_PHY_526_DATA 0x060100CC -#define DDRSS3_PHY_527_DATA 0x00030066 -#define DDRSS3_PHY_528_DATA 0x00000000 -#define DDRSS3_PHY_529_DATA 0x00000301 -#define DDRSS3_PHY_530_DATA 0x0000AAAA -#define DDRSS3_PHY_531_DATA 0x00005555 -#define DDRSS3_PHY_532_DATA 0x0000B5B5 -#define DDRSS3_PHY_533_DATA 0x00004A4A -#define DDRSS3_PHY_534_DATA 0x00005656 -#define DDRSS3_PHY_535_DATA 0x0000A9A9 -#define DDRSS3_PHY_536_DATA 0x0000A9A9 -#define DDRSS3_PHY_537_DATA 0x0000B5B5 -#define DDRSS3_PHY_538_DATA 0x00000000 -#define DDRSS3_PHY_539_DATA 0x00000000 -#define DDRSS3_PHY_540_DATA 0x2A000000 -#define DDRSS3_PHY_541_DATA 0x00000808 -#define DDRSS3_PHY_542_DATA 0x0F000000 -#define DDRSS3_PHY_543_DATA 0x00000F0F -#define DDRSS3_PHY_544_DATA 0x10400000 -#define DDRSS3_PHY_545_DATA 0x0C002006 -#define DDRSS3_PHY_546_DATA 0x00000000 -#define DDRSS3_PHY_547_DATA 0x00000000 -#define DDRSS3_PHY_548_DATA 0x55555555 -#define DDRSS3_PHY_549_DATA 0xAAAAAAAA -#define DDRSS3_PHY_550_DATA 0x55555555 -#define DDRSS3_PHY_551_DATA 0xAAAAAAAA -#define DDRSS3_PHY_552_DATA 0x00005555 -#define DDRSS3_PHY_553_DATA 0x01000100 -#define DDRSS3_PHY_554_DATA 0x00800180 -#define DDRSS3_PHY_555_DATA 0x00000001 -#define DDRSS3_PHY_556_DATA 0x00000000 -#define DDRSS3_PHY_557_DATA 0x00000000 -#define DDRSS3_PHY_558_DATA 0x00000000 -#define DDRSS3_PHY_559_DATA 0x00000000 -#define DDRSS3_PHY_560_DATA 0x00000000 -#define DDRSS3_PHY_561_DATA 0x00000000 -#define DDRSS3_PHY_562_DATA 0x00000000 -#define DDRSS3_PHY_563_DATA 0x00000000 -#define DDRSS3_PHY_564_DATA 0x00000000 -#define DDRSS3_PHY_565_DATA 0x00000000 -#define DDRSS3_PHY_566_DATA 0x00000000 -#define DDRSS3_PHY_567_DATA 0x00000000 -#define DDRSS3_PHY_568_DATA 0x00000000 -#define DDRSS3_PHY_569_DATA 0x00000000 -#define DDRSS3_PHY_570_DATA 0x00000000 -#define DDRSS3_PHY_571_DATA 0x00000000 -#define DDRSS3_PHY_572_DATA 0x00000000 -#define DDRSS3_PHY_573_DATA 0x00000000 -#define DDRSS3_PHY_574_DATA 0x00000000 -#define DDRSS3_PHY_575_DATA 0x00000000 -#define DDRSS3_PHY_576_DATA 0x00000000 -#define DDRSS3_PHY_577_DATA 0x00000000 -#define DDRSS3_PHY_578_DATA 0x00000104 -#define DDRSS3_PHY_579_DATA 0x00000120 -#define DDRSS3_PHY_580_DATA 0x00000000 -#define DDRSS3_PHY_581_DATA 0x00000000 -#define DDRSS3_PHY_582_DATA 0x00000000 -#define DDRSS3_PHY_583_DATA 0x00000000 -#define DDRSS3_PHY_584_DATA 0x00000000 -#define DDRSS3_PHY_585_DATA 0x00000000 -#define DDRSS3_PHY_586_DATA 0x00000000 -#define DDRSS3_PHY_587_DATA 0x00000001 -#define DDRSS3_PHY_588_DATA 0x07FF0000 -#define DDRSS3_PHY_589_DATA 0x0080081F -#define DDRSS3_PHY_590_DATA 0x00081020 -#define DDRSS3_PHY_591_DATA 0x04010000 -#define DDRSS3_PHY_592_DATA 0x00000000 -#define DDRSS3_PHY_593_DATA 0x00000000 -#define DDRSS3_PHY_594_DATA 0x00000000 -#define DDRSS3_PHY_595_DATA 0x00000100 -#define DDRSS3_PHY_596_DATA 0x01CC0C01 -#define DDRSS3_PHY_597_DATA 0x1003CC0C -#define DDRSS3_PHY_598_DATA 0x20000140 -#define DDRSS3_PHY_599_DATA 0x07FF0200 -#define DDRSS3_PHY_600_DATA 0x0000DD01 -#define DDRSS3_PHY_601_DATA 0x10100303 -#define DDRSS3_PHY_602_DATA 0x10101010 -#define DDRSS3_PHY_603_DATA 0x10101010 -#define DDRSS3_PHY_604_DATA 0x00021010 -#define DDRSS3_PHY_605_DATA 0x00100010 -#define DDRSS3_PHY_606_DATA 0x00100010 -#define DDRSS3_PHY_607_DATA 0x00100010 -#define DDRSS3_PHY_608_DATA 0x00100010 -#define DDRSS3_PHY_609_DATA 0x00050010 -#define DDRSS3_PHY_610_DATA 0x51517041 -#define DDRSS3_PHY_611_DATA 0x31C06001 -#define DDRSS3_PHY_612_DATA 0x07AB0340 -#define DDRSS3_PHY_613_DATA 0x00C0C001 -#define DDRSS3_PHY_614_DATA 0x0E0D0001 -#define DDRSS3_PHY_615_DATA 0x10001000 -#define DDRSS3_PHY_616_DATA 0x0C083E42 -#define DDRSS3_PHY_617_DATA 0x0F0C3701 -#define DDRSS3_PHY_618_DATA 0x01000140 -#define DDRSS3_PHY_619_DATA 0x0C000420 -#define DDRSS3_PHY_620_DATA 0x00000198 -#define DDRSS3_PHY_621_DATA 0x0A0000D0 -#define DDRSS3_PHY_622_DATA 0x00030200 -#define DDRSS3_PHY_623_DATA 0x02800000 -#define DDRSS3_PHY_624_DATA 0x80800000 -#define DDRSS3_PHY_625_DATA 0x000E2010 -#define DDRSS3_PHY_626_DATA 0x76543210 -#define DDRSS3_PHY_627_DATA 0x00000008 -#define DDRSS3_PHY_628_DATA 0x02800280 -#define DDRSS3_PHY_629_DATA 0x02800280 -#define DDRSS3_PHY_630_DATA 0x02800280 -#define DDRSS3_PHY_631_DATA 0x02800280 -#define DDRSS3_PHY_632_DATA 0x00000280 -#define DDRSS3_PHY_633_DATA 0x0000A000 -#define DDRSS3_PHY_634_DATA 0x00A000A0 -#define DDRSS3_PHY_635_DATA 0x00A000A0 -#define DDRSS3_PHY_636_DATA 0x00A000A0 -#define DDRSS3_PHY_637_DATA 0x00A000A0 -#define DDRSS3_PHY_638_DATA 0x00A000A0 -#define DDRSS3_PHY_639_DATA 0x00A000A0 -#define DDRSS3_PHY_640_DATA 0x00A000A0 -#define DDRSS3_PHY_641_DATA 0x00A000A0 -#define DDRSS3_PHY_642_DATA 0x01C200A0 -#define DDRSS3_PHY_643_DATA 0x01A00005 -#define DDRSS3_PHY_644_DATA 0x00000000 -#define DDRSS3_PHY_645_DATA 0x00000000 -#define DDRSS3_PHY_646_DATA 0x00080200 -#define DDRSS3_PHY_647_DATA 0x00000000 -#define DDRSS3_PHY_648_DATA 0x20202000 -#define DDRSS3_PHY_649_DATA 0x20202020 -#define DDRSS3_PHY_650_DATA 0xF0F02020 -#define DDRSS3_PHY_651_DATA 0x00000000 -#define DDRSS3_PHY_652_DATA 0x00000000 -#define DDRSS3_PHY_653_DATA 0x00000000 -#define DDRSS3_PHY_654_DATA 0x00000000 -#define DDRSS3_PHY_655_DATA 0x00000000 -#define DDRSS3_PHY_656_DATA 0x00000000 -#define DDRSS3_PHY_657_DATA 0x00000000 -#define DDRSS3_PHY_658_DATA 0x00000000 -#define DDRSS3_PHY_659_DATA 0x00000000 -#define DDRSS3_PHY_660_DATA 0x00000000 -#define DDRSS3_PHY_661_DATA 0x00000000 -#define DDRSS3_PHY_662_DATA 0x00000000 -#define DDRSS3_PHY_663_DATA 0x00000000 -#define DDRSS3_PHY_664_DATA 0x00000000 -#define DDRSS3_PHY_665_DATA 0x00000000 -#define DDRSS3_PHY_666_DATA 0x00000000 -#define DDRSS3_PHY_667_DATA 0x00000000 -#define DDRSS3_PHY_668_DATA 0x00000000 -#define DDRSS3_PHY_669_DATA 0x00000000 -#define DDRSS3_PHY_670_DATA 0x00000000 -#define DDRSS3_PHY_671_DATA 0x00000000 -#define DDRSS3_PHY_672_DATA 0x00000000 -#define DDRSS3_PHY_673_DATA 0x00000000 -#define DDRSS3_PHY_674_DATA 0x00000000 -#define DDRSS3_PHY_675_DATA 0x00000000 -#define DDRSS3_PHY_676_DATA 0x00000000 -#define DDRSS3_PHY_677_DATA 0x00000000 -#define DDRSS3_PHY_678_DATA 0x00000000 -#define DDRSS3_PHY_679_DATA 0x00000000 -#define DDRSS3_PHY_680_DATA 0x00000000 -#define DDRSS3_PHY_681_DATA 0x00000000 -#define DDRSS3_PHY_682_DATA 0x00000000 -#define DDRSS3_PHY_683_DATA 0x00000000 -#define DDRSS3_PHY_684_DATA 0x00000000 -#define DDRSS3_PHY_685_DATA 0x00000000 -#define DDRSS3_PHY_686_DATA 0x00000000 -#define DDRSS3_PHY_687_DATA 0x00000000 -#define DDRSS3_PHY_688_DATA 0x00000000 -#define DDRSS3_PHY_689_DATA 0x00000000 -#define DDRSS3_PHY_690_DATA 0x00000000 -#define DDRSS3_PHY_691_DATA 0x00000000 -#define DDRSS3_PHY_692_DATA 0x00000000 -#define DDRSS3_PHY_693_DATA 0x00000000 -#define DDRSS3_PHY_694_DATA 0x00000000 -#define DDRSS3_PHY_695_DATA 0x00000000 -#define DDRSS3_PHY_696_DATA 0x00000000 -#define DDRSS3_PHY_697_DATA 0x00000000 -#define DDRSS3_PHY_698_DATA 0x00000000 -#define DDRSS3_PHY_699_DATA 0x00000000 -#define DDRSS3_PHY_700_DATA 0x00000000 -#define DDRSS3_PHY_701_DATA 0x00000000 -#define DDRSS3_PHY_702_DATA 0x00000000 -#define DDRSS3_PHY_703_DATA 0x00000000 -#define DDRSS3_PHY_704_DATA 0x00000000 -#define DDRSS3_PHY_705_DATA 0x00000000 -#define DDRSS3_PHY_706_DATA 0x00000000 -#define DDRSS3_PHY_707_DATA 0x00000000 -#define DDRSS3_PHY_708_DATA 0x00000000 -#define DDRSS3_PHY_709_DATA 0x00000000 -#define DDRSS3_PHY_710_DATA 0x00000000 -#define DDRSS3_PHY_711_DATA 0x00000000 -#define DDRSS3_PHY_712_DATA 0x00000000 -#define DDRSS3_PHY_713_DATA 0x00000000 -#define DDRSS3_PHY_714_DATA 0x00000000 -#define DDRSS3_PHY_715_DATA 0x00000000 -#define DDRSS3_PHY_716_DATA 0x00000000 -#define DDRSS3_PHY_717_DATA 0x00000000 -#define DDRSS3_PHY_718_DATA 0x00000000 -#define DDRSS3_PHY_719_DATA 0x00000000 -#define DDRSS3_PHY_720_DATA 0x00000000 -#define DDRSS3_PHY_721_DATA 0x00000000 -#define DDRSS3_PHY_722_DATA 0x00000000 -#define DDRSS3_PHY_723_DATA 0x00000000 -#define DDRSS3_PHY_724_DATA 0x00000000 -#define DDRSS3_PHY_725_DATA 0x00000000 -#define DDRSS3_PHY_726_DATA 0x00000000 -#define DDRSS3_PHY_727_DATA 0x00000000 -#define DDRSS3_PHY_728_DATA 0x00000000 -#define DDRSS3_PHY_729_DATA 0x00000000 -#define DDRSS3_PHY_730_DATA 0x00000000 -#define DDRSS3_PHY_731_DATA 0x00000000 -#define DDRSS3_PHY_732_DATA 0x00000000 -#define DDRSS3_PHY_733_DATA 0x00000000 -#define DDRSS3_PHY_734_DATA 0x00000000 -#define DDRSS3_PHY_735_DATA 0x00000000 -#define DDRSS3_PHY_736_DATA 0x00000000 -#define DDRSS3_PHY_737_DATA 0x00000000 -#define DDRSS3_PHY_738_DATA 0x00000000 -#define DDRSS3_PHY_739_DATA 0x00000000 -#define DDRSS3_PHY_740_DATA 0x00000000 -#define DDRSS3_PHY_741_DATA 0x00000000 -#define DDRSS3_PHY_742_DATA 0x00000000 -#define DDRSS3_PHY_743_DATA 0x00000000 -#define DDRSS3_PHY_744_DATA 0x00000000 -#define DDRSS3_PHY_745_DATA 0x00000000 -#define DDRSS3_PHY_746_DATA 0x00000000 -#define DDRSS3_PHY_747_DATA 0x00000000 -#define DDRSS3_PHY_748_DATA 0x00000000 -#define DDRSS3_PHY_749_DATA 0x00000000 -#define DDRSS3_PHY_750_DATA 0x00000000 -#define DDRSS3_PHY_751_DATA 0x00000000 -#define DDRSS3_PHY_752_DATA 0x00000000 -#define DDRSS3_PHY_753_DATA 0x00000000 -#define DDRSS3_PHY_754_DATA 0x00000000 -#define DDRSS3_PHY_755_DATA 0x00000000 -#define DDRSS3_PHY_756_DATA 0x00000000 -#define DDRSS3_PHY_757_DATA 0x00000000 -#define DDRSS3_PHY_758_DATA 0x00000000 -#define DDRSS3_PHY_759_DATA 0x00000000 -#define DDRSS3_PHY_760_DATA 0x00000000 -#define DDRSS3_PHY_761_DATA 0x00000000 -#define DDRSS3_PHY_762_DATA 0x00000000 -#define DDRSS3_PHY_763_DATA 0x00000000 -#define DDRSS3_PHY_764_DATA 0x00000000 -#define DDRSS3_PHY_765_DATA 0x00000000 -#define DDRSS3_PHY_766_DATA 0x00000000 -#define DDRSS3_PHY_767_DATA 0x00000000 -#define DDRSS3_PHY_768_DATA 0x000004F0 -#define DDRSS3_PHY_769_DATA 0x00000000 -#define DDRSS3_PHY_770_DATA 0x00030200 -#define DDRSS3_PHY_771_DATA 0x00000000 -#define DDRSS3_PHY_772_DATA 0x00000000 -#define DDRSS3_PHY_773_DATA 0x01030000 -#define DDRSS3_PHY_774_DATA 0x00010000 -#define DDRSS3_PHY_775_DATA 0x01030004 -#define DDRSS3_PHY_776_DATA 0x01000000 -#define DDRSS3_PHY_777_DATA 0x00000000 -#define DDRSS3_PHY_778_DATA 0x00000000 -#define DDRSS3_PHY_779_DATA 0x01000001 -#define DDRSS3_PHY_780_DATA 0x00000100 -#define DDRSS3_PHY_781_DATA 0x000800C0 -#define DDRSS3_PHY_782_DATA 0x060100CC -#define DDRSS3_PHY_783_DATA 0x00030066 -#define DDRSS3_PHY_784_DATA 0x00000000 -#define DDRSS3_PHY_785_DATA 0x00000301 -#define DDRSS3_PHY_786_DATA 0x0000AAAA -#define DDRSS3_PHY_787_DATA 0x00005555 -#define DDRSS3_PHY_788_DATA 0x0000B5B5 -#define DDRSS3_PHY_789_DATA 0x00004A4A -#define DDRSS3_PHY_790_DATA 0x00005656 -#define DDRSS3_PHY_791_DATA 0x0000A9A9 -#define DDRSS3_PHY_792_DATA 0x0000A9A9 -#define DDRSS3_PHY_793_DATA 0x0000B5B5 -#define DDRSS3_PHY_794_DATA 0x00000000 -#define DDRSS3_PHY_795_DATA 0x00000000 -#define DDRSS3_PHY_796_DATA 0x2A000000 -#define DDRSS3_PHY_797_DATA 0x00000808 -#define DDRSS3_PHY_798_DATA 0x0F000000 -#define DDRSS3_PHY_799_DATA 0x00000F0F -#define DDRSS3_PHY_800_DATA 0x10400000 -#define DDRSS3_PHY_801_DATA 0x0C002006 -#define DDRSS3_PHY_802_DATA 0x00000000 -#define DDRSS3_PHY_803_DATA 0x00000000 -#define DDRSS3_PHY_804_DATA 0x55555555 -#define DDRSS3_PHY_805_DATA 0xAAAAAAAA -#define DDRSS3_PHY_806_DATA 0x55555555 -#define DDRSS3_PHY_807_DATA 0xAAAAAAAA -#define DDRSS3_PHY_808_DATA 0x00005555 -#define DDRSS3_PHY_809_DATA 0x01000100 -#define DDRSS3_PHY_810_DATA 0x00800180 -#define DDRSS3_PHY_811_DATA 0x00000000 -#define DDRSS3_PHY_812_DATA 0x00000000 -#define DDRSS3_PHY_813_DATA 0x00000000 -#define DDRSS3_PHY_814_DATA 0x00000000 -#define DDRSS3_PHY_815_DATA 0x00000000 -#define DDRSS3_PHY_816_DATA 0x00000000 -#define DDRSS3_PHY_817_DATA 0x00000000 -#define DDRSS3_PHY_818_DATA 0x00000000 -#define DDRSS3_PHY_819_DATA 0x00000000 -#define DDRSS3_PHY_820_DATA 0x00000000 -#define DDRSS3_PHY_821_DATA 0x00000000 -#define DDRSS3_PHY_822_DATA 0x00000000 -#define DDRSS3_PHY_823_DATA 0x00000000 -#define DDRSS3_PHY_824_DATA 0x00000000 -#define DDRSS3_PHY_825_DATA 0x00000000 -#define DDRSS3_PHY_826_DATA 0x00000000 -#define DDRSS3_PHY_827_DATA 0x00000000 -#define DDRSS3_PHY_828_DATA 0x00000000 -#define DDRSS3_PHY_829_DATA 0x00000000 -#define DDRSS3_PHY_830_DATA 0x00000000 -#define DDRSS3_PHY_831_DATA 0x00000000 -#define DDRSS3_PHY_832_DATA 0x00000000 -#define DDRSS3_PHY_833_DATA 0x00000000 -#define DDRSS3_PHY_834_DATA 0x00000104 -#define DDRSS3_PHY_835_DATA 0x00000120 -#define DDRSS3_PHY_836_DATA 0x00000000 -#define DDRSS3_PHY_837_DATA 0x00000000 -#define DDRSS3_PHY_838_DATA 0x00000000 -#define DDRSS3_PHY_839_DATA 0x00000000 -#define DDRSS3_PHY_840_DATA 0x00000000 -#define DDRSS3_PHY_841_DATA 0x00000000 -#define DDRSS3_PHY_842_DATA 0x00000000 -#define DDRSS3_PHY_843_DATA 0x00000001 -#define DDRSS3_PHY_844_DATA 0x07FF0000 -#define DDRSS3_PHY_845_DATA 0x0080081F -#define DDRSS3_PHY_846_DATA 0x00081020 -#define DDRSS3_PHY_847_DATA 0x04010000 -#define DDRSS3_PHY_848_DATA 0x00000000 -#define DDRSS3_PHY_849_DATA 0x00000000 -#define DDRSS3_PHY_850_DATA 0x00000000 -#define DDRSS3_PHY_851_DATA 0x00000100 -#define DDRSS3_PHY_852_DATA 0x01CC0C01 -#define DDRSS3_PHY_853_DATA 0x1003CC0C -#define DDRSS3_PHY_854_DATA 0x20000140 -#define DDRSS3_PHY_855_DATA 0x07FF0200 -#define DDRSS3_PHY_856_DATA 0x0000DD01 -#define DDRSS3_PHY_857_DATA 0x10100303 -#define DDRSS3_PHY_858_DATA 0x10101010 -#define DDRSS3_PHY_859_DATA 0x10101010 -#define DDRSS3_PHY_860_DATA 0x00021010 -#define DDRSS3_PHY_861_DATA 0x00100010 -#define DDRSS3_PHY_862_DATA 0x00100010 -#define DDRSS3_PHY_863_DATA 0x00100010 -#define DDRSS3_PHY_864_DATA 0x00100010 -#define DDRSS3_PHY_865_DATA 0x00050010 -#define DDRSS3_PHY_866_DATA 0x51517041 -#define DDRSS3_PHY_867_DATA 0x31C06001 -#define DDRSS3_PHY_868_DATA 0x07AB0340 -#define DDRSS3_PHY_869_DATA 0x00C0C001 -#define DDRSS3_PHY_870_DATA 0x0E0D0001 -#define DDRSS3_PHY_871_DATA 0x10001000 -#define DDRSS3_PHY_872_DATA 0x0C083E42 -#define DDRSS3_PHY_873_DATA 0x0F0C3701 -#define DDRSS3_PHY_874_DATA 0x01000140 -#define DDRSS3_PHY_875_DATA 0x0C000420 -#define DDRSS3_PHY_876_DATA 0x00000198 -#define DDRSS3_PHY_877_DATA 0x0A0000D0 -#define DDRSS3_PHY_878_DATA 0x00030200 -#define DDRSS3_PHY_879_DATA 0x02800000 -#define DDRSS3_PHY_880_DATA 0x80800000 -#define DDRSS3_PHY_881_DATA 0x000E2010 -#define DDRSS3_PHY_882_DATA 0x76543210 -#define DDRSS3_PHY_883_DATA 0x00000008 -#define DDRSS3_PHY_884_DATA 0x02800280 -#define DDRSS3_PHY_885_DATA 0x02800280 -#define DDRSS3_PHY_886_DATA 0x02800280 -#define DDRSS3_PHY_887_DATA 0x02800280 -#define DDRSS3_PHY_888_DATA 0x00000280 -#define DDRSS3_PHY_889_DATA 0x0000A000 -#define DDRSS3_PHY_890_DATA 0x00A000A0 -#define DDRSS3_PHY_891_DATA 0x00A000A0 -#define DDRSS3_PHY_892_DATA 0x00A000A0 -#define DDRSS3_PHY_893_DATA 0x00A000A0 -#define DDRSS3_PHY_894_DATA 0x00A000A0 -#define DDRSS3_PHY_895_DATA 0x00A000A0 -#define DDRSS3_PHY_896_DATA 0x00A000A0 -#define DDRSS3_PHY_897_DATA 0x00A000A0 -#define DDRSS3_PHY_898_DATA 0x01C200A0 -#define DDRSS3_PHY_899_DATA 0x01A00005 -#define DDRSS3_PHY_900_DATA 0x00000000 -#define DDRSS3_PHY_901_DATA 0x00000000 -#define DDRSS3_PHY_902_DATA 0x00080200 -#define DDRSS3_PHY_903_DATA 0x00000000 -#define DDRSS3_PHY_904_DATA 0x20202000 -#define DDRSS3_PHY_905_DATA 0x20202020 -#define DDRSS3_PHY_906_DATA 0xF0F02020 -#define DDRSS3_PHY_907_DATA 0x00000000 -#define DDRSS3_PHY_908_DATA 0x00000000 -#define DDRSS3_PHY_909_DATA 0x00000000 -#define DDRSS3_PHY_910_DATA 0x00000000 -#define DDRSS3_PHY_911_DATA 0x00000000 -#define DDRSS3_PHY_912_DATA 0x00000000 -#define DDRSS3_PHY_913_DATA 0x00000000 -#define DDRSS3_PHY_914_DATA 0x00000000 -#define DDRSS3_PHY_915_DATA 0x00000000 -#define DDRSS3_PHY_916_DATA 0x00000000 -#define DDRSS3_PHY_917_DATA 0x00000000 -#define DDRSS3_PHY_918_DATA 0x00000000 -#define DDRSS3_PHY_919_DATA 0x00000000 -#define DDRSS3_PHY_920_DATA 0x00000000 -#define DDRSS3_PHY_921_DATA 0x00000000 -#define DDRSS3_PHY_922_DATA 0x00000000 -#define DDRSS3_PHY_923_DATA 0x00000000 -#define DDRSS3_PHY_924_DATA 0x00000000 -#define DDRSS3_PHY_925_DATA 0x00000000 -#define DDRSS3_PHY_926_DATA 0x00000000 -#define DDRSS3_PHY_927_DATA 0x00000000 -#define DDRSS3_PHY_928_DATA 0x00000000 -#define DDRSS3_PHY_929_DATA 0x00000000 -#define DDRSS3_PHY_930_DATA 0x00000000 -#define DDRSS3_PHY_931_DATA 0x00000000 -#define DDRSS3_PHY_932_DATA 0x00000000 -#define DDRSS3_PHY_933_DATA 0x00000000 -#define DDRSS3_PHY_934_DATA 0x00000000 -#define DDRSS3_PHY_935_DATA 0x00000000 -#define DDRSS3_PHY_936_DATA 0x00000000 -#define DDRSS3_PHY_937_DATA 0x00000000 -#define DDRSS3_PHY_938_DATA 0x00000000 -#define DDRSS3_PHY_939_DATA 0x00000000 -#define DDRSS3_PHY_940_DATA 0x00000000 -#define DDRSS3_PHY_941_DATA 0x00000000 -#define DDRSS3_PHY_942_DATA 0x00000000 -#define DDRSS3_PHY_943_DATA 0x00000000 -#define DDRSS3_PHY_944_DATA 0x00000000 -#define DDRSS3_PHY_945_DATA 0x00000000 -#define DDRSS3_PHY_946_DATA 0x00000000 -#define DDRSS3_PHY_947_DATA 0x00000000 -#define DDRSS3_PHY_948_DATA 0x00000000 -#define DDRSS3_PHY_949_DATA 0x00000000 -#define DDRSS3_PHY_950_DATA 0x00000000 -#define DDRSS3_PHY_951_DATA 0x00000000 -#define DDRSS3_PHY_952_DATA 0x00000000 -#define DDRSS3_PHY_953_DATA 0x00000000 -#define DDRSS3_PHY_954_DATA 0x00000000 -#define DDRSS3_PHY_955_DATA 0x00000000 -#define DDRSS3_PHY_956_DATA 0x00000000 -#define DDRSS3_PHY_957_DATA 0x00000000 -#define DDRSS3_PHY_958_DATA 0x00000000 -#define DDRSS3_PHY_959_DATA 0x00000000 -#define DDRSS3_PHY_960_DATA 0x00000000 -#define DDRSS3_PHY_961_DATA 0x00000000 -#define DDRSS3_PHY_962_DATA 0x00000000 -#define DDRSS3_PHY_963_DATA 0x00000000 -#define DDRSS3_PHY_964_DATA 0x00000000 -#define DDRSS3_PHY_965_DATA 0x00000000 -#define DDRSS3_PHY_966_DATA 0x00000000 -#define DDRSS3_PHY_967_DATA 0x00000000 -#define DDRSS3_PHY_968_DATA 0x00000000 -#define DDRSS3_PHY_969_DATA 0x00000000 -#define DDRSS3_PHY_970_DATA 0x00000000 -#define DDRSS3_PHY_971_DATA 0x00000000 -#define DDRSS3_PHY_972_DATA 0x00000000 -#define DDRSS3_PHY_973_DATA 0x00000000 -#define DDRSS3_PHY_974_DATA 0x00000000 -#define DDRSS3_PHY_975_DATA 0x00000000 -#define DDRSS3_PHY_976_DATA 0x00000000 -#define DDRSS3_PHY_977_DATA 0x00000000 -#define DDRSS3_PHY_978_DATA 0x00000000 -#define DDRSS3_PHY_979_DATA 0x00000000 -#define DDRSS3_PHY_980_DATA 0x00000000 -#define DDRSS3_PHY_981_DATA 0x00000000 -#define DDRSS3_PHY_982_DATA 0x00000000 -#define DDRSS3_PHY_983_DATA 0x00000000 -#define DDRSS3_PHY_984_DATA 0x00000000 -#define DDRSS3_PHY_985_DATA 0x00000000 -#define DDRSS3_PHY_986_DATA 0x00000000 -#define DDRSS3_PHY_987_DATA 0x00000000 -#define DDRSS3_PHY_988_DATA 0x00000000 -#define DDRSS3_PHY_989_DATA 0x00000000 -#define DDRSS3_PHY_990_DATA 0x00000000 -#define DDRSS3_PHY_991_DATA 0x00000000 -#define DDRSS3_PHY_992_DATA 0x00000000 -#define DDRSS3_PHY_993_DATA 0x00000000 -#define DDRSS3_PHY_994_DATA 0x00000000 -#define DDRSS3_PHY_995_DATA 0x00000000 -#define DDRSS3_PHY_996_DATA 0x00000000 -#define DDRSS3_PHY_997_DATA 0x00000000 -#define DDRSS3_PHY_998_DATA 0x00000000 -#define DDRSS3_PHY_999_DATA 0x00000000 -#define DDRSS3_PHY_1000_DATA 0x00000000 -#define DDRSS3_PHY_1001_DATA 0x00000000 -#define DDRSS3_PHY_1002_DATA 0x00000000 -#define DDRSS3_PHY_1003_DATA 0x00000000 -#define DDRSS3_PHY_1004_DATA 0x00000000 -#define DDRSS3_PHY_1005_DATA 0x00000000 -#define DDRSS3_PHY_1006_DATA 0x00000000 -#define DDRSS3_PHY_1007_DATA 0x00000000 -#define DDRSS3_PHY_1008_DATA 0x00000000 -#define DDRSS3_PHY_1009_DATA 0x00000000 -#define DDRSS3_PHY_1010_DATA 0x00000000 -#define DDRSS3_PHY_1011_DATA 0x00000000 -#define DDRSS3_PHY_1012_DATA 0x00000000 -#define DDRSS3_PHY_1013_DATA 0x00000000 -#define DDRSS3_PHY_1014_DATA 0x00000000 -#define DDRSS3_PHY_1015_DATA 0x00000000 -#define DDRSS3_PHY_1016_DATA 0x00000000 -#define DDRSS3_PHY_1017_DATA 0x00000000 -#define DDRSS3_PHY_1018_DATA 0x00000000 -#define DDRSS3_PHY_1019_DATA 0x00000000 -#define DDRSS3_PHY_1020_DATA 0x00000000 -#define DDRSS3_PHY_1021_DATA 0x00000000 -#define DDRSS3_PHY_1022_DATA 0x00000000 -#define DDRSS3_PHY_1023_DATA 0x00000000 -#define DDRSS3_PHY_1024_DATA 0x00000000 -#define DDRSS3_PHY_1025_DATA 0x00000000 -#define DDRSS3_PHY_1026_DATA 0x00000000 -#define DDRSS3_PHY_1027_DATA 0x00000000 -#define DDRSS3_PHY_1028_DATA 0x00000000 -#define DDRSS3_PHY_1029_DATA 0x00000100 -#define DDRSS3_PHY_1030_DATA 0x00000200 -#define DDRSS3_PHY_1031_DATA 0x00000000 -#define DDRSS3_PHY_1032_DATA 0x00000000 -#define DDRSS3_PHY_1033_DATA 0x00000000 -#define DDRSS3_PHY_1034_DATA 0x00000000 -#define DDRSS3_PHY_1035_DATA 0x00400000 -#define DDRSS3_PHY_1036_DATA 0x00000080 -#define DDRSS3_PHY_1037_DATA 0x00DCBA98 -#define DDRSS3_PHY_1038_DATA 0x03000000 -#define DDRSS3_PHY_1039_DATA 0x00200000 -#define DDRSS3_PHY_1040_DATA 0x00000000 -#define DDRSS3_PHY_1041_DATA 0x00000000 -#define DDRSS3_PHY_1042_DATA 0x00000000 -#define DDRSS3_PHY_1043_DATA 0x00000000 -#define DDRSS3_PHY_1044_DATA 0x00000000 -#define DDRSS3_PHY_1045_DATA 0x0000002A -#define DDRSS3_PHY_1046_DATA 0x00000015 -#define DDRSS3_PHY_1047_DATA 0x00000015 -#define DDRSS3_PHY_1048_DATA 0x0000002A -#define DDRSS3_PHY_1049_DATA 0x00000033 -#define DDRSS3_PHY_1050_DATA 0x0000000C -#define DDRSS3_PHY_1051_DATA 0x0000000C -#define DDRSS3_PHY_1052_DATA 0x00000033 -#define DDRSS3_PHY_1053_DATA 0x00543210 -#define DDRSS3_PHY_1054_DATA 0x003F0000 -#define DDRSS3_PHY_1055_DATA 0x000F013F -#define DDRSS3_PHY_1056_DATA 0x20202003 -#define DDRSS3_PHY_1057_DATA 0x00202020 -#define DDRSS3_PHY_1058_DATA 0x20008008 -#define DDRSS3_PHY_1059_DATA 0x00000810 -#define DDRSS3_PHY_1060_DATA 0x00000F00 -#define DDRSS3_PHY_1061_DATA 0x00000000 -#define DDRSS3_PHY_1062_DATA 0x00000000 -#define DDRSS3_PHY_1063_DATA 0x00000000 -#define DDRSS3_PHY_1064_DATA 0x000305CC -#define DDRSS3_PHY_1065_DATA 0x00030000 -#define DDRSS3_PHY_1066_DATA 0x00000300 -#define DDRSS3_PHY_1067_DATA 0x00000300 -#define DDRSS3_PHY_1068_DATA 0x00000300 -#define DDRSS3_PHY_1069_DATA 0x00000300 -#define DDRSS3_PHY_1070_DATA 0x00000300 -#define DDRSS3_PHY_1071_DATA 0x42080010 -#define DDRSS3_PHY_1072_DATA 0x0000803E -#define DDRSS3_PHY_1073_DATA 0x00000001 -#define DDRSS3_PHY_1074_DATA 0x01000102 -#define DDRSS3_PHY_1075_DATA 0x00008000 -#define DDRSS3_PHY_1076_DATA 0x00000000 -#define DDRSS3_PHY_1077_DATA 0x00000000 -#define DDRSS3_PHY_1078_DATA 0x00000000 -#define DDRSS3_PHY_1079_DATA 0x00000000 -#define DDRSS3_PHY_1080_DATA 0x00000000 -#define DDRSS3_PHY_1081_DATA 0x00000000 -#define DDRSS3_PHY_1082_DATA 0x00000000 -#define DDRSS3_PHY_1083_DATA 0x00000000 -#define DDRSS3_PHY_1084_DATA 0x00000000 -#define DDRSS3_PHY_1085_DATA 0x00000000 -#define DDRSS3_PHY_1086_DATA 0x00000000 -#define DDRSS3_PHY_1087_DATA 0x00000000 -#define DDRSS3_PHY_1088_DATA 0x00000000 -#define DDRSS3_PHY_1089_DATA 0x00000000 -#define DDRSS3_PHY_1090_DATA 0x00000000 -#define DDRSS3_PHY_1091_DATA 0x00000000 -#define DDRSS3_PHY_1092_DATA 0x00000000 -#define DDRSS3_PHY_1093_DATA 0x00000000 -#define DDRSS3_PHY_1094_DATA 0x00000000 -#define DDRSS3_PHY_1095_DATA 0x00000000 -#define DDRSS3_PHY_1096_DATA 0x00000000 -#define DDRSS3_PHY_1097_DATA 0x00000000 -#define DDRSS3_PHY_1098_DATA 0x00000000 -#define DDRSS3_PHY_1099_DATA 0x00000000 -#define DDRSS3_PHY_1100_DATA 0x00000000 -#define DDRSS3_PHY_1101_DATA 0x00000000 -#define DDRSS3_PHY_1102_DATA 0x00000000 -#define DDRSS3_PHY_1103_DATA 0x00000000 -#define DDRSS3_PHY_1104_DATA 0x00000000 -#define DDRSS3_PHY_1105_DATA 0x00000000 -#define DDRSS3_PHY_1106_DATA 0x00000000 -#define DDRSS3_PHY_1107_DATA 0x00000000 -#define DDRSS3_PHY_1108_DATA 0x00000000 -#define DDRSS3_PHY_1109_DATA 0x00000000 -#define DDRSS3_PHY_1110_DATA 0x00000000 -#define DDRSS3_PHY_1111_DATA 0x00000000 -#define DDRSS3_PHY_1112_DATA 0x00000000 -#define DDRSS3_PHY_1113_DATA 0x00000000 -#define DDRSS3_PHY_1114_DATA 0x00000000 -#define DDRSS3_PHY_1115_DATA 0x00000000 -#define DDRSS3_PHY_1116_DATA 0x00000000 -#define DDRSS3_PHY_1117_DATA 0x00000000 -#define DDRSS3_PHY_1118_DATA 0x00000000 -#define DDRSS3_PHY_1119_DATA 0x00000000 -#define DDRSS3_PHY_1120_DATA 0x00000000 -#define DDRSS3_PHY_1121_DATA 0x00000000 -#define DDRSS3_PHY_1122_DATA 0x00000000 -#define DDRSS3_PHY_1123_DATA 0x00000000 -#define DDRSS3_PHY_1124_DATA 0x00000000 -#define DDRSS3_PHY_1125_DATA 0x00000000 -#define DDRSS3_PHY_1126_DATA 0x00000000 -#define DDRSS3_PHY_1127_DATA 0x00000000 -#define DDRSS3_PHY_1128_DATA 0x00000000 -#define DDRSS3_PHY_1129_DATA 0x00000000 -#define DDRSS3_PHY_1130_DATA 0x00000000 -#define DDRSS3_PHY_1131_DATA 0x00000000 -#define DDRSS3_PHY_1132_DATA 0x00000000 -#define DDRSS3_PHY_1133_DATA 0x00000000 -#define DDRSS3_PHY_1134_DATA 0x00000000 -#define DDRSS3_PHY_1135_DATA 0x00000000 -#define DDRSS3_PHY_1136_DATA 0x00000000 -#define DDRSS3_PHY_1137_DATA 0x00000000 -#define DDRSS3_PHY_1138_DATA 0x00000000 -#define DDRSS3_PHY_1139_DATA 0x00000000 -#define DDRSS3_PHY_1140_DATA 0x00000000 -#define DDRSS3_PHY_1141_DATA 0x00000000 -#define DDRSS3_PHY_1142_DATA 0x00000000 -#define DDRSS3_PHY_1143_DATA 0x00000000 -#define DDRSS3_PHY_1144_DATA 0x00000000 -#define DDRSS3_PHY_1145_DATA 0x00000000 -#define DDRSS3_PHY_1146_DATA 0x00000000 -#define DDRSS3_PHY_1147_DATA 0x00000000 -#define DDRSS3_PHY_1148_DATA 0x00000000 -#define DDRSS3_PHY_1149_DATA 0x00000000 -#define DDRSS3_PHY_1150_DATA 0x00000000 -#define DDRSS3_PHY_1151_DATA 0x00000000 -#define DDRSS3_PHY_1152_DATA 0x00000000 -#define DDRSS3_PHY_1153_DATA 0x00000000 -#define DDRSS3_PHY_1154_DATA 0x00000000 -#define DDRSS3_PHY_1155_DATA 0x00000000 -#define DDRSS3_PHY_1156_DATA 0x00000000 -#define DDRSS3_PHY_1157_DATA 0x00000000 -#define DDRSS3_PHY_1158_DATA 0x00000000 -#define DDRSS3_PHY_1159_DATA 0x00000000 -#define DDRSS3_PHY_1160_DATA 0x00000000 -#define DDRSS3_PHY_1161_DATA 0x00000000 -#define DDRSS3_PHY_1162_DATA 0x00000000 -#define DDRSS3_PHY_1163_DATA 0x00000000 -#define DDRSS3_PHY_1164_DATA 0x00000000 -#define DDRSS3_PHY_1165_DATA 0x00000000 -#define DDRSS3_PHY_1166_DATA 0x00000000 -#define DDRSS3_PHY_1167_DATA 0x00000000 -#define DDRSS3_PHY_1168_DATA 0x00000000 -#define DDRSS3_PHY_1169_DATA 0x00000000 -#define DDRSS3_PHY_1170_DATA 0x00000000 -#define DDRSS3_PHY_1171_DATA 0x00000000 -#define DDRSS3_PHY_1172_DATA 0x00000000 -#define DDRSS3_PHY_1173_DATA 0x00000000 -#define DDRSS3_PHY_1174_DATA 0x00000000 -#define DDRSS3_PHY_1175_DATA 0x00000000 -#define DDRSS3_PHY_1176_DATA 0x00000000 -#define DDRSS3_PHY_1177_DATA 0x00000000 -#define DDRSS3_PHY_1178_DATA 0x00000000 -#define DDRSS3_PHY_1179_DATA 0x00000000 -#define DDRSS3_PHY_1180_DATA 0x00000000 -#define DDRSS3_PHY_1181_DATA 0x00000000 -#define DDRSS3_PHY_1182_DATA 0x00000000 -#define DDRSS3_PHY_1183_DATA 0x00000000 -#define DDRSS3_PHY_1184_DATA 0x00000000 -#define DDRSS3_PHY_1185_DATA 0x00000000 -#define DDRSS3_PHY_1186_DATA 0x00000000 -#define DDRSS3_PHY_1187_DATA 0x00000000 -#define DDRSS3_PHY_1188_DATA 0x00000000 -#define DDRSS3_PHY_1189_DATA 0x00000000 -#define DDRSS3_PHY_1190_DATA 0x00000000 -#define DDRSS3_PHY_1191_DATA 0x00000000 -#define DDRSS3_PHY_1192_DATA 0x00000000 -#define DDRSS3_PHY_1193_DATA 0x00000000 -#define DDRSS3_PHY_1194_DATA 0x00000000 -#define DDRSS3_PHY_1195_DATA 0x00000000 -#define DDRSS3_PHY_1196_DATA 0x00000000 -#define DDRSS3_PHY_1197_DATA 0x00000000 -#define DDRSS3_PHY_1198_DATA 0x00000000 -#define DDRSS3_PHY_1199_DATA 0x00000000 -#define DDRSS3_PHY_1200_DATA 0x00000000 -#define DDRSS3_PHY_1201_DATA 0x00000000 -#define DDRSS3_PHY_1202_DATA 0x00000000 -#define DDRSS3_PHY_1203_DATA 0x00000000 -#define DDRSS3_PHY_1204_DATA 0x00000000 -#define DDRSS3_PHY_1205_DATA 0x00000000 -#define DDRSS3_PHY_1206_DATA 0x00000000 -#define DDRSS3_PHY_1207_DATA 0x00000000 -#define DDRSS3_PHY_1208_DATA 0x00000000 -#define DDRSS3_PHY_1209_DATA 0x00000000 -#define DDRSS3_PHY_1210_DATA 0x00000000 -#define DDRSS3_PHY_1211_DATA 0x00000000 -#define DDRSS3_PHY_1212_DATA 0x00000000 -#define DDRSS3_PHY_1213_DATA 0x00000000 -#define DDRSS3_PHY_1214_DATA 0x00000000 -#define DDRSS3_PHY_1215_DATA 0x00000000 -#define DDRSS3_PHY_1216_DATA 0x00000000 -#define DDRSS3_PHY_1217_DATA 0x00000000 -#define DDRSS3_PHY_1218_DATA 0x00000000 -#define DDRSS3_PHY_1219_DATA 0x00000000 -#define DDRSS3_PHY_1220_DATA 0x00000000 -#define DDRSS3_PHY_1221_DATA 0x00000000 -#define DDRSS3_PHY_1222_DATA 0x00000000 -#define DDRSS3_PHY_1223_DATA 0x00000000 -#define DDRSS3_PHY_1224_DATA 0x00000000 -#define DDRSS3_PHY_1225_DATA 0x00000000 -#define DDRSS3_PHY_1226_DATA 0x00000000 -#define DDRSS3_PHY_1227_DATA 0x00000000 -#define DDRSS3_PHY_1228_DATA 0x00000000 -#define DDRSS3_PHY_1229_DATA 0x00000000 -#define DDRSS3_PHY_1230_DATA 0x00000000 -#define DDRSS3_PHY_1231_DATA 0x00000000 -#define DDRSS3_PHY_1232_DATA 0x00000000 -#define DDRSS3_PHY_1233_DATA 0x00000000 -#define DDRSS3_PHY_1234_DATA 0x00000000 -#define DDRSS3_PHY_1235_DATA 0x00000000 -#define DDRSS3_PHY_1236_DATA 0x00000000 -#define DDRSS3_PHY_1237_DATA 0x00000000 -#define DDRSS3_PHY_1238_DATA 0x00000000 -#define DDRSS3_PHY_1239_DATA 0x00000000 -#define DDRSS3_PHY_1240_DATA 0x00000000 -#define DDRSS3_PHY_1241_DATA 0x00000000 -#define DDRSS3_PHY_1242_DATA 0x00000000 -#define DDRSS3_PHY_1243_DATA 0x00000000 -#define DDRSS3_PHY_1244_DATA 0x00000000 -#define DDRSS3_PHY_1245_DATA 0x00000000 -#define DDRSS3_PHY_1246_DATA 0x00000000 -#define DDRSS3_PHY_1247_DATA 0x00000000 -#define DDRSS3_PHY_1248_DATA 0x00000000 -#define DDRSS3_PHY_1249_DATA 0x00000000 -#define DDRSS3_PHY_1250_DATA 0x00000000 -#define DDRSS3_PHY_1251_DATA 0x00000000 -#define DDRSS3_PHY_1252_DATA 0x00000000 -#define DDRSS3_PHY_1253_DATA 0x00000000 -#define DDRSS3_PHY_1254_DATA 0x00000000 -#define DDRSS3_PHY_1255_DATA 0x00000000 -#define DDRSS3_PHY_1256_DATA 0x00000000 -#define DDRSS3_PHY_1257_DATA 0x00000000 -#define DDRSS3_PHY_1258_DATA 0x00000000 -#define DDRSS3_PHY_1259_DATA 0x00000000 -#define DDRSS3_PHY_1260_DATA 0x00000000 -#define DDRSS3_PHY_1261_DATA 0x00000000 -#define DDRSS3_PHY_1262_DATA 0x00000000 -#define DDRSS3_PHY_1263_DATA 0x00000000 -#define DDRSS3_PHY_1264_DATA 0x00000000 -#define DDRSS3_PHY_1265_DATA 0x00000000 -#define DDRSS3_PHY_1266_DATA 0x00000000 -#define DDRSS3_PHY_1267_DATA 0x00000000 -#define DDRSS3_PHY_1268_DATA 0x00000000 -#define DDRSS3_PHY_1269_DATA 0x00000000 -#define DDRSS3_PHY_1270_DATA 0x00000000 -#define DDRSS3_PHY_1271_DATA 0x00000000 -#define DDRSS3_PHY_1272_DATA 0x00000000 -#define DDRSS3_PHY_1273_DATA 0x00000000 -#define DDRSS3_PHY_1274_DATA 0x00000000 -#define DDRSS3_PHY_1275_DATA 0x00000000 -#define DDRSS3_PHY_1276_DATA 0x00000000 -#define DDRSS3_PHY_1277_DATA 0x00000000 -#define DDRSS3_PHY_1278_DATA 0x00000000 -#define DDRSS3_PHY_1279_DATA 0x00000000 -#define DDRSS3_PHY_1280_DATA 0x00000000 -#define DDRSS3_PHY_1281_DATA 0x00010100 -#define DDRSS3_PHY_1282_DATA 0x00000000 -#define DDRSS3_PHY_1283_DATA 0x00000000 -#define DDRSS3_PHY_1284_DATA 0x00050000 -#define DDRSS3_PHY_1285_DATA 0x04000000 -#define DDRSS3_PHY_1286_DATA 0x00000055 -#define DDRSS3_PHY_1287_DATA 0x00000000 -#define DDRSS3_PHY_1288_DATA 0x00000000 -#define DDRSS3_PHY_1289_DATA 0x00000000 -#define DDRSS3_PHY_1290_DATA 0x00000000 -#define DDRSS3_PHY_1291_DATA 0x00002001 -#define DDRSS3_PHY_1292_DATA 0x0000400F -#define DDRSS3_PHY_1293_DATA 0x50020028 -#define DDRSS3_PHY_1294_DATA 0x01010000 -#define DDRSS3_PHY_1295_DATA 0x80080001 -#define DDRSS3_PHY_1296_DATA 0x10200000 -#define DDRSS3_PHY_1297_DATA 0x00000008 -#define DDRSS3_PHY_1298_DATA 0x00000000 -#define DDRSS3_PHY_1299_DATA 0x01090E00 -#define DDRSS3_PHY_1300_DATA 0x00040101 -#define DDRSS3_PHY_1301_DATA 0x0000010F -#define DDRSS3_PHY_1302_DATA 0x00000000 -#define DDRSS3_PHY_1303_DATA 0x0000FFFF -#define DDRSS3_PHY_1304_DATA 0x00000000 -#define DDRSS3_PHY_1305_DATA 0x01010000 -#define DDRSS3_PHY_1306_DATA 0x01080402 -#define DDRSS3_PHY_1307_DATA 0x01200F02 -#define DDRSS3_PHY_1308_DATA 0x00194280 -#define DDRSS3_PHY_1309_DATA 0x00000004 -#define DDRSS3_PHY_1310_DATA 0x00042000 -#define DDRSS3_PHY_1311_DATA 0x00000000 -#define DDRSS3_PHY_1312_DATA 0x00000000 -#define DDRSS3_PHY_1313_DATA 0x00000000 -#define DDRSS3_PHY_1314_DATA 0x00000000 -#define DDRSS3_PHY_1315_DATA 0x00000000 -#define DDRSS3_PHY_1316_DATA 0x00000000 -#define DDRSS3_PHY_1317_DATA 0x01000000 -#define DDRSS3_PHY_1318_DATA 0x00000705 -#define DDRSS3_PHY_1319_DATA 0x00000054 -#define DDRSS3_PHY_1320_DATA 0x00030820 -#define DDRSS3_PHY_1321_DATA 0x00010820 -#define DDRSS3_PHY_1322_DATA 0x00010820 -#define DDRSS3_PHY_1323_DATA 0x00010820 -#define DDRSS3_PHY_1324_DATA 0x00010820 -#define DDRSS3_PHY_1325_DATA 0x00010820 -#define DDRSS3_PHY_1326_DATA 0x00010820 -#define DDRSS3_PHY_1327_DATA 0x00010820 -#define DDRSS3_PHY_1328_DATA 0x00010820 -#define DDRSS3_PHY_1329_DATA 0x00000000 -#define DDRSS3_PHY_1330_DATA 0x00000074 -#define DDRSS3_PHY_1331_DATA 0x00000400 -#define DDRSS3_PHY_1332_DATA 0x00000108 -#define DDRSS3_PHY_1333_DATA 0x00000000 -#define DDRSS3_PHY_1334_DATA 0x00000000 -#define DDRSS3_PHY_1335_DATA 0x00000000 -#define DDRSS3_PHY_1336_DATA 0x00000000 -#define DDRSS3_PHY_1337_DATA 0x00000000 -#define DDRSS3_PHY_1338_DATA 0x03000000 -#define DDRSS3_PHY_1339_DATA 0x00000000 -#define DDRSS3_PHY_1340_DATA 0x00000000 -#define DDRSS3_PHY_1341_DATA 0x00000000 -#define DDRSS3_PHY_1342_DATA 0x04102006 -#define DDRSS3_PHY_1343_DATA 0x00041020 -#define DDRSS3_PHY_1344_DATA 0x01C98C98 -#define DDRSS3_PHY_1345_DATA 0x3F400000 -#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F -#define DDRSS3_PHY_1347_DATA 0x0000001F -#define DDRSS3_PHY_1348_DATA 0x00000000 -#define DDRSS3_PHY_1349_DATA 0x00000000 -#define DDRSS3_PHY_1350_DATA 0x00000000 -#define DDRSS3_PHY_1351_DATA 0x00010000 -#define DDRSS3_PHY_1352_DATA 0x00000000 -#define DDRSS3_PHY_1353_DATA 0x00000000 -#define DDRSS3_PHY_1354_DATA 0x00000000 -#define DDRSS3_PHY_1355_DATA 0x00000000 -#define DDRSS3_PHY_1356_DATA 0x76543210 -#define DDRSS3_PHY_1357_DATA 0x00010198 -#define DDRSS3_PHY_1358_DATA 0x00000000 -#define DDRSS3_PHY_1359_DATA 0x00000000 -#define DDRSS3_PHY_1360_DATA 0x00000000 -#define DDRSS3_PHY_1361_DATA 0x00040700 -#define DDRSS3_PHY_1362_DATA 0x00000000 -#define DDRSS3_PHY_1363_DATA 0x00000000 -#define DDRSS3_PHY_1364_DATA 0x00000000 -#define DDRSS3_PHY_1365_DATA 0x00000000 -#define DDRSS3_PHY_1366_DATA 0x00000000 -#define DDRSS3_PHY_1367_DATA 0x00000002 -#define DDRSS3_PHY_1368_DATA 0x00000000 -#define DDRSS3_PHY_1369_DATA 0x00000000 -#define DDRSS3_PHY_1370_DATA 0x00000000 -#define DDRSS3_PHY_1371_DATA 0x00000000 -#define DDRSS3_PHY_1372_DATA 0x00000000 -#define DDRSS3_PHY_1373_DATA 0x00000000 -#define DDRSS3_PHY_1374_DATA 0x00080000 -#define DDRSS3_PHY_1375_DATA 0x000007FF -#define DDRSS3_PHY_1376_DATA 0x00000000 -#define DDRSS3_PHY_1377_DATA 0x00000000 -#define DDRSS3_PHY_1378_DATA 0x00000000 -#define DDRSS3_PHY_1379_DATA 0x00000000 -#define DDRSS3_PHY_1380_DATA 0x00000000 -#define DDRSS3_PHY_1381_DATA 0x00000000 -#define DDRSS3_PHY_1382_DATA 0x000FFFFF -#define DDRSS3_PHY_1383_DATA 0x000FFFFF -#define DDRSS3_PHY_1384_DATA 0x0000FFFF -#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0 -#define DDRSS3_PHY_1386_DATA 0x030FFFFF -#define DDRSS3_PHY_1387_DATA 0x01FFFFFF -#define DDRSS3_PHY_1388_DATA 0x0000FFFF -#define DDRSS3_PHY_1389_DATA 0x00000000 -#define DDRSS3_PHY_1390_DATA 0x00000000 -#define DDRSS3_PHY_1391_DATA 0x00000000 -#define DDRSS3_PHY_1392_DATA 0x00000000 -#define DDRSS3_PHY_1393_DATA 0x0001F7C0 -#define DDRSS3_PHY_1394_DATA 0x00000003 -#define DDRSS3_PHY_1395_DATA 0x00000000 -#define DDRSS3_PHY_1396_DATA 0x00001142 -#define DDRSS3_PHY_1397_DATA 0x010207AB -#define DDRSS3_PHY_1398_DATA 0x01000080 -#define DDRSS3_PHY_1399_DATA 0x03900390 -#define DDRSS3_PHY_1400_DATA 0x03900390 -#define DDRSS3_PHY_1401_DATA 0x00000390 -#define DDRSS3_PHY_1402_DATA 0x00000390 -#define DDRSS3_PHY_1403_DATA 0x00000390 -#define DDRSS3_PHY_1404_DATA 0x00000390 -#define DDRSS3_PHY_1405_DATA 0x00000005 -#define DDRSS3_PHY_1406_DATA 0x01813FCC -#define DDRSS3_PHY_1407_DATA 0x000000CC -#define DDRSS3_PHY_1408_DATA 0x0C000DFF -#define DDRSS3_PHY_1409_DATA 0x30000DFF -#define DDRSS3_PHY_1410_DATA 0x3F0DFF11 -#define DDRSS3_PHY_1411_DATA 0x000100F0 -#define DDRSS3_PHY_1412_DATA 0x780DFFCC -#define DDRSS3_PHY_1413_DATA 0x00007E31 -#define DDRSS3_PHY_1414_DATA 0x000CBF11 -#define DDRSS3_PHY_1415_DATA 0x01990010 -#define DDRSS3_PHY_1416_DATA 0x000CBF11 -#define DDRSS3_PHY_1417_DATA 0x01990010 -#define DDRSS3_PHY_1418_DATA 0x3F0DFF11 -#define DDRSS3_PHY_1419_DATA 0x00EF00F0 -#define DDRSS3_PHY_1420_DATA 0x3F0DFF11 -#define DDRSS3_PHY_1421_DATA 0x01FF00F0 -#define DDRSS3_PHY_1422_DATA 0x20040006 From 11dc7c06089c2c7e0f720d36cb0335d57aac0ba1 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 3 Nov 2025 12:40:35 +0530 Subject: [PATCH 28/65] doc: ti: k3: Add section for DDR configuration Add a concise section for DDR configuration pointing to the public tool that can be used to generate the configuration DTSI. Signed-off-by: Neha Malcom Francis Reviewed-by: Romain Naour --- doc/board/ti/k3.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 01fb9411688..de66b830703 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -649,6 +649,17 @@ Refer (:ref:`U-boot ARMV8 build `) This will need to be explicitly disabled by changing the boot_targets to disallow fallback during testing. +DDR Configuration +----------------- + +The K3 DDRSS driver (drivers/ram/k3-ddrss/k3-ddrss.c) configures the DDR during +the R5 SPL stage. The driver utilizes an auto-generated configuration file +containing necessary settings for the DDR. It configures the frequency, timing +parameters, training algorithms etc. for DDR initialization. The configuration +DTSI can be generated using the `Sysconfig tool `_ +and selecting the software product as "DDR Configuration for \*" as well as the +required device. + Saving environment ------------------ From 1ab49f6a91ea88889c4283348f18680d6f87131f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 9 Jun 2026 13:13:11 -0600 Subject: [PATCH 29/65] CI: Sage: Pin to labgrid 25.0.1 With the recent release of labgrid 26.0, we need to pin to 25.0.1 for the Sage lab until everything can be upgraded. Signed-off-by: Tom Rini --- .gitlab-ci-sage-lab.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci-sage-lab.yml b/.gitlab-ci-sage-lab.yml index 176d281868b..e2f36848604 100644 --- a/.gitlab-ci-sage-lab.yml +++ b/.gitlab-ci-sage-lab.yml @@ -26,7 +26,7 @@ . /tmp/venv/bin/activate; pip install -r test/py/requirements.txt -r tools/binman/requirements.txt -r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt - labgrid setuptools + labgrid==25.0.1 setuptools # Acquire and turn on the exporter. - labgrid-client reserve --wait board=${LABGRID_EXPORTER} && labgrid-client -p ${LABGRID_EXPORTER} acquire && From 8a4c199aa4b9192f8a545793005b575292b5c5e7 Mon Sep 17 00:00:00 2001 From: Petr Hodina Date: Fri, 5 Jun 2026 17:09:07 +0200 Subject: [PATCH 30/65] gpio: qcom_spmi_gpio: move PM8998 GPIO from legacy pmic driver Move the "qcom,pm8998-gpio" compatible from the legacy driver qcom_pmic_gpio.c to qcom_spmi_gpio.c. Enables on PM8998-based boards (sdm845: SHIFT 6mq, Pixel 3, OnePlus 6, Poco F1, Sony Xperia Akatsuki) the Volume UP gpio-key. Signed-off-by: Petr Hodina Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260605-qcom-gpio-v2-1-c34093041c66@protonmail.com Signed-off-by: Casey Connolly --- drivers/gpio/qcom_pmic_gpio.c | 1 - drivers/gpio/qcom_spmi_gpio.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 4458c55cd3d..6215f794e09 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -344,7 +344,6 @@ static int qcom_gpio_probe(struct udevice *dev) static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ - { .compatible = "qcom,pm8998-gpio" }, { .compatible = "qcom,pms405-gpio" }, { .compatible = "qcom,pm6125-gpio" }, { .compatible = "qcom,pm8150-gpio" }, diff --git a/drivers/gpio/qcom_spmi_gpio.c b/drivers/gpio/qcom_spmi_gpio.c index 77a69140213..fc1aac8b534 100644 --- a/drivers/gpio/qcom_spmi_gpio.c +++ b/drivers/gpio/qcom_spmi_gpio.c @@ -752,6 +752,7 @@ static const struct udevice_id qcom_spmi_pmic_gpio_ids[] = { { .compatible = "qcom,pm8550b-gpio" }, { .compatible = "qcom,pm8550ve-gpio" }, { .compatible = "qcom,pm8550vs-gpio" }, + { .compatible = "qcom,pm8998-gpio" }, { .compatible = "qcom,pmk8550-gpio" }, { .compatible = "qcom,pmr735d-gpio" }, { } From 688890d15cc7021a72ca9939e9eecaee6adea385 Mon Sep 17 00:00:00 2001 From: Sam Day Date: Sun, 31 May 2026 06:40:59 +0000 Subject: [PATCH 31/65] board: qualcomm: phone: fix 'Dump bootargs' This menu option wasn't dumping /chosen, because no FDT addr had been set yet. Signed-off-by: Sam Day Link: https://patch.msgid.link/20260531-qcom-phoneconfig-fix-v1-1-110a1c542dc3@samcday.com Signed-off-by: Casey Connolly --- board/qualcomm/qcom-phone.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/qualcomm/qcom-phone.env b/board/qualcomm/qcom-phone.env index e91ae3ecdfb..d1c586bd3fb 100644 --- a/board/qualcomm/qcom-phone.env +++ b/board/qualcomm/qcom-phone.env @@ -39,7 +39,7 @@ bootmenu_5=Reset device=reset bootmenu_6=Dump clocks=clk dump; pause bootmenu_7=Dump environment=printenv; pause bootmenu_8=Board info=bdinfo; pause -bootmenu_9=Dump bootargs=fdt print /chosen bootargs; pause +bootmenu_9=Dump bootargs=fdt addr $fdt_addr_r; fdt print /chosen bootargs; pause # Allow holding the volume down button while U-Boot loads to enter # the boot menu From 146963054be8ae66dc5de88979a04e067c19117e Mon Sep 17 00:00:00 2001 From: Sam Day Date: Sun, 31 May 2026 01:18:34 +0000 Subject: [PATCH 32/65] board: dragonboard410c: fix chainloaded.config Since c8a74db0c, SYS_INIT_SP_BSS_OFFSET only supports hex encoding. Signed-off-by: Sam Day Link: https://patch.msgid.link/20260531-db410c-chainloaded-fix-v1-1-94176aa147d1@samcday.com Signed-off-by: Casey Connolly --- board/qualcomm/dragonboard410c/configs/chainloaded.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config b/board/qualcomm/dragonboard410c/configs/chainloaded.config index 3fd064924a1..cf334d7ee20 100644 --- a/board/qualcomm/dragonboard410c/configs/chainloaded.config +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config @@ -4,4 +4,4 @@ CONFIG_TEXT_BASE=0x0 # CONFIG_REMAKE_ELF is not set CONFIG_POSITION_INDEPENDENT=y CONFIG_INIT_SP_RELATIVE=y -CONFIG_SYS_INIT_SP_BSS_OFFSET=524288 +CONFIG_SYS_INIT_SP_BSS_OFFSET=0x80000 From a50e32bae6abc8d86d4fa6fff9a1c8f5c88baa4f Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Tue, 26 May 2026 12:26:36 +0530 Subject: [PATCH 33/65] configs: qcs615/qcs9100: Enable watchdog autostart Enable watchdog autostart for QCS615 and QCS9100 platforms to ensure the watchdog timer is automatically started during U-Boot initialization. Signed-off-by: Balaji Selvanathan Link: https://patch.msgid.link/20260526-wdt-v1-1-8236040fe56a@oss.qualcomm.com Signed-off-by: Casey Connolly --- configs/qcom_qcs615_defconfig | 2 ++ configs/qcom_qcs9100_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/qcom_qcs615_defconfig b/configs/qcom_qcs615_defconfig index 27666a8129d..e060fac3726 100644 --- a/configs/qcom_qcs615_defconfig +++ b/configs/qcom_qcs615_defconfig @@ -22,3 +22,5 @@ CONFIG_REMAKE_ELF=y CONFIG_TEXT_BASE=0x9fc00000 CONFIG_FASTBOOT_BUF_ADDR=0xa1600000 + +CONFIG_WATCHDOG_AUTOSTART=y diff --git a/configs/qcom_qcs9100_defconfig b/configs/qcom_qcs9100_defconfig index 082106157bb..efd6c63f212 100644 --- a/configs/qcom_qcs9100_defconfig +++ b/configs/qcom_qcs9100_defconfig @@ -14,3 +14,5 @@ CONFIG_ENV_IS_IN_SCSI=y CONFIG_ENV_SCSI_PART_UUID="71cb9cd0-acf1-b6cb-ad91-be9572fe11a9" # CONFIG_ENV_IS_DEFAULT is not set # CONFIG_ENV_IS_NOWHERE is not set + +CONFIG_WATCHDOG_AUTOSTART=y From c2019e01d069c398921abdf8f159136f7e550078 Mon Sep 17 00:00:00 2001 From: Aswin Murugan Date: Fri, 24 Apr 2026 16:12:37 +0530 Subject: [PATCH 34/65] dts: lemans-evk-u-boot: add override dtsi Add initial support for the lemans EVK platform based on lemans SoC. Define memory layout statically. Signed-off-by: Aswin Murugan Signed-off-by: Sumit Garg Link: https://patch.msgid.link/20260424104237.968195-1-sumit.garg@kernel.org Signed-off-by: Casey Connolly --- arch/arm/dts/lemans-evk-u-boot.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 arch/arm/dts/lemans-evk-u-boot.dtsi diff --git a/arch/arm/dts/lemans-evk-u-boot.dtsi b/arch/arm/dts/lemans-evk-u-boot.dtsi new file mode 100644 index 00000000000..cdd3d32f61a --- /dev/null +++ b/arch/arm/dts/lemans-evk-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/ { + /* Will be removed when bootloader updates later */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x3ee00000>, + <0x0 0xc0000000 0x0 0x0fd00000>, + <0xD 0x00000000 0x2 0x54100000>, + <0xA 0x80000000 0x1 0x80000000>, + <0x9 0x00000000 0x1 0x80000000>, + <0x1 0x00000000 0x3 0x00000000>, + <0x0 0xd0000000 0x0 0x01900000>, + <0x0 0xd3500000 0x0 0x2cb00000>; + }; +}; From 757a95c7faae4bdc10dc463c1bb3cf3fee1418a0 Mon Sep 17 00:00:00 2001 From: Gurumoorthy Santhakumar Date: Wed, 3 Jun 2026 17:08:53 +0530 Subject: [PATCH 35/65] arm: dts: ipq5424-rdp466: add chosen node for serial console Add a /chosen node with stdout-path pointing to serial0 (uart1) to enable the DT-driven console discovery path in serial_find_console_or_panic(). Without this node, the live DT path in serial_find_console_or_panic() is skipped and the fallback path is used. Adding the /chosen node makes the console selection explicit and deterministic, ensuring the correct serial device is always selected as the console. Signed-off-by: Gurumoorthy Santhakumar Link: https://patch.msgid.link/20260603113853.3396271-1-gurumoorthy.santhakumar@oss.qualcomm.com Signed-off-by: Casey Connolly --- arch/arm/dts/ipq5424-rdp466-u-boot.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi index 9e4af4d9f72..36640f31d61 100644 --- a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi +++ b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi @@ -12,6 +12,9 @@ reg = <0x0 0x80000000 0x0 0x20000000>; }; + chosen { + stdout-path = "serial0:115200n8"; + }; }; &sdhc { From da8d438ae7aa9189b25abe49741aa64b244fe128 Mon Sep 17 00:00:00 2001 From: Franz Schnyder Date: Fri, 12 Jun 2026 10:59:00 +0200 Subject: [PATCH 36/65] configs: toradex-smarc-imx95: enable PCI_INIT_R Currently, the ENETC device on iMX95 is not enumerated before network initialization because pci_init() is not called. As a result, no Ethernet device is registered. Enable CONFIG_PCI_INIT_R so the PCI buses are enumerated early enough for the Ethernet Controller to be detected and used. Fixes: ff0540fcfe49 ("board: toradex: add Toradex SMARC iMX95") Signed-off-by: Franz Schnyder Reviewed-by: Francesco Dolcini --- configs/toradex-smarc-imx95_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/toradex-smarc-imx95_defconfig b/configs/toradex-smarc-imx95_defconfig index caf0718fc13..03515c51cb3 100644 --- a/configs/toradex-smarc-imx95_defconfig +++ b/configs/toradex-smarc-imx95_defconfig @@ -44,6 +44,7 @@ CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_BOARD_INIT is not set +CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x30000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_LOAD_IMX_CONTAINER=y From 4228d584ce6f7c54edf765b9231806314dae48ad Mon Sep 17 00:00:00 2001 From: Franz Schnyder Date: Fri, 12 Jun 2026 10:59:01 +0200 Subject: [PATCH 37/65] configs: verdin-imx95: enable PCI_INIT_R Currently, the ENETC device on iMX95 is not enumerated before network initialization because pci_init() is not called. As a result, no Ethernet device is registered. Enable CONFIG_PCI_INIT_R so the PCI buses are enumerated early enough for the Ethernet Controller to be detected and used. Fixes: 60d8255d8dc0 ("board: toradex: add Toradex Verdin iMX95") Signed-off-by: Franz Schnyder Reviewed-by: Francesco Dolcini --- configs/verdin-imx95_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/verdin-imx95_defconfig b/configs/verdin-imx95_defconfig index 50515250d17..a8025fda2c9 100644 --- a/configs/verdin-imx95_defconfig +++ b/configs/verdin-imx95_defconfig @@ -45,6 +45,7 @@ CONFIG_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y +CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x30000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_LOAD_IMX_CONTAINER=y From d043e977104650ce8f00eeaf57a7484e4684900d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 Jun 2026 20:04:26 +0200 Subject: [PATCH 38/65] arm: renesas: Build u-boot-elf.shdr for R-Car X5H Cortex-M33 RSIP port Currently, the default build target for all R-Car Gen3/4/5 is the u-boot-elf.srec, which depends on u-boot.bin and other vital build artifacts, which get built as prerequisites. The R-Car Gen5 RSIP port benefits from u-boot-elf.shdr being built as well, because the u-boot-elf.shdr contains header used by the BootROM to load and start U-Boot on the RSIP core. Because u-boot-elf.shdr depends on u-boot-elf.srec, switch the default build target for R-Car Gen5 RSIP port to u-boot-elf.shdr. This way, both u-boot-elf.shdr and u-boot-elf.srec are built for R-Car Gen5 RSIP port. Fixes: 9d47a5a4d560 ("arm: renesas: Add Renesas R-Car R8A78000 X5H Cortex-M33 RSIP port") Signed-off-by: Marek Vasut --- Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index 8428d039a1c..99b896b6cf1 100644 --- a/Kconfig +++ b/Kconfig @@ -548,7 +548,8 @@ config REMAKE_ELF config BUILD_TARGET string "Build target special images" - default "u-boot-elf.srec" if RCAR_64 + default "u-boot-elf.shdr" if RCAR_64 && RCAR_64_RSIP + default "u-boot-elf.srec" if RCAR_64 && !RCAR_64_RSIP default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL default "u-boot-with-spl.imx" if (ARCH_MX6 || ARCH_MX7) && SPL From 79d6bd525ce03fba9fe958eb11734c1ebb16838a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 Jun 2026 20:05:58 +0200 Subject: [PATCH 39/65] arm: renesas: Make R-Car Gen5 u-boot-elf.shdr compatible with SDK flash_writer The SDK 4.32 flash_writer tool, built from the SDK IPL source, requires SREC S7 "Start address (termination)" record [1] at the end of the SREC file that is sent to it during installation of content into storage, otherwise the tool waits for the S7 record indefinitelly and the payload does not get installed into storage. Specifically, the tool considers SREC S3 and S7 records as mandatory, S0, S5, S6 as ignored, and any other records as unsupported. Configure srec_cat such that it explicitly generates the trailing S7 record, and also that it never generates the ignored S5 Count record. This fixes installation of u-boot-elf.shdr using the flash_writer tool, which can not finish successfully without the trailing S7 record. [1] https://en.wikipedia.org/wiki/Motorola_S-record#Record_types Fixes: 3b2ce3743c1a ("arm: renesas: Generate u-boot-elf.shdr for R-Car Gen5 RSIP") Signed-off-by: Marek Vasut --- arch/arm/mach-renesas/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile index 83c576d6007..4c8dbc465a6 100644 --- a/arch/arm/mach-renesas/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -50,6 +50,8 @@ quiet_cmd_srec_cat = SRECCAT $@ quiet_cmd_srec_shdr_cat = SRECCAT $@ cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \ -Output_Block_Size 16 \ + -DISable Data_Count \ + -Execution_Start_Address 0x18400000 \ -generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \ -generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \ -generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \ From a298f3066ef292466f58c4f1d545830e184cd051 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 14 Jun 2026 03:52:08 +0200 Subject: [PATCH 40/65] arm64: renesas: Fold mach_cpu_init into board_init_f on R-Car S4/V4H/V4M SPL The mach_cpu_init() function is not invoked in SPL. Instead of having two functions, fold mach_cpu_init() into board_init_f(), which is called very early in the boot process and assures that the CPG and APMU setup will be invoked before DM is brought up. Fixes: 37997a214ed1 ("arm: renesas: Use stock lowlevel_init function and remove s_init") Signed-off-by: Marek Vasut --- board/renesas/common/gen4-spl.c | 41 +++++++++++++++------------------ 1 file changed, 18 insertions(+), 23 deletions(-) diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c index e4c1190eac7..5a0b0ebe115 100644 --- a/board/renesas/common/gen4-spl.c +++ b/board/renesas/common/gen4-spl.c @@ -18,6 +18,12 @@ #include #include +#define APMU_BASE 0xe6170000U +#define CL0GRP3_BIT BIT(3) +#define CL1GRP3_BIT BIT(7) +#define RTGRP3_BIT BIT(19) +#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) + #define CNTCR_EN BIT(0) #ifdef CONFIG_SPL_BUILD @@ -47,6 +53,18 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; + /* Unlock CPG access */ + writel(0x5A5AFFFF, CPGWPR); + writel(0xA5A50000, CPGWPCR); + init_generic_timer(); + + /* Define for Work Around of APMU */ + writel(0x00ff00ff, APMU_BASE + 0x10); + writel(0x00ff00ff, APMU_BASE + 0x14); + writel(0x00ff00ff, APMU_BASE + 0x18); + writel(0x00ff00ff, APMU_BASE + 0x1c); + clrbits_le32(APMU_BASE + 0x68, BIT(29)); + if (CONFIG_IS_ENABLED(OF_CONTROL)) { ret = spl_early_init(); if (ret) { @@ -76,29 +94,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0); } -#define APMU_BASE 0xe6170000U -#define CL0GRP3_BIT BIT(3) -#define CL1GRP3_BIT BIT(7) -#define RTGRP3_BIT BIT(19) -#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) - -int mach_cpu_init(void) -{ - /* Unlock CPG access */ - writel(0x5A5AFFFF, CPGWPR); - writel(0xA5A50000, CPGWPCR); - init_generic_timer(); - - /* Define for Work Around of APMU */ - writel(0x00ff00ff, APMU_BASE + 0x10); - writel(0x00ff00ff, APMU_BASE + 0x14); - writel(0x00ff00ff, APMU_BASE + 0x18); - writel(0x00ff00ff, APMU_BASE + 0x1c); - clrbits_le32(APMU_BASE + 0x68, BIT(29)); - - return 0; -} - void reset_cpu(void) { } From cc5d760ace890b57d78b23aafb47ba220e63ae4f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 14 Jun 2026 03:52:21 +0200 Subject: [PATCH 41/65] arm64: renesas: Initialize GIC600 fully on R-Car S4/V4H/V4M ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed to mark the frame as powered on, before accessing other registers in the frame. Before the switch to generic lowlevel_init function, this did not pose a problem as the previous custom lowlevel_init did not access the GICR registers. The generic function does and that does lead to a hang early in SPL. Enable the GIC600 initialization variant to mitigate the hang. Fixes: 37997a214ed1 ("arm: renesas: Use stock lowlevel_init function and remove s_init") Signed-off-by: Marek Vasut --- arch/arm/mach-renesas/Kconfig.rcar4 | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4 index 2439501d07e..39814950b1a 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar4 +++ b/arch/arm/mach-renesas/Kconfig.rcar4 @@ -11,12 +11,14 @@ config R8A779A0 config R8A779F0 bool "Renesas SoC R8A779F0" select GICV3 + select GICV3_SUPPORT_GIC600 imply CLK_R8A779F0 imply PINCTRL_PFC_R8A779F0 config R8A779G0 bool "Renesas SoC R8A779G0" select GICV3 + select GICV3_SUPPORT_GIC600 select BINMAN select SUPPORT_SPL imply SPL @@ -33,6 +35,7 @@ config R8A779G0 config R8A779H0 bool "Renesas SoC R8A779H0" select GICV3 + select GICV3_SUPPORT_GIC600 imply CLK_R8A779H0 imply PINCTRL_PFC_R8A779H0 From 1bd1d033377796418008e9a2351f18dbdf88940c Mon Sep 17 00:00:00 2001 From: Francois Berder Date: Sun, 24 May 2026 21:25:47 +0200 Subject: [PATCH 42/65] fastboot: Fix blk_dwrite error checking blk_dwrite() returns the number of blocks written. The code was only checking if the return value was different than 0. Hence, partial writes were considered successful. Fix blk_dwrite error handling by checking that all blocks are written. Signed-off-by: Francois Berder Reviewed-by: Mattijs Korpershoek Link: https://patch.msgid.link/BESP194MB2805BBD03E7C92727F116585DA0D2@BESP194MB2805.EURP194.PROD.OUTLOOK.COM Signed-off-by: Mattijs Korpershoek --- drivers/fastboot/fb_mmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 11d9c8e8460..9bc782ccd02 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -263,7 +263,7 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc, /* Write new kernel size to boot image header */ hdr->kernel_size = download_bytes; res = blk_dwrite(dev_desc, info.start, hdr_sectors, (void *)hdr); - if (res == 0) { + if (res != hdr_sectors) { pr_err("cannot writeback boot image header\n"); fastboot_fail("cannot write back boot image header", response); return -1; @@ -275,7 +275,7 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc, sectors_per_page; res = blk_dwrite(dev_desc, kernel_sector_start, kernel_sectors, download_buffer); - if (res == 0) { + if (res != kernel_sectors) { pr_err("cannot write new kernel\n"); fastboot_fail("cannot write new kernel", response); return -1; @@ -287,7 +287,7 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc, sectors_per_page; res = blk_dwrite(dev_desc, ramdisk_sector_start, ramdisk_sectors, ramdisk_buffer); - if (res == 0) { + if (res != ramdisk_sectors) { pr_err("cannot write back original ramdisk\n"); fastboot_fail("cannot write back original ramdisk", response); return -1; From e41e97e6e6061fec5a2fb069eaad662cf6359a93 Mon Sep 17 00:00:00 2001 From: Colin Pinnell McAllister Date: Mon, 25 May 2026 00:31:58 +0000 Subject: [PATCH 43/65] android_ab: fix slot selection The boot selection rules state that a slot is bootable if it is not corrupted and either has tries remaining or has already booted successfully. However, slots that have tries_remaining == 0 and successful_boot == 1 will be disregarded when picking the slot to attempt. Updates the selection logic so slots marked successful remain eligible even when their tries counter is zero. Debug message now also includes the successful_boot value. Signed-off-by: Colin Pinnell McAllister Reviewed-by: Mattijs Korpershoek Link: https://patch.msgid.link/20260525003158.11319-1-colinmca242@gmail.com Signed-off-by: Mattijs Korpershoek --- boot/android_ab.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/boot/android_ab.c b/boot/android_ab.c index 13e82dbcb7f..f2b1110aa24 100644 --- a/boot/android_ab.c +++ b/boot/android_ab.c @@ -289,11 +289,14 @@ int ab_select_slot(struct blk_desc *dev_desc, struct disk_partition *part_info, slot = -1; for (i = 0; i < abc->nb_slot; ++i) { if (abc->slot_info[i].verity_corrupted || - !abc->slot_info[i].tries_remaining) { + (!abc->slot_info[i].tries_remaining && + !abc->slot_info[i].successful_boot)) { log_debug("ANDROID: unbootable slot %d tries: %d, ", i, abc->slot_info[i].tries_remaining); - log_debug("corrupt: %d\n", + log_debug("corrupt: %d, ", abc->slot_info[i].verity_corrupted); + log_debug("successful: %d\n", + abc->slot_info[i].successful_boot); continue; } log_debug("ANDROID: bootable slot %d pri: %d, tries: %d, ", From 033eb908d0a8ed938bc652f34a2d702a29a8726f Mon Sep 17 00:00:00 2001 From: Zixun LI Date: Sat, 6 Jun 2026 10:27:09 +0200 Subject: [PATCH 44/65] usb: gadget: atmel: use calloc() to allocate endpoint list malloc() doesn't zero out memory, leaving ep->ep.enabled uninitiated, which could make this flag falsely true. In next usb_ep_enable() call since this flag is true, ep->ops->enable() will be skipped. Then usb_ep_queue() will fail on uninitialized endpoint. Fixes: 59310d1ecb9f ("usb: gadget: introduce 'enabled' flag in struct usb_ep") Signed-off-by: Zixun LI Reviewed-by: Marek Vasut Reviewed-by: Mattijs Korpershoek Link: https://patch.msgid.link/20260606-udc_malloc-v2-1-1155326b182b@hifiphile.com Signed-off-by: Mattijs Korpershoek --- drivers/usb/gadget/atmel_usba_udc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index a2eee2bca2c..0caf8b8b7b4 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -1201,7 +1201,7 @@ static struct usba_ep *usba_udc_pdata(struct usba_platform_data *pdata, struct usba_ep *eps; int i; - eps = malloc(sizeof(struct usba_ep) * pdata->num_ep); + eps = calloc(pdata->num_ep, sizeof(struct usba_ep)); if (!eps) { log_err("failed to alloc eps\n"); return NULL; From 895d3c67cd58fee6815d0e2799ea7d22474accb9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 13 Jun 2026 07:05:12 -0600 Subject: [PATCH 45/65] x86: edison: Avoid passing FORCE to the align command Commit bd3f9ee679b4 ("kbuild: Bump the build system to 6.1") adds FORCE as a prerequisite to the u-boot-align.bin rule, but cmd_mkalign_eds expands $^, so FORCE leaks in as a stray operand. The dd then fails (silently, since its stderr is discarded) and the following mv never runs, so u-boot.bin never gains its 4096-byte zero prefix. The mask ROM enters U-Boot 0x1000 (4KB) into the image and the board never starts, sitting in BootROM download mode (DnX). Use $< instead of $^, which excludes FORCE and restores the prefix. Fixes: bd3f9ee679b4 ("kbuild: Bump the build system to 6.1") Signed-off-by: Simon Glass Reviewed-by: Andy Shevchenko --- board/intel/edison/config.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/intel/edison/config.mk b/board/intel/edison/config.mk index 3afebf0f0b1..fff187caa15 100644 --- a/board/intel/edison/config.mk +++ b/board/intel/edison/config.mk @@ -7,8 +7,8 @@ # Add 4096 bytes of zeroes to u-boot.bin quiet_cmd_mkalign_eds = EDSALGN $@ cmd_mkalign_eds = \ - dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \ - mv $@ $^ + dd if=$< of=$@ bs=4k seek=1 2>/dev/null && \ + mv $@ $< INPUTS-y += u-boot-align.bin u-boot-align.bin: u-boot.bin FORCE From 3ac35afdd2cc73db0ac3911937ce75b58a6f90b8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 13 Jun 2026 07:05:13 -0600 Subject: [PATCH 46/65] arm: mxs: Avoid passing FORCE to commands Commit bd3f9ee679b4 ("kbuild: Bump the build system to 6.1") adds FORCE as a prerequisite to the if_changed rules here, but the commands use $^ so FORCE leaks in as a stray operand. The dd in cmd_mkalign_mxs fails (silently, since its stderr is discarded) and the binary is never aligned, stat in cmd_mkivt_mxs emits an error and cst receives a bogus argument. Use $< and $(real-prereqs) instead, which exclude FORCE. Fixes: bd3f9ee679b4 ("kbuild: Bump the build system to 6.1") Signed-off-by: Simon Glass --- arch/arm/cpu/arm926ejs/mxs/Makefile | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 0df501e91db..6bd95a5185b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -26,7 +26,7 @@ MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg # quiet_cmd_mkivt_mxs = MXSIVT $@ cmd_mkivt_mxs = \ - sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ; \ + sz=`expr \`stat -c "%s" $<\` + 64 + 3904 + 128` ; \ echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" | \ tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev | \ sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@ @@ -34,15 +34,15 @@ cmd_mkivt_mxs = \ # Align binary to 64B quiet_cmd_mkalign_mxs = MXSALGN $@ cmd_mkalign_mxs = \ - dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null && \ - mv $@ $^ + dd if=$< of=$@ ibs=64 conv=sync 2>/dev/null && \ + mv $@ $< # Assemble the CSF file quiet_cmd_mkcsfreq_mxs = MXSCSFR $@ cmd_mkcsfreq_mxs = \ - ivt=$(word 1,$^) ; \ - bin=$(word 2,$^) ; \ - csf=$(word 3,$^) ; \ + ivt=$(word 1,$(real-prereqs)) ; \ + bin=$(word 2,$(real-prereqs)) ; \ + csf=$(word 3,$(real-prereqs)) ; \ sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" | \ sed '/^\#\#Blocks/ d' > $@ ; \ echo " Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \ @@ -50,7 +50,7 @@ cmd_mkcsfreq_mxs = \ # Sign files quiet_cmd_mkcst_mxs = MXSCST $@ -cmd_mkcst_mxs = cst -o $@ < $^ \ +cmd_mkcst_mxs = cst -o $@ < $< \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) spl/u-boot-spl.ivt: spl/u-boot-spl.bin FORCE From 8b154abd31e499d7e90d125d36d997c75daa6b05 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 13 Jun 2026 19:24:44 +0200 Subject: [PATCH 47/65] lmb: Add the Rockchip architecture as requiring DMA below 4G Loading EFI parts like a Debian-Installer on Rockchip SoCs creates interesting results, in that on some boards the Grub bootloader can't find any partitions on a USB-Stick, or loading a kernel from Grub spews EHCI fail timeout STS_IAA set messages before failing and on others the loading something like efivars from an eMMC creates read errors and making the MMC vanish from U-Boot. This only affected boards with at least 4GB of RAM. These boards have at least 256MB of memory placed above the actual 4GB address space (due to the iomem being in between) and while kernel, initramfs, dt are generally loaded to predefined addresses, additional EFI parts (efivars, etc) are likely just loaded "somewhere" and it seems this always landed in that higher up memory part. Also in the Linux-kernel peripherals like EMMC, USB, etc already run with a 32bit dma-mask set. So far, I've seen this on RK3568 and RK3588, but as the same peripherals are used on most Rockchip SoCs, it makes sense to limit this on all. So add ARCH_ROCKCHIP to the default-y list of LMB_LIMIT_DMA_BELOW_RAM_TOP. Signed-off-by: Heiko Stuebner Reviewed-by: Jonas Karlman Reviewed-by: Peter Robinson --- lib/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Kconfig b/lib/Kconfig index cf13ac1bdad..9e0f0ad7d06 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1298,7 +1298,7 @@ config SPL_LMB_ARCH_MEM_MAP config LMB_LIMIT_DMA_BELOW_RAM_TOP bool depends on LMB - default y if ARCH_BCM283X + default y if ARCH_BCM283X || ARCH_ROCKCHIP help Some architectures can not DMA above ram_top boundary, which is after 4 GiB or 32-bit boundary too. Limit the From 93e5ca926101b3ffabfbff25057a38fd17ff9ea0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 10 Jun 2026 20:20:57 +0200 Subject: [PATCH 48/65] ram: renesas: rtvram: Add support for Renesas R-Car Gen5 Add support for Renesas R-Car Gen5 R8A78000 SoC into RT-VRAM initialization driver. The changes are only a slight adjustment to the register programming, therefore reuse the existing RT-VRAM driver and parametrize those changes using driver data. Signed-off-by: Marek Vasut --- drivers/ram/renesas/dbsc5/rtvram.c | 44 +++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/drivers/ram/renesas/dbsc5/rtvram.c b/drivers/ram/renesas/dbsc5/rtvram.c index 6c149284bc6..bf30a207142 100644 --- a/drivers/ram/renesas/dbsc5/rtvram.c +++ b/drivers/ram/renesas/dbsc5/rtvram.c @@ -13,34 +13,41 @@ #define RTVRAM_VBUF_CFG 0x6504 #define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1 << 8) #define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6 << 0) +#define RTVRAM_VBUF_CFG_VBUF_SIZE_32M (7 << 0) #define RTVRAM_EXT_MODE 0x8500 #define RTVRAM_EXT_MODE_EXT BIT(0) #define RTVRAM_VBUF_BADDR 0xC580 -#define RTVRAM_VBUF_NUM 7 - -#define SDRAM_40BIT_ADDR_TOP 0x0400000000ULL #define RTVRAM_VBUF_AREA_SIZE SZ_4M struct renesas_dbsc5_rtvram_priv { void __iomem *regs; }; +struct renesas_dbsc5_rtvram_data { + u8 sdram_40bit_addr_top; /* Left-shift by 32 */ + u8 vbuf_num; + u8 size; + u8 size_bit; +}; + static int renesas_dbsc5_rtvram_probe(struct udevice *dev) { struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); + struct renesas_dbsc5_rtvram_data *data = + (struct renesas_dbsc5_rtvram_data *)dev_get_driver_data(dev); u64 addr; int i; /* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */ - for (i = 0; i < RTVRAM_VBUF_NUM; i++) { - addr = (SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16; + for (i = 0; i < data->vbuf_num + 1; i++) { + addr = (((u64)(data->sdram_40bit_addr_top) << 32ULL) + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16; writel(lower_32_bits(addr), priv->regs + (RTVRAM_VBUF_BADDR + (4 * i))); } /* Cache Mode: 8-way, VBF size: 28M */ setbits_le32(priv->regs + RTVRAM_VBUF_CFG, - RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M); + RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | data->size_bit); /* Change from Compatible Mode to Extended Mode */ writel(RTVRAM_EXT_MODE_EXT, priv->regs + RTVRAM_EXT_MODE); @@ -65,9 +72,11 @@ static int renesas_dbsc5_rtvram_get_info(struct udevice *dev, struct ram_info *info) { struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); + struct renesas_dbsc5_rtvram_data *data = + (struct renesas_dbsc5_rtvram_data *)dev_get_driver_data(dev); info->base = (phys_addr_t)priv->regs; - info->size = 28 * SZ_1M; + info->size = data->size * SZ_1M; return 0; } @@ -76,14 +85,29 @@ static const struct ram_ops renesas_dbsc5_rtvram_ops = { .get_info = renesas_dbsc5_rtvram_get_info, }; +struct renesas_dbsc5_rtvram_data gen4_rtvram_data = { + .sdram_40bit_addr_top = 0x4, + .vbuf_num = 7, + .size = 28, + .size_bit = RTVRAM_VBUF_CFG_VBUF_SIZE_28M, +}; + +struct renesas_dbsc5_rtvram_data gen5_rtvram_data = { + .sdram_40bit_addr_top = 0x12, + .vbuf_num = 8, + .size = 32, + .size_bit = RTVRAM_VBUF_CFG_VBUF_SIZE_32M, +}; + static const struct udevice_id renesas_dbsc5_rtvram_ids[] = { - { .compatible = "renesas,r8a779g0-rtvram" }, - { .compatible = "renesas,r8a779h0-rtvram" }, + { .compatible = "renesas,r8a779g0-rtvram", .data = (ulong)&gen4_rtvram_data }, + { .compatible = "renesas,r8a779h0-rtvram", .data = (ulong)&gen4_rtvram_data }, + { .compatible = "renesas,r8a78000-rtvram", .data = (ulong)&gen5_rtvram_data }, { /* sentinel */ } }; U_BOOT_DRIVER(renesas_dbsc5_rtvram) = { - .name = "rtvram", + .name = "dbsc5_rtvram", .id = UCLASS_RAM, .of_match = renesas_dbsc5_rtvram_ids, .of_to_plat = renesas_dbsc5_rtvram_of_to_plat, From a06d8334e5f4cd31392e13a168b20a95139b2f18 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 10 Jun 2026 20:20:58 +0200 Subject: [PATCH 49/65] ram: renesas: dbsc5: Add Renesas R-Car Gen5 DBSC5 driver Add Renesas R-Car Gen5 DBSC5 DRAM controller driver. This driver is currently capable of bringing LPDDR5X DRAM on Renesas R-Car X5H Ironhide board. Further boards can be supported by supplying board specific DRAM configuration data via dbsc5_get_board_data(). The driver reuses parts of previous DBSC5 driver, but due to hardware changes, can not be fully integrated into existing DBSC and DRAM driver, therefore the currentl DBSC and DRAM drivers are moved into R8A779G0 V4H specific files, and the R8A78000 X5H files are added in parallel. The Gen5 DBSC driver is meant to be used in RSIP context, while the Gen4 DBSC driver is meant to be used in SPL, therefore the Kconfig conditionals have been adjusted to match. Signed-off-by: Marek Vasut --- board/renesas/sparrowhawk/sparrowhawk.c | 2 +- drivers/ram/renesas/Kconfig | 6 +- drivers/ram/renesas/Makefile | 2 - drivers/ram/renesas/dbsc5/Makefile | 4 +- drivers/ram/renesas/dbsc5/ecc.c | 168 + drivers/ram/renesas/dbsc5/qos.c | 2 +- .../dbsc5/{dbsc5.c => r8a779g0-dbsc5.c} | 2 +- .../dbsc5/{dbsc5.h => r8a779g0-dbsc5.h} | 6 +- .../renesas/dbsc5/{dram.c => r8a779g0-dram.c} | 4 +- drivers/ram/renesas/dbsc5/r8a78000-dbsc5.c | 76 + drivers/ram/renesas/dbsc5/r8a78000-dbsc5.h | 17 + drivers/ram/renesas/dbsc5/r8a78000-dram.c | 2795 +++++++ drivers/ram/renesas/dbsc5/r8a78000-dram.h | 7385 +++++++++++++++++ include/{dbsc5.h => r8a779g0-dbsc5.h} | 0 include/r8a78000-dbsc5.h | 63 + 15 files changed, 10518 insertions(+), 14 deletions(-) create mode 100644 drivers/ram/renesas/dbsc5/ecc.c rename drivers/ram/renesas/dbsc5/{dbsc5.c => r8a779g0-dbsc5.c} (98%) rename drivers/ram/renesas/dbsc5/{dbsc5.h => r8a779g0-dbsc5.h} (80%) rename drivers/ram/renesas/dbsc5/{dram.c => r8a779g0-dram.c} (99%) create mode 100644 drivers/ram/renesas/dbsc5/r8a78000-dbsc5.c create mode 100644 drivers/ram/renesas/dbsc5/r8a78000-dbsc5.h create mode 100644 drivers/ram/renesas/dbsc5/r8a78000-dram.c create mode 100644 drivers/ram/renesas/dbsc5/r8a78000-dram.h rename include/{dbsc5.h => r8a779g0-dbsc5.h} (100%) create mode 100644 include/r8a78000-dbsc5.h diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c index f5b1a5614b1..a229542ba7e 100644 --- a/board/renesas/sparrowhawk/sparrowhawk.c +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -5,7 +5,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/ram/renesas/Kconfig b/drivers/ram/renesas/Kconfig index 6a1ef2a0c63..8c3e5fab96f 100644 --- a/drivers/ram/renesas/Kconfig +++ b/drivers/ram/renesas/Kconfig @@ -1,7 +1,7 @@ config RAM_RENESAS_DBSC5 - bool "Renesas R-Car V4H/V4M DBSC5 controller driver" - depends on SPL && RAM && (R8A779G0 || R8A779H0) + bool "Renesas R-Car V4H/V4M/X5H DBSC5 controller driver" + depends on RAM && (R8A78000 || (SPL && (R8A779G0 || R8A779H0))) default n help Enable this to support the DBSC5 DRAM controller initialization - on Renesas R8A779G0/R8A779H0 SoCs. + on Renesas R8A779G0/R8A779H0/R8A78000 SoCs. diff --git a/drivers/ram/renesas/Makefile b/drivers/ram/renesas/Makefile index 578d05622d7..699b726972b 100644 --- a/drivers/ram/renesas/Makefile +++ b/drivers/ram/renesas/Makefile @@ -1,6 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_XPL_BUILD obj-$(CONFIG_RAM_RENESAS_DBSC5) += dbsc5/ -endif obj-$(CONFIG_RZN1) += rzn1/ diff --git a/drivers/ram/renesas/dbsc5/Makefile b/drivers/ram/renesas/dbsc5/Makefile index 177be893e10..0ae2193e09b 100644 --- a/drivers/ram/renesas/dbsc5/Makefile +++ b/drivers/ram/renesas/dbsc5/Makefile @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-y += dbsc5.o dram.o qos.o rtvram.o +obj-$(CONFIG_R8A779G0) += r8a779g0-dbsc5.o r8a779g0-dram.o qos.o +obj-$(CONFIG_R8A78000) += r8a78000-dbsc5.o r8a78000-dram.o ecc.o +obj-y += rtvram.o diff --git a/drivers/ram/renesas/dbsc5/ecc.c b/drivers/ram/renesas/dbsc5/ecc.c new file mode 100644 index 00000000000..77295a696ab --- /dev/null +++ b/drivers/ram/renesas/dbsc5/ecc.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include + +#define DBSC5_DBSC_CNT 8 + +#define DBSC_D_BASE(n) (0xe9900000 + ((n) * 0x4000)) +#define DBSC_A_BASE(n) (0xe9800000 + ((n) * 0x8000)) +#define DBSYSCNT 0x100 +#define DBACEN 0x200 +#define DBFSINTENB02A 0x7088 +#define DBFSINTENB04A 0x7090 +#define DBFSCONFAXI0 0x7400 +#define DBFSDRAMECCAREA00 0x7450 +#define DBFSCTRL01A 0x7604 +#define DBFSCONF00A 0x7640 +#define DBFSCONF01A 0x7644 +#define DBFSCONF02A 0x7648 +#define DBFSSTAT00A 0x7680 +#define DBFSSTAT01A 0x7684 + +#define DBSYSCNT_ENABLE 0x1234 +#define DBSYSCNT_DISABLE 0x0 +#define DBACEN_ACCESS_DISABLE 0 +#define DBACEN_ACCESS_ENABLE 1 + +#define ECM_BASE 0xb89a0000 +#define ECMERRCTLR0 (ECM_BASE + 0x0) +#define ECMERRINCR0 (ECM_BASE + 0x200) +#define ECMERROMKR0 (ECM_BASE + 0x600) +#define ECMERRCTLR6 (ECM_BASE + (0x4 * 6)) +#define ECMERRINCR6 (ECM_BASE + 0x200U + (0x4 * 6)) +#define ECMERROMKR6 (ECM_BASE + 0x600U + (0x4 * 6)) +#define ECMWPCNTR (ECM_BASE + 0xa00) +#define ECMWACNTR (ECM_BASE + 0xa04) + +struct renesas_dbsc5_ecc_priv { + void __iomem *regs; +}; + +static void ecm_reg_unlock(void) +{ + writel(0xacce0001, ECMWPCNTR); +} + +static void ecm_reg_lock(void) +{ + writel(0xacce0000, ECMWPCNTR); +} + +static void ecm_reg_write(u32 adr, u32 val) +{ + writel(0xacce0000 | (adr & 0xffff), ECMWACNTR); + writel(val, adr); +} + +static int renesas_dbsc5_ecc_probe(struct udevice *dev) +{ + int i; + + ecm_reg_unlock(); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) { + writel(DBSYSCNT_ENABLE, DBSC_D_BASE(i) + DBSYSCNT); + writel(DBSYSCNT_ENABLE, DBSC_A_BASE(i) + DBSYSCNT); + } + + ecm_reg_write(ECMERRINCR0, readl(ECMERRINCR0) | 0xAAA); + ecm_reg_write(ECMERROMKR0, readl(ECMERROMKR0) | 0xAAA); + ecm_reg_write(ECMERRCTLR0, readl(ECMERRCTLR0) | 0xAAA); + ecm_reg_write(ECMERRINCR6, readl(ECMERRINCR6) | 0xA000); + ecm_reg_write(ECMERROMKR6, readl(ECMERROMKR6) | 0xA000); + ecm_reg_write(ECMERRCTLR6, readl(ECMERRCTLR6) | 0xA000); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0xcccc, DBSC_A_BASE(i) + DBFSDRAMECCAREA00); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(DBACEN_ACCESS_DISABLE, DBSC_A_BASE(i) + DBACEN); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0, DBSC_A_BASE(i) + DBFSCONF00A); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0, DBSC_A_BASE(i) + DBFSCONF01A); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0xcccb, DBSC_A_BASE(i) + DBFSCONF02A); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0x1, DBSC_A_BASE(i) + DBFSCTRL01A); + + u32 fsstat; + do { + fsstat = 0x1; + for (i = 0; i < DBSC5_DBSC_CNT; i++) + fsstat &= readl(DBSC_A_BASE(i) + DBFSSTAT01A); + } while (!(fsstat & 0x1)); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(DBACEN_ACCESS_ENABLE, DBSC_A_BASE(i) + DBACEN); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + setbits_le32(DBSC_A_BASE(i) + DBFSCONFAXI0, 0x100); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0xff00ff00, DBSC_A_BASE(i) + DBFSINTENB02A); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0xffffffff, DBSC_A_BASE(i) + DBFSINTENB04A); + + ecm_reg_lock(); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) { + writel(DBSYSCNT_DISABLE, DBSC_D_BASE(i) + DBSYSCNT); + writel(DBSYSCNT_DISABLE, DBSC_A_BASE(i) + DBSYSCNT); + } + + return 0; +} + +static int renesas_dbsc5_ecc_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_ecc_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +static int renesas_dbsc5_ecc_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct renesas_dbsc5_ecc_priv *priv = dev_get_priv(dev); + + info->base = (phys_addr_t)priv->regs; + info->size = 32 * SZ_1M; + + return 0; +} + +static const struct ram_ops renesas_dbsc5_ecc_ops = { + .get_info = renesas_dbsc5_ecc_get_info, +}; + +static const struct udevice_id renesas_dbsc5_ecc_ids[] = { + { .compatible = "renesas,r8a78000-ecc" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(renesas_dbsc5_ecc) = { + .name = "dbsc5_ecc", + .id = UCLASS_RAM, + .of_match = renesas_dbsc5_ecc_ids, + .of_to_plat = renesas_dbsc5_ecc_of_to_plat, + .ops = &renesas_dbsc5_ecc_ops, + .probe = renesas_dbsc5_ecc_probe, + .priv_auto = sizeof(struct renesas_dbsc5_ecc_priv), +}; diff --git a/drivers/ram/renesas/dbsc5/qos.c b/drivers/ram/renesas/dbsc5/qos.c index 56a60b987af..a9fc0b1439a 100644 --- a/drivers/ram/renesas/dbsc5/qos.c +++ b/drivers/ram/renesas/dbsc5/qos.c @@ -9,7 +9,7 @@ #include #include #include -#include "dbsc5.h" +#include "r8a779g0-dbsc5.h" /* AXMM */ #define AXMM_ADSPLCR0 0x4008 diff --git a/drivers/ram/renesas/dbsc5/dbsc5.c b/drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.c similarity index 98% rename from drivers/ram/renesas/dbsc5/dbsc5.c rename to drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.c index 4cbc6aeda43..b57c885fc59 100644 --- a/drivers/ram/renesas/dbsc5/dbsc5.c +++ b/drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.c @@ -10,7 +10,7 @@ #include #include #include -#include "dbsc5.h" +#include "r8a779g0-dbsc5.h" static int renesas_dbsc5_probe(struct udevice *dev) { diff --git a/drivers/ram/renesas/dbsc5/dbsc5.h b/drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.h similarity index 80% rename from drivers/ram/renesas/dbsc5/dbsc5.h rename to drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.h index bf22fcb8c11..592c9badbd7 100644 --- a/drivers/ram/renesas/dbsc5/dbsc5.h +++ b/drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.h @@ -3,8 +3,8 @@ * Copyright (C) 2024 Renesas Electronics Corp. */ -#ifndef __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ -#define __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ +#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__ +#define __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__ /* * DBSC5 ... 0xe678_0000..0xe67fffff @@ -26,4 +26,4 @@ struct renesas_dbsc5_data { const char *otp_node; }; -#endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */ +#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__ */ diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/r8a779g0-dram.c similarity index 99% rename from drivers/ram/renesas/dbsc5/dram.c rename to drivers/ram/renesas/dbsc5/r8a779g0-dram.c index 3ed02e11f9e..8dd4e321849 100644 --- a/drivers/ram/renesas/dbsc5/dram.c +++ b/drivers/ram/renesas/dbsc5/r8a779g0-dram.c @@ -4,14 +4,14 @@ */ #include -#include +#include #include #include #include #include #include #include -#include "dbsc5.h" +#include "r8a779g0-dbsc5.h" /* Number of array elements in Data Slice */ #define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100 diff --git a/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.c b/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.c new file mode 100644 index 00000000000..b6b4ed8a5c0 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "r8a78000-dbsc5.h" + +static int renesas_dbsc5_probe(struct udevice *dev) +{ + struct udevice *ddev, *vdev, *edev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_dram", &ddev); + if (ret) + return ret; + + ret = uclass_get_device_by_name(UCLASS_RAM, "ram@b8940000", &vdev); + if (ret) + return ret; + + ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_ecc", &edev); + if (ret) + return ret; + + return 0; +} + +int renesas_dbsc5_bind(struct udevice *dev) +{ + struct udevice *ramdev, *eccdev; + struct driver *ramdrv, *eccdrv; + int ret; + + ramdrv = lists_driver_lookup_name("dbsc5_dram"); + if (!ramdrv) + return -ENOENT; + + eccdrv = lists_driver_lookup_name("dbsc5_ecc"); + if (!eccdrv) + return -ENOENT; + + ret = device_bind_with_driver_data(dev, ramdrv, "dbsc5_dram", + dev_get_driver_data(dev), + dev_ofnode(dev), &ramdev); + if (ret) + return ret; + + ret = device_bind_with_driver_data(dev, eccdrv, "dbsc5_ecc", 0, + dev_ofnode(dev), &eccdev); + if (ret) + device_unbind(ramdev); + + return ret; +} + +static const struct udevice_id renesas_dbsc5_ids[] = { + { .compatible = "renesas,r8a78000-dbsc", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(renesas_dbsc5) = { + .name = "dbsc5", + .id = UCLASS_NOP, + .of_match = renesas_dbsc5_ids, + .bind = renesas_dbsc5_bind, + .probe = renesas_dbsc5_probe, +}; diff --git a/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.h b/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.h new file mode 100644 index 00000000000..b8c9a6f81fa --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__ +#define __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__ + +struct renesas_dbsc5_data { + const char *clock_node; + const char *reset_node; + const char *otp_node; +}; + +#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__ */ diff --git a/drivers/ram/renesas/dbsc5/r8a78000-dram.c b/drivers/ram/renesas/dbsc5/r8a78000-dram.c new file mode 100644 index 00000000000..f1c12901d52 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a78000-dram.c @@ -0,0 +1,2795 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "r8a78000-dbsc5.h" +#include "r8a78000-dram.h" + +#define DBSC5_PHYNUM_CNT 8 +#define DBSC5_DBSC_CNT 8 +#define DBSC5_PLL3_CNT 4 + +/* Minimum value table for JS1 configuration table that can be taken */ +#define JS1_USABLEC_SPEC_LO 5 +/* Maximum value table for JS1 configuration table that can be taken */ +#define JS1_USABLEC_SPEC_HI 14 +/* The number of JS1 setting table */ +#define JS1_FREQ_TBL_NUM 15 +/* Macro to set the value of MR1 */ +#define JS1_MR1(f) ((f) << 4) /* CK mode = 0B */ +/* Macro to set the value of MR2 */ +#define JS1_MR2(f) (((f) << 4) | (f)) + +#define JS2_tSR 0 /* Element for self refresh */ +#define JS2_tXP 1 /* Exit power-down mode to first valid command */ +#define JS2_tRCD 2 /* Active to read or write delay */ +#define JS2_tRPpb 3 /* Minimum Row Precharge Delay Time */ +#define JS2_tRPab 4 /* Minimum Row Precharge Delay Time */ +#define JS2_tRAS 5 /* ACTIVE-to-PRECHARGE command */ +#define JS2_tWTR_S 6 /* Internal WRITE-to-READ command delay */ +#define JS2_tWTR_L 7 /* Internal WRITE-to-READ command delay */ +#define JS2_tRRD 8 /* Active bank a to active bank b command */ +#define JS2_tPPD 9 /* Precharge Power Down */ +#define JS2_tFAW 10 /* Four bank ACT window */ +#define JS2_tMRR 11 /* Mode Register Read */ +#define JS2_tMRW 12 /* Mode Register Write */ +#define JS2_tMRD 13 /* LOAD MODE REGISTER command cycle time */ +#define JS2_tZQCALns 14 /* ZQ Calibration */ +#define JS2_tZQLAT 15 /* ZQ Latency */ +#define JS2_tODTon_min 16 /* Minimum time on die termination */ +#define JS2_tPDN_DSM 17 /* Recommended minimum time for Deep Sleep Mode duration */ +#define JS2_tXSR_DSM 18 /* Required time to be fully re-powered up from Deep Sleep Mode */ +#define JS2_tXDSM_XP 19 /* Delay from Deep Sleep Mode Exit to Power-Down Exit */ +#define JS2_tWCK2DQI_HF 20 /* Setting value of DQ to WCK input offset */ +#define JS2_tWCK2DQO_HF 21 /* Setting value of WCK to DQ output offset */ +#define JS2_tWCK2DQI_LF 22 /* Setting value of DQ to WCK input offset */ +#define JS2_tWCK2DQO_LF 23 /* Setting value of WCK to DQ output offset */ +#define JS2_tOSCODQI 24 /* Delay time from Stop WCK2DQI Interval Oscillator command to Mode Register Readout */ +#define JS2_tOSCODQO 25 +#define JS2_tDQ72DQns 26 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode2 */ +#define JS2_tCAENTns 27 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode1 */ +#define JS2_tCSCAL 28 /* Minimum CA Low Duration time */ +#define JS2_tWCKSTOP 29 +#define JS2_tpbR2act 30 +#define JS2_TBLCNT 31 /* The number of table */ + +#define JS2_tRCpb JS2_TBLCNT /* ACTIVATE-to-ACTIVATE command period with per bank precharge */ +#define JS2_tRCab (JS2_TBLCNT + 1) /* ACTIVATE-to-ACTIVATE command period with all bank precharge */ +#define JS2_tRFCab (JS2_TBLCNT + 2) /* Refresh Cycle Time with All Banks */ +#define JS2_tRBTP (JS2_TBLCNT + 3) /* READ Burst end to PRECHARGE command delay */ +#define JS2_tXSR (JS2_TBLCNT + 4) /* Exit Self Refresh to Valid commands */ +#define JS2_tPDN (JS2_TBLCNT + 5) +#define JS2_tWLWCKOFF (JS2_TBLCNT + 6) +#define JS2_tRFCpb (JS2_TBLCNT + 7) +#define JS2_tpbR2pbR (JS2_TBLCNT + 8) +#define JS2_tRFMab (JS2_TBLCNT + 9) +#define JS2_tRFMpb (JS2_TBLCNT + 10) +#define JS2_CNT (JS2_TBLCNT + 11) + +#define JS2_DERATE 0 +#define DBSC_REFINT 1920 +#define PERIODIC_TRAINING_INTERVAL 20000 + +#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) \ + (((d3) << 30) | ((row) << 24) | ((BG) << 20) | \ + ((bank) << 16) | ((col) << 8) | (dw)) + +#define DBMEMCONF_REGD(density) \ + (DBMEMCONF_REG(((density) % 2), (((density) + 1) / 2) + (28 - 2 - 2 - 10 - 1), \ + 2, 2, 10, 1)) + +struct jedec_spec1 { + u32 fx3; + u32 RLset0; + u32 RLset1; + u32 RLset2; + u32 WLsetA; + u32 WLsetB; + u32 nWR; + u32 nRBTP; + u32 ODTLon; + u32 MR1; + u32 MR2; + u32 WCKENLR0; + u32 WCKENLR1; + u32 WCKENLW; + u32 WCKENLF; + u32 WCKPRESTA; + u32 WCKPRETGLR; + u32 tRRD; + u32 tFAW; +}; + +static const struct jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { + /* fx3,RL0,RL1,RL2,WLA.WLB.nWR.nRBTP,ODTLon */ + { 800, 3, 3, 3, 2, 2, 3, 0, 1, JS1_MR1(0), JS1_MR2(0), 0, 0, 0, 0, 1, 3, 3750, 15000 }, /* 533.333Mbps */ + { 1600, 4, 4, 4, 2, 3, 5, 0, 1, JS1_MR1(1), JS1_MR2(1), 0, 0, 0, 0, 1, 4, 3750, 15000 }, /* 1066.666Mbps */ + { 2400, 5, 5, 6, 3, 4, 7, 0, 2, JS1_MR1(2), JS1_MR2(2), 1, 1, 1, 1, 1, 4, 3750, 15000 }, /* 1600.000Mbps */ + { 3200, 6, 7, 7, 4, 5, 10, 0, 2, JS1_MR1(3), JS1_MR2(3), 1, 2, 1, 1, 2, 4, 3750, 15000 }, /* 2133.333Mbps */ + { 4000, 8, 8, 9, 4, 7, 12, 1, 2, JS1_MR1(4), JS1_MR2(4), 2, 2, 1, 1, 2, 5, 3750, 15000 }, /* 2666.666Mbps */ + { 4800, 9, 10, 10, 5, 8, 14, 1, 3, JS1_MR1(5), JS1_MR2(5), 3, 4, 2, 1, 2, 5, 3750, 15000 }, /* 3200.000Mbps */ + { 5600, 10, 11, 12, 6, 9, 16, 2, 4, JS1_MR1(6), JS1_MR2(6), 3, 4, 2, 1, 3, 5, 3750, 15000 }, /* 3733.333Mbps */ + { 6400, 12, 13, 14, 6, 11, 19, 2, 3, JS1_MR1(7), JS1_MR2(7), 4, 5, 2, 1, 3, 6, 3750, 15000 }, /* 4266.666Mbps */ + { 7200, 13, 14, 15, 7, 12, 21, 3, 4, JS1_MR1(8), JS1_MR2(8), 5, 6, 3, 2, 3, 6, 3750, 15000 }, /* 4800.000Mbps */ + { 8250, 15, 16, 17, 8, 14, 24, 4, 5, JS1_MR1(9), JS1_MR2(9), 6, 7, 3, 2, 4, 6, 3750, 15000 }, /* 5500.000Mbps */ + { 9000, 16, 17, 19, 9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 6, 7, 4, 2, 4, 7, 3750, 15000 }, /* 6000.000Mbps */ + { 9600, 17, 18, 20, 9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 7, 8, 4, 2, 4, 7, 3750, 15000 }, /* 6400.000Mbps */ + { 11250, 20, 22, 24, 11, 19, 32, 6, 7, JS1_MR1(12), JS1_MR2(12), 7, 9, 5, 3, 5, 9, 3750, 15000 }, /* 7500.000Mbps */ + { 12800, 23, 25, 26, 12, 22, 37, 6, 8, JS1_MR1(13), JS1_MR2(13), 8, 10, 5, 3, 6, 10, 3750, 15000 }, /* 8533.333Mbps */ + { 14400, 25, 28, 29, 14, 24, 41, 7, 9, JS1_MR1(14), JS1_MR2(14), 8, 11, 6, 3, 7, 11, 3330, 13320 } /* 9600.000Mbps */ +}; + +struct jedec_spec2 { + u32 ps; + u32 cyc; +}; + +static const struct jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { + { + { 15000, 2 }, /* tSR */ + { 7000, 3 }, /* tXP */ + { 18000, 2 }, /* tRCD */ + { 18000, 2 }, /* tRPpb */ + { 21000, 2 }, /* tRPab */ + { 42000, 3 }, /* tRAS */ + { 6250, 4 }, /* tWTR_S */ + { 12000, 4 }, /* tWTR_L */ + { 0, 2 }, /* tRRD */ + { 0, 2 }, /* tPPD */ + { 0, 0 }, /* tFAW */ + { 0, 4 }, /* tMRR */ + { 10000, 5 }, /* tMRW */ + { 14000, 5 }, /* tMRD */ + { 1500, 0 }, /* tZQCALns */ + { 30000, 4 }, /* tZQLAT */ + { 1500, 0 }, /* tODTon_min */ + { 4000, 0 }, /* tPDN_DSMus */ + { 200, 0 }, /* tXSR_DSMus */ + { 190, 0 }, /* tXDSM_XPus */ + { 700, 0 }, /* tWCK2DQI_HF */ + { 1600, 0 }, /* tWCK2DQO_HF */ + { 900, 0 }, /* tWCK2DQI_LF */ + { 1900, 0 }, /* tWCK2DQO_LF */ + { 40000, 8 }, /* tOSCODQI */ + { 40000, 8 }, /* tOSCODQO */ + { 125, 0 }, /* tDQ72DQns */ + { 250, 0 }, /* tCAENTns */ + { 1750, 0 }, /* tCSCAL */ + { 6000, 2 }, /* tWCKSTOP */ + { 7500, 0 }, /* tpbR2act */ + }, { + { 15000, 2 }, /* tSR */ + { 7000, 3 }, /* tXP */ + { 19875, 2 }, /* tRCD */ + { 19875, 2 }, /* tRPpb */ + { 22875, 2 }, /* tRPab */ + { 43875, 3 }, /* tRAS */ + { 6250, 4 }, /* tWTR_S */ + { 12000, 4 }, /* tWTR_L */ + { 0, 2 }, /* tRRD */ + { 0, 2 }, /* tPPD */ + { 0, 0 }, /* tFAW */ + { 0, 4 }, /* tMRR */ + { 10000, 5 }, /* tMRW */ + { 14000, 5 }, /* tMRD */ + { 1500, 0 }, /* tZQCALns */ + { 30000, 4 }, /* tZQLAT */ + { 1500, 0 }, /* tODTon_min */ + { 4000, 0 }, /* tPDN_DSMus */ + { 200, 0 }, /* tXSR_DSMus */ + { 190, 0 }, /* tXDSM_XPus */ + { 715, 0 }, /* tWCK2DQI_HF */ + { 1635, 0 }, /* tWCK2DQO_HF */ + { 920, 0 }, /* tWCK2DQI_LF */ + { 1940, 0 }, /* tWCK2DQO_LF */ + { 40000, 8 }, /* tOSCODQI */ + { 40000, 8 }, /* tOSCODQO */ + { 125, 0 }, /* tDQ72DQns */ + { 250, 0 }, /* tCAENTns */ + { 1750, 0 }, /* tCSCAL */ + { 6000, 2 }, /* tWCKSTOP */ + { 7500, 0 }, /* tpbR2act */ + } +}; + +static const u32 jedec_spec2_tRFC_ab[9] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 130, 180, 180, 210, 210, 280, 280, 380, 380 +}; + +static const u32 jedec_spec2_tRFC_pb[9] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 60, 90, 90, 120, 120, 140, 140, 190, 190 +}; + +static const u32 jedec_spec2_tpbR2pbR[9] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 60, 90, 90, 90, 90, 90, 90, 90, 90 +}; + +static const u32 jedec_spec2_tRFM_ab[9] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 0, 0, 0, 0, 210, 280, 280, 380, 380 +}; + +static const u32 jedec_spec2_tRFM_pb[9] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 0, 0, 0, 0, 170, 190, 190, 260, 260 +}; + +/* System registers */ +#define SYSSS_TOP_BASE 0xc6480000 +#define SYSSS_ZB3CKCR0 (SYSSS_TOP_BASE + 0x10a0) +#define SYSSS_ZB3CKCR1 (SYSSS_TOP_BASE + 0x10a4) +#define SYSSS_ZB3CKCR_KICK BIT(31) +#define SYSSS_ZB3CKCR_PHYx(ch) ((0x7 * ((ch) & 0x1)) + (0x8 * ((ch) & 0x2))) +#define SYSSS_PLL1_1_CR0 (SYSSS_TOP_BASE + 0x1114) +#define SYSSS_PLL1_1DCR (SYSSS_TOP_BASE + 0x127c) +#define SYSSS_PLL3_x_CR0(ch) (SYSSS_TOP_BASE + 0x1180 + ((ch) * 0xc)) +#define SYSSS_PLL3_x_CR1(ch) (SYSSS_TOP_BASE + 0x1184 + ((ch) * 0xc)) +#define SYSSS_PLL3_x_CR2(ch) (SYSSS_TOP_BASE + 0x1188 + ((ch) * 0xc)) +#define SYSSS_PLL3_x_DCR(ch) (SYSSS_TOP_BASE + 0x12c4 + ((ch) * 0x8)) +#define SYSSS_PLL6_CR0 (SYSSS_TOP_BASE + 0x11c8) +#define SYSSS_PLL3_xSCR(ch) (SYSSS_TOP_BASE + 0x12c0 + ((ch) * 0x8)) +#define SYSSS_CLKTOPPKCPROT0 (SYSSS_TOP_BASE + 0x1370) +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) + +/* MDLC registers */ +#define MODULE_CONTROL_DDRx_BASE(ch) (0xe8000000 + ((ch) * 0x80000)) +#define MODULE_CONTROL_DDRFI_BASE 0xc6480000 +#define MODULE_CONTROL_MDLC12PKCPROT1 (MODULE_CONTROL_DDRFI_BASE + 0xCF4) +#define MODULE_CONTROL_MDLC0xPKCPROT1(ch) (MODULE_CONTROL_DDRx_BASE(ch) + 0xCF4) +#define MODULE_CONTROL_MDLC15MSRES8 (MODULE_CONTROL_DDRFI_BASE + 0x920) +#define MODULE_CONTROL_MDLC0xMSRES1(ch) (MODULE_CONTROL_DDRx_BASE(ch) + 0x904) +#define MODULE_CONTROL_MDLC0xMSRES3(ch) (MODULE_CONTROL_DDRx_BASE(ch) + 0x90C) +#define MODULE_CONTROL_MDLC15MSRESS8 (MODULE_CONTROL_DDRFI_BASE + 0x980) +#define MODULE_CONTROL_MDLC0xMSRESS1(ch) (MODULE_CONTROL_DDRx_BASE(ch) + 0x964) +#define MODULE_CONTROL_MDLC0xMSRESS3(ch) (MODULE_CONTROL_DDRx_BASE(ch) + 0x96C) +#define MODULE_STANDBY 0 +#define MODULE_RUN 3 + +/* DBSC5 registers */ +#define DBSC_A_BASE 0xE9800000 +#define DBSC_D_BASE 0xE9900000 + +#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0) +#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0) +#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x4) +#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x4) +#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x8) +#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x8) +#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x20) +#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x20) +#define DBSC_DBMEMCONF(ch, cs) \ + (DBSC_D_BASE + 0x30 + (0x2000 * ((ch) & 0xE)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) +#define DBSC_DBMEMCONFA(ch, cs) \ + (DBSC_A_BASE + 0x30 + (0x4000 * ((ch) & 0xE)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) +#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x100) +#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x100) +#define DBSC_DBSYSCNT1A (DBSC_A_BASE + 0x104) +#define DBSC_DBACEN (DBSC_A_BASE + 0x200) +#define DBSC_DBRFEN (DBSC_D_BASE + 0x204) +#define DBSC_DBCMD (DBSC_D_BASE + 0x208) +#define DBSC_DBWAIT (DBSC_D_BASE + 0x210) +#define DBSC_DBTR(x) (DBSC_D_BASE + 0x300 + (0x4 * (x))) +#define DBSC_DBBL (DBSC_D_BASE + 0x400) +#define DBSC_DBBLA (DBSC_A_BASE + 0x400) +#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x414) +#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x418) +#define DBSC_DBCALCNF (DBSC_D_BASE + 0x424) +#define DBSC_DBSNOOPC (DBSC_D_BASE + 0x42C) +#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x430 + (0x4 * (x))) +#define DBSC_DBDBICNT (DBSC_D_BASE + 0x518) +#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x520) +#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x540) +#define DBSC_DBDFISTAT(ch) \ + (DBSC_D_BASE + 0x600 + (0x2000 * ((ch) & 0xE)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBDFICNT(ch) \ + (DBSC_D_BASE + 0x604 + (0x2000 * ((ch) & 0xE)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDSTAT01(ch) (DBSC_D_BASE + 0x634 + (0x4000 * (ch))) +#define DBSC_DBBUS0CNF1 (DBSC_A_BASE + 0x804) +#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x9FC) +#define DBSC_DBSCHRW(x) (DBSC_A_BASE + 0x1020 + (0x4 * (x))) +#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030) +#define DBSC_DBSCHFCTST(x) (DBSC_A_BASE + 0x1040 + (0x4 * (x))) + +/* DDR PHY registers */ +#define DDR_PHY_BASE(ch) (0xA0000000 + (0x1000000 * (ch))) +#define DDR_PHY_DMA_TRANS_BASE(ch) (0xE0000000 + (0x1000000 * (ch))) + +#define PHY_HMAC_BASE(n) ((n) * 0x1000) +#define PHY_HMAC_TXSLEWAC(n) (PHY_HMAC_BASE(n) + 0x6d) +#define PHY_HMAC_TXIMPEDANCEAC(n) (PHY_HMAC_BASE(n) + 0x70) +#define PHY_HMAC_ODTIMPEDANCEAC(n) (PHY_HMAC_BASE(n) + 0x79) + +#define PHY_DBYTE_BASE(n) (0x10000 + ((n) * 0x1000)) +#define PHY_DBYTE_ENABLEWRITELINKECC(n) (PHY_DBYTE_BASE(n) + 0x01) +#define PHY_DBYTE_DQ0LNSEL(n) (PHY_DBYTE_BASE(n) + 0x80) +#define PHY_DBYTE_DQ1LNSEL(n) (PHY_DBYTE_BASE(n) + 0x81) +#define PHY_DBYTE_DQ2LNSEL(n) (PHY_DBYTE_BASE(n) + 0x82) +#define PHY_DBYTE_DQ3LNSEL(n) (PHY_DBYTE_BASE(n) + 0x83) +#define PHY_DBYTE_DQ4LNSEL(n) (PHY_DBYTE_BASE(n) + 0x84) +#define PHY_DBYTE_DQ5LNSEL(n) (PHY_DBYTE_BASE(n) + 0x85) +#define PHY_DBYTE_DQ6LNSEL(n) (PHY_DBYTE_BASE(n) + 0x86) +#define PHY_DBYTE_DQ7LNSEL(n) (PHY_DBYTE_BASE(n) + 0x87) +#define PHY_DBYTE_DQ8LNSEL(n) (PHY_DBYTE_BASE(n) + 0x88) +#define PHY_DBYTE_PPTCTLSTATIC(n) (PHY_DBYTE_BASE(n) + 0xa3) + +#define PHY_AC_BASE(n) (0x30000 + ((n) * 0x1000)) +#define PHY_AC_MAPCA0TODFI(n) (PHY_AC_BASE(n) + 0x90) +#define PHY_AC_MAPCA1TODFI(n) (PHY_AC_BASE(n) + 0x91) +#define PHY_AC_MAPCA2TODFI(n) (PHY_AC_BASE(n) + 0x92) +#define PHY_AC_MAPCA3TODFI(n) (PHY_AC_BASE(n) + 0x93) +#define PHY_AC_MAPCA4TODFI(n) (PHY_AC_BASE(n) + 0x94) +#define PHY_AC_MAPCA5TODFI(n) (PHY_AC_BASE(n) + 0x95) +#define PHY_AC_MAPCA6TODFI(n) (PHY_AC_BASE(n) + 0x96) +#define PHY_AC_ACLNDISABLE(n) (PHY_AC_BASE(n) + 0xac) +#define PHY_AC_DFICLKACLNDIS(n) (PHY_AC_BASE(n) + 0xad) +#define PHY_AC_PCLKACLNDIS(n) (PHY_AC_BASE(n) + 0xae) + +#define PHY_APB_BASE 0x58000 +#define PHY_APB_DRAMFREQ (PHY_APB_BASE + 0x01) +#define PHY_APB_DCAOPTS (PHY_APB_BASE + 0x02) +#define PHY_APB_SEQUENCECTRL (PHY_APB_BASE + 0x04) +#define PHY_APB_HDTCTRL (PHY_APB_BASE + 0x04) +#define PHY_APB_RXDFEOPT (PHY_APB_BASE + 0x07) +#define PHY_APB_CSPRESENTCHA (PHY_APB_BASE + 0x09) +#define PHY_APB_CSPRESENTCHB (PHY_APB_BASE + 0x10) +#define PHY_APB_MR1_A0 (PHY_APB_BASE + 0x16) +#define PHY_APB_MR1_A1 (PHY_APB_BASE + 0x16) +#define PHY_APB_MR1_B0 (PHY_APB_BASE + 0x17) +#define PHY_APB_MR1_B1 (PHY_APB_BASE + 0x17) +#define PHY_APB_MR2_A0 (PHY_APB_BASE + 0x17) +#define PHY_APB_MR2_A1 (PHY_APB_BASE + 0x17) +#define PHY_APB_MR2_B0 (PHY_APB_BASE + 0x18) +#define PHY_APB_MR2_B1 (PHY_APB_BASE + 0x18) +#define PHY_APB_MR3_A0 (PHY_APB_BASE + 0x18) +#define PHY_APB_MR3_A1 (PHY_APB_BASE + 0x18) +#define PHY_APB_MR3_B0 (PHY_APB_BASE + 0x19) +#define PHY_APB_MR3_B1 (PHY_APB_BASE + 0x19) +#define PHY_APB_MR11_A0 (PHY_APB_BASE + 0x1A) +#define PHY_APB_MR11_A1 (PHY_APB_BASE + 0x1A) +#define PHY_APB_MR11_B0 (PHY_APB_BASE + 0x1B) +#define PHY_APB_MR11_B1 (PHY_APB_BASE + 0x1B) +#define PHY_APB_MR12_A0 (PHY_APB_BASE + 0x1B) +#define PHY_APB_MR12_A1 (PHY_APB_BASE + 0x1B) +#define PHY_APB_MR12_B0 (PHY_APB_BASE + 0x1C) +#define PHY_APB_MR12_B1 (PHY_APB_BASE + 0x1C) +#define PHY_APB_MR22_A0 (PHY_APB_BASE + 0x25) +#define PHY_APB_MR22_A1 (PHY_APB_BASE + 0x25) +#define PHY_APB_MR22_B0 (PHY_APB_BASE + 0x26) +#define PHY_APB_MR22_B1 (PHY_APB_BASE + 0x26) +#define PHY_APB_MR24_A0 (PHY_APB_BASE + 0x26) +#define PHY_APB_MR24_A1 (PHY_APB_BASE + 0x26) +#define PHY_APB_MR24_B0 (PHY_APB_BASE + 0x27) +#define PHY_APB_MR24_B1 (PHY_APB_BASE + 0x27) +#define PHY_APB_MR41_A0 (PHY_APB_BASE + 0x32) +#define PHY_APB_MR41_A1 (PHY_APB_BASE + 0x32) +#define PHY_APB_MR41_B0 (PHY_APB_BASE + 0x33) +#define PHY_APB_MR41_B1 (PHY_APB_BASE + 0x33) +#define PHY_APB_MR58_A0 (PHY_APB_BASE + 0x34) +#define PHY_APB_MR58_A1 (PHY_APB_BASE + 0x34) +#define PHY_APB_MR58_B0 (PHY_APB_BASE + 0x35) +#define PHY_APB_MR58_B1 (PHY_APB_BASE + 0x35) +#define PHY_APB_TXDFETRAINOPT (PHY_APB_BASE + 0x3E) +#define PHY_APB_UPPERLOWERBYTE (PHY_APB_BASE + 0x48) +#define PHY_APB_ALT_RL (PHY_APB_BASE + 0x48) +#define PHY_APB_MAIN_RL (PHY_APB_BASE + 0x49) +#define PHY_APB_RXVREFSTARTPAT (PHY_APB_BASE + 0x4E) +#define PHY_APB_RXVREFSTARTPRBS (PHY_APB_BASE + 0x4E) +#define PHY_APB_RXVREFENDPAT (PHY_APB_BASE + 0x4F) +#define PHY_APB_RXVREFENDPRBS (PHY_APB_BASE + 0x4F) +#define PHY_APB_RXVREFSTEPPAT (PHY_APB_BASE + 0x50) +#define PHY_APB_TXVREFSTART (PHY_APB_BASE + 0x50) +#define PHY_APB_TXVREFEND (PHY_APB_BASE + 0x50) +#define PHY_APB_TXVREFSTEP (PHY_APB_BASE + 0x51) +#define PHY_APB_RXVREFSTEPPRBS (PHY_APB_BASE + 0x51) +#define PHY_APB_RXDFEBITTIMECONTROL (PHY_APB_BASE + 0x59) + +#define PHY_HMMAS_BASE 0x60000 +#define PHY_HMMAS_CPLLCTRL1 (PHY_HMMAS_BASE + 0x05) +#define PHY_HMMAS_CPLLCTRL4 (PHY_HMMAS_BASE + 0x07) +#define PHY_HMMAS_CPLLCTRL5 (PHY_HMMAS_BASE + 0x08) +#define PHY_HMMAS_CPLLUPLLPROG0 (PHY_HMMAS_BASE + 0x0d) +#define PHY_HMMAS_CPLLUPLLPROG1 (PHY_HMMAS_BASE + 0x0e) +#define PHY_HMMAS_CPLLUPLLPROG2 (PHY_HMMAS_BASE + 0x0f) +#define PHY_HMMAS_CPLLUPLLPROG3 (PHY_HMMAS_BASE + 0x10) + +#define PHY_PPGC_BASE 0x70000 +#define PHY_PPGC_ACSMDONE (PHY_PPGC_BASE + 0x121) +#define PHY_PPGC_ACSMSTARTADDRXLATVAL0 (PHY_PPGC_BASE + 0x324) +#define PHY_PPGC_ACSMSTOPADDRXLATVAL0 (PHY_PPGC_BASE + 0x38b) +#define PHY_PPGC_HWTLPCSENA (PHY_PPGC_BASE + 0x072) +#define PHY_PPGC_HWTLPCSENB (PHY_PPGC_BASE + 0x073) +#define PHY_PPGC_HWTCONTROLVAL (PHY_PPGC_BASE + 0x07e) +#define PHY_PPGC_ACSMRPTCNTOVERRIDE (PHY_PPGC_BASE + 0x145) +#define PHY_PPGC_ACSMNOPADDR (PHY_PPGC_BASE + 0x18a) + +#define PHY_INITENG_BASE 0x90000 +#define PHY_INITENG_SEQ0BDISABLEFLAG0 (PHY_INITENG_BASE + 0x70c) +#define PHY_INITENG_SEQ0BGPR1 (PHY_INITENG_BASE + 0x801) +#define PHY_INITENG_SEQ0BDLY0 (PHY_INITENG_BASE + 0x8e0) +#define PHY_INITENG_SEQ0BGPR14 (PHY_INITENG_BASE + 0x80e) +#define PHY_INITENG_SEQ0BGPR15 (PHY_INITENG_BASE + 0x80f) + +#define PHY_DRTUB_BASE 0xc0000 +#define PHY_DRTUB_PIEINITVECSEL (PHY_DRTUB_BASE + 0x01) +#define PHY_DRTUB_UCCLKHCLKENABLES (PHY_DRTUB_BASE + 0x80) +#define PHY_DRTUB_STARTDCCMCLEAR (PHY_DRTUB_BASE + 0x88) + +#define PHY_APBONLY_BASE 0xd0000 +#define PHY_APBONLY_MICROCONTMUXSEL (PHY_APBONLY_BASE + 0x00) +#define PHY_APBONLY_UCTSHADOWREGS (PHY_APBONLY_BASE + 0x04) +#define PHY_APBONLY_DCTWRITEPROT (PHY_APBONLY_BASE + 0x31) +#define PHY_APBONLY_UCTWRITEONLYSHADOW (PHY_APBONLY_BASE + 0x32) +#define PHY_APBONLY_UCTDATWRITEONLYSHADOW (PHY_APBONLY_BASE + 0x34) +#define PHY_APBONLY_MICRORESET (PHY_APBONLY_BASE + 0x99) +#define PHY_APBONLY_SEQUENCEROVERRIDE (PHY_APBONLY_BASE + 0xe7) + +#define PHY_HMDBYTE_BASE(n) (0xe0000 + ((n) * 0x1000)) +#define PHY_HMDBYTE_VREGCTRL1DQ(n) (PHY_HMDBYTE_BASE(n) + 0x00) +#define PHY_HMDBYTE_TXDQSLEW(n) (PHY_HMDBYTE_BASE(n) + 0x1c) +#define PHY_HMDBYTE_TXIMPEDANCEDQ(n) (PHY_HMDBYTE_BASE(n) + 0x2c) +#define PHY_HMDBYTE_TXIMPEDANCEDQS(n) (PHY_HMDBYTE_BASE(n) + 0x2d) +#define PHY_HMDBYTE_ODTIMPEDANCEDQ(n) (PHY_HMDBYTE_BASE(n) + 0x2e) +#define PHY_HMDBYTE_ODTIMPEDANCEDQS(n) (PHY_HMDBYTE_BASE(n) + 0x2f) + +/* RENESAS X5H Board (64Gb 1rank x 4pcs) */ +static const struct renesas_dbsc5_board_config renesas_x5h_dbsc5_board_config = { + .bdcfg_phyvalid = 0xffff, + .bdcfg_tx_drv = 0x77777, + .bdcfg_tx_ffc = 0x30000000, + .bdcfg_rx_odt = 0x33333, + .bdcfg_rx_dfe = 0x0, + .bdcfg_tx_odt = 0x43, + .bdcfg_tx_ntodt = 0x3, + .bdcfg_tx_dfe = 0x0, + .bdcfg_rx_dca = 0x1, + .bdcfg_rx_drv = 0x6, + .bdcfg_rx_emphasis = 0x0, + .bdcfg_tx_dca = 0x1, + .bdcfg_ca_vref = 0x2e, + .bdcfg_rx_vref = 0xff001e, + .bdcfg_rx_vref_step = 0xf, + .bdcfg_tx_vref = 0x56e0a, + .bdcfg_rfm_chk = 0x1, + .ch = { + [0] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x2641350, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x47583016, 0x85013247 }, + .bdcfg_dm_swap = { 0x2, 0x6 }, + }, + [1] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x3265410, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x54263701, 0x84650312 }, + .bdcfg_dm_swap = { 0x8, 0x7 }, + }, + [2] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x1240635, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x56420713, 0x57802134 }, + .bdcfg_dm_swap = { 0x8, 0x6 }, + }, + [3] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x5462301, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x74560128, 0x58760312 }, + .bdcfg_dm_swap = { 0x3, 0x4 }, + }, + [4] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x4215306, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x45760138, 0x75803124 }, + .bdcfg_dm_swap = { 0x2, 0x6 }, + }, + [5] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x4065321, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x65420371, 0x78560213 }, + .bdcfg_dm_swap = { 0x8, 0x4 }, + }, + [6] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x4612035, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x25481730, 0x56703128 }, + .bdcfg_dm_swap = { 0x6, 0x4 }, + }, + [7] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x5023416, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x54783026, 0x41650238 }, + .bdcfg_dm_swap = { 0x1, 0x7 }, + }, + [8] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x521463, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x76453012, 0x85430127 }, + .bdcfg_dm_swap = { 0x8, 0x6 }, + }, + [9] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x5326041, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x43620781, 0x81653420 }, + .bdcfg_dm_swap = { 0x5, 0x7 }, + }, + [10] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x2104635, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x54763210, 0x75831062 }, + .bdcfg_dm_swap = { 0x8, 0x4 }, + }, + [11] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x3654021, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x74561082, 0x56473012 }, + .bdcfg_dm_swap = { 0x3, 0x8 }, + }, + [12] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x514362, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x45761032, 0x74830126 }, + .bdcfg_dm_swap = { 0x8, 0x5 }, + }, + [13] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x4523016, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x54763021, 0x58470312 }, + .bdcfg_dm_swap = { 0x8, 0x6 }, + }, + [14] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x2315064, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x43620718, 0x68134207 }, + .bdcfg_dm_swap = { 0x5, 0x5 }, + }, + [15] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x6315042, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x47653082, 0x64583012 }, + .bdcfg_dm_swap = { 0x1, 0x7 }, + } + } +}; + +struct renesas_dbsc5_dram_priv { + void __iomem *regs; + + /* The board parameter structure of the board */ + const struct renesas_dbsc5_board_config *dbsc5_board_config; + + /* The board clock frequency */ + u32 brd_clk; + u32 brd_clkdiv; + u32 brd_clkdiva; + /* The Mbps of DDR */ + u32 ddr_mbps; + u32 ddr_mbpsdiv; + /* Value indicating the enabled channel */ + u32 ddr_phyvalid; + u32 ddr_dramvalid; + /* Channels used for each memory rank */ + u32 ch_have_this_cs[CS_CNT]; + u32 upper_lower_byte[DBSC5_PHYNUM_CNT]; + u32 link_ecc_en; + /* The maximum memory capacity */ + u32 max_density; + /* Index of jedec spec1 setting table you use */ + u32 js1_ind; +}; + +/** + * vch_nxt() - Macro for channel selection loop + * @dev: DBSC5 device + * @pos: Iterator position + * + * Return the ID of the channel to be used. Check for valid channels + * between the value of posn and the maximum number of CHs. If a valid + * channel is found, returns the value of that channel. + */ +static u32 vch_nxt(struct udevice *dev, u32 pos) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) + if (priv->ddr_dramvalid & BIT(posn)) + break; + + return posn; +} + +/** + * vphych_nxt() - Macro for PHY channel selection loop + * @dev: DBSC5 device + * @pos: Iterator position + * + * Return the ID of the channel to be used. Check for valid channels + * between the value of posn and the maximum number of CHs. If a valid + * channel is found, returns the value of that channel. + */ +static u32 vphych_nxt(struct udevice *dev, u32 pos) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 posn; + + for (posn = pos; posn < DBSC5_PHYNUM_CNT; posn++) + if (priv->ddr_phyvalid & BIT(posn)) + break; + + return posn; +} + +#define foreach_vch(dev, ch) \ + for ((ch) = vch_nxt((dev), 0); (ch) < DRAM_CH_CNT; (ch) = vch_nxt((dev), (ch) + 1)) + +#define foreach_vphych(dev, ch) \ + for ((ch) = vphych_nxt((dev), 0); (ch) < DBSC5_PHYNUM_CNT; (ch) = vphych_nxt((dev), (ch) + 1)) + +#define foreach_ech(ch) \ + for (ch = 0; ch < DRAM_CH_CNT; ch++) + +/** + * dbsc5_soft_delay() - Wait loop number of CPU cycles + * @loop: Number of cycles to wait + * + * This is a cycle counting approximate delay loop, used in very + * early code to wait for near future events. + */ +static void dbsc5_soft_delay(const int loop) +{ + int i; + + for (i = 0; i < loop; i++) + asm volatile("nop"); +} + +/** + * dbsc5_init_pll3() - Set PLL3 + * @dev: DBSC5 device + */ +static void dbsc5_init_pll3(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 data_cr0, data_cr1, data_div, data_dcr_1st, data_dcr_2nd, data_dcr_3rd; + u32 ddr_mul, ddr_mul_div, ddr_mul_ni, ddr_mul_nf; + const int pll3_frac_mode_threshold = 9000; + u32 ssmode, pll3vco, pll3_valid = 0; + u32 ddr_zb3ckcr[DBSC5_PHYNUM_CNT]; + u32 zb3ckcr0, zb3ckcr1; + u32 fvv, ch; + + /* Calculate valid PLL3 channel */ + for (ch = 0; ch < DBSC5_PHYNUM_CNT; ch++) { + pll3_valid |= (((priv->ddr_phyvalid >> (ch * 2)) | + (priv->ddr_phyvalid >> ((ch * 2) + 1))) & 0x1) << ch; + } + + /* Calculate PLL3 settings */ + if (priv->ddr_mbps < (pll3_frac_mode_threshold * priv->ddr_mbpsdiv)) + ssmode = 4; + else + ssmode = 0; + + ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2, priv->brd_clk, + priv->brd_clkdiv * (priv->brd_clkdiva + 1)); + + /* PLL3VCO = EXTAL * ddr_mul */ + pll3vco = ddr_mul * priv->brd_clk / (priv->brd_clkdiv * (priv->brd_clkdiva + 1)); + + if (pll3vco < 3000) { /* div = 4 */ + data_div = 2; + pll3vco = pll3vco * 2; + ddr_mul = ddr_mul * 2; + ddr_mul_div = 2; + } else { /* div = 2 */ + data_div = 0; + ddr_mul_div = 1; + } + + /* + * PLL3VCO FVV + * 3000 - 4000 0 + * 3750 - 4900 1 + * 4600 - 5800 2 + * 5450 - 6200 3 + */ + if (pll3vco > 5800) + fvv = 3; + else if (pll3vco > 4900) + fvv = 2; + else if (pll3vco > 4000) + fvv = 1; + else + fvv = 0; + + ddr_mul_ni = (ddr_mul / 2) - 1; + if (priv->ddr_mbps < (pll3_frac_mode_threshold * priv->ddr_mbpsdiv)) { + ddr_mul_nf = ((8 * priv->ddr_mbps * priv->brd_clkdiv * (priv->brd_clkdiva + 1) * ddr_mul_div) / + (priv->ddr_mbpsdiv * 2 * priv->brd_clk)) - (8 * (ddr_mul_ni + 1) * 2); + } else { + ddr_mul_nf = 0; + } + + data_cr0 = (ddr_mul_ni << 20) | (ssmode << 16); + data_cr1 = (fvv << 26) | ddr_mul_nf; + + /* Gradually frequency change settings */ + data_dcr_1st = 0x18; + data_dcr_2nd = 0x10; + data_dcr_3rd = 0; + + /* Disable write protection */ + writel(0xa5a5a501, SYSSS_CLKTOPPKCPROT0); + while (!((readl(SYSSS_CLKTOPPKCPROT0)) & BIT(0))) + ; + + /* Clock change & setting PLL3_x_CR0 and PLL3_x_CR1 */ + for (ch = 0; ch < DBSC5_PLL3_CNT; ch++) { + if (!(pll3_valid & BIT(ch))) + continue; + + /* 1. Confirm that the PLL3_x are stable with PLLCLKSTAB */ + while (!(readl(SYSSS_PLL3_x_CR2(ch)) & BIT(31))) + ; + + /* 2-1. Select PLL3_0SELID to CLK_IOSC1 */ + writel(0x1, SYSSS_PLL3_xSCR(ch)); + /* 2-2. Confirm PLL3_0SELACT register to ID equals CLK_IOSC1 */ + while (((readl(SYSSS_PLL3_xSCR(ch))) & 0x10001) != 0x10001) + ; + + /* 3. Stop the PLL3_x (PLLDISTRG = 1) */ + writel(0x20000000, SYSSS_PLL3_x_CR2(ch)); + /* 4. Confirm that the PLL3_0 has been stopped (PLLCLKSTAB = 0) */ + while (readl(SYSSS_PLL3_x_CR2(ch)) & BIT(31)) + ; + + /* set PLL3_x_CR0 */ + clrsetbits_le32(SYSSS_PLL3_x_CR0(ch), 0x1ff70000, data_cr0); + /* set PLL3_x_CR1 */ + clrsetbits_le32(SYSSS_PLL3_x_CR1(ch), 0x0dffffff, data_cr1); + /* set PLL3_x_DCR */ + writel(data_dcr_1st, SYSSS_PLL3_x_DCR(ch)); + /* set PLL3_x_CR2 (PLLENTRG = 1) */ + writel(BIT(28), SYSSS_PLL3_x_CR2(ch)); + } + + /* Clock change */ + for (ch = 0; ch < DBSC5_PLL3_CNT; ch++) { + if (!(pll3_valid & BIT(ch))) + continue; + + /* 1. Confirm that the PLL3_0 have been stable (PLLCLKSTAB = 1) */ + while (!(readl(SYSSS_PLL3_x_CR2(ch)) & BIT(31))) + ; + + /* 2-1. Select PLL input clock by PLLSELID register */ + writel(0, SYSSS_PLL3_xSCR(ch)); + /* 2-2. Confirm that PLL3_0SELACT register becomes same value with PLL3_0SELID */ + while (readl(SYSSS_PLL3_xSCR(ch)) & 0x10001) + ; + } + + /* Set PLL3_DCR gradually */ + for (ch = 0; ch < DBSC5_PLL3_CNT; ch++) { + if (!(pll3_valid & BIT(ch))) + continue; + + /* Set PLL3_x_DCR */ + writel(data_dcr_2nd, SYSSS_PLL3_x_DCR(ch)); + /* Wait PLL3DIVSYNC is changed from 0 to 1 */ + while (!(readl(SYSSS_PLL3_x_DCR(ch)) & BIT(16))) + ; + } + + /* Wait until the current stabilizes */ + dbsc5_soft_delay(1000); + + for (ch = 0; ch < DBSC5_PLL3_CNT; ch++) { + if (!(pll3_valid & BIT(ch))) + continue; + + /* Set PLL3_x_DCR */ + writel(data_dcr_3rd, SYSSS_PLL3_x_DCR(ch)); + /* Wait PLL3DIVSYNC is changed from 0 to 1 */ + while (((readl(SYSSS_PLL3_x_DCR(ch))) & 0x10000) != 0x10000) + ; + } + + /* Wait until the current stabilizes */ + dbsc5_soft_delay(1000); + + /* Set PLL3 divider */ + zb3ckcr0 = readl(SYSSS_ZB3CKCR0); + zb3ckcr1 = readl(SYSSS_ZB3CKCR1); + for (ch = 0; ch < DBSC5_PHYNUM_CNT; ch++) { + if (priv->ddr_phyvalid & BIT(ch)) { + /* set FC[3:0] = data_div */ + ddr_zb3ckcr[ch] = data_div; + } else { + if (ch < 4) + ddr_zb3ckcr[ch] = (zb3ckcr0 >> SYSSS_ZB3CKCR_PHYx(ch)) & 0x1f; + else + ddr_zb3ckcr[ch] = (zb3ckcr1 >> SYSSS_ZB3CKCR_PHYx(ch)) & 0x1f; + } + } + + zb3ckcr0 = (ddr_zb3ckcr[3] << 23) | (ddr_zb3ckcr[2] << 16) | + (ddr_zb3ckcr[1] << 7) | ddr_zb3ckcr[0]; + zb3ckcr1 = (ddr_zb3ckcr[7] << 23) | (ddr_zb3ckcr[6] << 16) | + (ddr_zb3ckcr[5] << 7) | ddr_zb3ckcr[4]; + + /* Check ZB3CKCR0/1 KICK bit = 0 */ + while (readl(SYSSS_ZB3CKCR0) & SYSSS_ZB3CKCR_KICK) + ; + while (readl(SYSSS_ZB3CKCR1) & SYSSS_ZB3CKCR_KICK) + ; + + /* Set ZB3CKCR0/1 */ + writel(zb3ckcr0, SYSSS_ZB3CKCR0); + writel(zb3ckcr1, SYSSS_ZB3CKCR1); + + /* Set kickbit = 1 */ + setbits_le32(SYSSS_ZB3CKCR0, SYSSS_ZB3CKCR_KICK); + setbits_le32(SYSSS_ZB3CKCR1, SYSSS_ZB3CKCR_KICK); + + /* Wait ZB3CKCR0/1 KICK bit neg */ + while (readl(SYSSS_ZB3CKCR0) & SYSSS_ZB3CKCR_KICK) + ; + while (readl(SYSSS_ZB3CKCR1) & SYSSS_ZB3CKCR_KICK) + ; +} + +/** + * dbsc5_msres_sync_wait() - Wait for MSRES and MSRESS to synchronize + * @msres: MSRES register + * @msress: MSRESS register + */ +static void dbsc5_msres_sync_wait(u32 msres, u32 msress) +{ + while (readl(msres) != readl(msress)) + ; +} + +/** + * dbsc5_msres_status_set - Set DBSC5 into RUN or STANDBY mode + * @dev: DBSC5 device + * @status: RUN or STANDBY mode + */ +static void dbsc5_msres_status_set(struct udevice *dev, u32 status) +{ + u32 ch; + + foreach_vphych(dev, ch) { + /* + * Enable write access of protected registers + * dbq_reset / ddr_reset_apb / ddr_reset_hard / ddr_reset + */ + writel(0xa5a5a501, MODULE_CONTROL_MDLC0xPKCPROT1(ch)); + /* ddrfi */ + writel(0xa5a5a501, MODULE_CONTROL_MDLC12PKCPROT1); + + /* Check MDLCnMSRESS[i] = MDLCnMSRES[i] */ + /* dbq_reset */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC0xMSRES1(ch), + MODULE_CONTROL_MDLC0xMSRESS1(ch)); + + /* ddr_reset_apb / ddr_reset_hard / ddr_reset */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC0xMSRES3(ch), + MODULE_CONTROL_MDLC0xMSRESS3(ch)); + + /* ddrfi */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC15MSRES8, + MODULE_CONTROL_MDLC15MSRESS8); + + /* Set MDLCnMSRESx */ + /* dbq_reset */ + clrsetbits_le32(MODULE_CONTROL_MDLC0xMSRES1(ch), 0x3, status); + + /* ddr_reset_apb / ddr_reset_hard / ddr_reset */ + clrsetbits_le32(MODULE_CONTROL_MDLC0xMSRES3(ch), 0x3f, + (status << 4) | (status << 2) | status); + + /* ddrfi */ + clrsetbits_le32(MODULE_CONTROL_MDLC15MSRES8, 0x3 << (ch * 2), + status << (ch * 2)); + + /* Check MDLCnMSRESS[i] = MDLCnMSRES[i] */ + /* dbq_reset */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC0xMSRES1(ch), + MODULE_CONTROL_MDLC0xMSRESS1(ch)); + + /* ddr_reset_apb / ddr_reset_hard / ddr_reset */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC0xMSRES3(ch), + MODULE_CONTROL_MDLC0xMSRESS3(ch)); + + /* ddrfi */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC15MSRES8, + MODULE_CONTROL_MDLC15MSRESS8); + + /* Disables write access of protected registers */ + /* dbq_reset / ddr_reset_apb / ddr_reset_hard / ddr_reset */ + writel(0xa5a5a500, MODULE_CONTROL_MDLC0xPKCPROT1(ch)); + /* ddrfi */ + writel(0xa5a5a500, MODULE_CONTROL_MDLC12PKCPROT1); + } +} + +/** + * dbsc5_reg_write() - Write DBSC register + * @dev: DBSC5 device + * @addr: Destination address + * @data: Setting value to be written + * + * Write 32bit value @data to register at @addr . + */ +static void dbsc5_reg_write(struct udevice *dev, uintptr_t addr, u32 data) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < DBSC5_DBSC_CNT; i++) { + if (!(priv->ddr_phyvalid & BIT(i))) + continue; + + if ((addr & 0xFFF00000) == 0xE9900000) /* clk_dbsc region */ + writel(data, addr + (0x4000 * i)); + else /* clk_axim region */ + writel(data, addr + (0x8000 * i)); + } +} + +/** + * dbsc5_regset_unlock() - Unlock DBSC access + * @dev: DBSC5 device + */ +static void dbsc5_regset_unlock(struct udevice *dev) +{ + dbsc5_reg_write(dev, DBSC_DBSYSCNT0, 0x1234); + dbsc5_reg_write(dev, DBSC_DBSYSCNT0A, 0x1234); +} + +/** + * dbsc5_regset_lock() - Lock DBSC access + * @dev: DBSC5 device + */ +static void dbsc5_regset_lock(struct udevice *dev) +{ + dbsc5_reg_write(dev, DBSC_DBSYSCNT0, 0); + dbsc5_reg_write(dev, DBSC_DBSYSCNT0A, 0); +} + +/** + * dbsc5_send_dbcmd() - DRAM Command Write + * @dev: DBSC5 device + * @cmd: Command + */ +static void dbsc5_send_dbcmd(struct udevice *dev, u32 cmd) +{ + readl(DBSC_DBCMD); /* Dummy read */ + + while (readl(DBSC_DBWAIT) & BIT(0)) /* Wait for not busy */ + ; + + dbsc5_reg_write(dev, DBSC_DBCMD, cmd); +} + +/** + * dbsc5_send_dbcmd_ch() - DRAM Command Write on channel + * @ch: DBSC5 channel + * @cmd: Command + */ +static void dbsc5_send_dbcmd_ch(u32 ch, u32 cmd) +{ + readl(DBSC_DBCMD); /* Dummy read */ + + while (readl(DBSC_DBWAIT) & BIT(0)) /* Wait for not busy */ + ; + + writel(cmd, DBSC_DBCMD + (0x4000 * ch)); +} + +/** + * dbsc5_f_scale_rate() - Calculate the best value for DBSC timing setting + * @priv: Driver private data + * @frac: Perform fractional rounding + * @ddr_mbps: DRAM Mbps + * @ddr_mbpsdiv: DRAM Mbps divider + * @ps: Optimal setting value in pico second + * @cyc: Optimal setting value in cycle count + * + * Convert the optimal value in pico second to in cycle count. Optionally, if @frac is true, + * perform fractional rounding. Compare the value of the result of the conversion with the + * value of the argument @cyc and return the larger value. + */ +static u32 dbsc5_f_scale_rate(struct renesas_dbsc5_dram_priv *priv, const bool frac, + u32 ddr_mbps, u32 ddr_mbpsdiv, u32 ps, u32 cyc) +{ + const u32 mul = frac ? 8 : 800000; + const u32 tmp = DIV_ROUND_UP(ps, 10UL) * ddr_mbps; + const u32 f_scale_div = DIV_ROUND_UP(tmp, mul * ddr_mbpsdiv); + + return (f_scale_div > cyc) ? f_scale_div : cyc; +} + +/** + * dbsc5_f_scale() - Calculate the best value for DBSC timing setting + * @priv: Driver private data + * @frac: Perform fractional rounding + * @ps: Optimal setting value in pico second + * @cyc: Optimal setting value in cycle count + * + * Convert the optimal value in pico second to in cycle count. Optionally, if @frac is true, + * perform fractional rounding. Compare the value of the result of the conversion with the + * value of the argument @cyc and return the larger value. + */ +static u32 dbsc5_f_scale(struct renesas_dbsc5_dram_priv *priv, const bool frac, u32 ps, u32 cyc) +{ + return dbsc5_f_scale_rate(priv, frac, priv->ddr_mbps, priv->ddr_mbpsdiv, ps, cyc); +} + +/** + * dbsc5_f_scale_js2() - Select optimal settings based on jedec_spec2 + * @priv: Driver private data + * @js2: Array of jedec spec2 setting table + * + * Calculate and assign each setting value of jedec_spec2 by "dbsc5_f_scale" function. + * Only the following array elements are calculated using different formulas from those + * described above -- JS2_tRRD/JS2_tFAW/JS2_tZQCALns/JS2_tRCpb/JS2_tRCab. + */ +static void dbsc5_f_scale_js2(struct renesas_dbsc5_dram_priv *priv, u32 *f_js2) +{ + int i; + + for (i = 0; i < JS2_TBLCNT; i++) { + f_js2[i] = dbsc5_f_scale(priv, false, + jedec_spec2[JS2_DERATE][i].ps, + jedec_spec2[JS2_DERATE][i].cyc); + } + + f_js2[JS2_tRRD] = dbsc5_f_scale(priv, false, + js1[priv->js1_ind].tRRD + jedec_spec2[JS2_DERATE][JS2_tRRD].ps, + jedec_spec2[JS2_DERATE][JS2_tRRD].cyc); + f_js2[JS2_tFAW] = dbsc5_f_scale(priv, false, + js1[priv->js1_ind].tFAW + jedec_spec2[JS2_DERATE][JS2_tFAW].ps, + jedec_spec2[JS2_DERATE][JS2_tFAW].cyc); + f_js2[JS2_tZQCALns] = dbsc5_f_scale(priv, false, + jedec_spec2[JS2_DERATE][JS2_tZQCALns].ps * 1000, 0); + f_js2[JS2_tDQ72DQns] = dbsc5_f_scale(priv, false, + jedec_spec2[JS2_DERATE][JS2_tDQ72DQns].ps * 1000, 0); + f_js2[JS2_tCAENTns] = dbsc5_f_scale(priv, false, + jedec_spec2[JS2_DERATE][JS2_tCAENTns].ps * 1000, 0); + f_js2[JS2_tRCpb] = f_js2[JS2_tRAS] + f_js2[JS2_tRPpb]; + f_js2[JS2_tRCab] = f_js2[JS2_tRAS] + f_js2[JS2_tRPab]; + f_js2[JS2_tRFCab] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFC_ab[priv->max_density] * 1000, 0); + f_js2[JS2_tRFCpb] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFC_pb[priv->max_density] * 1000, 0); + f_js2[JS2_tpbR2pbR] = dbsc5_f_scale(priv, false, + jedec_spec2_tpbR2pbR[priv->max_density] * 1000, 0); + f_js2[JS2_tRFMab] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFM_ab[priv->max_density] * 1000, 0); + f_js2[JS2_tRFMpb] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFM_pb[priv->max_density] * 1000, 0); + + f_js2[JS2_tRBTP] = dbsc5_f_scale(priv, false, 7500, 2) - 2; + f_js2[JS2_tXSR] = f_js2[JS2_tRFCab] + dbsc5_f_scale(priv, false, 7500, 2); + f_js2[JS2_tPDN] = dbsc5_f_scale(priv, false, 10000, 0) + 1; + f_js2[JS2_tPDN_DSM] = dbsc5_f_scale(priv, true, + jedec_spec2[JS2_DERATE][JS2_tPDN_DSM].ps * 10, 0); + f_js2[JS2_tXSR_DSM] = dbsc5_f_scale(priv, true, + jedec_spec2[JS2_DERATE][JS2_tXSR_DSM].ps * 10, 0); + f_js2[JS2_tXDSM_XP] = dbsc5_f_scale(priv, true, + jedec_spec2[JS2_DERATE][JS2_tXDSM_XP].ps * 10, 0); + f_js2[JS2_tWLWCKOFF] = dbsc5_f_scale(priv, false, 14000, 5); +} + +/** + * dbsc5_dbsc_regset_pre() - Configure primary DDR registers + * @dev: DBSC5 device + * + * Set SDRAM type, Burst length, and PHY type. Frequency mode setting. + * Write SDRAM configuration contents to registers. + */ +static void dbsc5_dbsc_regset_pre(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ddr_density[DRAM_CH_CNT][CS_CNT]; + u32 RL, WL, WCKENLR; + u32 ch, cs, i, val; + u32 js2[JS2_CNT]; + u32 param_trdwr; + u32 tmp[4]; + + /* Determine DBSC clock frequency (in MHz) */ + const u32 ni = (readl(SYSSS_PLL1_1_CR0) >> 20) & 0x1FF; + const u32 cksel = (readl(SYSSS_PLL1_1_CR0) >> 7) & 0x1; + const u32 div = 0x20 - ((readl(SYSSS_PLL1_1DCR)) & 0x1F); + const u32 bus_clk = ((priv->brd_clk * (ni + 1) * 2) * div) / (cksel + 1) / 32 / 4; + + /* Determine board density */ + priv->max_density = 0; + for (ch = 0; ch < DRAM_CH_CNT; ch++) { + for (cs = 0; cs < CS_CNT; cs++) { + ddr_density[ch][cs] = priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs]; + if (priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs] == 0xFF) + continue; + + if (priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs] > priv->max_density) + priv->max_density = priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs]; + } + } + + /* Search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < (JS1_FREQ_TBL_NUM - 1); i++) + if ((js1[i].fx3 * 2 * priv->ddr_mbpsdiv) >= (priv->ddr_mbps * 3)) + break; + + if (i > JS1_USABLEC_SPEC_HI) + priv->js1_ind = JS1_USABLEC_SPEC_HI; + else + priv->js1_ind = i; + + RL = js1[priv->js1_ind].RLset0; + WL = js1[priv->js1_ind].WLsetA; + WCKENLR = js1[priv->js1_ind].WCKENLR0; + + /* Calculate jedec_spec2 */ + dbsc5_f_scale_js2(priv, js2); + + /* LPDDR5, BL=16, DFI interface */ + dbsc5_reg_write(dev, DBSC_DBMEMKIND, 0xC); + dbsc5_reg_write(dev, DBSC_DBMEMKINDA, 0xC); + dbsc5_reg_write(dev, DBSC_DBBL, 0x2); + dbsc5_reg_write(dev, DBSC_DBBLA, 0x2); + + /* dcmpmd = 2 : bypass mode */ + dbsc5_reg_write(dev, DBSC_DBSYSCNT1A, 0x2); + dbsc5_reg_write(dev, DBSC_DBPHYCONF0, 0x1); + dbsc5_reg_write(dev, DBSC_DBSYSCONF0, 0x1); + + /* FREQRATIO=2 */ + dbsc5_reg_write(dev, DBSC_DBSYSCONF1, 0x20000); + dbsc5_reg_write(dev, DBSC_DBSYSCONF1A, 0); + dbsc5_reg_write(dev, DBSC_DBSYSCONF2, 0x1); + dbsc5_reg_write(dev, DBSC_DBSYSCONF2A, 0x241); + + for (ch = 0; ch < DRAM_CH_CNT; ch++) { + for (cs = 0; cs < CS_CNT; cs++) { + if (ddr_density[ch][cs] == 0xFF) { + writel(0, DBSC_DBMEMCONF(ch, cs)); + writel(0, DBSC_DBMEMCONFA(ch, cs)); + } else { + writel(DBMEMCONF_REGD(ddr_density[ch][cs]), + DBSC_DBMEMCONF(ch, cs)); + writel(DBMEMCONF_REGD(ddr_density[ch][cs]), + DBSC_DBMEMCONFA(ch, cs)); + } + } + } + + /* DBTR0.cl : RL */ + dbsc5_reg_write(dev, DBSC_DBTR(0), RL); + + /* DBTR1.cwl : WL */ + dbsc5_reg_write(dev, DBSC_DBTR(1), WL); + + /* DBTR2.al = 0 */ + dbsc5_reg_write(dev, DBSC_DBTR(2), 0); + + /* DBTR3.trcd : tRCD */ + dbsc5_reg_write(dev, DBSC_DBTR(3), js2[JS2_tRCD]); + + /* DBTR4.trpa,trp : tRPab,tRPpb */ + dbsc5_reg_write(dev, DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]); + + /* DBTR5.trc : tRCpb */ + dbsc5_reg_write(dev, DBSC_DBTR(5), js2[JS2_tRCpb]); + + /* DBTR6.tras : tRAS */ + dbsc5_reg_write(dev, DBSC_DBTR(6), js2[JS2_tRAS]); + + /* DBTR7.trrd : tRRD */ + dbsc5_reg_write(dev, DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]); + + /* DBTR8.tfaw : tFAW */ + dbsc5_reg_write(dev, DBSC_DBTR(8), js2[JS2_tFAW]); + + /* DBTR9.trdpr : nRBTP */ + dbsc5_reg_write(dev, DBSC_DBTR(9), js1[priv->js1_ind].nRBTP); + + /* DBTR10.twr : nWR */ + dbsc5_reg_write(dev, DBSC_DBTR(10), js1[priv->js1_ind].nWR); + + /* + * DBTR11.trdwr : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + RD(tRPST/tCK) - + * ODTLon - RD(tODTon(min)/tCK) + 1 + feature + */ + param_trdwr = RL + 4 + js2[JS2_tWCK2DQO_HF] + 0 - js1[priv->js1_ind].ODTLon - + (js2[JS2_tODTon_min] - 1) + 1 + 0; + dbsc5_reg_write(dev, DBSC_DBTR(11), param_trdwr); + + /* DBTR12.twrrd_s,twrrd : WL + BL/2 + tWTR_S,WL + BL + tWTR_L */ + dbsc5_reg_write(dev, DBSC_DBTR(12), ((WL + 2 + js2[JS2_tWTR_S]) << 16) | + (WL + 4 + js2[JS2_tWTR_L])); + + /* DBTR13.trfcpb,trfc : tRFCpb,tRFCab */ + dbsc5_reg_write(dev, DBSC_DBTR(13), (js2[JS2_tRFCpb] << 16) | (js2[JS2_tRFCab])); + + /* DBTR14.tcscal,tckehdll,tckeh : tCSCAL,tXP,tXP */ + dbsc5_reg_write(dev, DBSC_DBTR(14), (js2[JS2_tCSCAL] << 24) | (js2[JS2_tXP] << 16) | + js2[JS2_tXP]); + + /* DBTR15 */ + /* tckel : tSR */ + tmp[0] = js2[JS2_tSR]; + /* tckesr : tSR */ + tmp[1] = js2[JS2_tSR]; + /* tespd : tESPD = 2 */ + tmp[2] = 0x2; + dbsc5_reg_write(dev, DBSC_DBTR(15), (tmp[2] << 24) | (tmp[1] << 16) | tmp[0]); + + /* DBTR16 */ + /* wdql(tphy_wrlat + tphy_wrdata) */ + tmp[0] = (WL * 4) - 5 + 2; + /* dqenltcy(tphy_wrlat) */ + tmp[1] = (WL * 4) - 5; + /* dql(tphy_rdlat + trddata_en) : (6 + csrDFIMRL) * 4 + trddata_en */ + tmp[2] = ((6 + 7) * 4) + ((RL * 4) - 13); + /* dqienltncy(trddata_en) : RL * 4 - 13 */ + tmp[3] = (RL * 4) - 13; + dbsc5_reg_write(dev, DBSC_DBTR(16), (tmp[3] << 25) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR17.tmodrd,tmod : tMRR,tMRW */ + dbsc5_reg_write(dev, DBSC_DBTR(17), (js2[JS2_tMRR] << 24) | (js2[JS2_tMRW] << 16)); + + /* DBTR18.rodtl,rodta = 0 */ + dbsc5_reg_write(dev, DBSC_DBTR(18), 0); + + /* DBTR19.tzqcl,tzqcs = 0 */ + dbsc5_reg_write(dev, DBSC_DBTR(19), 0); + + /* DBTR20.txsdll,txs : tXSR,tXSR */ + dbsc5_reg_write(dev, DBSC_DBTR(20), (js2[JS2_tXSR] << 16) | js2[JS2_tXSR]); + + /* DBTR21.tccdmw, tccd */ + /* tccd(BL/2_max) */ + tmp[0] = 0x4; + /* tccd_s(BL/2_min) */ + tmp[1] = 0x2; + /* tccdmw */ + if ((priv->ddr_mbps * 3) > (25600 * priv->ddr_mbpsdiv)) + tmp[2] = 0x14; + else + tmp[2] = 0x10; + dbsc5_reg_write(dev, DBSC_DBTR(21), (tmp[2] << 24) | (tmp[1] << 16) | tmp[0]); + + /* DBTR22.tzqcal,tzqlat : tZQCAL,tZQLAT */ + dbsc5_reg_write(dev, DBSC_DBTR(22), (js2[JS2_tZQCALns] << 16) | js2[JS2_tZQLAT]); + + /* DBTR23.rrspc = 0 */ + dbsc5_reg_write(dev, DBSC_DBTR(23), 0); + + /* DBTR24 */ + /* wrcslat(tphy_wrcslat) */ + tmp[0] = (WL * 4) - 5; + /* wrcsgap(tphy_wrcsgap) */ + tmp[1] = 0x4; + /* rdcslat(tphy_rdcslat) */ + tmp[2] = (RL * 4) - 13; + /* rdcsgap(tphy_rdcsgap) */ + tmp[3] = 0x4; + dbsc5_reg_write(dev, DBSC_DBTR(24), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR25 */ + dbsc5_reg_write(dev, DBSC_DBTR(25), 0); + + /* DBTR26 */ + dbsc5_reg_write(dev, DBSC_DBTR(26), 0); + + /* DBTR27.tpdn : tPDN */ + dbsc5_reg_write(dev, DBSC_DBTR(27), js2[JS2_tPDN]); + + /* DBTR28.txsrdsm : tXSR_DSM */ + dbsc5_reg_write(dev, DBSC_DBTR(28), js2[JS2_tXSR_DSM]); + + /* DBTR29.tdsmxp : tXDSM_XP */ + dbsc5_reg_write(dev, DBSC_DBTR(29), js2[JS2_tXDSM_XP]); + + /* DBTR30.tcmdpd : tCMDPD = 3 */ + dbsc5_reg_write(dev, DBSC_DBTR(30), 0x3); + + /* DBTR31.twck2dqomax,twck2dqimax : tWCK2DQO_HF/LF,tWCK2DQI_HF/LF */ + dbsc5_reg_write(dev, DBSC_DBTR(31), (js2[JS2_tWCK2DQO_HF] << 4) | js2[JS2_tWCK2DQI_HF]); + + /* DBTR32 */ + /* twckenr */ + tmp[0] = (WCKENLR * 4) - 4 - 1; + /* twckenw */ + tmp[1] = (js1[priv->js1_ind].WCKENLW * 4) - 4 - 1; + /* twckenlf */ + tmp[2] = (js1[priv->js1_ind].WCKENLF * 4) - 4; + /* twckpresta */ + tmp[3] = js1[priv->js1_ind].WCKPRESTA * 4; + dbsc5_reg_write(dev, DBSC_DBTR(32), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR33 */ + /* twcktgl */ + tmp[0] = 4; + /* twckdis : (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK),tWCKPST = MR10[3:2] = 2.5 */ + tmp[1] = ((RL + 4) * 4) + 3; + dbsc5_reg_write(dev, DBSC_DBTR(33), (tmp[1] << 8) | tmp[0]); + + /* DBTR34 */ + /* twcksus = 4 */ + tmp[0] = 4; + /* twckpst : RU(tWCKPST/tCK),tWCKPST = MR10[3:2] = 2.5 */ + tmp[1] = 1; + dbsc5_reg_write(dev, DBSC_DBTR(34), (tmp[1] << 8) | tmp[0]); + + /* DBTR35 */ + /* trd2wckoff : RL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[0] = RL + 4 + 0 + 1; + /* twr2wckoff : WL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[1] = WL + 4 + 0 + 1; + dbsc5_reg_write(dev, DBSC_DBTR(35), (tmp[1] << 16) | tmp[0]); + + /* DBTR36 */ + /* twssuswrx : CAS(WCKSUS)WRX */ + tmp[0] = 3; + /* twsoffwrx : CAS(WS_OFF)WRX */ + tmp[1] = 3; + /* twsfswrx : CAS(WS_FS)WRX */ + tmp[2] = 2; + dbsc5_reg_write(dev, DBSC_DBTR(36), (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR37 */ + /* tosco : tOSCODQI */ + tmp[0] = js2[JS2_tOSCODQI]; + /* toscodqi : tOSCODQI */ + tmp[1] = js2[JS2_tOSCODQI]; + /* toscodqo : tOSCODQO */ + tmp[2] = js2[JS2_tOSCODQO]; + dbsc5_reg_write(dev, DBSC_DBTR(37), (tmp[2] << 24) | (tmp[1] << 16) | tmp[0]); + + /* DBTR38.tpbr2act,tpbr2pbr : tpbR2act,tpbR2pbR */ + dbsc5_reg_write(dev, DBSC_DBTR(38), (js2[JS2_tpbR2act] << 8) | js2[JS2_tpbR2pbR]); + + /* DBTR39.trfmpb,trmbab : tRFMpb,tRFMab */ + dbsc5_reg_write(dev, DBSC_DBTR(39), (js2[JS2_tRFMpb] << 16) | js2[JS2_tRFMab]); + + /* DBRNK2 */ + /* rnkrr = tphy_wckcsgap + tWCK2DQO_rank2rank_HF/tWCK */ + val = dbsc5_f_scale_rate(priv, false, priv->ddr_mbps * 4, priv->ddr_mbpsdiv, 650, 0); + tmp[0] = (4 + val) / 4; + if ((tmp[0] * 4) == (4 + val)) + val = tmp[0]; + else + val = tmp[0] + 1; + dbsc5_reg_write(dev, DBSC_DBRNK(2), (val << 4) | val); + + /* DBRNK3 */ + /* rnkrw = tphy_wckcsgap + tWCK2DQO_rank2rank_HF/tWCK */ + val = dbsc5_f_scale_rate(priv, false, priv->ddr_mbps * 4, priv->ddr_mbpsdiv, 650, 0); + tmp[0] = (4 + val) / 4; + if ((tmp[0] * 4) == (4 + val)) + val = tmp[0]; + else + val = (tmp[0] + 1); + + /* trd2wckoff - trdwr */ + tmp[0] = (RL + 4 + 0 + 1) - param_trdwr; + if (tmp[0] > val) + val = tmp[0]; + dbsc5_reg_write(dev, DBSC_DBRNK(3), (val << 4) | val); + + /* DBRNK4 */ + /* rnkwr = tphy_wckcsgap */ + dbsc5_reg_write(dev, DBSC_DBRNK(4), 0x11); + + /* DBRNK5 */ + /* rnkww = tphy_wckcsgap */ + dbsc5_reg_write(dev, DBSC_DBRNK(5), 0x11); + + /* DBRNK6 */ + /* refmode = tphy_wckcsgap */ + /* per_bank_refresh */ + dbsc5_reg_write(dev, DBSC_DBRNK(6), 0x1); + + /* SCFCTST0 */ + /* scpreact */ + tmp[0] = 1UL * js2[JS2_tRPpb] * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + /* scactrdwr */ + tmp[1] = 1UL * (WL + 2 + 1 + js1[priv->js1_ind].nWR + js2[JS2_tRPpb]) * + bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv; + /* scrdacrt */ + tmp[2] = 1UL * ((js1[priv->js1_ind].nRBTP + 2) + js2[JS2_tRPpb]) * + bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv; + /* scactact */ + tmp[3] = 1UL * js2[JS2_tRCpb] * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + dbsc5_reg_write(dev, DBSC_DBSCHFCTST(0), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* SCFCTST1 */ + /* scasyncofs */ + tmp[0] = 12; + /* scactrdwr */ + tmp[1] = 1UL * js2[JS2_tRCD] * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + /* scwrrd */ + tmp[2] = 1UL * (WL + 4 + js2[JS2_tWTR_L]) * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + /* scrdwr */ + tmp[3] = 1UL * param_trdwr * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + dbsc5_reg_write(dev, DBSC_DBSCHFCTST(1), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW1 */ + /* sctrfcab */ + val = 1UL * (js2[JS2_tRFCab] + js2[JS2_tZQLAT]) * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + /* sctrfcab[7:0] = DBSCHRW1[7:0] */ + tmp[0] = val & 0xFF; + /* sctrfcab[8] = DBSCHRW1[24] */ + tmp[3] = val & 0x100; + /* sctrfcpb */ + tmp[1] = 1UL * (js2[JS2_tRFCpb]) * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + /* sctrfcpb */ + tmp[2] = 1UL * (js2[JS2_tpbR2pbR]) * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + dbsc5_reg_write(dev, DBSC_DBSCHRW(1), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW2 */ + /* scrfpben */ + tmp[0] = 1; + /* screfipb : tREFIpb */ + tmp[1] = DBSC_REFINT * bus_clk / priv->brd_clkdiv / 1000 / 8; + dbsc5_reg_write(dev, DBSC_DBSCHRW(2), (tmp[1] << 16) | tmp[0]); + + /* DBSCHTR0 */ + /* scdt0 */ + tmp[0] = (1UL * 4 * bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv) - 1; + /* scdt1 */ + tmp[1] = (1UL * 8 * bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv) - 1; + /* scdt2 */ + tmp[2] = (1UL * 12 * bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv) - 1; + /* scdt3 */ + tmp[3] = (1UL * 16 * bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv) - 1; + dbsc5_reg_write(dev, DBSC_DBSCHTR0, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + dbsc5_reg_write(dev, DBSC_DBBCAMDIS, 0x10); + + /* Dummy PDE */ + dbsc5_send_dbcmd(dev, 0x8840000); + /* Dummy PDX */ + dbsc5_send_dbcmd(dev, 0x8840001); +} + +/** + * dbsc5_dbsc_regset_post() - Set DBSC registers + * @dev: DBSC5 device + */ +static void dbsc5_dbsc_regset_post(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 val; + u32 tmp; + + dbsc5_reg_write(dev, DBSC_DBBUS0CNF1, 0); + + /* SRX */ + dbsc5_send_dbcmd(dev, 0xA840001); + + /* Write DBI ON */ + dbsc5_reg_write(dev, DBSC_DBDBICNT, 0x1); + + /* set REFCYCLE */ + val = DBSC_REFINT * priv->ddr_mbps / 8000 / priv->ddr_mbpsdiv; + /* refpmax=8 */ + dbsc5_reg_write(dev, DBSC_DBRFCNF1, 0x80000 | (val & 0xFFFF)); + /* refpmin=1 */ + dbsc5_reg_write(dev, DBSC_DBRFCNF2, 0x10000); + + /* periodic dram zqcal enable */ + dbsc5_reg_write(dev, DBSC_DBCALCNF, 0x1000010); + + /* wtmode = 1, pmstrmd = 2(WA for WS1), pmstren = 1 */ + dbsc5_reg_write(dev, DBSC_DBDFIPMSTRCNF, 0x15); + + /* periodic phy ctrl update enable */ + /* max = 80, min = 76, en = 1 */ + dbsc5_reg_write(dev, DBSC_DBDFICUPDCNF, 0x504C0001); + + /* set Auto Refresh */ + dbsc5_reg_write(dev, DBSC_DBRFEN, 0x1); + + /* dram access enable */ + dbsc5_reg_write(dev, DBSC_DBACEN, 0x1); + + tmp = (PERIODIC_TRAINING_INTERVAL * 1000) / DBSC_REFINT; + /* (ZQCalibration_interval + 1) / ZQCalibration_interval */ + val = (tmp * (0x10 + 1)) / 0x10; + /* snoopen=1 */ + dbsc5_reg_write(dev, DBSC_DBSNOOPC, BIT(24) | val); +} + +#define RTMMAC_BASE 0xb8900000 +#define RTDMAC_RDMSAR_0(ch) (RTMMAC_BASE + 0x0 + ((ch) * 0x1000)) +#define RTDMAC_RDMDAR_0(ch) (RTMMAC_BASE + 0x4 + ((ch) * 0x1000)) +#define RTDMAC_RDMTCR_0(ch) (RTMMAC_BASE + 0x8 + ((ch) * 0x1000)) +#define RTDMAC_RDMCHCR_0(ch) (RTMMAC_BASE + 0xc + ((ch) * 0x1000)) +#define RTDMAC_RDMCHCLR(ch) (RTMMAC_BASE + 0x100 + ((ch) * 0x1000)) +#define RTDMAC_RDMOR 0xb9438060 + +/** + * dbsc5_rtdmac_init() - Configure RTDMAC DMA controller + * @ch: DMA Channel + * @dst: Destination address + * @src: Source address + * @cnt: Byte count + */ +static void dbsc5_rtdmac_init(u32 ch, u32 dst, u32 src, u32 cnt) +{ + /* DMA Setting - 64Byte/AutoRequest mode */ + writel(src, RTDMAC_RDMSAR_0(ch)); + writel(dst, RTDMAC_RDMDAR_0(ch)); + writel(cnt, RTDMAC_RDMTCR_0(ch)); + writel(0x105409, RTDMAC_RDMCHCR_0(ch)); +} + +/** + * dbsc5_rtdmac_start() - Start RTDMAC DMA controller + */ +static void dbsc5_rtdmac_start(void) +{ + /* Start DMA */ + writew(0x1, RTDMAC_RDMOR); +} + +/** + * dbsc5_rtdmac_wait() - Wait for RTDMAC DMA completion + * @ch: DMA Channel + */ +static void dbsc5_rtdmac_wait(int ch) +{ + u32 val; + + /* Wait for DMA completion */ + for (;;) { + val = readl(RTDMAC_RDMCHCR_0(ch)); + if (val & BIT(1)) { /* Clear TE */ + writel(val & ~BIT(1), RTDMAC_RDMCHCR_0(ch)); + break; + } + + if (val & BIT(31)) { /* Clear CAE */ + writel(val & ~BIT(31), RTDMAC_RDMCHCR_0(ch)); + break; + } + } +} + +/** + * dbsc5_rtdmac_stop() - Stop RTDMAC DMA controller + */ +static void dbsc5_rtdmac_stop(void) +{ + u32 ch; + + /* Disable DMA */ + writew(0, RTDMAC_RDMOR); + for (ch = 0; ch < 16; ch++) + writel(readl(RTDMAC_RDMCHCR_0(ch)) | BIT(0), RTDMAC_RDMCHCLR(ch)); +} + +/** + * dbsc5_rtdmac_phyinit_trans_ach() - Load PHY using RTDMAC + * @dev: DBSC5 device + * @dst: Destination address + * @src: Source address + * @size: Transfer size + */ +static void dbsc5_rtdmac_phyinit_trans_ach(struct udevice *dev, u32 dst, u32 src, u32 size) +{ + u32 ch; + + foreach_vphych(dev, ch) { + dbsc5_rtdmac_init(ch, DDR_PHY_DMA_TRANS_BASE(ch) + (dst << 2), + src, (size + 0x3f) >> 6); + dbsc5_rtdmac_start(); + } + + foreach_vphych(dev, ch) + dbsc5_rtdmac_wait(ch); + + dbsc5_rtdmac_stop(); +} + +/** + * dbsc5_phy_apb_wr() - Write PHY register + * @ch: PHY channel + * @addr: Register address + * @data: Register value + */ +static void dbsc5_phy_apb_wr(u32 ch, u32 addr, u32 data) +{ + writel(data, DDR_PHY_BASE(ch) + (addr << 2)); +} + +/** + * dbsc5_phy_apb_wr_ach() - Write PHY register on all channels + * @addr: Register address + * @data: Register value + */ +static void dbsc5_phy_apb_wr_ach(struct udevice *dev, u32 addr, u32 data) +{ + u32 ch; + + foreach_vphych(dev, ch) + dbsc5_phy_apb_wr(ch, addr, data); +} + +/** + * dbsc5_phy_apb_rd() - Read PHY register + * @ch: PHY channel + * @addr: Register address + */ +static u32 dbsc5_phy_apb_rd(u32 ch, u32 addr) +{ + return readl(DDR_PHY_BASE(ch) + (addr << 2)); +} + +/** + * ddrphy_apb_rd_mod_wr() - Read-modify-Write PHY register + * @ch: PHY channel + * @addr: Register address + * @len: Clearing bitmask length + * @lsb: Clearing bitmask shift + * @data: Register value + */ +static void ddrphy_apb_rd_mod_wr(u32 ch, u32 addr, u32 len, u32 lsb, u32 data) +{ + u32 msk = 0xffffffff; + u32 val; + + if (len != 32) + msk = (BIT(len) - 1) << lsb; + + val = dbsc5_phy_apb_rd(ch, addr); + val &= ~msk; + val |= data << lsb; + dbsc5_phy_apb_wr(ch, addr, val); +} + +/** + * dbsc5_phy_apb_rd() - Read PHY message block + * @ch: PHY channel + */ +static u32 dbsc5_phy_apb_msg_rd(u32 ch) +{ + u32 ret; + + while (dbsc5_phy_apb_rd(ch, PHY_APBONLY_UCTSHADOWREGS) & BIT(0)) + ; + + ret = dbsc5_phy_apb_rd(ch, PHY_APBONLY_UCTWRITEONLYSHADOW); + dbsc5_phy_apb_wr(ch, PHY_APBONLY_DCTWRITEPROT, 0); + + while (!(dbsc5_phy_apb_rd(ch, PHY_APBONLY_UCTSHADOWREGS) & BIT(0))) + ; + + dbsc5_phy_apb_wr(ch, PHY_APBONLY_DCTWRITEPROT, BIT(0)); + + return ret; +} + +/** + * dbsc5_ddr_config_post() - Set DDR user configuration + * @dev: DBSC5 device + */ +static void dbsc5_ddr_config_post(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, tmp; + + foreach_vphych(dev, ch) { + /* 2-Rank settings */ + if (priv->ch_have_this_cs[1] & (0x3 << (ch * 2))) + dbsc5_phy_apb_wr(ch, PHY_PPGC_HWTCONTROLVAL, 0xc3); + + /* Configure IO parameters */ + /* DRAM Tx ODT for DQ */ + ddrphy_apb_rd_mod_wr(ch, 0x41036, 3, 7, + (priv->dbsc5_board_config->bdcfg_tx_odt >> 4) & 0x7); + + /* DRAM Tx ODT for CA */ + ddrphy_apb_rd_mod_wr(ch, 0x41036, 3, 11, + (priv->dbsc5_board_config->bdcfg_tx_odt) & 0x7); + + /* DRAM Tx NT DQ ODT */ + tmp = (priv->dbsc5_board_config->bdcfg_tx_ntodt) & 0x7; + if (tmp < 0x4) { + ddrphy_apb_rd_mod_wr(ch, 0x4105A, 1, 6, 0x0); + tmp += 4; + } + ddrphy_apb_rd_mod_wr(ch, 0x4105A, 3, 12, tmp); + + /* DRAM Tx NT ODT */ + ddrphy_apb_rd_mod_wr(ch, 0x41036, 1, 10, + ((priv->dbsc5_board_config->bdcfg_tx_ntodt) >> 4) & 0x1); + + /* DRAM Tx Per-pin DFE */ + ddrphy_apb_rd_mod_wr(ch, 0x4105A, 1, 7, + (priv->dbsc5_board_config->bdcfg_tx_dfe) & 0x1); + + /* DRAM Rx DRV */ + ddrphy_apb_rd_mod_wr(ch, 0x41026, 3, 7, + (priv->dbsc5_board_config->bdcfg_rx_drv) & 0x7); + + /* Link ECC setting */ + if (priv->link_ecc_en) { + ddrphy_apb_rd_mod_wr(ch, 0x41052, 1, 11, 0x1); + ddrphy_apb_rd_mod_wr(ch, 0x41052, 1, 13, 0x1); + } + } +} + +/** + * dbsc5_ddr_smb_config() - Set user configuration + * @dev: DBSC5 device + */ +static void dbsc5_ddr_smb_config(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, val; + + foreach_vphych(dev, ch) { + /* Frequency settings */ + if (priv->ddr_mbps < (6401 * priv->ddr_mbpsdiv)) { + /* 5501 - 6400 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_DRAMFREQ, 16, 16, 0x1900); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A0, 8, 16, 0xB0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A1, 8, 24, 0xB0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B0, 8, 0, 0xB0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B1, 8, 8, 0xB0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A0, 8, 16, 0xBB); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A1, 8, 24, 0xBB); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B0, 8, 0, 0xBB); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B1, 8, 8, 0xBB); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_ALT_RL, 8, 24, 0x3B); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MAIN_RL, 8, 0, 0x37); + } else if (priv->ddr_mbps < (7501 * priv->ddr_mbpsdiv)) { + /* 6401 - 7500 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_DRAMFREQ, 16, 16, 0x1D48); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A0, 8, 16, 0xC0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A1, 8, 24, 0xC0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B0, 8, 0, 0xC0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B1, 8, 8, 0xC0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A0, 8, 16, 0xCC); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A1, 8, 24, 0xCC); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B0, 8, 0, 0xCC); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B1, 8, 8, 0xCC); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_ALT_RL, 8, 24, 0x4B); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MAIN_RL, 8, 0, 0x43); + } else if (priv->ddr_mbps < (8534 * priv->ddr_mbpsdiv)) { + /* 7501 - 8533 -- None */ + } else { + /* 8534 - 9600 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_DRAMFREQ, 16, 16, 0x2580); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_DCAOPTS, 8, 8, 0x44); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A0, 8, 16, 0xE0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A1, 8, 24, 0xE0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B0, 8, 0, 0xE0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B1, 8, 8, 0xE0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A0, 8, 16, 0xEE); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A1, 8, 24, 0xEE); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B0, 8, 0, 0xEE); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B1, 8, 8, 0xEE); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_ALT_RL, 8, 24, 0x63); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MAIN_RL, 8, 0, 0x57); + } + + /* 2Rank settings */ + if (priv->ch_have_this_cs[1] & (0x3 << (ch * 2))) { + ddrphy_apb_rd_mod_wr(ch, PHY_APB_CSPRESENTCHA, 2, 8, 0x3); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_CSPRESENTCHB, 2, 0, 0x3); + } + + /* Board settings, data byte swap */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_UPPERLOWERBYTE, 4, 8, priv->upper_lower_byte[ch]); + + /* Configure Training settings */ + /* SOC Rx DFE function */ + if (!(priv->dbsc5_board_config->bdcfg_rx_dfe & BIT(0))) { + /* Rx DFE Disable */ + /* RxDFEBitTimeControl[4] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXDFEBITTIMECONTROL, 1, 4, 0x1); + } else { + /* Rx DFE DQ 1tap */ + /* RxDFEOpt[6] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXDFEOPT, 1, 30, 0); + /* RxClk scan skip */ + /* RxDFEBitTimeControl[6] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXDFEBITTIMECONTROL, 1, 6, 1); + } + + /* DRAM Tx DFE function */ + val = priv->dbsc5_board_config->bdcfg_tx_dfe & 0x7; + if (val == 0x0) { + /* Tx DFE Disable */ + /* PHY_APB_SEQUENCECTRL[10] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_SEQUENCECTRL, 1, 10, 0x0); + } else { + /* Select Tx DFE step */ + /* DRAM Tx DFE for Upper */ + /* PHY_APB_MR24_A0, PHY_APB_MR24_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_A0, 3, 20, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_A1, 3, 28, val); + /* PHY_APB_MR24_B0, PHY_APB_MR24_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_B0, 3, 4, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_B1, 3, 12, val); + + /* DRAM Tx DFE for Lower */ + /* PHY_APB_MR24_A0, PHY_APB_MR24_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_A0, 3, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_A1, 3, 24, val); + /* PHY_APB_MR24_B0, PHY_APB_MR24_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_B0, 3, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_B1, 3, 8, val); + } + + /* DRAM Tx Per-pin DFE */ + val = (priv->dbsc5_board_config->bdcfg_tx_dfe >> 4) & 0x1; + /* PHY_APB_MR41_A0, PHY_APB_MR41_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_A0, 1, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_A1, 1, 24, val); + /* PHY_APB_MR41_B0, PHY_APB_MR41_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_B0, 1, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_B1, 1, 8, val); + /* TxDFETrainOpt[0] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_TXDFETRAINOPT, val, 1, 0); + + /* DRAM Rx DCA function */ + /* PHY_APB_SEQUENCECTRL[7] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_SEQUENCECTRL, 1, 7, + priv->dbsc5_board_config->bdcfg_rx_dca & 0x1); + + /* DRAM Tx DCA function */ + /* PHY_APB_SEQUENCECTRL[6] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_SEQUENCECTRL, 1, 6, + priv->dbsc5_board_config->bdcfg_tx_dca & 0x1); + + /* CA Vref training initial value */ + val = priv->dbsc5_board_config->bdcfg_ca_vref & 0x7F; + /* PHY_APB_MR12_A0, PHY_APB_MR12_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR12_A0, 7, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR12_A1, 7, 24, val); + /* PHY_APB_MR12_B0, PHY_APB_MR12_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR12_B0, 7, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR12_B1, 7, 8, val); + + /* Rx Vref training range */ + /* RxVrefStartPat, RxVrefStartPrbs */ + val = priv->dbsc5_board_config->bdcfg_rx_vref & 0xFFFF; + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFSTARTPAT, 16, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFSTARTPRBS, 16, 16, val); + /* RxVrefEndPat, RxVrefEndPrbs */ + val = (priv->dbsc5_board_config->bdcfg_rx_vref >> 16) & 0xFFFF; + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFENDPAT, 16, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFENDPRBS, 16, 16, val); + /* RxVrefStepPat, RxVrefStepPrbs */ + val = priv->dbsc5_board_config->bdcfg_rx_vref_step & 0xFFFF; + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFSTEPPAT, 16, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFSTEPPRBS, 16, 0, val); + + /* Tx Vref training range */ + /* TxVrefStart */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_TXVREFSTART, 8, 0, + priv->dbsc5_board_config->bdcfg_tx_vref & 0xFF); + /* TxVrefEnd */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_TXVREFEND, 8, 8, + (priv->dbsc5_board_config->bdcfg_tx_vref >> 8) & 0xFF); + /* TxVrefStep */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_TXVREFSTEP, 8, 16, + (priv->dbsc5_board_config->bdcfg_tx_vref >> 16) & 0xFF); + + /* FW message setting */ + /* HdtCtrl */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_HDTCTRL, 8, 16, 0xff); + + /* Configure IO parameters */ + /* DRAM Tx ODT for DQ */ + val = (priv->dbsc5_board_config->bdcfg_tx_odt >> 4) & 0x7; + /* PHY_APB_MR11_A0, PHY_APB_MR11_B0 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A0, 3, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A1, 3, 24, val); + /* PHY_APB_MR11_A1, PHY_APB_MR11_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B0, 3, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B1, 3, 8, val); + + /* DRAM Tx ODT for CA */ + val = priv->dbsc5_board_config->bdcfg_tx_odt & 0x7; + /* PHY_APB_MR11_A0, PHY_APB_MR11_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A0, 3, 20, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A1, 3, 28, val); + /* PHY_APB_MR11_B0, PHY_APB_MR11_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B0, 3, 4, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B1, 3, 12, val); + + /* DRAM Tx NT DQ ODT */ + val = priv->dbsc5_board_config->bdcfg_tx_ntodt & 0x7; + /* PHY_APB_MR41_A0, PHY_APB_MR41_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_A0, 3, 21, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_A1, 3, 29, val); + /* PHY_APB_MR41_B0, PHY_APB_MR41_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_B0, 3, 5, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_B1, 3, 13, val); + + /* DRAM Tx NT ODT */ + val = (priv->dbsc5_board_config->bdcfg_tx_ntodt >> 4) & 0x1; + /* PHY_APB_MR11_A0, PHY_APB_MR11_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A0, 1, 19, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A1, 1, 27, val); + /* PHY_APB_MR11_B0, PHY_APB_MR11_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B0, 1, 3, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B1, 1, 11, val); + + /* DRAM Rx DRV */ + val = priv->dbsc5_board_config->bdcfg_rx_drv & 0x7; + /* PHY_APB_MR3_A0, PHY_APB_MR3_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR3_A0, 3, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR3_A1, 3, 24, val); + /* PHY_APB_MR3_B0, PHY_APB_MR3_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR3_B0, 3, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR3_B1, 3, 8, val); + + /* DRAM Rx Pre-emphasis */ + val = ((priv->dbsc5_board_config->bdcfg_rx_emphasis >> 12) & 0x3); + val |= ((priv->dbsc5_board_config->bdcfg_rx_emphasis >> 8) & 0x3) << 2; + val |= ((priv->dbsc5_board_config->bdcfg_rx_emphasis >> 4) & 0x3) << 4; + val |= (priv->dbsc5_board_config->bdcfg_rx_emphasis & 0x3) << 6; + /* PHY_APB_MR58_A0, PHY_APB_MR58_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR58_A0, 8, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR58_A1, 8, 24, val); + /* PHY_APB_MR58_B0, PHY_APB_MR58_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR58_B0, 8, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR58_B1, 8, 8, val); + + /* Link ECC setting */ + if (priv->link_ecc_en) { + /* PHY_APB_MR22_A0, PHY_APB_MR22_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_A0, 1, 20, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_A1, 1, 28, 0x1); + /* PHY_APB_MR22_B0, PHY_APB_MR22_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_B0, 1, 4, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_B1, 1, 12, 0x1); + /* PHY_APB_MR22_A0, PHY_APB_MR22_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_A0, 1, 22, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_A1, 1, 30, 0x1); + /* PHY_APB_MR22_B0, PHY_APB_MR22_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_B0, 1, 6, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_B1, 1, 14, 0x1); + /* PHY_APB_ALT_RL, PHY_APB_MAIN_RL */ + if (priv->ddr_mbps < (7501 * priv->ddr_mbpsdiv)) { + /* 6401 - 7500 */ + val = 0x5B; + } else { + /* 7501 - 8533 */ + val = 0x4F; + } + ddrphy_apb_rd_mod_wr(ch, PHY_APB_ALT_RL, 8, 24, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MAIN_RL, 8, 0, val); + } + } +} + +/** + * dbsc5_phy_data_load() - Load PHY data memory + * @dev: DBSC5 device + */ +static void dbsc5_phy_data_load(struct udevice *dev) +{ + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_STARTDCCMCLEAR, 0x0); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0x0); + dbsc5_rtdmac_phyinit_trans_ach(dev, DDR_PHY_DCCM_OFS, + (uintptr_t)DMAC_TRANS_DCCM, + ARRAY_SIZE(DMAC_TRANS_DCCM) * 4); + dbsc5_ddr_smb_config(dev); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0x1); +} + +/** + * dbsc5_phy_init_load() - Load PHY init memory + * @dev: DBSC5 device + */ +static void dbsc5_phy_init_load(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, i; + + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab4); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab4[i].addr, cpu_trans_tab4[i].data); + + if (priv->ddr_mbps < (6401 * priv->ddr_mbpsdiv)) /* 5501 - 6400 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x2d56); + + foreach_vphych(dev, ch) { + if ((priv->ch_have_this_cs[1] & (0x3 << (ch * 2))) != 0x0) { + dbsc5_phy_apb_wr(ch, PHY_PPGC_HWTLPCSENA, 0x3); + dbsc5_phy_apb_wr(ch, PHY_INITENG_SEQ0BGPR14, 0x3); + dbsc5_phy_apb_wr(ch, PHY_PPGC_HWTLPCSENB, 0x3); + dbsc5_phy_apb_wr(ch, PHY_INITENG_SEQ0BGPR15, 0x3); + } + } + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0); + dbsc5_phy_apb_wr_ach(dev, 0x41000, 0); + dbsc5_phy_apb_wr_ach(dev, 0x41001, 0); + dbsc5_phy_apb_wr_ach(dev, 0x41002, 0); + dbsc5_phy_apb_wr_ach(dev, 0x41003, 0); + + dbsc5_rtdmac_phyinit_trans_ach(dev, DDR_PHY_ACSM_OFS, + (uintptr_t)DMAC_TRANS_ACSM, + ARRAY_SIZE(DMAC_TRANS_ACSM) * 4); + + dbsc5_rtdmac_phyinit_trans_ach(dev, DDR_PHY_PIE_OFS, + (uintptr_t)DMAC_TRANS_PIE, + ARRAY_SIZE(DMAC_TRANS_PIE) * 4); + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_SEQUENCEROVERRIDE, 0x600); + dbsc5_phy_apb_wr_ach(dev, PHY_PPGC_ACSMNOPADDR, 0x0); + + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_PPGC_ACSMSTARTADDRXLATVAL0, + (uintptr_t)DATA_A, 64); + + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab5); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab5[i].addr, cpu_trans_tab5[i].data); + + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_PPGC_ACSMSTOPADDRXLATVAL0, + (uintptr_t)DATA_B, 64); + + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab6); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab6[i].addr, cpu_trans_tab6[i].data); + + if (priv->ddr_mbps < (6401 * priv->ddr_mbpsdiv)) /* 5501 - 6400 */ + dbsc5_phy_apb_wr_ach(dev, PHY_PPGC_ACSMRPTCNTOVERRIDE, 0x2); + else if (priv->ddr_mbps < (7501 * priv->ddr_mbpsdiv)) /* 6401 - 7500 */ + dbsc5_phy_apb_wr_ach(dev, PHY_PPGC_ACSMRPTCNTOVERRIDE, 0x3); + else if (priv->ddr_mbps < (8534 * priv->ddr_mbpsdiv)) { /* 7501 - 8533 */ + } else /* 8534 - 9600 */ + dbsc5_phy_apb_wr_ach(dev, PHY_PPGC_ACSMRPTCNTOVERRIDE, 0x5); + + dbsc5_rtdmac_phyinit_trans_ach(dev, 0x41004, (uintptr_t)ACSM_0, 384); + + if (priv->ddr_mbps < (6401 * priv->ddr_mbpsdiv)) { /* 5501 - 6400 */ + dbsc5_phy_apb_wr_ach(dev, 0x41009, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41011, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41016, 0xD848); + dbsc5_phy_apb_wr_ach(dev, 0x41019, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4101E, 0xDDC8); + dbsc5_phy_apb_wr_ach(dev, 0x41021, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41029, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41031, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41039, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41045, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4104D, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41055, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4105D, 0x4B000000); + } else if (priv->ddr_mbps < (7501 * priv->ddr_mbpsdiv)) { /* 6401 - 7500 */ + dbsc5_phy_apb_wr_ach(dev, 0x41016, 0xE048); + dbsc5_phy_apb_wr_ach(dev, 0x4101E, 0xE648); + } else if (priv->ddr_mbps < (8534 * priv->ddr_mbpsdiv)) { /* 7501 - 8533 */ + /* Nothing */ + } else { /* 8534 - 9600 */ + dbsc5_phy_apb_wr_ach(dev, 0x41009, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41011, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41016, 0xF048); + dbsc5_phy_apb_wr_ach(dev, 0x41019, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4101E, 0xF748); + dbsc5_phy_apb_wr_ach(dev, 0x41021, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41029, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41031, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41039, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41045, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4104D, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41055, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4105D, 0x6B000000); + } + + dbsc5_rtdmac_phyinit_trans_ach(dev, 0x4110C, (uintptr_t)ACSM_123, 384); + dbsc5_rtdmac_phyinit_trans_ach(dev, 0x41214, (uintptr_t)ACSM_123, 384); + dbsc5_rtdmac_phyinit_trans_ach(dev, 0x4131C, (uintptr_t)ACSM_123, 384); + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_SEQUENCEROVERRIDE, 0x400); + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_PIEINITVECSEL, 0x5821); + + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_INITENG_SEQ0BDISABLEFLAG0, + (uintptr_t)DATA_C, 64); + + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab7); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab7[i].addr, cpu_trans_tab7[i].data); + + dbsc5_ddr_config_post(dev); + + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_UCCLKHCLKENABLES, 0x6); + + if (priv->ddr_mbps < (6481 * priv->ddr_mbpsdiv)) { /* 5401 - 6480 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x1C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x1C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x2D56); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } else if (priv->ddr_mbps < (8537 * priv->ddr_mbpsdiv)) { /* 6481 - 8536 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x1956); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } else { /* 8537 - 9600 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x1956); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0x1); +} + +/** + * dbsc5_phy_training() - Perform PHY training and read message block back + * @dev: DBSC5 device + */ +static u32 dbsc5_phy_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 phytrainingok = 0; + u32 fail_flag = 0; + u32 ch, val; + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0x1); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICRORESET, 0x9); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICRORESET, 0x1); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICRORESET, 0x0); + + while ((phytrainingok != priv->ddr_phyvalid) && !fail_flag) { + foreach_vphych(dev, ch) { + val = dbsc5_phy_apb_msg_rd(ch); + if (val == 0x7) /* Training complete */ + phytrainingok |= BIT(ch); + else if (val == 0xFF) /* Training FAIL */ + fail_flag = 1; + } + } + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICRORESET, 1); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0); + + return phytrainingok; +} + +/** + * dbsc5_ddr_config() - Configure DBSC5 registers + * @dev: DBSC5 device + */ +static void dbsc5_ddr_config(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, ddr_ch, i, tmp, val; + + foreach_vphych(dev, ch) { + /* Frequency settings */ + if (priv->ddr_mbps < (6401 * priv->ddr_mbpsdiv)) { /* 5501 - 6400 */ + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab3_6400); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab3_6400[i].addr, cpu_trans_tab3_6400[i].data); + } else if (priv->ddr_mbps < (7501 * priv->ddr_mbpsdiv)) { /* 6401 - 7500 */ + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab3_7500); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab3_7500[i].addr, cpu_trans_tab3_7500[i].data); + } else if (priv->ddr_mbps < (8534 * priv->ddr_mbpsdiv)) { /* 7501 - 8533 */ + /* Nothing */ + } else { /* 8534 - 9600 */ + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab3_9600); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab3_9600[i].addr, cpu_trans_tab3_9600[i].data); + } + + /* 2-Rank settings */ + if (priv->ch_have_this_cs[1] & (0x3 << (ch * 2))) { + /* PHY_ACx_P0_PCLKACLNDIS[9] : Tx SEC lane1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_AC_PCLKACLNDIS(0), 1, 9, 0x0); + ddrphy_apb_rd_mod_wr(ch, PHY_AC_PCLKACLNDIS(1), 1, 9, 0x0); + /* PHY_ACx_P0_DFICLKACLNDIS[9] : Tx SEC lane1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_AC_DFICLKACLNDIS(0), 1, 9, 0x0); + ddrphy_apb_rd_mod_wr(ch, PHY_AC_DFICLKACLNDIS(1), 1, 9, 0x0); + /* PHY_ACx_P0_ACLNDISABLE[9] : Tx SEC lane1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_AC_ACLNDISABLE(0), 1, 9, 0x0); + ddrphy_apb_rd_mod_wr(ch, PHY_AC_ACLNDISABLE(1), 1, 9, 0x0); + /* PHY_DBYTEx_P0_PPTCTLSTATIC[1] : PptEnDqs2DqTg1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(0), 1, 1, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(1), 1, 1, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(2), 1, 1, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(3), 1, 1, 0x1); + /* PHY_DBYTEx_P0_PPTCTLSTATIC[5] : PptEnWck2DqoTg1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(0), 1, 5, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(1), 1, 5, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(2), 1, 5, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(3), 1, 5, 0x1); + /* PHY_DBYTEx_P0_PPTCTLSTATIC[9] : PptEnRxEnDlyTg1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(0), 1, 9, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(1), 1, 9, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(2), 1, 9, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(3), 1, 9, 0x1); + } + + /* BOARD SETTINGS (CA, DQ, DMI) */ + /* CA_SWAP_CHA */ + ddr_ch = (ch * 2); + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_ca_swap & 0xfffffff; + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA0TODFI(0), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA1TODFI(0), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA2TODFI(0), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA3TODFI(0), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA4TODFI(0), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA5TODFI(0), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA6TODFI(0), (val >> 24) & 0xf); + + /* DQ_SWAP_CHA_SLICE0 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dq_swap[0] & 0xffffffff; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ0LNSEL(0), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ1LNSEL(0), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ2LNSEL(0), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ3LNSEL(0), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ4LNSEL(0), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ5LNSEL(0), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ6LNSEL(0), (val >> 24) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ7LNSEL(0), (val >> 28) & 0xf); + + /* DM_SWAP_CHA_SLICE0 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dm_swap[0] & 0xf; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ8LNSEL(0), val & 0xf); + + /* DQ_SWAP_CHA_SLICE1 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dq_swap[1] & 0xffffffff; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ0LNSEL(1), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ1LNSEL(1), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ2LNSEL(1), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ3LNSEL(1), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ4LNSEL(1), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ5LNSEL(1), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ6LNSEL(1), (val >> 24) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ7LNSEL(1), (val >> 28) & 0xf); + + /* DM_SWAP_CHA_SLICE1 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dm_swap[1] & 0xf; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ8LNSEL(1), val & 0xf); + + /* CA_SWAP_CHB */ + ddr_ch = ((ch * 2) + 1); + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_ca_swap & 0xfffffff; + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA0TODFI(1), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA1TODFI(1), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA2TODFI(1), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA3TODFI(1), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA4TODFI(1), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA5TODFI(1), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA6TODFI(1), (val >> 24) & 0xf); + + /* DQ_SWAP_CHB_SLICE0 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dq_swap[0] & 0xffffffff; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ0LNSEL(2), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ1LNSEL(2), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ2LNSEL(2), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ3LNSEL(2), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ4LNSEL(2), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ5LNSEL(2), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ6LNSEL(2), (val >> 24) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ7LNSEL(2), (val >> 28) & 0xf); + + /* DM_SWAP_CHB_SLICE0 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dm_swap[0] & 0xf; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ8LNSEL(2), val & 0xf); + + /* DQ_SWAP_CHB_SLICE1 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dq_swap[1] & 0xffffffff; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ0LNSEL(3), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ1LNSEL(3), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ2LNSEL(3), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ3LNSEL(3), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ4LNSEL(3), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ5LNSEL(3), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ6LNSEL(3), (val >> 24) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ7LNSEL(3), (val >> 28) & 0xf); + + /* DM_SWAP_CHB_SLICE1 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dm_swap[1] & 0xf; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ8LNSEL(3), val & 0xf); + + /* BOARD SETTINGS (DATA_BYTE_SWAP) */ + priv->upper_lower_byte[ch] = 0x0; + ddr_ch = ch * 2; + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dqs_swap; + if ((val & 0xff) == 0x1) { + /* PHY_DBYTEx_P0_PPTCTLSTATIC[3][2] : DOCByteSelTg1/0 */ + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(0), 2, 2, 0x3); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(1), 2, 2, 0x0); + priv->upper_lower_byte[ch] |= 0x3; + } + + ddr_ch = (ch * 2) + 1; + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dqs_swap; + if ((val & 0xFF) == 0x1) { + /* PHY_DBYTEx_P0_PPTCTLSTATIC[3][2] : DOCByteSelTg1/0 */ + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(2), 2, 2, 0x3); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(3), 2, 2, 0x0); + priv->upper_lower_byte[ch] |= 0xc; + } + } + + /* Configure IO parameters */ + /* SOC Tx DRV for DQ */ + val = priv->dbsc5_board_config->bdcfg_tx_drv & 0xf; + tmp = (val << 4) | val; + for (i = 0; i < 8; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_TXIMPEDANCEDQ(i), tmp); + + /* SOC Tx DRV for DQS */ + val = (priv->dbsc5_board_config->bdcfg_tx_drv >> 4) & 0xF; + tmp = (val << 8) | val; + for (i = 0; i < 8; i += 2) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_TXIMPEDANCEDQS(i), tmp); + + /* SOC Tx DRV for WCK */ + val = (priv->dbsc5_board_config->bdcfg_tx_drv >> 8) & 0xF; + tmp = (val << 12) | (val << 8) | (val << 4) | val; + for (i = 0; i < 8; i += 2) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_TXIMPEDANCEDQS(i + 1), tmp); + + /* SOC Tx DRV for CK */ + val = (priv->dbsc5_board_config->bdcfg_tx_drv >> 12) & 0xF; + tmp = (val << 4) | val; + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXIMPEDANCEAC(5), tmp); + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXIMPEDANCEAC(12), tmp); + + /* SOC Tx DRV for AC */ + val = (priv->dbsc5_board_config->bdcfg_tx_drv >> 16) & 0xF; + tmp = (val << 4) | val; + for (i = 0; i < 4; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXIMPEDANCEAC(i), tmp); + for (i = 0; i < 4; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXIMPEDANCEAC(i + 7), tmp); + + /* SOC Tx FFC for DQ */ + /* Rise */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 28) & 0xF; + tmp = val; + /* Fall */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 24) & 0xF; + tmp |= (val << 4); + for (i = 0; i < 8; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_TXDQSLEW(i), tmp); + + /* SOC Tx FFC for CA */ + /* Rise */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 20) & 0xF; + tmp = val; + /* Fall */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 16) & 0xF; + tmp |= (val << 4); + for (i = 0; i < 4; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXSLEWAC(i), tmp); + for (i = 0; i < 4; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXSLEWAC(i + 7), tmp); + + /* SOC Tx FFC for CK */ + /* Rise */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 12) & 0xF; + tmp = val; + /* Fall */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 8) & 0xF; + tmp |= (val << 4); + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXSLEWAC(5), tmp); + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXSLEWAC(12), tmp); + + /* SOC Rx ODT for DQ */ + val = priv->dbsc5_board_config->bdcfg_rx_odt & 0xF; + tmp = val << 4; + for (i = 0; i < 8; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_ODTIMPEDANCEDQ(i), tmp); + + /* SOC Rx ODT for DQS */ + val = (priv->dbsc5_board_config->bdcfg_rx_odt >> 4) & 0xF; + tmp = (val << 12) | (val << 8); + for (i = 0; i < 8; i += 2) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_ODTIMPEDANCEDQS(i), tmp); + + /* SOC Rx ODT for WCK */ + val = (priv->dbsc5_board_config->bdcfg_rx_odt >> 8) & 0xF; + tmp = (val << 12) | (val << 8); + for (i = 0; i < 8; i += 2) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_ODTIMPEDANCEDQS(i + 1), tmp); + + /* SOC Rx ODT for CK */ + val = (priv->dbsc5_board_config->bdcfg_rx_odt >> 12) & 0xF; + tmp = val << 4; + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_ODTIMPEDANCEAC(5), tmp); + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_ODTIMPEDANCEAC(12), tmp); + + /* SOC Rx ODT for AC */ + val = (priv->dbsc5_board_config->bdcfg_rx_odt >> 16) & 0xF; + tmp = val << 4; + for (i = 0; i < 5; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_ODTIMPEDANCEAC(i), tmp); + for (i = 0; i < 5; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_ODTIMPEDANCEAC(i + 7), tmp); + + /* Link ECC setting */ + if (priv->link_ecc_en) + for (i = 0; i < 4; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_DBYTE_ENABLEWRITELINKECC(i), 0x1); +} + +/** + * dbsc5_phy_init() - Initialize DBSC5 PHY + * @dev: DBSC5 device + */ +static void dbsc5_phy_init(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, i; + + /* Initialize PHY Configuration */ + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab1); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab1[i].addr, cpu_trans_tab1[i].data); + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab2); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab2[i].addr, cpu_trans_tab2[i].data); + + if (priv->ddr_mbps < (6481 * priv->ddr_mbpsdiv)) { /* 5401 - 6480 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x808); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x1C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x2E9A); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } else if (priv->ddr_mbps < (8537 * priv->ddr_mbpsdiv)) { /* 6481 - 8536 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x1008); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x1A9A); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } else { + /* 8537 - 9600 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x1008); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x1A9A); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } + + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_UCCLKHCLKENABLES, 0x5); + + dbsc5_rtdmac_phyinit_trans_ach(dev, DDR_PHY_ICCM_OFS, + (uintptr_t)DMAC_TRANS_ICCM, + ARRAY_SIZE(DMAC_TRANS_ICCM) * 4); + + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_UCCLKHCLKENABLES, 0x7); + + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab3); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab3[i].addr, cpu_trans_tab3[i].data); + + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_PPGC_ACSMDONE, ((uintptr_t)DATA_3_1), 128); + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_INITENG_SEQ0BGPR1, ((uintptr_t)DATA_3_2), 128); + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_INITENG_SEQ0BDLY0, ((uintptr_t)DATA_3_3), 64); + for (i = 0; i < 8; i += 2) { + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_HMDBYTE_VREGCTRL1DQ(i), + (uintptr_t)DATA_3_4, 256); + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_HMDBYTE_VREGCTRL1DQ(i + i), + (uintptr_t)DATA_3_5, 256); + } + + dbsc5_ddr_config(dev); + + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_STARTDCCMCLEAR, 0x1); +} + +/** + * dbsc5_dfi_wait_init_complete() - Wait DFI init completion + * @dev: DBSC5 device + */ +static void dbsc5_dfi_wait_init_complete(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 retry = 0, phytrainingok = 0; + const u32 RETRY_MAX = 0x10000; + u32 ch, val; + + while (retry < RETRY_MAX) { + foreach_vch(dev, ch) { + val = readl(DBSC_DBDFISTAT(ch)); + if (val & 0x1) + phytrainingok |= BIT(ch); + } + + if (phytrainingok == priv->ddr_dramvalid) + break; + + retry++; + } +} + +/** + * dbsc5_dfi_init_start() - Start DFI initialization + * @dev: DBSC5 device + */ +static void dbsc5_dfi_init_start(struct udevice *dev) +{ + u32 ch; + + foreach_vch(dev, ch) + writel(0x21, DBSC_DBDFICNT(ch)); + + dbsc5_dfi_wait_init_complete(dev); + + foreach_vch(dev, ch) + writel(0x20, DBSC_DBDFICNT(ch)); +} + +/** + * dbsc5_ddr_mode_register_set() - Set DDR mode registers + * @dev: DBSC5 device + */ +static void dbsc5_ddr_mode_register_set(struct udevice *dev) +{ + dbsc5_send_dbcmd(dev, 0xE841C24); /* MR28 */ + dbsc5_send_dbcmd(dev, 0xE842540); + dbsc5_send_dbcmd(dev, 0xE842840); +} + +/** + * dbsc5_ddr_mode_register_read() - Read DDR mode registers + * @dev: DBSC5 device + */ +static void dbsc5_ddr_mode_register_read(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, val; + + val = priv->dbsc5_board_config->bdcfg_rfm_chk; + if (!val) + return; + + dbsc5_send_dbcmd(dev, 0xF801B00); /* MR27:0 */ + dbsc5_send_dbcmd(dev, 0xF803900); /* MR57:0 */ + + foreach_vphych(dev, ch) { + if ((priv->ch_have_this_cs[1] & (0x3 << (ch * 2)))) { + dbsc5_send_dbcmd_ch(ch, 0xF811B00); /* MR27:1 */ + dbsc5_send_dbcmd_ch(ch, 0xF813900); /* MR57:1 */ + } + } +} + +/** + * dbsc5_phy_pll_lock_status_read() - Read PHY PLL lock status + * @dev: DBSC5 device + */ +static u32 dbsc5_phy_pll_lock_status_read(struct udevice *dev) +{ + u32 ch, ret = 0; + + foreach_vphych(dev, ch) + ret |= (readl(DBSC_DBPDSTAT01(ch)) & BIT(0)) << ch; + + return ret; +} + +/** + * dbsc5_ddr_initialize() - Initialize DDR + * @dev: DBSC5 device + */ +static int dbsc5_ddr_initialize(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ddrphy_pll_lock_ok, phytrainingok; + + dbsc5_regset_unlock(dev); + dbsc5_msres_status_set(dev, MODULE_STANDBY); + dbsc5_init_pll3(dev); + dbsc5_msres_status_set(dev, MODULE_RUN); + dbsc5_phy_init(dev); + dbsc5_dbsc_regset_pre(dev); + dbsc5_phy_data_load(dev); + phytrainingok = dbsc5_phy_training(dev); + if (phytrainingok != priv->ddr_phyvalid) + return -EINVAL; + + dbsc5_phy_init_load(dev); + dbsc5_dfi_init_start(dev); + ddrphy_pll_lock_ok = dbsc5_phy_pll_lock_status_read(dev); + if (ddrphy_pll_lock_ok != priv->ddr_phyvalid) + return -EINVAL; + + dbsc5_ddr_mode_register_set(dev); + dbsc5_ddr_mode_register_read(dev); + + dbsc5_dbsc_regset_post(dev); + dbsc5_regset_lock(dev); + + return 0; +} + +/** + * dbsc5_get_board_data() - Obtain board specific DRAM configuration + * @dev: DBSC5 device + * + * Return board specific DRAM configuration structure pointer. + */ +__weak const struct renesas_dbsc5_board_config * +dbsc5_get_board_data(struct udevice *dev) +{ + return &renesas_x5h_dbsc5_board_config; +} + +/** + * renesas_dbsc5_dram_probe() - DDR Initialize entry + * @dev: DBSC5 device + * + * Remove write protection on DBSC register. Read DDR configuration + * information from driver data. Calculate board clock frequency and + * operating frequency from DDR configuration information. Call the + * main function of DDR initialization. Perform DBSC write protection + * after initialization is complete. + */ +static int renesas_dbsc5_dram_probe(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, cs, i; + + priv->dbsc5_board_config = dbsc5_get_board_data(dev); + + /* Link ECC only on SoC > 1.0 */ + if (renesas_get_cpu_rev_integer() == 1 && renesas_get_cpu_rev_fraction() == 0) + priv->link_ecc_en = 0; + else + priv->link_ecc_en = 1; + + priv->ddr_dramvalid = (u32)(priv->dbsc5_board_config->bdcfg_phyvalid); + priv->ddr_phyvalid = 0x0; + for (i = 0; i < DBSC5_PHYNUM_CNT; i++) { + priv->ddr_phyvalid |= ((((priv->ddr_dramvalid >> (i * 2)) | + (priv->ddr_dramvalid >> ((i * 2) + 1))) & 0x1) << i); + } + + for (cs = 0; cs < CS_CNT; cs++) + priv->ch_have_this_cs[cs] = 0; + + foreach_vch(dev, ch) + for (cs = 0; cs < CS_CNT; cs++) + if (priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs] != 0xff) + priv->ch_have_this_cs[cs] |= BIT(ch); + + /* Determine board clock frequency (in MHz) */ + priv->brd_clkdiv = 3; + switch (readl(SYSSS_PLL6_CR0)) { + case 0xa700000: /* 50 / 3 = 16.66MHz */ + priv->brd_clk = 50; + break; + case 0x8b00000: /* 60 / 3 = 20.00MHz */ + priv->brd_clk = 60; + break; + case 0xa700080: /* 100 / 3 = 33.33MHz */ + priv->brd_clk = 100; + break; + default: /* 50 / 3 = 16.66MHz */ + priv->brd_clk = 50; + break; + } + + priv->brd_clkdiva = !!(readl(SYSSS_PLL6_CR0) & BIT(7)); + + /* Determine DDR operating frequency clock (in Mbps) */ + priv->ddr_mbps = 6400; + priv->ddr_mbpsdiv = 1; + + /* Initialize DDR */ + return dbsc5_ddr_initialize(dev); +} + +/** + * renesas_dbsc5_dram_of_to_plat() - Convert OF data to plat data + * @dev: DBSC5 device + * + * Extract DBSC5 address from DT and store it in driver data. + */ +static int renesas_dbsc5_dram_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +/** + * renesas_dbsc5_dram_get_info() - Return RAM size + * @dev: DBSC5 device + * @info: Output RAM info + * + * Return size of the RAM managed by this RAM driver. + */ +static int renesas_dbsc5_dram_get_info(struct udevice *dev, + struct ram_info *info) +{ + info->base = 0x40000000; + info->size = 0; + + return 0; +} + +static const struct ram_ops renesas_dbsc5_dram_ops = { + .get_info = renesas_dbsc5_dram_get_info, +}; + +U_BOOT_DRIVER(renesas_dbsc5_dram) = { + .name = "dbsc5_dram", + .id = UCLASS_RAM, + .of_to_plat = renesas_dbsc5_dram_of_to_plat, + .ops = &renesas_dbsc5_dram_ops, + .probe = renesas_dbsc5_dram_probe, + .priv_auto = sizeof(struct renesas_dbsc5_dram_priv), +}; diff --git a/drivers/ram/renesas/dbsc5/r8a78000-dram.h b/drivers/ram/renesas/dbsc5/r8a78000-dram.h new file mode 100644 index 00000000000..ec810cd54bb --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a78000-dram.h @@ -0,0 +1,7385 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DRAM_H__ +#define __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DRAM_H__ + +#define DDR_PHY_ICCM_OFS 0x00050000U +#define DDR_PHY_DCCM_OFS 0x00058000U +#define DDR_PHY_ACSM_OFS 0x00041454U +#define DDR_PHY_PIE_OFS 0x00044000U + +struct phyinitdata { + u32 addr; + u32 data; +}; + +static const struct phyinitdata cpu_trans_tab1[] = { + { 0x00030022, 0x00000002 }, + { 0x00031022, 0x00000002 }, + { 0x00004070, 0x000000FF }, + { 0x00005070, 0x00000077 }, + { 0x0000B070, 0x000000FF }, + { 0x0000C070, 0x00000077 }, + { 0x00104070, 0x000000FF }, + { 0x00105070, 0x00000077 }, + { 0x0010B070, 0x000000FF }, + { 0x0010C070, 0x00000077 }, + { 0x00204070, 0x000000FF }, + { 0x00205070, 0x00000077 }, + { 0x0020B070, 0x000000FF }, + { 0x0020C070, 0x00000077 }, + { 0x00304070, 0x000000FF }, + { 0x00305070, 0x00000077 }, + { 0x0030B070, 0x000000FF }, + { 0x0030C070, 0x00000077 }, + { 0x00000005, 0x00000003 }, + { 0x00001005, 0x00000003 }, + { 0x00002005, 0x00000003 }, + { 0x00003005, 0x00000003 }, + { 0x00004005, 0x00000003 }, + { 0x00005005, 0x00000003 }, + { 0x00007005, 0x00000003 }, + { 0x00008005, 0x00000003 }, + { 0x00009005, 0x00000003 }, + { 0x0000A005, 0x00000003 }, + { 0x0000B005, 0x00000003 }, + { 0x0000C005, 0x00000003 }, + { 0x000A0308, 0x00000002 }, + { 0x000A0002, 0x00000001 }, + { 0x000E0046, 0x00000006 }, + { 0x000E0047, 0x00000006 }, + { 0x000E0048, 0x00000006 }, + { 0x000E0049, 0x00000006 }, + { 0x000E1046, 0x00000006 }, + { 0x000E1047, 0x00000006 }, + { 0x000E1048, 0x00000006 }, + { 0x000E1049, 0x00000006 }, + { 0x000E104A, 0x00000006 }, + { 0x000E004B, 0x00000006 }, + { 0x000E104B, 0x00000006 }, + { 0x000E2046, 0x00000006 }, + { 0x000E2047, 0x00000006 }, + { 0x000E2048, 0x00000006 }, + { 0x000E2049, 0x00000006 }, + { 0x000E3046, 0x00000006 }, + { 0x000E3047, 0x00000006 }, + { 0x000E3048, 0x00000006 }, + { 0x000E3049, 0x00000006 }, + { 0x000E304A, 0x00000006 }, + { 0x000E204B, 0x00000006 }, + { 0x000E304B, 0x00000006 }, + { 0x000E4046, 0x00000006 }, + { 0x000E4047, 0x00000006 }, + { 0x000E4048, 0x00000006 }, + { 0x000E4049, 0x00000006 }, + { 0x000E5046, 0x00000006 }, + { 0x000E5047, 0x00000006 }, + { 0x000E5048, 0x00000006 }, + { 0x000E5049, 0x00000006 }, + { 0x000E504A, 0x00000006 }, + { 0x000E404B, 0x00000006 }, + { 0x000E504B, 0x00000006 }, + { 0x000E6046, 0x00000006 }, + { 0x000E6047, 0x00000006 }, + { 0x000E6048, 0x00000006 }, + { 0x000E6049, 0x00000006 }, + { 0x000E7046, 0x00000006 }, + { 0x000E7047, 0x00000006 }, + { 0x000E7048, 0x00000006 }, + { 0x000E7049, 0x00000006 }, + { 0x000E704A, 0x00000006 }, + { 0x000E604B, 0x00000006 }, + { 0x000E704B, 0x00000006 }, + { 0x00030020, 0x00000001 }, + { 0x00031020, 0x00000001 } +}; + +static const struct phyinitdata cpu_trans_tab2[] = { + { 0x00000005, 0x00000003 }, + { 0x00001005, 0x00000003 }, + { 0x00002005, 0x00000003 }, + { 0x00003005, 0x00000003 }, + { 0x00004005, 0x00000003 }, + { 0x00005005, 0x00000003 }, + { 0x00007005, 0x00000003 }, + { 0x00008005, 0x00000003 }, + { 0x00009005, 0x00000003 }, + { 0x0000A005, 0x00000003 }, + { 0x0000B005, 0x00000003 }, + { 0x0000C005, 0x00000003 }, + { 0x000A0308, 0x00000000 }, + { 0x000A0002, 0x00000001 }, + { 0x000E0046, 0x00000000 }, + { 0x000E0047, 0x00000000 }, + { 0x000E0048, 0x00000000 }, + { 0x000E0049, 0x00000000 }, + { 0x000E1046, 0x00000000 }, + { 0x000E1047, 0x00000000 }, + { 0x000E1048, 0x00000000 }, + { 0x000E1049, 0x00000000 }, + { 0x000E104A, 0x00000000 }, + { 0x000E004B, 0x00000002 }, + { 0x000E104B, 0x00000004 }, + { 0x000E2046, 0x00000000 }, + { 0x000E2047, 0x00000000 }, + { 0x000E2048, 0x00000000 }, + { 0x000E2049, 0x00000000 }, + { 0x000E3046, 0x00000000 }, + { 0x000E3047, 0x00000000 }, + { 0x000E3048, 0x00000000 }, + { 0x000E3049, 0x00000000 }, + { 0x000E304A, 0x00000000 }, + { 0x000E204B, 0x00000002 }, + { 0x000E304B, 0x00000004 }, + { 0x000E4046, 0x00000000 }, + { 0x000E4047, 0x00000000 }, + { 0x000E4048, 0x00000000 }, + { 0x000E4049, 0x00000000 }, + { 0x000E5046, 0x00000000 }, + { 0x000E5047, 0x00000000 }, + { 0x000E5048, 0x00000000 }, + { 0x000E5049, 0x00000000 }, + { 0x000E504A, 0x00000000 }, + { 0x000E404B, 0x00000002 }, + { 0x000E504B, 0x00000004 }, + { 0x000E6046, 0x00000000 }, + { 0x000E6047, 0x00000000 }, + { 0x000E6048, 0x00000000 }, + { 0x000E6049, 0x00000000 }, + { 0x000E7046, 0x00000000 }, + { 0x000E7047, 0x00000000 }, + { 0x000E7048, 0x00000000 }, + { 0x000E7049, 0x00000000 }, + { 0x000E704A, 0x00000000 }, + { 0x000E604B, 0x00000002 }, + { 0x000E704B, 0x00000004 }, + { 0x000200A5, 0x00000001 }, + { 0x00010097, 0x000007FF }, + { 0x00011097, 0x000007FF }, + { 0x00012097, 0x000007FF }, + { 0x00013097, 0x000007FF }, + { 0x0001003F, 0x00000001 }, + { 0x0001003F, 0x00000000 }, + { 0x0001103F, 0x00000001 }, + { 0x0001103F, 0x00000000 }, + { 0x0001203F, 0x00000001 }, + { 0x0001203F, 0x00000000 }, + { 0x0001303F, 0x00000001 }, + { 0x0001303F, 0x00000000 }, + { 0x000B0303, 0x00000009 }, + { 0x000A0302, 0x00000026 }, + { 0x000B0301, 0x00000000 }, + { 0x000B030F, 0x0000001D }, + { 0x00070067, 0x00000000 }, + { 0x000700E7, 0x00000000 }, + { 0x000300AE, 0x00001A80 }, + { 0x000300AD, 0x00001A80 }, + { 0x000300AC, 0x00001A80 }, + { 0x000310AE, 0x00001A80 }, + { 0x000310AD, 0x00001A80 }, + { 0x000310AC, 0x00001A80 }, + { 0x000100A3, 0x00000911 }, + { 0x000110A3, 0x0000091D }, + { 0x000120A3, 0x00000911 }, + { 0x000130A3, 0x0000091D }, + { 0x000C00F0, 0x00000001 }, + { 0x000C00F1, 0x00000002 }, + { 0x000C00F2, 0x00000007 }, + { 0x000C00F3, 0x00000034 }, + { 0x00090733, 0x0000002D }, + { 0x000C00F4, 0x00000005 }, + { 0x000C00F7, 0x0000F000 }, + { 0x00090737, 0x00000A00 }, + { 0x0009071F, 0x00000004 }, + { 0x00090829, 0x0000000F }, + { 0x00020007, 0x00000000 }, + { 0x000E007A, 0x00000000 }, + { 0x000E107A, 0x00000001 }, + { 0x000E207A, 0x00000000 }, + { 0x000E307A, 0x00000001 }, + { 0x000E407A, 0x00000000 }, + { 0x000E507A, 0x00000001 }, + { 0x000E607A, 0x00000000 }, + { 0x000E707A, 0x00000001 }, + { 0x0000061E, 0x00000000 }, + { 0x0000E61E, 0x00000000 }, + { 0x0000161E, 0x00000000 }, + { 0x0000261E, 0x00000000 }, + { 0x0000361E, 0x00000000 }, + { 0x0000461E, 0x00000000 }, + { 0x0000561E, 0x00000000 }, + { 0x0000761E, 0x00000000 }, + { 0x0000861E, 0x00000000 }, + { 0x0000961E, 0x00000000 }, + { 0x0000A61E, 0x00000000 }, + { 0x0000B61E, 0x00000000 }, + { 0x0000C61E, 0x00000000 }, + { 0x00010E1F, 0x00000000 }, + { 0x00011E1F, 0x00000000 }, + { 0x00012E1F, 0x00000000 }, + { 0x00013E1F, 0x00000000 }, + { 0x00030807, 0x0000EE66 }, + { 0x00031807, 0x0000EE66 }, + { 0x00010807, 0x0000EE66 }, + { 0x00011807, 0x0000EE66 }, + { 0x00012807, 0x0000EE66 }, + { 0x00013807, 0x0000EE66 }, + { 0x000300A0, 0x00003FFF }, + { 0x000310A0, 0x00003FFF }, + { 0x00010089, 0x00001FFF }, + { 0x0001008A, 0x000007FF }, + { 0x00011089, 0x00001FFF }, + { 0x0001108A, 0x000007FF }, + { 0x00012089, 0x00001FFF }, + { 0x0001208A, 0x000007FF }, + { 0x00013089, 0x00001FFF }, + { 0x0001308A, 0x000007FF }, + { 0x00020006, 0x0000000F }, + { 0x0002000C, 0x00000000 }, + { 0x000E000D, 0x00000001 }, + { 0x000E100D, 0x00000001 }, + { 0x000E200D, 0x00000001 }, + { 0x000E300D, 0x00000001 }, + { 0x000E400D, 0x00000001 }, + { 0x000E500D, 0x00000001 }, + { 0x000E600D, 0x00000001 }, + { 0x000E700D, 0x00000001 }, + { 0x00030027, 0x00000001 }, + { 0x0000003F, 0x00000001 }, + { 0x0000103F, 0x00000001 }, + { 0x0000203F, 0x00000001 }, + { 0x0000303F, 0x00000001 }, + { 0x0000403F, 0x00000001 }, + { 0x0000503F, 0x00000001 }, + { 0x00031027, 0x00000001 }, + { 0x0000703F, 0x00000001 }, + { 0x0000803F, 0x00000001 }, + { 0x0000903F, 0x00000001 }, + { 0x0000A03F, 0x00000001 }, + { 0x0000B03F, 0x00000001 }, + { 0x0000C03F, 0x00000001 } +}; + +static const struct phyinitdata cpu_trans_tab3[] = { + { 0x0002008B, 0x00000000 }, + { 0x000A03FF, 0x00004101 }, + { 0x000A030B, 0x00000000 }, + { 0x00060008, 0x00000E9A }, + { 0x00020002, 0x00000007 }, + { 0x00060040, 0x00000007 }, + { 0x00020000, 0x00000002 }, + { 0x000100FB, 0x00000000 }, + { 0x000110FB, 0x00000000 }, + { 0x000120FB, 0x00000000 }, + { 0x000130FB, 0x00000000 }, + { 0x00010024, 0x00000200 }, + { 0x00011024, 0x00000200 }, + { 0x00012024, 0x00000200 }, + { 0x00013024, 0x00000200 }, + { 0x00010025, 0x0000002C }, + { 0x00011025, 0x0000002C }, + { 0x00012025, 0x0000002C }, + { 0x00013025, 0x0000002C }, + { 0x00010004, 0x00000000 }, + { 0x00010003, 0x00000000 }, + { 0x00011004, 0x00000000 }, + { 0x00011003, 0x00000000 }, + { 0x00012004, 0x00000000 }, + { 0x00012003, 0x00000000 }, + { 0x00013004, 0x00000000 }, + { 0x00013003, 0x00000000 }, + { 0x000B0004, 0x0000042A }, + { 0x000A030C, 0x00000000 }, + { 0x0001003E, 0x00000005 }, + { 0x0001103E, 0x00000005 }, + { 0x0001203E, 0x00000005 }, + { 0x0001303E, 0x00000005 }, + { 0x00020003, 0x00000001 }, + { 0x0002000B, 0x00001111 }, + { 0x00010108, 0x00000000 }, + { 0x00011108, 0x00000000 }, + { 0x00012108, 0x00000000 }, + { 0x00013108, 0x00000000 }, + { 0x00070005, 0x00000003 }, + { 0x0007000F, 0x00000000 }, + { 0x0001000E, 0x00001301 }, + { 0x0001100E, 0x00001301 }, + { 0x0001200E, 0x00001301 }, + { 0x0001300E, 0x00001301 }, + { 0x00020019, 0x00000004 }, + { 0x00000070, 0x00000077 }, + { 0x00001070, 0x00000077 }, + { 0x00002070, 0x00000077 }, + { 0x00003070, 0x00000077 }, + { 0x00004070, 0x000000FF }, + { 0x00005070, 0x00000077 }, + { 0x00007070, 0x00000077 }, + { 0x00008070, 0x00000077 }, + { 0x00009070, 0x00000077 }, + { 0x0000A070, 0x00000077 }, + { 0x0000B070, 0x000000FF }, + { 0x0000C070, 0x00000077 }, + { 0x00000079, 0x00000030 }, + { 0x00001079, 0x00000030 }, + { 0x00002079, 0x00000030 }, + { 0x00003079, 0x00000030 }, + { 0x00004079, 0x00000030 }, + { 0x00005079, 0x00000030 }, + { 0x00007079, 0x00000030 }, + { 0x00008079, 0x00000030 }, + { 0x00009079, 0x00000030 }, + { 0x0000A079, 0x00000030 }, + { 0x0000B079, 0x00000030 }, + { 0x0000C079, 0x00000030 }, + { 0x0000006D, 0x00000000 }, + { 0x0000106D, 0x00000000 }, + { 0x0000206D, 0x00000000 }, + { 0x0000306D, 0x00000000 }, + { 0x0000406D, 0x00000000 }, + { 0x0000506D, 0x00000000 }, + { 0x0000706D, 0x00000000 }, + { 0x0000806D, 0x00000000 }, + { 0x0000906D, 0x00000000 }, + { 0x0000A06D, 0x00000000 }, + { 0x0000B06D, 0x00000000 }, + { 0x0000C06D, 0x00000000 }, + { 0x00010001, 0x00000000 }, + { 0x00011001, 0x00000000 }, + { 0x00012001, 0x00000000 }, + { 0x00013001, 0x00000000 }, + { 0x00070040, 0x00000050 }, + { 0x00070041, 0x0000000F }, + { 0x000100A5, 0x00000001 }, + { 0x000110A5, 0x00000001 }, + { 0x000120A5, 0x00000001 }, + { 0x000130A5, 0x00000001 }, + { 0x00010209, 0x00003232 }, + { 0x00011209, 0x00003232 }, + { 0x00012209, 0x00003232 }, + { 0x00013209, 0x00003232 }, + { 0x0001020F, 0x00000006 }, + { 0x0001120F, 0x00000006 }, + { 0x0001220F, 0x00000006 }, + { 0x0001320F, 0x00000006 }, + { 0x00020005, 0x00001111 }, + { 0x00010008, 0x00000001 }, + { 0x00011008, 0x00000001 }, + { 0x00012008, 0x00000001 }, + { 0x00013008, 0x00000001 }, + { 0x0007006B, 0x00000111 }, + { 0x00070066, 0x00000A10 }, + { 0x000700EB, 0x00000111 }, + { 0x000700E6, 0x00000A10 }, + { 0x00030008, 0x00000000 }, + { 0x00031008, 0x00000000 }, + { 0x000005E3, 0x00000004 }, + { 0x000015E3, 0x00000004 }, + { 0x000025E3, 0x00000004 }, + { 0x000035E3, 0x00000004 }, + { 0x000045E3, 0x00000004 }, + { 0x000055E3, 0x00000004 }, + { 0x000075E3, 0x00000004 }, + { 0x000085E3, 0x00000004 }, + { 0x000095E3, 0x00000004 }, + { 0x0000A5E3, 0x00000004 }, + { 0x0000B5E3, 0x00000004 }, + { 0x0000C5E3, 0x00000004 }, + { 0x000E05E3, 0x00000004 }, + { 0x000E15E3, 0x00000004 }, + { 0x000E25E3, 0x00000004 }, + { 0x000E35E3, 0x00000004 }, + { 0x000E45E3, 0x00000004 }, + { 0x000E55E3, 0x00000004 }, + { 0x000E65E3, 0x00000004 }, + { 0x000E75E3, 0x00000004 }, + { 0x0000050A, 0x00000001 }, + { 0x0000150A, 0x00000001 }, + { 0x0000250A, 0x00000001 }, + { 0x0000350A, 0x00000001 }, + { 0x0000450A, 0x00000001 }, + { 0x0000550A, 0x00000001 }, + { 0x0000750A, 0x00000001 }, + { 0x0000850A, 0x00000001 }, + { 0x0000950A, 0x00000001 }, + { 0x0000A50A, 0x00000001 }, + { 0x0000B50A, 0x00000001 }, + { 0x0000C50A, 0x00000001 }, + { 0x0001080B, 0x00000001 }, + { 0x0001180B, 0x00000001 }, + { 0x0001280B, 0x00000001 }, + { 0x0001380B, 0x00000001 }, + { 0x00030803, 0x0000108A }, + { 0x00031803, 0x0000108A }, + { 0x00010803, 0x0000108A }, + { 0x00011803, 0x0000108A }, + { 0x00012803, 0x0000108A }, + { 0x00013803, 0x0000108A }, + { 0x00000503, 0x0000002B }, + { 0x00001503, 0x0000002B }, + { 0x00002503, 0x0000002B }, + { 0x00003503, 0x0000002B }, + { 0x00004503, 0x0000002B }, + { 0x00005503, 0x0000002B }, + { 0x00007503, 0x0000002B }, + { 0x00008503, 0x0000002B }, + { 0x00009503, 0x0000002B }, + { 0x0000A503, 0x0000002B }, + { 0x0000B503, 0x0000002B }, + { 0x0000C503, 0x0000002B }, + { 0x00010C03, 0x0000002B }, + { 0x00011C03, 0x0000002B }, + { 0x00012C03, 0x0000002B }, + { 0x00013C03, 0x0000002B }, + { 0x00000110, 0x0000001F }, + { 0x00001110, 0x0000001F }, + { 0x00002110, 0x0000001F }, + { 0x00003110, 0x0000001F }, + { 0x00004110, 0x0000001F }, + { 0x00005110, 0x0000001F }, + { 0x00007110, 0x0000001F }, + { 0x00008110, 0x0000001F }, + { 0x00009110, 0x0000001F }, + { 0x0000A110, 0x0000001F }, + { 0x0000B110, 0x0000001F }, + { 0x0000C110, 0x0000001F }, + { 0x000E0110, 0x0000001F }, + { 0x000E1110, 0x0000001F }, + { 0x000E2110, 0x0000001F }, + { 0x000E3110, 0x0000001F }, + { 0x000E4110, 0x0000001F }, + { 0x000E5110, 0x0000001F }, + { 0x000E6110, 0x0000001F }, + { 0x000E7110, 0x0000001F }, + { 0x0001010B, 0x00000003 }, + { 0x0001110B, 0x00000003 }, + { 0x0001210B, 0x00000003 }, + { 0x0001310B, 0x00000003 }, + { 0x00000063, 0x0000004E }, + { 0x00001063, 0x0000004E }, + { 0x00002063, 0x0000004E }, + { 0x00003063, 0x0000004E }, + { 0x00004063, 0x0000004E }, + { 0x00005063, 0x0000004E }, + { 0x00007063, 0x0000004E }, + { 0x00008063, 0x0000004E }, + { 0x00009063, 0x0000004E }, + { 0x0000A063, 0x0000004E }, + { 0x0000B063, 0x0000004E }, + { 0x0000C063, 0x0000004E }, + { 0x000E0063, 0x0000004E }, + { 0x000E0064, 0x0000004E }, + { 0x000E0087, 0x0000004E }, + { 0x000E1063, 0x0000004E }, + { 0x000E1064, 0x0000004E }, + { 0x000E1087, 0x0000004E }, + { 0x000E2063, 0x0000004E }, + { 0x000E2064, 0x0000004E }, + { 0x000E2087, 0x0000004E }, + { 0x000E3063, 0x0000004E }, + { 0x000E3064, 0x0000004E }, + { 0x000E3087, 0x0000004E }, + { 0x000E4063, 0x0000004E }, + { 0x000E4064, 0x0000004E }, + { 0x000E4087, 0x0000004E }, + { 0x000E5063, 0x0000004E }, + { 0x000E5064, 0x0000004E }, + { 0x000E5087, 0x0000004E }, + { 0x000E6063, 0x0000004E }, + { 0x000E6064, 0x0000004E }, + { 0x000E6087, 0x0000004E }, + { 0x000E7063, 0x0000004E }, + { 0x000E7064, 0x0000004E }, + { 0x000E7087, 0x0000004E }, + { 0x000C0080, 0x00000007 }, + { 0x000300EB, 0x00000000 }, + { 0x000310EB, 0x00000000 } +}; + +static const struct phyinitdata cpu_trans_tab4[] = { + { 0x000B0310, 0x00000001 }, + { 0x000B0311, 0x00000001 }, + { 0x00060008, 0x00000D56 }, + { 0x00060006, 0x000003F0 }, + { 0x00010075, 0x00000001 }, + { 0x00011075, 0x00000001 }, + { 0x00012075, 0x00000001 }, + { 0x00013075, 0x00000001 }, + { 0x00030015, 0x00000000 }, + { 0x00031015, 0x00000000 }, + { 0x0001007C, 0x00000000 }, + { 0x0001107C, 0x00000000 }, + { 0x0001207C, 0x00000000 }, + { 0x0001307C, 0x00000000 }, + { 0x00070141, 0x00000000 }, + { 0x000B0001, 0x00000003 }, + { 0x0009080C, 0x00000003 }, + { 0x00010027, 0x00000001 }, + { 0x00011027, 0x00000001 }, + { 0x00012027, 0x00000001 }, + { 0x00013027, 0x00000001 }, + { 0x0001020F, 0x00000009 }, + { 0x0001120F, 0x00000009 }, + { 0x0001220F, 0x00000009 }, + { 0x0001320F, 0x00000009 }, + { 0x000E003F, 0x00000001 }, + { 0x000E008D, 0x00000001 }, + { 0x000E103F, 0x00000001 }, + { 0x000E108D, 0x00000001 }, + { 0x000E203F, 0x00000001 }, + { 0x000E208D, 0x00000001 }, + { 0x000E303F, 0x00000001 }, + { 0x000E308D, 0x00000001 }, + { 0x000E403F, 0x00000001 }, + { 0x000E408D, 0x00000001 }, + { 0x000E503F, 0x00000001 }, + { 0x000E508D, 0x00000001 }, + { 0x000E603F, 0x00000001 }, + { 0x000E608D, 0x00000001 }, + { 0x000E703F, 0x00000001 }, + { 0x000E708D, 0x00000001 }, + { 0x00090903, 0x00000000 }, + { 0x00070072, 0x00000001 }, + { 0x0009080E, 0x00000001 }, + { 0x00070073, 0x00000001 }, + { 0x0009080F, 0x00000001 } +}; + +static const struct phyinitdata cpu_trans_tab5[] = { + { 0x00070334, 0x0000011B }, + { 0x00070335, 0x0000011F }, + { 0x00070336, 0x00000121 }, + { 0x00070337, 0x00000122 }, + { 0x00070339, 0x00000123 }, + { 0x0007033A, 0x00000124 }, + { 0x0007033C, 0x00000125 }, + { 0x0007033D, 0x0000013E }, + { 0x0007033E, 0x00000148 }, + { 0x0007033F, 0x00000160 }, + { 0x00070350, 0x00000170 }, + { 0x00070351, 0x00000188 }, + { 0x00070352, 0x00000191 }, + { 0x00070353, 0x000001A3 } +}; + +static const struct phyinitdata cpu_trans_tab6[] = { + { 0x0007039B, 0x0000011E }, + { 0x0007039C, 0x00000120 }, + { 0x0007039D, 0x00000121 }, + { 0x0007039E, 0x00000122 }, + { 0x000703A0, 0x00000123 }, + { 0x000703A1, 0x00000124 }, + { 0x000703A3, 0x0000013D }, + { 0x000703A4, 0x00000147 }, + { 0x000703A5, 0x0000015F }, + { 0x000703A6, 0x0000016F }, + { 0x000703B7, 0x00000187 }, + { 0x000703B8, 0x00000190 }, + { 0x000703B9, 0x000001A2 }, + { 0x000703BA, 0x000001B3 }, + { 0x00070200, 0x0000040E }, + { 0x00070202, 0x0000044F }, + { 0x00070204, 0x000000C0 }, + { 0x00070205, 0x00000246 }, + { 0x00070206, 0x00000101 }, + { 0x00070207, 0x00000287 }, + { 0x00070208, 0x00000142 }, + { 0x00070209, 0x000002C8 }, + { 0x0007020A, 0x00000012 }, + { 0x0007020B, 0x0000034C }, + { 0x0007020C, 0x00000015 }, + { 0x0007020E, 0x00000016 }, + { 0x00070212, 0x0000002C }, + { 0x00070213, 0x00000018 }, + { 0x00070214, 0x0000002D }, + { 0x00070215, 0x00000019 }, + { 0x00070216, 0x0000002E }, + { 0x00070217, 0x0000001A }, + { 0x00070218, 0x0000002F }, + { 0x00070219, 0x0000001B }, + { 0x0007021A, 0x00000013 }, + { 0x0009001C, 0x00000267 }, + { 0x0009001D, 0x00000267 }, + { 0x0009001E, 0x00000267 }, + { 0x0009001F, 0x00000267 }, + { 0x00090020, 0x000002A0 }, + { 0x00090021, 0x00000267 }, + { 0x00090022, 0x00000000 }, + { 0x00090023, 0x00000000 }, + { 0x00090024, 0x00000000 }, + { 0x00090025, 0x00000000 }, + { 0x00090026, 0x00000000 }, + { 0x00090027, 0x00000000 }, + { 0x0009002B, 0x0000029D }, + { 0x00070145, 0x00000004 } +}; + +static const struct phyinitdata cpu_trans_tab7[] = { + { 0x000700F0, 0x00000B6D }, + { 0x000100B9, 0x00000001 }, + { 0x000100B1, 0x00000180 }, + { 0x000100BA, 0x00000001 }, + { 0x000100A2, 0x00000000 }, + { 0x000100B5, 0x00000001 }, + { 0x00010E2B, 0x00005A3C }, + { 0x00010E2A, 0x00005A3C }, + { 0x00010E20, 0x00000002 }, + { 0x000110B9, 0x00000001 }, + { 0x000110B1, 0x00000180 }, + { 0x000110BA, 0x00000001 }, + { 0x000110A2, 0x00000000 }, + { 0x000110B5, 0x00000001 }, + { 0x00011E2B, 0x00005A3C }, + { 0x00011E2A, 0x00005A3C }, + { 0x00011E20, 0x00000002 }, + { 0x000120B9, 0x00000001 }, + { 0x000120B1, 0x00000180 }, + { 0x000120BA, 0x00000001 }, + { 0x000120A2, 0x00000000 }, + { 0x000120B5, 0x00000001 }, + { 0x00012E2B, 0x00005A3C }, + { 0x00012E2A, 0x00005A3C }, + { 0x00012E20, 0x00000002 }, + { 0x000130B9, 0x00000001 }, + { 0x000130B1, 0x00000180 }, + { 0x000130BA, 0x00000001 }, + { 0x000130A2, 0x00000000 }, + { 0x000130B5, 0x00000001 }, + { 0x00013E2B, 0x00005A3C }, + { 0x00013E2A, 0x00005A3C }, + { 0x00013E20, 0x00000002 }, + { 0x0007001C, 0x00005A3C }, + { 0x0007001B, 0x00005A3C }, + { 0x00070010, 0x00000002 }, + { 0x0007007E, 0x00000041 }, + { 0x000701EF, 0x00007FFF }, + { 0x000300A6, 0x00000001 }, + { 0x000310A6, 0x00000001 }, + { 0x000701A8, 0x00000000 }, + { 0x00070128, 0x00000000 }, + { 0x00070131, 0x00000000 }, + { 0x00070132, 0x00000000 }, + { 0x00070133, 0x00000000 }, + { 0x00070134, 0x00000000 }, + { 0x00070142, 0x00000000 }, + { 0x00070144, 0x00000000 } +}; + +static const struct phyinitdata cpu_trans_tab3_7500[] = { + { 0x000908E0, 0x00000076 }, + { 0x000908E1, 0x00000160 }, + { 0x000908E2, 0x00000927 }, + { 0x000908E4, 0x00000018 }, + { 0x000908EA, 0x00000005 }, + { 0x000908EB, 0x00000005 }, + { 0x000908EC, 0x0000000C }, + { 0x000908ED, 0x0000005B }, + { 0x000B0004, 0x000003A9 }, + { 0x00070066, 0x00000910 }, + { 0x000700E6, 0x00000910 }, + { 0x00070135, 0x00001410 }, + { 0x00070136, 0x00001410 }, + { 0x00070137, 0x00000424 }, + { 0x00070138, 0x00001928 }, + { 0x00070139, 0x00001418 }, + { 0x0007013A, 0x00001418 }, + { 0x0007013B, 0x0000042C }, + { 0x0007013C, 0x00003530 }, + { 0x0007013D, 0x00001408 }, + { 0x0007013E, 0x00001408 }, + { 0x0007013F, 0x0000041C }, + { 0x00070140, 0x00001120 }, + { 0x0007012C, 0x00000843 }, + { 0x0007012D, 0x00000843 }, + { 0x00070130, 0x00000843 }, + { 0x0007012E, 0x00000827 }, + { 0x0007012F, 0x00000827 }, + { 0x00030803, 0x0000107A }, + { 0x00031803, 0x0000107A }, + { 0x00010803, 0x0000107A }, + { 0x00011803, 0x0000107A }, + { 0x00012803, 0x0000107A }, + { 0x00013803, 0x0000107A }, + { 0x00000503, 0x00000027 }, + { 0x00001503, 0x00000027 }, + { 0x00002503, 0x00000027 }, + { 0x00003503, 0x00000027 }, + { 0x00004503, 0x00000027 }, + { 0x00005503, 0x00000027 }, + { 0x00007503, 0x00000027 }, + { 0x00008503, 0x00000027 }, + { 0x00009503, 0x00000027 }, + { 0x0000A503, 0x00000027 }, + { 0x0000B503, 0x00000027 }, + { 0x0000C503, 0x00000027 }, + { 0x00010C03, 0x00000027 }, + { 0x00011C03, 0x00000027 }, + { 0x00012C03, 0x00000027 }, + { 0x00013C03, 0x00000027 }, + { 0x000908E8, 0x00000015 }, + { 0x000908E9, 0x00000048 }, + { 0x00000063, 0x00000058 }, + { 0x00001063, 0x00000058 }, + { 0x00002063, 0x00000058 }, + { 0x00003063, 0x00000058 }, + { 0x00004063, 0x00000058 }, + { 0x00005063, 0x00000058 }, + { 0x00007063, 0x00000058 }, + { 0x00008063, 0x00000058 }, + { 0x00009063, 0x00000058 }, + { 0x0000A063, 0x00000058 }, + { 0x0000B063, 0x00000058 }, + { 0x0000C063, 0x00000058 }, + { 0x0009080A, 0x00000258 }, + { 0x0009080B, 0x00000058 }, + { 0x00090815, 0x00000258 }, + { 0x00090816, 0x00000058 }, + { 0x000E0063, 0x00000058 }, + { 0x000E0064, 0x00000058 }, + { 0x000E0087, 0x00000058 }, + { 0x000E1063, 0x00000058 }, + { 0x000E1064, 0x00000058 }, + { 0x000E1087, 0x00000058 }, + { 0x000E2063, 0x00000058 }, + { 0x000E2064, 0x00000058 }, + { 0x000E2087, 0x00000058 }, + { 0x000E3063, 0x00000058 }, + { 0x000E3064, 0x00000058 }, + { 0x000E3087, 0x00000058 }, + { 0x000E4063, 0x00000058 }, + { 0x000E4064, 0x00000058 }, + { 0x000E4087, 0x00000058 }, + { 0x000E5063, 0x00000058 }, + { 0x000E5064, 0x00000058 }, + { 0x000E5087, 0x00000058 }, + { 0x000E6063, 0x00000058 }, + { 0x000E6064, 0x00000058 }, + { 0x000E6087, 0x00000058 }, + { 0x000E7063, 0x00000058 }, + { 0x000E7064, 0x00000058 }, + { 0x000E7087, 0x00000058 }, + { 0x00090817, 0x00000061 } +}; + +static const struct phyinitdata cpu_trans_tab3_9600[] = { + { 0x000908E0, 0x00000096 }, + { 0x000908E1, 0x000001C2 }, + { 0x000908E2, 0x00000BB8 }, + { 0x000908E4, 0x0000001E }, + { 0x000908EC, 0x0000000F }, + { 0x000908ED, 0x00000075 }, + { 0x000B0004, 0x000004B0 }, + { 0x00070066, 0x00000B10 }, + { 0x000700E6, 0x00000B10 }, + { 0x00070135, 0x00001C14 }, + { 0x00070136, 0x00001C14 }, + { 0x00070137, 0x00000430 }, + { 0x00070138, 0x00001934 }, + { 0x00070139, 0x00001C1C }, + { 0x0007013A, 0x00001C1C }, + { 0x0007013B, 0x00000438 }, + { 0x0007013C, 0x00003D3C }, + { 0x0007013D, 0x00001C08 }, + { 0x0007013E, 0x00001C08 }, + { 0x0007013F, 0x00000424 }, + { 0x00070140, 0x00001128 }, + { 0x0007012C, 0x00000857 }, + { 0x0007012D, 0x00000857 }, + { 0x00070130, 0x00000857 }, + { 0x0007012E, 0x00000833 }, + { 0x0007012F, 0x00000833 }, + { 0x00030803, 0x0000109A }, + { 0x00031803, 0x0000109A }, + { 0x00010803, 0x0000109A }, + { 0x00011803, 0x0000109A }, + { 0x00012803, 0x0000109A }, + { 0x00013803, 0x0000109A }, + { 0x00000503, 0x0000002F }, + { 0x00001503, 0x0000002F }, + { 0x00002503, 0x0000002F }, + { 0x00003503, 0x0000002F }, + { 0x00004503, 0x0000002F }, + { 0x00005503, 0x0000002F }, + { 0x00007503, 0x0000002F }, + { 0x00008503, 0x0000002F }, + { 0x00009503, 0x0000002F }, + { 0x0000A503, 0x0000002F }, + { 0x0000B503, 0x0000002F }, + { 0x0000C503, 0x0000002F }, + { 0x00010C03, 0x0000002F }, + { 0x00011C03, 0x0000002F }, + { 0x00012C03, 0x0000002F }, + { 0x00013C03, 0x0000002F }, + { 0x000908E8, 0x00000019 }, + { 0x000908E9, 0x00000056 }, + { 0x00000063, 0x00000045 }, + { 0x00001063, 0x00000045 }, + { 0x00002063, 0x00000045 }, + { 0x00003063, 0x00000045 }, + { 0x00004063, 0x00000045 }, + { 0x00005063, 0x00000045 }, + { 0x00007063, 0x00000045 }, + { 0x00008063, 0x00000045 }, + { 0x00009063, 0x00000045 }, + { 0x0000A063, 0x00000045 }, + { 0x0000B063, 0x00000045 }, + { 0x0000C063, 0x00000045 }, + { 0x0009080A, 0x00000245 }, + { 0x0009080B, 0x00000045 }, + { 0x00090815, 0x00000245 }, + { 0x00090816, 0x00000045 }, + { 0x000E0063, 0x00000045 }, + { 0x000E0064, 0x00000045 }, + { 0x000E0087, 0x00000045 }, + { 0x000E1063, 0x00000045 }, + { 0x000E1064, 0x00000045 }, + { 0x000E1087, 0x00000045 }, + { 0x000E2063, 0x00000045 }, + { 0x000E2064, 0x00000045 }, + { 0x000E2087, 0x00000045 }, + { 0x000E3063, 0x00000045 }, + { 0x000E3064, 0x00000045 }, + { 0x000E3087, 0x00000045 }, + { 0x000E4063, 0x00000045 }, + { 0x000E4064, 0x00000045 }, + { 0x000E4087, 0x00000045 }, + { 0x000E5063, 0x00000045 }, + { 0x000E5064, 0x00000045 }, + { 0x000E5087, 0x00000045 }, + { 0x000E6063, 0x00000045 }, + { 0x000E6064, 0x00000045 }, + { 0x000E6087, 0x00000045 }, + { 0x000E7063, 0x00000045 }, + { 0x000E7064, 0x00000045 }, + { 0x000E7087, 0x00000045 }, + { 0x00090817, 0x0000007D } +}; + +static const struct phyinitdata cpu_trans_tab3_6400[] = { + { 0x00060008, 0x00002E9A }, + { 0x000908E0, 0x00000064 }, + { 0x000908E1, 0x0000012C }, + { 0x000908E2, 0x000007D0 }, + { 0x000908E4, 0x00000014 }, + { 0x000908EA, 0x00000004 }, + { 0x000908EB, 0x00000004 }, + { 0x000908EC, 0x0000000A }, + { 0x000908ED, 0x0000004E }, + { 0x000B0004, 0x00000320 }, + { 0x00070066, 0x00000810 }, + { 0x000700E6, 0x00000810 }, + { 0x00070135, 0x0000100C }, + { 0x00070136, 0x0000100C }, + { 0x00070137, 0x0000041C }, + { 0x00070138, 0x00001920 }, + { 0x00070139, 0x00001018 }, + { 0x0007013A, 0x00001018 }, + { 0x0007013B, 0x00000428 }, + { 0x0007013C, 0x00002D2C }, + { 0x0007013D, 0x00001004 }, + { 0x0007013E, 0x00001004 }, + { 0x0007013F, 0x00000414 }, + { 0x00070140, 0x00001118 }, + { 0x0007012C, 0x00000837 }, + { 0x0007012D, 0x00000837 }, + { 0x00070130, 0x00000837 }, + { 0x0007012E, 0x0000081F }, + { 0x0007012F, 0x0000081F }, + { 0x00030803, 0x0000107A }, + { 0x00031803, 0x0000107A }, + { 0x00010803, 0x0000107A }, + { 0x00011803, 0x0000107A }, + { 0x00012803, 0x0000107A }, + { 0x00013803, 0x0000107A }, + { 0x00000503, 0x00000023 }, + { 0x00001503, 0x00000023 }, + { 0x00002503, 0x00000023 }, + { 0x00003503, 0x00000023 }, + { 0x00004503, 0x00000023 }, + { 0x00005503, 0x00000023 }, + { 0x00007503, 0x00000023 }, + { 0x00008503, 0x00000023 }, + { 0x00009503, 0x00000023 }, + { 0x0000A503, 0x00000023 }, + { 0x0000B503, 0x00000023 }, + { 0x0000C503, 0x00000023 }, + { 0x00010C03, 0x00000023 }, + { 0x00011C03, 0x00000023 }, + { 0x00012C03, 0x00000023 }, + { 0x00013C03, 0x00000023 }, + { 0x000908E8, 0x00000015 }, + { 0x000908E9, 0x00000048 }, + { 0x00000063, 0x00000068 }, + { 0x00001063, 0x00000068 }, + { 0x00002063, 0x00000068 }, + { 0x00003063, 0x00000068 }, + { 0x00004063, 0x00000068 }, + { 0x00005063, 0x00000068 }, + { 0x00007063, 0x00000068 }, + { 0x00008063, 0x00000068 }, + { 0x00009063, 0x00000068 }, + { 0x0000A063, 0x00000068 }, + { 0x0000B063, 0x00000068 }, + { 0x0000C063, 0x00000068 }, + { 0x0009080A, 0x00000268 }, + { 0x0009080B, 0x00000068 }, + { 0x00090815, 0x00000268 }, + { 0x00090816, 0x00000068 }, + { 0x000E0063, 0x00000068 }, + { 0x000E0064, 0x00000068 }, + { 0x000E0087, 0x00000068 }, + { 0x000E1063, 0x00000068 }, + { 0x000E1064, 0x00000068 }, + { 0x000E1087, 0x00000068 }, + { 0x000E2063, 0x00000068 }, + { 0x000E2064, 0x00000068 }, + { 0x000E2087, 0x00000068 }, + { 0x000E3063, 0x00000068 }, + { 0x000E3064, 0x00000068 }, + { 0x000E3087, 0x00000068 }, + { 0x000E4063, 0x00000068 }, + { 0x000E4064, 0x00000068 }, + { 0x000E4087, 0x00000068 }, + { 0x000E5063, 0x00000068 }, + { 0x000E5064, 0x00000068 }, + { 0x000E5087, 0x00000068 }, + { 0x000E6063, 0x00000068 }, + { 0x000E6064, 0x00000068 }, + { 0x000E6087, 0x00000068 }, + { 0x000E7063, 0x00000068 }, + { 0x000E7064, 0x00000068 }, + { 0x000E7087, 0x00000068 }, + { 0x00090817, 0x00000053 } +}; + +static const u32 DMAC_TRANS_ICCM[] = { + 0x0000058C, 0x00000090, 0x00000090, 0x00000090, + 0x00000090, 0x00000090, 0x00000090, 0x00000090, + 0x00000090, 0x00000090, 0x00000090, 0x00000090, + 0x00000090, 0x00000090, 0x00000090, 0x00000090, + 0x00000050, 0x00000050, 0x00000050, 0x00000050, + 0x7000264A, 0x7000264A, 0x7000264A, 0x7000264A, + 0x00402069, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC0D1C0F1, 0x00007EE0, 0xC0D1C0F1, 0x00007EE0, + 0x0F80220A, 0x00008000, 0x0F80230A, 0xDEAD1234, + 0x00C01A00, 0x23AA7444, 0x1A000010, 0x744400C0, + 0x00D023AA, 0x00C01A00, 0x1A007444, 0x74440000, + 0x00401A00, 0x1A007444, 0x74440700, 0x06C01A00, + 0x230A7444, 0xABCD0F80, 0x1A00DEAD, 0x206900C0, + 0x78E00040, 0x803C2242, 0x42007CE0, 0x018020A8, + 0x04831101, 0x00D21A01, 0x78E07EE0, 0x803C2242, + 0x42007CE0, 0x010020A8, 0x00521A01, 0x78E07EE0, + 0xB6881CFC, 0xB6481CFC, 0xB6081CFC, 0xB5C81CFC, + 0xB5881CFC, 0xB5481CFC, 0xB5081CFC, 0xB4C81CFC, + 0xB4881CFC, 0xB4481CFC, 0xB4081CFC, 0xB3C81CFC, + 0xB3881CFC, 0x1CFC7FE0, 0x78E0B348, 0x78E07EE0, + 0xDD38748D, 0x78E0F038, 0xDD34748D, 0x78E0F036, + 0xDD30748D, 0x78E0F034, 0xDD2C748D, 0x78E0F032, + 0xDD28748D, 0x78E0F030, 0xDD24748D, 0x78E0F02E, + 0xDD20748D, 0x78E0F02C, 0xDD1C748D, 0x78E0F02A, + 0xDD18748D, 0x78E0F028, 0xDD14748D, 0x78E0F026, + 0xDD10748D, 0x78E0F024, 0xDD0C748D, 0x78E0F022, + 0xDD08748D, 0x78E0F01F, 0x74AD748D, 0x78E0F01C, + 0xF01C748D, 0x301A1434, 0x30191430, 0x3018142C, + 0x30171428, 0x30161424, 0x30151420, 0x3014141C, + 0x30131418, 0x30121414, 0x30111410, 0x3010140C, + 0xC601C702, 0x334D24B0, 0x331F24B0, 0x78E07EE0, + 0x1CFCC4C1, 0x1CFCB1C8, 0x1CFCB188, 0x1CFCB148, + 0xC3E1B108, 0xC1E1C2E1, 0xC4E1C0E1, 0xC0017FE0, + 0x0A11C2F0, 0x42300032, 0x0081292F, 0xF00369E1, + 0x280070ED, 0x274E03D1, 0x2A011800, 0x70F52000, + 0x03D02A00, 0x200921C5, 0x240E2841, 0x0AB24022, + 0x41C10020, 0x23C22A00, 0x000042D3, 0x4508FFFF, + 0xBA307F50, 0x2408232F, 0x20542240, 0x23640A13, + 0x04002940, 0x14C3251A, 0x080F6058, 0x61D900C5, + 0x852409ED, 0x294077A5, 0x251A2411, 0x72221400, + 0x0A6E4A10, 0x41C10020, 0x0A154300, 0x294020E4, + 0x231A0400, 0x60F804C2, 0x0085080D, 0x09EF61D9, + 0x77648524, 0x14002D40, 0x2000BD30, 0x254180C0, + 0xC6D09001, 0xEB884408, 0x00A5090D, 0x07554020, + 0x4181FFEF, 0x00200071, 0x78E04081, 0x4548C2E8, + 0x44084220, 0x41407034, 0x700CF646, 0x900C240E, + 0x80812003, 0x00330B11, 0x700C4668, 0x900D250E, + 0x80CE2003, 0x07CF2B41, 0x07D02A41, 0x0917EE8B, + 0x40200365, 0x42A14181, 0x2007FFC2, 0xF40EA3FE, + 0x4081C6C8, 0x082242A1, 0x43C10020, 0xA3FE2007, + 0x2505F3F8, 0xF3F693BE, 0x200E704C, 0x22038080, + 0xC6C88041, 0x00200031, 0x78E0708C, 0x00C42107, + 0xF040262F, 0x001270AC, 0x242F0026, 0x200E0104, + 0x25038140, 0x70740041, 0x0003000C, 0x8142220E, + 0x00C32503, 0x80852305, 0x00010116, 0x44484368, + 0x43204200, 0x82C0250A, 0x001A704D, 0x22C00004, + 0x25CA1821, 0x2F2F8301, 0x22C00141, 0x22C01063, + 0x70EC11C3, 0x80C0250A, 0x082127C0, 0x00040014, + 0x808125CA, 0x0141282F, 0x006327C0, 0x000327C0, + 0x8287270E, 0x002427CA, 0x45E071E4, 0x8800274C, + 0x0012702C, 0x700C0024, 0x42604140, 0x2742706C, + 0x240A8807, 0x002A7140, 0x274E0001, 0x007C880A, + 0x29000001, 0x29010280, 0x2A0001C1, 0x71A00285, + 0x01C22A01, 0x02852B00, 0x01C32B01, 0x224C72A0, + 0x00629800, 0x20A80009, 0x200005C0, 0x21018000, + 0x22018041, 0x23018082, 0x220200C3, 0x23038302, + 0x000E82C3, 0x22000006, 0x23018302, 0x20C082C3, + 0x70940066, 0x002270AC, 0x000E0001, 0x220E000A, + 0x25038142, 0x242F00C3, 0x000E8100, 0x200E0003, + 0x25038140, 0x7EE00041, 0x41404020, 0x706C4260, + 0x20A8F1CF, 0x20000380, 0x21018000, 0x22018041, + 0x72918082, 0x030622C2, 0x006620C5, 0x704CF1DB, + 0x706C6A09, 0x0002212F, 0x78E0F1E7, 0x81422253, + 0x224E7CE0, 0x00168803, 0x2801000C, 0x290000CC, + 0x28000081, 0x7FE00080, 0x234E7985, 0x28000003, + 0x7FE000C1, 0x78E07802, 0x81422253, 0x224E7CE0, + 0x00168803, 0x2900000C, 0x290100CC, 0x28010081, + 0x7FE00080, 0x234E7885, 0x29010003, 0x7FE000C0, + 0x78E07922, 0x00402069, 0xF1FE78E0, 0x0020001D, + 0x78E0700D, 0x87C82941, 0x002221CE, 0x87C32842, + 0x002220CE, 0x10C82007, 0x8040220A, 0x00210050, + 0x700C4100, 0x2D2F6869, 0x25CA8041, 0x2E2F00C4, + 0x26CA8081, 0x260200C4, 0x23CA8143, 0x23400024, + 0x2AC0007C, 0x20A800C3, 0x210202C0, 0x20CF8081, + 0x21C00F06, 0x222F0085, 0x202F0082, 0x202F9202, + 0x20CE0003, 0x7FE00025, 0x002221CE, 0x0F802020, + 0x05740000, 0xF000260A, 0x0FBF208A, 0x006420CA, + 0x202F7FE0, 0x7FE00003, 0x78E0770C, 0x704C702C, + 0x708C706C, 0x70CC70AC, 0x700D70EC, 0x704D702D, + 0x708D706D, 0x70CD70AD, 0x700E70ED, 0x704E702E, + 0x708E706E, 0x70CE70AE, 0x700F70EE, 0x706F702F, + 0x3000254A, 0x3000264A, 0x800144DB, 0x42DB8000, + 0x04008000, 0xFFCF0AB6, 0x05400E52, 0x0719D830, + 0xF1FEFFCF, 0x0C1EC0F1, 0xC1A1FFCF, 0x7487E805, + 0x7FE0C0D1, 0x40C3C0A8, 0x12218000, 0x206F8840, + 0xA84007C3, 0x208C8803, 0xF20D8FC3, 0xC040C084, + 0x08524020, 0xC18409A0, 0xD8FFD911, 0x02600AC2, + 0x0EF6B911, 0xD8FF0960, 0x20AB700C, 0x7FFF00C4, + 0x78E0F1FF, 0x47CBC2F8, 0x11DA8000, 0x10951746, + 0x23784310, 0x40580000, 0x4130781B, 0x2040704E, + 0x23140057, 0x19002556, 0x252F0001, 0x0FAF1487, + 0x72B52364, 0x2FC1208A, 0x20542244, 0x352E089B, + 0x202620CA, 0x70801600, 0x001B8000, 0x800146CB, + 0x08214D64, 0x40C3009E, 0x04868000, 0xE88A8800, + 0x20300B1F, 0x09E67EB4, 0x961200E0, 0xF00D961E, + 0x00E009DA, 0x134026F4, 0x96067EB4, 0x09CEF005, + 0x960C00E0, 0x09D69618, 0x700C00C0, 0x00A00D56, + 0x2C40712C, 0x70AD20CE, 0x23C02632, 0x10250D3B, + 0x21002D40, 0x04C02016, 0xE02460B8, 0x294060E9, + 0x20050380, 0x90040F80, 0x90000234, 0x02600AE6, + 0xB8C6B8C8, 0x200771A5, 0x40260401, 0x782579D8, + 0x20001900, 0x7146F1E2, 0xC6D8F1A9, 0xC1B4C3F6, + 0x16004110, 0x80007080, 0x4750000C, 0x800046CB, + 0x081B11DA, 0x4728003F, 0xF483B8E1, 0x41E14022, + 0x0F0642E2, 0x4380FFEF, 0x1F00C7D6, 0xC0801001, + 0x10951646, 0x800041C3, 0xDA4E0F12, 0xFFEF099A, + 0x700C708E, 0x704C702C, 0x04600B26, 0x42C3706C, + 0xFFFF0000, 0x722C700C, 0x44404340, 0x04600A8A, + 0xC0804540, 0x09E009F6, 0x2114D94E, 0x43D32552, + 0xF8049007, 0x21051B00, 0x208A7296, 0x24442FC1, + 0x0F8B2056, 0x20CA25AE, 0x45CB2026, 0x4D648001, + 0x07800AE2, 0x00E008D6, 0x150025F4, 0x15002514, + 0x00E008DA, 0x218A9006, 0x40C30FCF, 0xC2EC9007, + 0x712CB020, 0x00051800, 0x0C4A700C, 0x70AD00A0, + 0x23802232, 0x2E40E823, 0x2D4020D6, 0x20162100, + 0x60B80440, 0x60C9E024, 0x03802940, 0x0F802005, + 0x26FC9004, 0x208A9040, 0x09DA0FC7, 0x78460260, + 0x71A5B8C6, 0x04002007, 0x05812800, 0x78258700, + 0x2232A700, 0x0DC72380, 0x71869004, 0xA1140C6D, + 0x70051E00, 0x0004901C, 0x20051B00, 0x1F00C7D6, + 0x708E1001, 0x10931646, 0x24D22114, 0x208A7296, + 0x24442FC1, 0x0F692055, 0x20CA256E, 0x45CB2026, + 0x4D648001, 0x07800A2E, 0x00E00822, 0x150025F4, + 0x150D2514, 0x00E00826, 0x700C9506, 0x00A00BA6, + 0x2232712C, 0xE81C2380, 0x20D52D40, 0x2B4070AD, + 0x41222100, 0x04402016, 0xE02460B8, 0x076008DA, + 0xB8C660C8, 0x200771A5, 0x28000400, 0x87000541, + 0xA7007825, 0x23802232, 0x90040DD7, 0x0C917186, + 0xF144A114, 0x1CFCC2FA, 0x2482B6C8, 0x710C3E07, + 0x0FDF218A, 0x056008D6, 0xC808704C, 0x3643236F, + 0x685270AD, 0x0F802205, 0x00949004, 0xC0449000, + 0x30801300, 0x80BE2053, 0xC004F20B, 0x0F812205, + 0xC0949007, 0x0080206C, 0x00C02045, 0x2205B100, + 0x90080F80, 0x9040002C, 0x2443276F, 0x17004040, + 0x20842081, 0x217800CC, 0x20B80103, 0x41C30084, + 0x00020190, 0x40C37B04, 0x12DA8000, 0x0FB2A860, + 0x740C0220, 0x702CC08E, 0xFFAF0FC6, 0x0007228A, + 0xA08017F9, 0x019141C3, 0x20440000, 0x1C0C0200, + 0x20783344, 0xC5420000, 0xC540C541, 0xFFEF0C8A, + 0x1713C54B, 0x47CB2081, 0x04848000, 0x01002941, + 0x00DF0815, 0x009F0819, 0x007F081D, 0x1F00710C, + 0xF00D1043, 0x1F00D808, 0xF0091203, 0x1F00740C, + 0xF0051103, 0x1F00720C, 0xB9E21083, 0x800041C3, + 0x20CA0F0C, 0x764C0062, 0x0F3EAF01, 0xC08CFFAF, + 0x712CC08C, 0x07E00822, 0x0E1E714C, 0xC08003A0, + 0x050009A6, 0x46CB700E, 0x12208000, 0x30031C17, + 0x0408202F, 0x2440C187, 0x0B6E3AC2, 0x244003E0, + 0x08C535C3, 0x40C30011, 0x11388000, 0x00431800, + 0x30801417, 0x02E00A56, 0x0F2A4210, 0x142B0400, + 0x17133091, 0xB8E22080, 0x1F024022, 0xF42B1003, + 0x0C1A712C, 0xC28E0820, 0xC18B8E40, 0x3093141C, + 0x019645CB, 0x23140002, 0x61792083, 0xA9004362, + 0x0EAE740C, 0x41A10220, 0x0FFA4042, 0xC18E0260, + 0x702C4022, 0x08200BE6, 0x8E40C28E, 0x1401254F, + 0x0E8E740C, 0x43620220, 0x0FDA4042, 0xC18E0260, + 0xC18EF022, 0x706C714C, 0x0FC1248A, 0x00200C8E, + 0x8E2070AC, 0x2514C527, 0xC18B1042, 0xA9006159, + 0x088E4022, 0xC18E03A0, 0x740C8E40, 0x019441C3, + 0x0E4E0002, 0x43A10220, 0x0F9A4042, 0xC18E0260, + 0x10431F02, 0x202F7106, 0x08290408, 0xC8088114, + 0xDD07708D, 0x20057885, 0x00030F80, 0x0DB6F0D8, + 0x702C0960, 0x258DC808, 0x24561E3F, 0xB802180C, + 0x2005700F, 0x900F0F80, 0x0AF6C364, 0x18000720, + 0x14170604, 0x44D33080, 0x01668000, 0x30192440, + 0x1C00700E, 0x1CFF2FC3, 0xC046AFC3, 0x200CC006, + 0x02A2A000, 0xD9690026, 0x20801713, 0x00FF0821, + 0x0F52D840, 0x43000780, 0x41C3740C, 0x00020199, + 0x02200DBE, 0x228A4202, 0xF00E2001, 0x07A00F36, + 0x4300700C, 0x41C3740C, 0x00020198, 0x02200DA2, + 0x704E4202, 0x28152255, 0x2480260A, 0x203E2680, + 0x7676706E, 0x002D014A, 0x2FC3218A, 0x70AD70CD, + 0x708D706C, 0xC18E4002, 0x0803209A, 0x2B406038, + 0x61192141, 0x1F802604, 0xFFF80000, 0x610AB823, + 0x78C6D807, 0x7918712C, 0x0448202F, 0x8FC3208C, + 0x794BF408, 0xD8FF41A1, 0x41D170AD, 0xF02BF429, + 0xF224794B, 0x218C79D0, 0xF79D8042, 0x79707AB0, + 0x00850933, 0x07800EAE, 0x8F014300, 0x0EA64E10, + 0x781007A0, 0x0E9E4400, 0x404007A0, 0x740C4500, + 0x019B41C3, 0x0D0A0004, 0x42620220, 0x442A8F61, + 0x41A163BB, 0xF005D8FF, 0x40228F21, 0x452861B9, + 0x8F014110, 0x79D0661E, 0x8004218C, 0xFFC50768, + 0x262F7970, 0x2179F348, 0x651D0001, 0x006121C5, + 0x3082120B, 0x80412144, 0x78B0757C, 0x00A5081D, + 0x41C3D80A, 0x0001019F, 0x02000CB6, 0x702C7BAE, + 0x00832B44, 0xF01F710F, 0x70347BAE, 0x00832B44, + 0x144124CA, 0x23002600, 0x262F6078, 0x0016F006, + 0x704C0024, 0x0D137910, 0x25022065, 0x42A22001, + 0x4100F005, 0x702CF003, 0xC0874200, 0x04C02014, + 0x6179B040, 0x2048782E, 0x08170000, 0x780F2030, + 0x20811400, 0x00402009, 0x20021C00, 0x14FFF007, + 0x2009A081, 0x1CFF0040, 0x7166A002, 0x2840F15B, + 0x2440230D, 0xDE073713, 0x2640250A, 0x25001302, + 0x24831501, 0x07A00DAE, 0x44004610, 0x07A00DA6, + 0x45004042, 0x4202750C, 0x01A041C3, 0x0C120004, + 0x41700220, 0x22012940, 0x79A5C808, 0x20057825, + 0x00030F80, 0x0B8E00D8, 0x41C20960, 0x183F268D, + 0x3B112440, 0x24112114, 0x20C01100, 0x20487042, + 0x7E100000, 0x07A00D5E, 0x430040C1, 0x07A00D56, + 0x44004042, 0x41C3750C, 0x000301A1, 0x02200BC2, + 0xC8084202, 0x200578A5, 0x00030F80, 0x0B4608D8, + 0x41C10960, 0x20C01101, 0x20487042, 0x7E100000, + 0x07A00D22, 0x430040C1, 0x07A00D1A, 0x44004042, + 0x41C3750C, 0x000301A2, 0x02200B86, 0xC8084202, + 0x200578A5, 0x00030F80, 0x0B0A09D8, 0x41C10960, + 0x07A00CF2, 0x43004042, 0x41C3750C, 0x000201A3, + 0x02200B5E, 0xC8084202, 0x200578A5, 0x00030F80, + 0x0AE200D9, 0x41420960, 0x31D92140, 0xFFEF0561, + 0x20787106, 0x08423000, 0xB912FFEF, 0x07000822, + 0x07400CD2, 0x20801713, 0x003E0815, 0xB88D700C, + 0x70041E00, 0x00148000, 0x05000EBA, 0x30801300, + 0x80BE2053, 0x0CAEF20B, 0xC8080740, 0x2005B802, + 0x90070F81, 0xC004C094, 0xC08CB100, 0x0BEA712C, + 0x704C07A0, 0x702C700C, 0x05200BA2, 0x2480704C, + 0x14043E07, 0xC6DA341B, 0x47CBC2F4, 0x11DA8000, + 0x10921746, 0x46304550, 0x07600C6A, 0x40C24410, + 0x428241A2, 0x09A00B0A, 0x40C3706C, 0x27100000, + 0x05A00ED2, 0x2453702C, 0x702E2040, 0x00902078, + 0x201470CD, 0x70AD2493, 0x23C02332, 0x10250D4B, + 0x21002A40, 0x04002016, 0xE02460B8, 0x160060E9, + 0x80007080, 0x2053000C, 0xF20780BE, 0x0AFA4020, + 0x41020720, 0x2940F00B, 0x20050380, 0x90040F80, + 0x90000234, 0x02200B4E, 0x2053B8C8, 0x71A581BE, + 0x106226C5, 0x0BEEF1DA, 0x40C20740, 0x428241A2, + 0x09A00A8E, 0x2332DB7F, 0x094D23C0, 0x2A402025, + 0x20162100, 0x70220400, 0x60E9E024, 0x70801600, + 0x000C8000, 0x80BE2053, 0x4020F206, 0x07200A9A, + 0xF00C4102, 0x03802940, 0x0F802005, 0x02349004, + 0x0AF29000, 0xB8C80220, 0x7126B8C6, 0x0FC120B9, + 0xF1DB7E05, 0xC6D478CF, 0xC1A1C3FA, 0xD8404210, + 0x210AB89F, 0x250A3140, 0x47682100, 0x00901000, + 0x10E54350, 0x46308097, 0x800041D3, 0xEA081138, + 0x0F2A4042, 0x712C02A0, 0x20031900, 0x70801600, + 0x001B8000, 0x800045CB, 0x08291220, 0x708E007E, + 0x20300B21, 0x0A724042, 0x8D4004C0, 0x750C4410, + 0x018741C3, 0x43420003, 0x02200986, 0x0500240A, + 0x740C8D40, 0x41C34342, 0x0005018A, 0x04C0240A, + 0x260A45E1, 0x096A0540, 0x22530220, 0x46CB2058, + 0x04878000, 0xE8128E00, 0x201F0F09, 0x201E080B, + 0x04200E7A, 0x0F0B710C, 0x080D205F, 0x0E6E205E, + 0x720C0420, 0x10031E00, 0x41C37156, 0x08D80003, + 0x2078C808, 0x21D63097, 0x78250822, 0xB90C8D20, + 0x08B27825, 0xD9400960, 0x710E7076, 0x24A220CA, + 0x0DA57EF0, 0x740C23A4, 0x234A708D, 0xC80811C0, + 0x03012005, 0xB80C8D00, 0x20057825, 0x00030F80, + 0x088200D8, 0x41C10960, 0x1CFF238D, 0x180C2456, + 0x06C00DCE, 0xC18040E2, 0x716C734C, 0xFFAF0F02, + 0x1400718C, 0x26553009, 0xD8071801, 0x10C82E41, + 0x2006B923, 0x244A038B, 0x708D71C0, 0x088020A8, + 0x13002901, 0xB8C06C75, 0x02C62800, 0x209F8D00, + 0x70C20803, 0x70016078, 0x22058840, 0xA8400182, + 0x29014C18, 0x71851000, 0x2800B8C0, 0x8D0002C2, + 0x0803209F, 0x631B70C2, 0x88606338, 0xA8407A65, + 0xF1B07702, 0x43428D40, 0x018C41C3, 0x08620003, + 0x240A0220, 0x70AD04C0, 0xC808DC07, 0x200578A5, + 0x00030F80, 0x0FDEF0D8, 0x702C0920, 0x1DFF248D, + 0x180D2556, 0x06C00D2A, 0x30100915, 0x20310B11, + 0x702C4042, 0x02E00F1E, 0x20431900, 0xC7DA4082, + 0x41C3C2E2, 0x12208000, 0x89208941, 0x02C1229F, + 0x0582219F, 0x621A6038, 0xB8C38A02, 0x002009D6, + 0x068D205F, 0x00802079, 0x0186209F, 0x2534651D, + 0x80001F80, 0xC6C20A7C, 0x0AEEC0F1, 0x716C0100, + 0xDA62E89D, 0x800140C3, 0xBA9F4E77, 0x8A208800, + 0x262F7825, 0x0026F005, 0x12340004, 0x208B0080, + 0xF40D8401, 0x01000A7A, 0x0AA2E889, 0xE8870100, + 0x00801230, 0x04032044, 0xC0D1BB24, 0x40607FE0, + 0x4508C2EA, 0xD8FA4110, 0x46284748, 0x05200B1E, + 0x22C1219F, 0x0020096A, 0x40C34010, 0x12208000, + 0x762C8800, 0x0582209F, 0x244ADA22, 0x70CC0400, + 0x20327022, 0x80010F83, 0x710C4E84, 0xB80278B8, + 0x0340200F, 0x7D0FBB86, 0x0AB2700C, 0x45A10060, + 0x0402202F, 0x0F33E008, 0x202F103E, 0x700C2007, + 0x724CD907, 0x708C706C, 0x0A9270AC, 0x260A0060, + 0x700C0400, 0xDA22762C, 0x244A43C1, 0x45A10380, + 0x00600A7A, 0x0F2F70CC, 0x700C107E, 0x724CD907, + 0x708C706C, 0x0A6670AC, 0x260A0060, 0x700C0400, + 0xDA22762C, 0x244A43C1, 0x45A103C0, 0x00600A4E, + 0x700C70CC, 0x724CD907, 0x708C706C, 0x0A3E70AC, + 0x260A0060, 0x700C0400, 0x724CD907, 0x708C706C, + 0x0A2A70AC, 0x264A0060, 0x700C0A00, 0x006009CE, + 0xC6CA712C, 0x800040C3, 0x7FE00462, 0x00051800, + 0x1E00700C, 0x901C7004, 0x7EE00480, 0xE08E4100, + 0xF707710C, 0x704E0E0B, 0x40410000, 0xE1A87EE0, + 0x7FE07CE0, 0x78E0700C, 0x45CBC2E4, 0x1A108000, + 0xE8049511, 0x10451D28, 0x00200872, 0x460840A1, + 0x800040C3, 0xB0C00462, 0x702C40A1, 0xFF6F0E82, + 0x700CDA20, 0xB513B514, 0xB511B512, 0xC6C440C1, + 0x800041C3, 0x91030462, 0x71109120, 0x7CE0700C, + 0xFFCF07B9, 0x800040C3, 0x90000462, 0xB8227FE0, + 0x800040C3, 0x7FE0046E, 0x78E08800, 0x0DBEC0F1, + 0x700C0060, 0x00600DC6, 0x0C12700C, 0x700C0060, + 0xFFCF0F56, 0x7EE0C0D1, 0xC1A4C3F6, 0x800043C3, + 0x8B280462, 0xE90770CD, 0x71C56949, 0x80812104, + 0x904FF5FC, 0x100E8BA3, 0xB0B30115, 0x01171004, + 0x01161002, 0x1028BD0A, 0x1000010B, 0x10240109, + 0x10120108, 0x10140107, 0x2B400106, 0x101012CB, + 0x90910104, 0x01051020, 0x011E100A, 0x011F1006, + 0x01101008, 0x01131016, 0x0111101A, 0x0114100C, + 0x01121018, 0x226D902E, 0x1C0C0300, 0xB9C33004, + 0xDA7F6A14, 0x24537825, 0x1C0A20C1, 0x256D3004, + 0x1C042300, 0x2D403004, 0x78252100, 0x1C02BA07, + 0x2A403004, 0x235321C0, 0x78442181, 0x29407905, + 0x78252380, 0x31812753, 0x30041C08, 0x21C02840, + 0x93E37844, 0x2E407905, 0x78253380, 0x02012D40, + 0x30041C00, 0x21846C17, 0x2004000C, 0x00000F80, + 0x78257C00, 0x01012C40, 0x04012144, 0x7905BC0C, + 0x01402F40, 0x08012084, 0x79058B4A, 0x01C02E40, + 0x7825780F, 0x12012840, 0x30041C0E, 0x1F802404, + 0x70000000, 0x000C2184, 0x782578A5, 0x1F812304, + 0x08000000, 0x29407825, 0x21441101, 0x79050401, + 0x21402E40, 0x08012084, 0x2F407905, 0x780F21C0, + 0x79FD7825, 0x30041C06, 0x0A6DEA08, 0x7CCF0071, + 0x641C8B09, 0x12140C57, 0x244A6912, 0x20057100, + 0x00100F81, 0xC0804000, 0x03C020A8, 0x050B1002, + 0x0F8D2105, 0x00009000, 0x050C1002, 0xBC107424, + 0x12CC2405, 0x4F98A580, 0x907E2053, 0xB323B9A0, + 0x710CF205, 0x02002006, 0x40C3AB0B, 0x1A308000, + 0x00710A15, 0x00051800, 0x60D88B09, 0x00031B08, + 0xAB09B8C2, 0xC7D67830, 0x4350C2EE, 0x09D74130, + 0x47080030, 0x2FC3208A, 0x800045CB, 0x70CD1A10, + 0x2448222F, 0x21140A1D, 0x20300B19, 0x90BE2753, + 0x700CF219, 0xA5077726, 0xA505A506, 0xF02EA504, + 0x90BE2753, 0x0A69F21F, 0x74E52070, 0xA5C6A5C7, + 0x0D8AA5C5, 0xA5C4FFEF, 0x20B00A49, 0x77264708, + 0x40A1F1E0, 0x0C1A702C, 0xDA20FF6F, 0xA048228C, + 0x00250046, 0x1D22732C, 0x21801404, 0xB5322038, + 0x0A21F00C, 0x40A12070, 0x0BF6702C, 0xDA20FF6F, + 0x20B00A3B, 0x20912142, 0xFFCF0D42, 0xF1C24708, + 0x74E5A5C3, 0xA5C1A5C2, 0xF01DA5C0, 0xA5C6A5C7, + 0xA5C4A5C5, 0x2104F017, 0x00002F80, 0x781DFFFE, + 0x203F090F, 0xB5327704, 0xE708B511, 0xB532F00B, + 0xFFEF0D0A, 0x702CB511, 0xA52068E4, 0xA522A521, + 0x78F0A523, 0x78E0C6CE, 0x4508C2E2, 0x0060096E, + 0x080C208A, 0x752CD809, 0xDA0CB813, 0x0008238A, + 0x45A1708C, 0x00200EB6, 0x700C70CC, 0x724C762C, + 0x244A736C, 0x45A10680, 0x00200EA2, 0x0EF270CC, + 0x700C03C0, 0x724C762C, 0x244A716C, 0x45A10680, + 0x00200E8A, 0x0EDA70CC, 0x700C03C0, 0x724C762C, + 0x244A706C, 0x45A10680, 0x00200E72, 0x700C70CC, + 0x095ED922, 0x704C0060, 0x752C700C, 0x238A744C, + 0x708C000E, 0x0E5645A1, 0x70CC0020, 0xD907D880, + 0x744CB893, 0x708C706C, 0x0E4270AC, 0x70CC0020, + 0xFFCF0CA6, 0x78107704, 0x78E0C6C2, 0x4508C2EA, + 0x70801600, 0x00088000, 0x00B1080D, 0x2280204A, + 0xF00574CD, 0x2240204A, 0x0C9672CD, 0x08AEFFCF, + 0x208A0060, 0x08B2080C, 0x706C0040, 0x4768D907, + 0xBF8F724C, 0x40E1708C, 0x0DF270AC, 0x70CC0020, + 0xD907700C, 0x706C704C, 0x70AC708C, 0x00200DDE, + 0x6F1570CC, 0x704C752C, 0x708CDB80, 0x0DCE45A1, + 0x70CC0020, 0x12002F40, 0x42C1D929, 0x708C706C, + 0x70CC45A1, 0x00200DB6, 0x40224110, 0x42C1D929, + 0x708C706C, 0x0DA645A1, 0x70CC0020, 0x30821204, + 0xD907700C, 0x708C706C, 0x0D9270AC, 0x70CC0020, + 0xD907700C, 0x706C704C, 0x70AC708C, 0x00200D7E, + 0x6F1670CC, 0x704C752C, 0x0004238A, 0x45A1708C, + 0x00200D6A, 0xD80870CC, 0xB898D92A, 0x706C42C1, + 0x45A1708C, 0x00200D56, 0xD84170CC, 0xB812D92A, + 0x706C42C1, 0x45A1708C, 0x00200D42, 0x700C70CC, + 0x744CD907, 0x708C706C, 0x0D3270AC, 0x260A0020, + 0x0FBE0400, 0x700C0000, 0x704CD907, 0x708C706C, + 0x0D1A70AC, 0x70CC0020, 0xD907D880, 0x706C704C, + 0x70AC708C, 0x00200D06, 0x0B6E70CC, 0x7704FFCF, + 0xC6CA7810, 0x40C3C0F1, 0x61A80000, 0x0000080E, + 0xFFCF0AE2, 0x7EE0C0D1, 0x0072081D, 0x1600714C, + 0x901C7101, 0xE9850484, 0x71447210, 0x2179F6B9, + 0xF0030000, 0xD90B700C, 0xFF6F066D, 0x78E0B912, + 0x082DC2E2, 0x43200072, 0x800045CB, 0x8D420462, + 0x28057810, 0x0B110081, 0x9500027F, 0xEA848D4B, + 0xF003714C, 0x0CE6704C, 0xB500FFCF, 0x78E0C6C2, + 0x70ADC0E6, 0xB0A2E2B3, 0xB0A7B0A1, 0x0302B0A6, + 0xB0A0002D, 0x24AD4468, 0x20241203, 0x00F50080, + 0x01090000, 0x01310000, 0x015B0000, 0x01850000, + 0x01A50000, 0x01B30000, 0x00B70000, 0x00BB0000, + 0x02CF0000, 0x00BD0000, 0x01AB0000, 0x01B30000, + 0x02BF0000, 0x01AF0000, 0x01C10000, 0x01C70000, + 0x00A10000, 0x02AB0000, 0x02A70000, 0x02A30000, + 0x029F0000, 0x029B0000, 0x02970000, 0x02930000, + 0x01AD0000, 0x01BB0000, 0x006F0000, 0x01C10000, + 0x01E90000, 0x01E90000, 0x01EB0000, 0x006F0000, + 0x017D0000, 0x01E90000, 0x01E90000, 0x01F10000, + 0x01F30000, 0x00570000, 0x00370000, 0x01F30000, + 0x01F70000, 0x01F70000, 0x01F70000, 0x01F90000, + 0x01F90000, 0x01FD0000, 0x020B0000, 0x02210000, + 0x000F0000, 0x021D0000, 0x021D0000, 0xB0A40000, + 0x0020021F, 0xDB78B0A3, 0x2453B063, 0xF0A600C3, + 0xB063DB38, 0x00832453, 0x0203F0A0, 0xBBC60020, + 0x02F270D4, 0x23530021, 0xBB24018C, 0x0E012384, + 0x2345B084, 0xF0F400C3, 0x2C406BF3, 0x2453008C, + 0x274400C4, 0x24841C0E, 0x24051001, 0x24050384, + 0x7B7B110C, 0x2384B084, 0x27440C01, 0x7B85120C, + 0xF0DEBB80, 0x2C406BF3, 0x2453008C, 0x274400C4, + 0x24841C0E, 0x24051001, 0x24050384, 0x7B7B110C, + 0x2384B084, 0x27440C01, 0x7B85120C, 0x01432345, + 0x6BF3F0C6, 0x008C2C40, 0x00C42453, 0x1C0E2744, + 0x10012484, 0x03842405, 0x110C2405, 0xB0847B7B, + 0x0C012384, 0x120C2744, 0x23457B85, 0xF0B00183, + 0xBB037C7B, 0x1C012484, 0x0C032344, 0xB083BC82, + 0x008C2C40, 0x00C42453, 0x10012484, 0x01032305, + 0xF03C7B85, 0x2453BB23, 0x2384018C, 0xB0840C01, + 0x03032345, 0x0E25F094, 0x02370011, 0x18080020, + 0xBB050104, 0x2384DC68, 0xB0830801, 0xDB28F026, + 0x70D4F060, 0x00010218, 0x018C2353, 0x23847B7D, + 0xB0840001, 0xF07CBB83, 0x01041808, 0x06051806, + 0xDB38F077, 0x2453B063, 0xF00F0083, 0x018C2353, + 0x23847B7D, 0xB0840001, 0x0C032345, 0xDB78F068, + 0x2453B063, 0xBB8600C3, 0xF063B064, 0x2C406BF3, + 0x2453008C, 0x274400C4, 0x24841C0E, 0x24051001, + 0x24050384, 0x7B7B110C, 0x2384B084, 0x27440C01, + 0x7B85120C, 0xF04CBB81, 0xF049DB58, 0xB083B084, + 0x7B7DF047, 0x00012384, 0xF041BB83, 0xF041B084, + 0x2384BB23, 0x23450C01, 0xF0390303, 0x01832453, + 0x7B7DF035, 0x00012384, 0x0C032345, 0x70D4F02F, + 0xDB40F51F, 0xDB60F006, 0xDB20F004, 0xDB50F002, + 0xF026B0A4, 0xF023DB38, 0x00832453, 0xF01FBB86, + 0xBB037C7B, 0x1C012484, 0x02032344, 0xBB807B85, + 0xBB03F015, 0x008C2C40, 0x00C42453, 0x0C032344, + 0x10012484, 0x01032305, 0xF0097B85, 0xF007DB40, + 0xF005DB68, 0x2384BB05, 0xB0640801, 0x091DB063, + 0x0A19041F, 0x22780C70, 0x230B0A03, 0xF4068180, + 0x00432553, 0xF003B065, 0x0939B0A5, 0xDB0D053F, + 0x057F0937, 0x0939DBD0, 0xDB0D05BF, 0x05FF0937, + 0x0939DB08, 0xDB80063F, 0x067F09B3, 0x0010238A, + 0x06BF09D3, 0x0004238A, 0x06FF09D3, 0xF010706C, + 0x0345180E, 0xB067F00C, 0xF00ADBD0, 0xB067BB08, + 0x180EF006, 0xF0040205, 0xDB80B067, 0x0909BB8C, + 0xB06704DE, 0x07550A13, 0x708F0E21, 0x00181000, + 0x0B21766C, 0x2242008F, 0x0B190843, 0x0A150094, + 0xE2A90AF0, 0xF414704C, 0x180C744C, 0xF0100105, + 0x00832941, 0x7A66724C, 0x01032144, 0x21447074, + 0x0B0D0303, 0x22CF0330, 0xB0460021, 0x049E090B, + 0x00C22245, 0x262FB046, 0x000AF046, 0x18040003, + 0x090B0045, 0xBA83033E, 0x090DB046, 0x0D09019F, + 0xC4C6005F, 0x00451800, 0xB067C4C6, 0xBB0A756C, + 0x2B41F1BF, 0xBB2B01CC, 0x1C012484, 0x0E012384, + 0x110E2405, 0x01C32345, 0xF17AB0C4, 0xDB58B084, + 0xB067F176, 0xBB08DB11, 0x238AF1AB, 0xB0670008, + 0xBB09DB09, 0x78E0F1A5, 0x0C1AC2E2, 0x45280020, + 0x05600886, 0x0EB2760C, 0x7704FF8F, 0x00200C8E, + 0x0C6E7810, 0x70B50000, 0xFFC20B3C, 0x78E0C6C2, + 0x0BF2C2E2, 0x45280020, 0x0560085E, 0x0C52760C, + 0x70B50000, 0xFFC20B20, 0x78E0C6C2, 0x800040C3, + 0x7FE0046F, 0x00431800, 0x46CBC2F4, 0x04628000, + 0x8E4D4050, 0x2180260A, 0x2140240A, 0x2100250A, + 0x43304270, 0x01B1092D, 0xEA144110, 0x8E008EA2, + 0x80BE2053, 0x7DBBF402, 0x0487212F, 0x0A8640A2, + 0x42820020, 0x23402002, 0xFFEF0B0A, 0xF0C94122, + 0x081D8E0A, 0x40620071, 0xFFAF0DB6, 0x20788E68, + 0xBB240000, 0xB870B806, 0xAE086078, 0x47CB7054, + 0x1A108000, 0x223E090F, 0x206120C0, 0xB8819710, + 0x090DB710, 0x9710235E, 0xB710B880, 0x0E699620, + 0x21532030, 0x08190080, 0x700C0131, 0xA706A707, + 0xA704A705, 0x0D866904, 0xB600FFAF, 0x42628E23, + 0x43428E04, 0x41227825, 0x00002079, 0x0540240A, + 0x40E1AE03, 0x0500250A, 0x0ABA70CC, 0x70ADFFEF, + 0xFFAF0D3E, 0x08C54062, 0x4FA80030, 0x41224020, + 0x43424262, 0x0540240A, 0x0500250A, 0xFFEF0A96, + 0xF05871CC, 0x01110829, 0x225F0911, 0x8E438E04, + 0x00010A09, 0xE80C9712, 0xA704700C, 0xA706A705, + 0x6904A707, 0xFFAF0D16, 0x9620B600, 0x09CBB9C2, + 0x40620130, 0x003109C1, 0x8E23700C, 0x8E044262, + 0x78254342, 0x20794122, 0x240A0000, 0xAE030540, + 0x250A40E1, 0x0A3E0500, 0x70CCFFEF, 0x96008E22, + 0x090F7404, 0xB600227E, 0xB8819712, 0x4062B712, + 0xFFAF0CAE, 0x204D2002, 0x4F28E813, 0x42624122, + 0x240A4342, 0x250A0540, 0x0A0A0500, 0x71CCFFEF, + 0x74049600, 0xFFAF0CDE, 0x8E02B600, 0x40A17D02, + 0xFFEF09C2, 0xF0234122, 0xA1A2A1A3, 0xA1A0A1A1, + 0x96008EA2, 0xB600E008, 0x23402017, 0x0072082B, + 0x15841F22, 0x1F2460B8, 0x77041085, 0xFFAF0C6E, + 0x2F057F10, 0x96001341, 0xFFAF0E92, 0xB600704C, + 0x22D1214F, 0x1F24F003, 0x8E0410C5, 0x0E32AE03, + 0x40220620, 0x0C2AC6D4, 0x4308FF8F, 0x41224F28, + 0x43424262, 0x0540240A, 0x0500250A, 0xFFEF0986, + 0x960070CC, 0x0B357404, 0xB6001030, 0xFF8F0C1E, + 0x40E18EA2, 0x42624122, 0x240A4342, 0x250A0540, + 0x09620500, 0x71CCFFEF, 0x20029600, 0x74042341, + 0x8E02B600, 0xF10A4910, 0x20028E02, 0x0D13200D, + 0x0BEA1052, 0x40A1FF8F, 0xFFEF090A, 0x09934122, + 0x9712A2DE, 0xB712B880, 0x78E0F1C3, 0xC1ABC3E6, + 0x45284748, 0xC0804608, 0x0A66702C, 0xDA2AFF2F, + 0x41838E00, 0x8E01B103, 0x8E02B104, 0x8E03B10B, + 0x103E0F0B, 0x1C0AB10C, 0x0F0B3344, 0x1C1A105E, + 0x0C1A3344, 0xC080FFAF, 0x78E0C7C6, 0x800040C3, + 0x7FE00466, 0x00031800, 0x800041C3, 0xB1000462, + 0xB1037FE0, 0x800040C3, 0x7FE00466, 0x00431800, + 0x800043C3, 0xB30419E4, 0xB303D858, 0x01802153, + 0x2253B30C, 0xB30D0040, 0x800044CB, 0xB3050462, + 0xB308781D, 0x783DB300, 0x0140206C, 0xB8839440, + 0xB30BE208, 0x03B54060, 0xB440FFAF, 0xC1A4C3E8, + 0x800046CB, 0x47480462, 0x45289640, 0x00812253, + 0x700C4010, 0xC042C043, 0x091FC041, 0xC0400131, + 0x800041C3, 0xA1001A20, 0xA102A101, 0x6A04A103, + 0xFFAF0AFA, 0x8E02B600, 0x781B70F5, 0x080F780F, + 0x20CA2031, 0x0D090062, 0x45081005, 0x100E2D05, + 0x781078C9, 0x26C27510, 0x78D01061, 0x8004208C, + 0xD908F792, 0xB80AD81F, 0xB2074283, 0x08002059, + 0x0892B203, 0xC0800920, 0x107C2680, 0x208C78D0, + 0xF7328FC3, 0xF388262F, 0x2E40F212, 0x20041300, + 0x00000F80, 0xB8887000, 0xB88BB889, 0x30041C06, + 0x20046E17, 0x00000F80, 0xF0057C00, 0x1C06700C, + 0x1C0E3005, 0xC0803004, 0x0920084A, 0xC7C8D908, + 0x800041C3, 0x19020462, 0x7FE00043, 0x78E0A90C, + 0x70041E00, 0x049C901C, 0x78E07EE0, 0xC1A8C3E6, + 0x47284648, 0x24404508, 0x702C3080, 0xFF2F08E2, + 0x6E13DA1E, 0x2044BE0E, 0x42830400, 0xB203B20B, + 0x1F802605, 0x2C580000, 0x2753B200, 0x68371180, + 0xB20C7825, 0x11802553, 0x78256837, 0x78FDB204, + 0x0140206C, 0x2605B883, 0xB8071001, 0xC0807905, + 0x0FD2B228, 0xD91008E0, 0x78E0C7C6, 0x1E00710C, + 0x901C7004, 0x7EE00480, 0xB9025020, 0x0F812105, + 0x0488901C, 0xB1007FE0, 0xB9025020, 0x0F812105, + 0x048C901C, 0xB1007FE0, 0x4708C2E8, 0x20846A15, + 0x204F0001, 0x204F06D0, 0x2148068E, 0x77040040, + 0x68A17810, 0x400270F5, 0x038120CA, 0x704CD907, + 0x708C706C, 0x0B7670AC, 0x70CCFFEF, 0x1D3F258C, + 0x78E0C6C8, 0x256FC2E8, 0x46081743, 0x10D01500, + 0x20402040, 0x7314780F, 0x002500F0, 0x0D1E70ED, + 0x42C10880, 0x00842280, 0xE8188A60, 0x10C21500, + 0x780F6A01, 0x00F408D5, 0x2A446B01, 0xB8220081, + 0x0FC02049, 0x10002615, 0x0A999081, 0x242F00B2, + 0x90200045, 0xF0497180, 0x20B2082D, 0x20812844, + 0x170B1682, 0x240A6B01, 0x20A87000, 0x26150300, + 0x908110C0, 0x12C40C41, 0x0B3D9000, 0x77641004, + 0xF01B700C, 0x700CE3BF, 0x1682F717, 0xDC40170B, + 0x240A7C62, 0x20A87300, 0x261503C0, 0x94A110CC, + 0x12C40D15, 0x0B119480, 0xE3BF1324, 0x20CA7164, + 0xF0030FE1, 0x60384060, 0x7B0FAA00, 0x17021682, + 0xF749E3C0, 0x96017E75, 0x0084080B, 0x0A3D9600, + 0x242F0005, 0xD8C80045, 0x022041C3, 0xF0130003, + 0x792D7933, 0x1E824C31, 0x9000105C, 0x10240C0F, + 0x0C0B7A30, 0x0A151084, 0xD8C80005, 0x021F41C3, + 0x0F0E0003, 0xDF070140, 0xC6C840E1, 0x0DA2C2F2, + 0x451001A0, 0x704E4410, 0x800047CB, 0x0AA91222, + 0xD82520B5, 0x8820B89F, 0x7825881B, 0x048E0895, + 0x1A0D8FC0, 0x7DCF3482, 0x08898F01, 0x40C30344, + 0x12D98000, 0x08798800, 0x40A2036E, 0x085641A1, + 0x1A0B0760, 0x43103358, 0x0865700E, 0x0B5D2295, + 0x210A242E, 0x1A0C2500, 0x40C33418, 0x28F00000, + 0x221A7A1B, 0x211A2001, 0xB8222082, 0x623A78AA, + 0x40026219, 0x0184209A, 0x70C36038, 0x1A3C8000, + 0xFFEF0E76, 0x34581A0D, 0x3082120D, 0x00002078, + 0x3603120B, 0x021E41C3, 0x0B6E0003, 0x120CFF2F, + 0x71363604, 0xF5DB712E, 0xF1D17106, 0xF1BD71C5, + 0xF1AF7146, 0x78E0C6D2, 0x1CFCC2FA, 0xC1A8B6C8, + 0xD8254318, 0x1600B89F, 0x80007091, 0x44D31222, + 0x00489004, 0x24428820, 0x881B2210, 0x20787825, + 0x204000C0, 0x16000055, 0x80007080, 0x08E11223, + 0x40C30444, 0x12D98000, 0x08D18800, 0x212F046E, + 0x0F920447, 0x40630720, 0x23182940, 0x706E4118, + 0x34EE09B3, 0x22002B40, 0x200570AD, 0xC8080601, + 0x69127905, 0x20054230, 0x90040F96, 0x215A0320, + 0xC7802A00, 0x800041C3, 0x7FB4C004, 0x04C02015, + 0x603278B4, 0x11A06119, 0x20340101, 0x80000F80, + 0xB740BEC4, 0x1C08B722, 0x25053004, 0x68D21480, + 0x15002605, 0x00E009D6, 0xB7059000, 0x140E2605, + 0x00E009CA, 0xB7079600, 0x160071A5, 0x0DB32100, + 0x1C129564, 0x40A23004, 0x062009E6, 0x706CC180, + 0x2305C485, 0x14020480, 0xB8021501, 0x20057164, + 0xB2200502, 0x04012005, 0x0BEB9401, 0xB1008564, + 0x70801600, 0x00EE8000, 0x141CE885, 0x1E003100, + 0x71662004, 0xA2540B4D, 0xF18F7126, 0x1404C0A8, + 0xC6DA341B, 0xC1A3C3F8, 0xD8254018, 0x1600B89F, + 0x8000708D, 0x16001222, 0x80007092, 0x88200187, + 0x881B7056, 0x242122CA, 0x20787825, 0x204000C0, + 0x16000053, 0x80007080, 0x08DB1223, 0x40C30344, + 0x12D98000, 0x08CB8800, 0x79AF036E, 0x07200E76, + 0x2D404003, 0x47101316, 0x0FB1700E, 0x2840242E, + 0x702E2200, 0x05812005, 0x2105C808, 0x25050015, + 0xC1812440, 0x260568D2, 0x90041F8F, 0x0B960048, + 0x97000260, 0x1F8E2605, 0x00409004, 0x0B869600, + 0xC1820260, 0x30821409, 0x30811405, 0x0483223D, + 0x0480213D, 0xC022786B, 0xE810F410, 0x08022254, + 0x2154C321, 0x77040801, 0x1C097764, 0xC0623082, + 0x1C05C361, 0xF0033042, 0x792FC321, 0x0007252F, + 0x262FC140, 0x272F0087, 0x740C00C7, 0x41C34222, + 0x0007025A, 0x0C4A43A1, 0x240A0160, 0x0CF60400, + 0xC0810160, 0x0CEEB700, 0xC0820160, 0x2140B600, + 0x086F2040, 0x712E84E4, 0x08537106, 0x71A5A254, + 0xC7D8F191, 0x88606038, 0xA8607B44, 0x0083104B, + 0x184B7B44, 0x109600C2, 0x7B440083, 0x00C21896, + 0x008310E1, 0x7FE07A64, 0x008218E1, 0x2482C3F4, + 0x250A3306, 0x230A2180, 0x40702100, 0x45284650, + 0x248A4410, 0x24407001, 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0x1902D8FF, 0xB1000005, + 0x2015F007, 0x180222C0, 0x18000005, 0x71650204, + 0xF1CA71C5, 0xA3C0200C, 0x7001248A, 0x02A220E8, + 0x25001002, 0x10141F02, 0x25001002, 0x10141F02, + 0xC7CC700C, 0x1CFCC2FA, 0xC1A8B6C8, 0x31401C04, + 0x41C34520, 0x28F00000, 0x42504078, 0x0042201F, + 0xC0177B3B, 0x009B2D41, 0x1C1C786C, 0x44C33100, + 0x1A3C8000, 0x00962440, 0x31C01C00, 0x31801C14, + 0x00972000, 0x30191460, 0x25802700, 0xC000C042, + 0xD8406849, 0x00952801, 0x800040C3, 0x10B71222, + 0x43500081, 0x00861000, 0x8821C143, 0x222FC144, + 0xC0040187, 0x01DC7210, 0xC003000D, 0x80802011, + 0x221FF2E6, 0x00000F90, 0x225F0A3C, 0xC0020281, + 0x029E265E, 0x2700700D, 0x20002414, 0xC0012010, + 0x21112400, 0xC0467834, 0x9240204C, 0x002D01A0, + 0x3787272F, 0x702D700C, 0x702C706C, 0x436870CD, + 0xF005262F, 0x800043C3, 0x0044C444, 0x44EB0024, + 0x100E249F, 0x092B641C, 0x646B1030, 0x68A9EB95, + 0x12C7242F, 0x4B977BAF, 0x7BCF7C2F, 0x7B7B7B82, + 0x03E50B17, 0x706C702D, 0x46A94161, 0xEB05F006, + 0x4300712D, 0x4361F002, 0xF1DB7104, 0x1030091F, + 0x7ECF782F, 0x12C7242F, 0x7E02DD7F, 0x7EDB7D82, + 0x20CA75D1, 0x21CA030D, 0x70A202CD, 0x8002208C, + 0x41A2F784, 0x0FC12187, 0x7D2F4709, 0x1184279A, + 0x7D0AC000, 0x308021F4, 0x7782702D, 0x03CC2400, + 0x1C8060B8, 0xC005101C, 0x248AE824, 0x27007001, + 0x80001F8B, 0x20A81B40, 0x40E30740, 0x14CC2901, + 0x000E209F, 0x7C8F643C, 0x609845A8, 0xB8816068, + 0x700C7314, 0x40A0F203, 0x271570AD, 0x7125124C, + 0x110E2400, 0xB60074C2, 0x1B00B4A0, 0xF05016C4, + 0x7001248A, 0x0400270A, 0x1440230A, 0x020120A8, + 0x290145EB, 0x259F14C0, 0x6038100E, 0x708D7F0F, + 0x606E65F8, 0xEE2540A0, 0x1180275F, 0x40C3651D, + 0xC1448000, 0x10B00E11, 0x0E1760BC, 0x444A1071, + 0xF0176510, 0x94816510, 0x160C2402, 0x60BEF011, + 0x96816515, 0x160C2402, 0x7F104CB0, 0x22029602, + 0x7ED0200E, 0x20CA76F1, 0x24CA034E, 0x7D90148D, + 0x10040D23, 0xED07C507, 0x25F4C506, 0x60B8120D, + 0x7E1064BC, 0x7DC27D90, 0x0D0B71A5, 0x708D1155, + 0x1B0440A0, 0x71251014, 0x03141F04, 0x21842180, + 0x21842080, 0x26407105, 0xF130305E, 0xF11171C4, + 0x1404C0A8, 0xC6DA341B, 0x4130C2EA, 0xFFEF0AE6, + 0x0D154508, 0x401011F5, 0x203278AD, 0x80000F89, + 0xF00A0D80, 0x41C3700C, 0x00010087, 0xFE6F0CAA, + 0x702D42A1, 0x900446CB, 0x6D0A02D4, 0x01750821, + 0x294096E0, 0x27041289, 0x00001F80, 0x2005C3FF, + 0x1E000240, 0x90077004, 0xC6CAFED4, 0x800040C3, + 0x10B71222, 0x21540086, 0x88612F08, 0x240B2140, + 0x45CB8880, 0x00009004, 0x36071208, 0x83040BDF, + 0x032E0E59, 0x13042C40, 0x7240244A, 0x20A870AC, + 0x25050980, 0x20050100, 0x220501C2, 0xB90202C1, + 0x912079A5, 0x20300817, 0x2205B927, 0xBA020202, + 0x92407AA5, 0x0182226D, 0xB9E06159, 0x21C74121, + 0xB90A03E2, 0x1F8F2704, 0xC3FFFFFF, 0x2556B802, + 0x7F250805, 0xB0E078C5, 0xF1D27185, 0x226FC2E2, + 0x44CB0443, 0x04988000, 0x8A6084A7, 0x7D6C8406, + 0x0001231C, 0x810212FE, 0x231A61B9, 0x219A000D, + 0x40A1041F, 0x141F259A, 0x041F209C, 0x61197BBD, + 0x20798C10, 0x2447004C, 0x799817C0, 0x00002B01, + 0x7905706C, 0xFE6F0892, 0x13002D00, 0x78E0C6C2, + 0xC1A1C3E6, 0x000F2315, 0x260A4008, 0x97013080, + 0x703070AD, 0x002E0120, 0x97204328, 0x21CC7171, + 0x01148005, 0x2B400026, 0x258A1407, 0x27050FC3, + 0x772D0207, 0x334E2616, 0x9E609E01, 0x00E2082B, + 0x0240260A, 0x7A7079AF, 0x40E07B10, 0x00E00C6A, + 0x30C42440, 0x210C4600, 0x14039000, 0x26CA3080, + 0x25090245, 0x9E030005, 0x082D9E62, 0x210A00E2, + 0x79AF1180, 0x7B107A70, 0x0C3E40E0, 0x244000E0, + 0x410830C4, 0x8000260C, 0x30801403, 0x118521CA, + 0x00052509, 0xE5C071A5, 0xFFC5079C, 0x45CB9720, + 0xFFFF0000, 0x02C5091B, 0x0B179701, 0x20021025, + 0x7A1002C0, 0x10402302, 0x20097810, 0xD840008D, + 0x3703121D, 0x02002002, 0x201A780C, 0x204000C1, + 0x780A1040, 0x2509786C, 0x210C0203, 0x20CA9000, + 0x70300245, 0x000521CA, 0x0008208A, 0x02C22002, + 0x7A4CCC1C, 0x71507A0C, 0x004522CA, 0x1FC1204E, + 0x2309792F, 0x16000043, 0x80007081, 0xB9E0000E, + 0xF409705C, 0x10412340, 0x782C792C, 0x20CA7210, + 0x41C30085, 0xFFFF00FF, 0x657D7030, 0x000521CA, + 0x7D25B908, 0xC7C640A1, 0x1200C0E6, 0x70AD3087, + 0x47CB706C, 0x113A8000, 0x0B69710D, 0x2B4001E5, + 0x235A0386, 0x702D0A0E, 0x704C706D, 0xB0A167D8, + 0x0A47B0A0, 0x26050255, 0x21050241, 0x90040F81, + 0x91200200, 0x0A157C2F, 0x28000321, 0x9020130C, + 0x0081210F, 0xF00DB020, 0x71249021, 0xB902B021, + 0x0F0F2184, 0x61F961D9, 0x02C41902, 0x7425B180, + 0x71447165, 0x9020F1DF, 0xB9897164, 0xF1CFB020, + 0x78E0C4C6, 0xC1A1C3E6, 0x16004608, 0x80007100, + 0x4528000A, 0x0980206D, 0x0817E808, 0x080D0050, + 0x1A0000D1, 0xF00700C3, 0x00831A00, 0x1A00F003, + 0x24400043, 0x244030C0, 0x0E123081, 0x42C101E0, + 0xC7C6E802, 0x30821402, 0x308C1403, 0x7B3D6459, + 0x10C12615, 0x91E0AD60, 0x61F99121, 0xB521793D, + 0x7C3D6399, 0x13012615, 0x91E0AD84, 0x61F99121, + 0xB523793D, 0x793D6359, 0xAD287E35, 0x96219640, + 0x793D6159, 0xC7C6B525, 0xC1A2C3E4, 0x45084628, + 0x30011C04, 0xFEAF0E3A, 0x30011C00, 0xD907D841, + 0xDA08B813, 0x708C706C, 0x0FA270AC, 0x70CCFEEF, + 0x742C700C, 0xFF2F0A8A, 0xC080714C, 0x09E241A1, + 0x734CFF2F, 0x700C4508, 0x0A76742C, 0x714CFF2F, + 0xD907706C, 0x744C4060, 0x708CB892, 0x0F6E70AC, + 0x70CCFEEF, 0xD907D880, 0xDA08B893, 0x708C706C, + 0x0F5A70AC, 0x70CCFEEF, 0xFE8F0DBE, 0xB600B802, + 0xC7C440A1, 0x2044781B, 0xD8E40181, 0x7FE07839, + 0x78E0B8C1, 0x01422053, 0x206DA941, 0x20AD0182, + 0x605801C1, 0xA9007FE0, 0x43E3C1A1, 0xFFEF0FEA, + 0xC020C180, 0x30811401, 0x6038B806, 0x74877B20, + 0x1CFCC2FA, 0x2482B6C8, 0x1CC83B06, 0x40383080, + 0x30001CC0, 0x1CC4700C, 0x1C403000, 0x1CFC3018, + 0x1CF83000, 0x1CF43000, 0x14C83000, 0x1CA03000, + 0x20843000, 0x1CA00004, 0x14A03000, 0x1C8C3010, + 0x148C30C0, 0x1CE43001, 0x28413180, 0x1CE02200, + 0x1CAC3140, 0x09AA3100, 0x401000E0, 0x70911600, + 0x000D8000, 0x30001CEC, 0x02A00FBA, 0x46084003, + 0x702CC808, 0x2005B802, 0x90380F80, 0x90E00008, + 0x3F802400, 0x01040000, 0xFE2F0B46, 0x148CDA50, + 0xB8A03000, 0x30001C98, 0x22002144, 0x000D2078, + 0x30001498, 0x00910811, 0xFF8F0E3A, 0x30001CC4, + 0xF004710C, 0x00C00986, 0x30001CBC, 0x40037DC4, + 0x02A00F62, 0x33401CD4, 0x30011498, 0x00B1092D, + 0x24012144, 0x71001600, 0x00148000, 0x04110819, + 0x07800F86, 0x0832E888, 0x701407C0, 0x1CA4710C, + 0xF40B3000, 0xF007700C, 0x00002052, 0x00012178, + 0x1CA47824, 0x148C3000, 0xBFC13000, 0x00002078, + 0x07A00F56, 0x30001C9C, 0x300214C0, 0x024541C3, + 0x148C0005, 0x240A3003, 0x1CD80600, 0x740C3000, + 0x300614AC, 0x00A00A7A, 0x0400250A, 0x300014D4, + 0x00102079, 0x30402042, 0x081B7D0F, 0x1CB001F5, + 0x14B03000, 0xB8C63000, 0x0050080B, 0x300014A0, + 0x1600E88A, 0x80007080, 0xB8E00107, 0x1C94700C, + 0xF2073000, 0x05800B96, 0x1C94710C, 0x27793000, + 0xDA7D1000, 0x30001CB4, 0x148C708E, 0x41DB3000, + 0xC1448000, 0x0080207C, 0x30001CB8, 0x20402040, + 0x30001CCC, 0x3000149C, 0x0F80201F, 0x51E00000, + 0x30001CF0, 0x800070C3, 0x1CD01B3C, 0x14B03000, + 0xB8C63000, 0x00012A01, 0x11C0257C, 0x1CE87824, + 0x2A013000, 0xB8C00340, 0x800045CB, 0x1CDC1221, + 0x14983000, 0x20783000, 0x1CA80080, 0x72963000, + 0x00260702, 0xB89FD825, 0x881B8820, 0x710C7905, + 0x05002800, 0x200FB802, 0x7E2B050E, 0x002106D4, + 0x0D0A730C, 0x1D000120, 0x148C1502, 0x24553001, + 0x14E03F42, 0x24553004, 0x14A43FC3, 0x202F3005, + 0x43180507, 0x01600CB2, 0x300614D4, 0x300014A0, + 0x00002079, 0x100115BB, 0x30001C90, 0x14904063, + 0x0A623002, 0x14900320, 0x14D83003, 0x7FCF3000, + 0x3003148C, 0x3F452455, 0x30061490, 0x14CCC182, + 0x42033007, 0x093E44E1, 0x43F10060, 0x300014AC, + 0x14A870AE, 0xC3823001, 0x35441C0A, 0x300214E8, + 0x02200C8E, 0x30431C0C, 0x300014A4, 0xC808E839, + 0x15B8700D, 0x15021086, 0x8DE11089, 0x78EF68D2, + 0x1004095F, 0x002E0E57, 0x038C2840, 0x7240244A, + 0x70EC7CC5, 0x20A8706C, 0x205F0600, 0x24000501, + 0x00003F82, 0x623A015C, 0x02812F40, 0x22147985, + 0x210501CB, 0x90040F81, 0x91200320, 0x633B71E4, + 0x10441B00, 0x3F812400, 0x01540000, 0x78707914, + 0x02402845, 0x02041A12, 0x71E5B100, 0x14B0F1D1, + 0x08173000, 0x14A801D5, 0x14DC3001, 0x20053000, + 0xF207807E, 0x1498F00D, 0x08173000, 0x16000090, + 0x80007080, 0x2044000B, 0x2D410815, 0x0C9B2155, + 0x0D972011, 0x70ED2030, 0x310B1412, 0x3108140E, + 0x12C02002, 0x31071410, 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0x06587191, 0x0B41FFCD, + 0x2400104E, 0x00003F80, 0x20F40154, 0x16000042, + 0x80007080, 0x6058011B, 0xD81170F1, 0x1600F7CA, + 0x80007080, 0x4A10011C, 0xD89170F1, 0x006B20CA, + 0x2105B90E, 0x90040F81, 0xB1003ED4, 0xF1DD7164, + 0x08C1C022, 0x140E0030, 0x8DE13113, 0x8D0279EF, + 0x006408E3, 0x40C34030, 0x12D98000, 0x08A18800, + 0x70CD042E, 0x1291275E, 0x0447202F, 0x01A00DE2, + 0x205F4210, 0x14CC2502, 0xC182300C, 0x248A7C09, + 0x623A7001, 0x923A7AD4, 0x41C3643C, 0x28F00000, + 0x2043241A, 0x201FB922, 0x14F02041, 0x627A3002, + 0x41C1623A, 0x0184219A, 0x2300623B, 0x80000F81, + 0x43681B3C, 0x708DB180, 0x078020A8, 0x300114D4, + 0x43627A8F, 0x62197A39, 0x218C704C, 0xF74C8002, + 0x215A4242, 0x229F0181, 0x623A000E, 0x06432234, + 0x92417223, 0x13012315, 0x71C37185, 0x1A3C8000, + 0xB141B160, 0x0E7571C5, 0x712692B4, 0xF1A871E5, + 0x3FC02455, 0x916A4183, 0x41629149, 0x240AC041, + 0x149C0540, 0x24003000, 0x00003F85, 0x14CC015C, + 0xC0403007, 0x300014AC, 0x00062078, 0xFFAF094A, + 0x149C4063, 0x40633001, 0x30021490, 0x300314C4, + 0x01A00A06, 0x300414E4, 0x300114B8, 0x300014B4, + 0xF234790B, 0x7EEF8DE1, 0x08618D02, 0x40C30384, + 0x12D98000, 0x08518800, 0x41C103AE, 0x06200CB6, + 0x300014C8, 0x2E404408, 0xC1071300, 0x7280244A, + 0xC8087905, 0x700C7905, 0x20A86952, 0x0C270580, + 0x265F100E, 0x24001503, 0x00003F81, 0x61790104, + 0x000321F4, 0x02812840, 0xB9927945, 0xB99FB99C, + 0x7104B160, 0xF1D171E5, 0x0A9EC082, 0x702C0020, + 0x300014D0, 0x20967186, 0x01070794, 0x1CD0FFEF, + 0x14943000, 0x70143000, 0x05C208A0, 0x3B062480, + 0x341B1404, 0x78E0C6DA, 0x4110C2EA, 0x70801600, + 0x00088000, 0x08114548, 0x462800B1, 0x2280204A, + 0xF00574ED, 0x2240204A, 0x088272ED, 0x208AFEEF, + 0x0EC1080C, 0x208A1275, 0x08B90144, 0x0923038E, + 0x706C2030, 0xFECF0872, 0xD907706C, 0x724C4060, + 0x708CB88F, 0x0DB670AC, 0x70CCFEAF, 0xD907F00C, + 0xDA184060, 0x708CB88F, 0x0DA270AC, 0x70CCFEAF, + 0xFECF0846, 0xD907700C, 0x706C704C, 0x45A1708C, + 0xFEAF0D8A, 0x704C70CC, 0x4648752C, 0xBE94DB80, + 0x40C1708C, 0x0D7645A1, 0x70CCFEAF, 0xD9296E13, + 0x706C42E1, 0x45A1708C, 0xFEAF0D62, 0x01C0264A, + 0x30821204, 0xD907700C, 0x708C706C, 0x0D4E45A1, + 0x70CCFEAF, 0xD907700C, 0x706C704C, 0x45A1708C, + 0xFEAF0D3A, 0x78DB70CC, 0x704C752C, 0x0004238A, + 0x45A1708C, 0xFEAF0D26, 0xD84170CC, 0xF03CD92A, + 0x20300921, 0x0FC2706C, 0x706CFE8F, 0x4060D907, + 0xB88F724C, 0x70AC708C, 0xFEAF0D02, 0xF00D70CC, + 0x4060D907, 0xB88FDA28, 0x70AC708C, 0xFEAF0CEE, + 0x0F9670CC, 0x700CFE8F, 0xDA08D907, 0x708C706C, + 0x0CDA45A1, 0x70CCFEAF, 0xD907700C, 0x706C704C, + 0x45A1708C, 0xFEAF0CC6, 0x704C70CC, 0x4040752C, + 0x0004238A, 0x708CB895, 0x0CB245A1, 0x70CCFEAF, + 0xD92BD841, 0x42E1B812, 0x708C706C, 0x0C9E45A1, + 0x264AFEAF, 0x700C01C0, 0x744CD907, 0x708C706C, + 0x0C8A45A1, 0x260AFEAF, 0x0F160400, 0x700CFE8F, + 0x704CD907, 0x708C706C, 0x0C7270AC, 0x70CCFEAF, + 0xD907700C, 0x706C704C, 0x70AC708C, 0xFEAF0C5E, + 0x0AC670CC, 0x7704FE4F, 0x78E0C6CA, 0x88A0C0E6, + 0x900743C3, 0xED07C2CC, 0x00051B00, 0x00051B04, + 0x248AF005, 0xB3801FC7, 0x1600B382, 0x80007083, + 0x23780008, 0x6B920103, 0x900743C3, 0xED16C2C0, + 0x1B04B380, 0x09130085, 0xDB1000F5, 0x26F47B2D, + 0x800070C3, 0x908810BC, 0x23CF7295, 0x1E000361, + 0x900770C4, 0xF007C29C, 0x1C0C2445, 0x1B04B380, + 0x43C30045, 0x12228000, 0x008B13B7, 0x8BC08BE1, + 0x0F417BCF, 0x0B3910C4, 0x201410EE, 0x091300CC, + 0xDD0A0070, 0x1C24E988, 0x75AD1285, 0x1C24F007, + 0xF0051145, 0x1C24DD0F, 0x09151005, 0x221400B5, + 0x130000C3, 0x0B0900C3, 0xB4B20013, 0xF1E271C5, + 0x78E0C4C6, 0x702CC0F1, 0x900742C3, 0x1E00C2C0, + 0x90077044, 0xB220FED4, 0x1E00B222, 0x90087044, + 0x800801E4, 0x2005B802, 0x90070F80, 0xB020C000, + 0x002009E2, 0x80441ADC, 0x01800C2A, 0x7EE0C0D1, + 0x46C8C2F2, 0x47084528, 0x416040C1, 0x21C0250A, + 0x2140220A, 0x2100200A, 0x0E364170, 0x43500060, + 0x40E14410, 0x704C41A1, 0x240A4322, 0x250A0400, + 0x46C10480, 0x0020085E, 0x0540270A, 0xEF0870CD, + 0x000040C3, 0x0C32FFFF, 0x712C05E0, 0x4102D840, + 0x70041E00, 0x01E49008, 0x42828508, 0x2005B802, + 0x90070F80, 0x1800C000, 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0xF789E0C0, 0x003F2080, + 0x30021C01, 0x7104C020, 0xC080C060, 0x00200EF6, + 0x13902514, 0x2004182C, 0xF1D071C5, 0x78E0C7D0, + 0x42C3700C, 0x0000901C, 0x900741C3, 0xB200F800, + 0x00151984, 0x00041A44, 0x80151980, 0x191CB202, + 0x19040015, 0x19040015, 0x19080015, 0xB1000015, + 0x7FE0B102, 0x78E0B104, 0x4050C2EA, 0x082D4130, + 0x45080275, 0x000046CB, 0x2025FFFF, 0xF0310340, + 0xF008F015, 0xF006F016, 0xF01CF018, 0xF026F01E, + 0x000046CB, 0xF025A536, 0x41C3700C, 0x00010224, + 0xFDEF0AC6, 0x70CD42A1, 0xDEFFF01B, 0xF019BE08, + 0x000046CB, 0xF015AAAA, 0x000046CB, 0xF011B2B2, + 0x000046CB, 0xF00D8241, 0x800040C3, 0x88C10104, + 0xBE088820, 0xF0057E25, 0x000046CB, 0x70165A3C, + 0x0A26DFAA, 0x27CA0760, 0xE8061021, 0x708F1600, + 0x01068000, 0x08E96D0B, 0x26040155, 0x00001F81, + 0xB928FF00, 0x42E178CF, 0x0B8A43E1, 0x240A05E0, + 0x16000440, 0x80007080, 0x72140008, 0x901C41C3, + 0x40C30000, 0xF8009007, 0x1900F406, 0x18000005, + 0xF0060005, 0x00451900, 0x00451800, 0x12300DA7, + 0x0D59D8FF, 0x0D551110, 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0x43E142C2, 0xFC6F0D1A, + 0x40A144A1, 0x0184209A, 0x20102000, 0x18002656, + 0x0D2A7002, 0x180005E0, 0xE80E0502, 0x25002015, + 0x213460D1, 0x60382000, 0x2000791D, 0x80002F80, + 0xB0201B40, 0xE58A71A5, 0xFFC506CE, 0xF15671E5, + 0x341B1404, 0x78E0C6DA, 0x7034C2E6, 0x03012A40, + 0x79654608, 0x47CBC808, 0x00409004, 0x27C07825, + 0x28401222, 0xE688008B, 0x404846C1, 0x026126CA, + 0x000045CB, 0x702DFFFF, 0x706C708D, 0x01A50B37, + 0x0E137890, 0x20001275, 0x101C1680, 0x0B1F0080, + 0x21050000, 0x78E512C0, 0xFEEF0842, 0x79B09000, + 0x004D2009, 0x20087990, 0x2180004C, 0x71641010, + 0x79B0F1E6, 0x781D6038, 0x78E0C6C6, 0x44CBC0E6, + 0x12228000, 0x108814B7, 0x14008CE1, 0x0F9B1086, + 0x08931184, 0x244A11AE, 0x265A7280, 0x20A8028B, + 0x446900C1, 0x800045CB, 0x249AC144, 0x2432100E, + 0x80001F89, 0x0927C444, 0x659E10F0, 0x10B00915, + 0x7135659E, 0x702D70EC, 0x2434F417, 0xF0131347, + 0x13472434, 0x11091602, 0x2434F00F, 0x16021347, + 0xDD801109, 0x21029682, 0x7D8211C4, 0x03450C0B, + 0x218A4781, 0x21001002, 0x211411CC, 0x7E9D02CD, + 0x018C20F4, 0xB58064DC, 0x02CD2214, 0x018C20F4, + 0xB58074E0, 0x02CD2314, 0x018C20F4, 0x74217165, + 0x71C4B580, 0xC4C6F1B5, 0x706CC0F1, 0x2240DC3F, + 0x248A008B, 0x18007001, 0xA9800003, 0x01C020A8, + 0x15081304, 0x10110809, 0xF0037164, 0x2280A860, + 0x248A0F83, 0x20A87001, 0x12FC01C0, 0xEB858503, + 0x89807785, 0xA980F002, 0x7B8F8840, 0xCA0B4B51, + 0x44207110, 0xF649700C, 0x021D41C3, 0x0E520003, + 0xD8C9FEAF, 0xC0D1760C, 0x78E07EE0, 0x7002248A, + 0x20A8706C, 0x41000480, 0x0182235A, 0x000E219A, + 0x41C3623A, 0xC1448000, 0x61596234, 0x090D9121, + 0x71640305, 0xD8807FE0, 0x786F7FE0, 0xF717E1FF, + 0x7A22DA80, 0x7080240A, 0x044020A8, 0x215A4200, + 0x229A0183, 0x635B000E, 0x800042C3, 0x6354C144, + 0x9241627A, 0x03040A09, 0xD9807124, 0x78307FE0, + 0x01422053, 0xA941B826, 0xA9007FE0, 0xC1A3C3EC, + 0x700C4210, 0x458B4130, 0xB504B505, 0x018D41C3, + 0xB5030000, 0x0DBAB502, 0x740CFEAF, 0x4122710C, + 0x32822440, 0x00200F26, 0x31832440, 0x4122700C, + 0x0F1AC282, 0xC3810020, 0x3140140A, 0x2042D980, + 0x40C38443, 0x12208000, 0x23CA9582, 0x8840002C, + 0xE411E4EE, 0x24CA95E4, 0x1406104D, 0x7E703110, + 0x740C7D90, 0x018E41C3, 0x43420007, 0x45C1718C, + 0x0400260A, 0x0D5A47E1, 0xC540FEAF, 0x13840D1B, + 0x23E40817, 0x27CC7512, 0xF7599385, 0x41224042, + 0x43E1704C, 0x4042F00D, 0x704C4122, 0x44A143E1, + 0xFCAF0B4A, 0x404270AC, 0x704C4122, 0x240A43C1, + 0x0B3A0400, 0x71ACFCAF, 0x0E15C7CC, 0x0DEB13C5, + 0x40429424, 0x704C4122, 0xF00F43C1, 0x14250D13, + 0x41C3740C, 0x0000018F, 0xFE8F0CF6, 0x4042C7CC, + 0x704C4122, 0x44A143E1, 0x78E0F1E5, 0x800042C3, + 0x24AA0450, 0x21AA1144, 0x82610104, 0x200E8200, + 0xA2008040, 0x90C12403, 0xA2217FE0, 0x1CFCC2FA, + 0xC1B6B6C8, 0x800046CB, 0x8EA01222, 0x780F4310, + 0x714CC180, 0x1C04706C, 0x24403001, 0x0BE63019, + 0x1C000020, 0x23403001, 0x23402A18, 0x09D62A9B, + 0x255F03A0, 0x16001251, 0x272F1092, 0x8E011487, + 0x03E40885, 0x2F412354, 0x33CD21F4, 0x41C3740C, + 0x000103EA, 0xFEAF0C6A, 0x2F4042A1, 0xC8081315, + 0x26C12505, 0x900447CB, 0x78250000, 0xB802708E, + 0x2440270A, 0x902078E5, 0x01502153, 0xE5207502, + 0x2348262F, 0x05C7222F, 0x7854C082, 0x03EB41C3, + 0x43020004, 0xB0A04440, 0x0C26740C, 0x250AFEAF, + 0x71860580, 0x0507202F, 0x827408DD, 0x250571E6, + 0xC8082601, 0x21007825, 0xB8022511, 0x78E57146, + 0xF1BDB0A0, 0x7825C808, 0x714CC182, 0x708C706C, + 0x06200D7E, 0xC0B670AC, 0x341B1404, 0x78E0C6DA, + 0xD820C2E2, 0x900745CB, 0x1D00C40C, 0x0F6A1045, + 0x1D000220, 0xD8201005, 0x02200F5E, 0x10451D00, + 0x10051D00, 0x78E0C6C2, 0x803C2042, 0x42C3F208, + 0x12EA8000, 0x010020A8, 0x00521A14, 0x06200475, + 0x78E0712C, 0x2482C3EA, 0x45083212, 0x38802455, + 0x0BAE702C, 0x228AFC2F, 0x710C0010, 0xB80278B8, + 0x00200E42, 0x0350200F, 0x00200E46, 0x07912040, + 0x8E82208C, 0xDEFE70ED, 0x0E36F705, 0x20540000, + 0x740C088E, 0x040841C3, 0x714C0002, 0xFEAF0B52, + 0x120843A1, 0xC084360D, 0x800041C3, 0x0B4A1042, + 0xDA78FC2F, 0x0BC6C084, 0xD9780620, 0x1E00D80F, + 0x900773C4, 0x0FDEC29C, 0xD90FFDAF, 0x212F78CF, + 0x0FA60447, 0x222F0160, 0x25050407, 0x00011F90, + 0x45CB002A, 0x12228000, 0x8D208D01, 0x00640829, + 0xB90E7822, 0x28407104, 0x240A2082, 0x20A87000, + 0x22050300, 0x71C30040, 0x40000000, 0xB89FB89C, + 0x00051800, 0xD80F70CD, 0xFDAF0F8A, 0x700CD90F, + 0xFCEF0DDA, 0x8D01712C, 0x77108DE0, 0x002D006C, + 0x106D26C0, 0x712C78E2, 0x26046861, 0x00001F82, + 0x2653FFF8, 0xBA231080, 0x71C57918, 0x70C0240A, + 0x090020A8, 0x13032F40, 0x73C026F4, 0x048C8000, + 0x2F407865, 0xB802120C, 0x0F802005, 0x02DC9004, + 0x010B1000, 0x38802455, 0x70756098, 0x8C00605C, + 0x004220C5, 0x7826F402, 0x04032305, 0x6B12AC00, + 0xB89C71E5, 0xB0C0B89F, 0x03400F9A, 0x087B78D0, + 0x00008F84, 0x8DC00800, 0x8D01700E, 0x03A408DD, + 0x41C3740C, 0x00010409, 0xFEAF0A36, 0x702E42C1, + 0xAFDF218C, 0x002D00B6, 0x218B740C, 0x1C0CA803, + 0x1C083400, 0xF4123400, 0x28002156, 0x21822941, + 0x0F802004, 0xFFC00000, 0x41C3B826, 0x0002040A, + 0x09FE6869, 0x740CFEAF, 0x70CCDF08, 0xC282706C, + 0x627A708D, 0x00892653, 0x7100244A, 0x200A736D, + 0x1A001440, 0x20A80003, 0x2E400500, 0x24551200, + 0x61193881, 0x10C02841, 0x61087105, 0x02402801, + 0xB8C07125, 0x02C02800, 0x7C057765, 0x00862652, + 0x71647426, 0x177F278D, 0x140DAA80, 0x140B3087, + 0x140C3085, 0x140A3086, 0xC2223084, 0x30831409, + 0x3081140E, 0x3080140F, 0x41C3C140, 0x0008040B, + 0x097EC041, 0x740CFEAF, 0x41C3F1A4, 0x0000040C, + 0xFE8F096E, 0xF19371C5, 0x78E0C7CA, 0x082E43E3, + 0x20780000, 0x16000001, 0x80007080, 0x08110008, + 0x217800B1, 0xB8020000, 0x7B007404, 0x00002178, + 0x7204781B, 0x78E07B00, 0x800040C3, 0x88201220, + 0x219F8841, 0x229F0582, 0x10BC02C1, 0x60380000, + 0x8A03621A, 0x86002044, 0x02002078, 0x20CA7FE0, + 0x78E000A1, 0x244AC5E1, 0x706C71C0, 0x702C704C, + 0x900C44CB, 0x20A80240, 0x21050280, 0x7424030D, + 0x651D95A0, 0x7144AD40, 0x70811600, 0x00408000, + 0x244AE90E, 0x704C71C0, 0x028020A8, 0x1381244F, + 0x74447945, 0x61199120, 0x7164A967, 0x78E0C4C2, + 0x4310C2F2, 0x4570710C, 0x42304450, 0xFCAF0A92, + 0x04CD2800, 0x10512553, 0xD90B700C, 0x706C704C, + 0x250A708C, 0x0BF60440, 0x70CCFCEF, 0xD9FF700C, + 0xFCEF0EDE, 0x6D12704C, 0x200F762C, 0xDA2204C0, + 0x700C7E0F, 0x20300D1D, 0x244ADB40, 0x45C10A00, + 0xFCEF0BCA, 0xD88070CC, 0x744CD919, 0xF00CDB83, + 0x0940244A, 0x0BB645C1, 0x70CCFCEF, 0xD919D880, + 0xDB81744C, 0x250A708C, 0x0BA20440, 0x70CCFCEF, + 0x0B4A700C, 0x712CFCEF, 0x0BCE700C, 0xB88B0220, + 0x000040C3, 0x0C4E9C40, 0xD9080220, 0x20300D0B, + 0xD92640C1, 0xD923F002, 0xFE8F0F7A, 0x800047CB, + 0x8FA01222, 0x082B8F01, 0x79AF0344, 0x0C4E4062, + 0x403000A0, 0x4002E809, 0x0F9A742C, 0x42620360, + 0x23412214, 0x8F01B100, 0x71A57510, 0x0D0DF7AF, + 0x40C12030, 0xF003D927, 0x0F3AD924, 0x8FA0FE8F, + 0x0B7D8F61, 0x7EAF0364, 0x0C124062, 0x41C100A0, + 0x40C1E834, 0x0F5E742C, 0x42620360, 0x22F4B808, + 0x22142341, 0x78252342, 0x1600B200, 0x80007101, + 0x218C0006, 0xF70581C3, 0x00451A00, 0x7810F004, + 0x0095080D, 0x000040C3, 0xF009FFFF, 0x70811600, + 0x00088000, 0x2905B911, 0xB2000000, 0x0D117B10, + 0x740C2030, 0x035941C3, 0xF0050002, 0x035A41C3, + 0x0F5E0002, 0x42A1FE6F, 0xF1C471A5, 0x0B298FA0, + 0x79AF0364, 0x00A00B96, 0xE88B4062, 0x103F0D0D, + 0x23402214, 0xF0049021, 0x810110FE, 0x8F61B020, + 0xF1EF71A5, 0x0B438F40, 0x0C3F0084, 0x23782030, + 0x0D0F2000, 0x20782030, 0x48AC0000, 0x489CF002, + 0x68614B50, 0x7825C808, 0x70C0240A, 0x20A86892, + 0x2A400340, 0x22F40380, 0x78852081, 0xB8927144, + 0xB89FB89C, 0x08CAB020, 0x700CFC8F, 0x744CD90C, + 0x708C706C, 0x0440250A, 0xFCEF0A32, 0x700C70CC, + 0x764CD907, 0x708C706C, 0x0A2270AC, 0x268AFCEF, + 0x700C0FC3, 0x744CD910, 0x708C706C, 0x0440250A, + 0xFCEF0A0A, 0xD88070CC, 0x764CD907, 0x708C706C, + 0x09FA70AC, 0x268AFCEF, 0x700C0FC3, 0xFCEF099E, + 0x0832712C, 0xC6D203C0, 0xC1A4C3EA, 0x45484668, + 0x41104030, 0x0F9770ED, 0x244A11F5, 0x40C37200, + 0x12208000, 0x20300935, 0x704C8820, 0x20A8706C, + 0x40200540, 0x209F6F95, 0x70020803, 0x2B41641C, + 0x640C00C0, 0x01802344, 0x01C02047, 0x102E0C3B, + 0xE212C080, 0xF029E312, 0xDA7EDBFE, 0x050020A8, + 0x6F954020, 0x0803209F, 0x641C7002, 0x00C02B41, + 0x2344640C, 0x20470180, 0x0C1901C0, 0xC080102E, + 0xBB72BA72, 0x41C3F011, 0x00020183, 0xF00878F4, + 0x003E2380, 0x41C378F4, 0x00020184, 0x740CB040, + 0xFE6F0DEE, 0x71E542E1, 0x1400F1B7, 0x244A3100, + 0xC28071C0, 0xB600B500, 0x038020A8, 0x05011202, + 0x090B9560, 0xB52000C5, 0x080B9600, 0x40200045, + 0x78E0B620, 0x78E0C7CA, 0xE808702C, 0x8002222F, + 0x6119B8C0, 0xF5FC4040, 0x78307FE0, 0x71001600, + 0x02909008, 0x78E07EE0, 0x0872C2E2, 0x08C6FD8F, + 0x4508FDAF, 0x70811600, 0x001C8000, 0xE80CE906, + 0xD87DED8B, 0xF019B807, 0xED8CE80B, 0x000040C3, + 0xF0134650, 0x40C3ED0A, 0x4A380000, 0xED0AF00D, + 0x000040C3, 0xF0095208, 0x000040C3, 0xF0052EE0, + 0x000040C3, 0x097E36B0, 0x742C0220, 0xC6C2780F, + 0x800040C3, 0x051D12DC, 0x8000FC6F, 0x45CBC2E4, + 0x12208000, 0x8D218D00, 0x0582209F, 0x02C1219F, + 0x100215BC, 0x60386058, 0xB8248801, 0xFC6F0EE6, + 0x058E205F, 0x00832079, 0x8D418D00, 0x0582209F, + 0x02C1229F, 0x100115BC, 0x0285239F, 0x60586038, + 0x63DB8803, 0xD80AB8E5, 0x022120CA, 0x2332631B, + 0x80000F80, 0xC6C407E0, 0x40C3C2E2, 0x12208000, + 0x88418820, 0x0582219F, 0x02C1229F, 0x000010BC, + 0x621A6038, 0xB8C38A02, 0xFC6F0E8A, 0x038D205F, + 0x00812079, 0x800040C3, 0x219F0646, 0x61B90483, + 0x60386112, 0x621A9001, 0xC6C27850, 0x4568C2E8, + 0x4050DB7F, 0x44604220, 0x248AE983, 0x8D850FC7, + 0x11041D06, 0xEA14E80E, 0x70811600, 0x01468000, + 0x40C3E91E, 0x01408000, 0xB5268861, 0xF0158820, + 0x1D08710C, 0xB8901001, 0xC6C8A503, 0x20100831, + 0x71011600, 0x01428000, 0x40C3E92E, 0x01388000, + 0xB5269062, 0xB5249020, 0xF031B565, 0x11041D0A, + 0x10051D08, 0x1D0CEC2A, 0xF0291085, 0x71011600, + 0x01448000, 0x40C3E918, 0x013E8000, 0x10FC9060, + 0xB5268100, 0xB504B565, 0x70801600, 0x000B8000, + 0x017E082B, 0x8008238C, 0x10051D08, 0x238AF78F, + 0xF1DC0FC7, 0x0FC7238A, 0x11041D0A, 0x10051D08, + 0x1D0CEC04, 0xF0031205, 0x41C3B506, 0x00030227, + 0xFC2F08D6, 0x00C0243D, 0x1104150C, 0x0400250A, + 0x95059544, 0x1D0E4851, 0x29081104, 0x78220101, + 0x022841C3, 0xB5050004, 0x0BA67B10, 0x740CFE6F, + 0x78E0C6C8, 0x084BC5E1, 0x712D00B5, 0x2078DD25, + 0xBD9F0008, 0x8D8D700C, 0x10F00C0F, 0x2444716D, + 0x20521040, 0x7015000B, 0x20CA8D80, 0xA90002C1, + 0x10002900, 0x7C0BAA00, 0x700C712C, 0xAB20F207, + 0x800041C3, 0x702D1220, 0x4021A900, 0xDD40C4C2, + 0x00882078, 0x700CBD9F, 0x0C118D8D, 0x716D10F0, + 0x10402444, 0x000B2052, 0x8D807015, 0x02C120CA, + 0x2900A900, 0xAA001000, 0x722C7C0B, 0xF5E1710C, + 0x78E0F1E5, 0x00700821, 0x7DE07014, 0x70801600, + 0x00258000, 0x00C02078, 0xA1007104, 0x800040C3, + 0xF0151224, 0x70801600, 0x00408000, 0x0050080F, + 0x00D10811, 0x00811900, 0x1900F006, 0xF0040041, + 0x00011900, 0x800040C3, 0x88201226, 0x8801AA20, + 0xAB007FE0, 0x0883C2E2, 0x45080030, 0x71021600, + 0x00148000, 0x00CF41C3, 0x0AB60001, 0xD8FFFE6F, + 0x08676D09, 0x120D01D5, 0x120B3083, 0x120C3604, + 0x20253605, 0xF0080000, 0xF010F00B, 0xF018F013, + 0xF024F01B, 0x41C3700C, 0x000300D0, 0x700CF022, + 0x00D141C3, 0xF01E0003, 0x41C3700C, 0x000300D2, + 0x700CF018, 0x00D341C3, 0xF0140003, 0x41C3700C, + 0x000300D4, 0x120BF00E, 0x41C33082, 0x000400D5, + 0xFBEF0F56, 0xC6C2700C, 0x41C3700C, 0x000300D6, + 0x43804260, 0xFBEF0F42, 0x0140240A, 0x78E0C6C2, + 0x000043CB, 0x242F28F0, 0x201F12C0, 0x7B8A02C0, + 0x108B2B41, 0x02C1211F, 0x0184229F, 0x60386078, + 0x42C36058, 0x1A3E8000, 0x08012256, 0x78356029, + 0x61116A2A, 0x48326050, 0x71447030, 0x002522CA, + 0x78507FE0, 0x1CFCC2FA, 0xC1A6B6C8, 0x16004608, + 0x80007100, 0x4528000A, 0xC3414358, 0x781DC043, + 0x87812044, 0xC045710C, 0xC042D810, 0x090DF207, + 0x700C00B1, 0xF003C045, 0x208AC142, 0xB6010004, + 0xAE00D820, 0x081FC003, 0xD8C8007E, 0x8D409561, + 0x021A41C3, 0x121C0004, 0x09963705, 0x121DFE6F, + 0x8D003704, 0xC2014363, 0x95E14210, 0x0AE641E1, + 0x41F1FDAF, 0xC0034010, 0x007E081D, 0x9561D8C8, + 0x41C38D40, 0x0004021B, 0x0400240A, 0xFE6F0962, + 0x0400250A, 0x7014C002, 0x7216F2BC, 0x00250174, + 0xC002746E, 0x70CE8DE0, 0xB82295A1, 0x1410C044, + 0x22003015, 0x240A24C0, 0x210A2440, 0x20533400, + 0x22020150, 0x0D1124C0, 0x20531521, 0x0F1B0151, + 0x70EE1460, 0x4022C201, 0x0A7A4182, 0x4363FDAF, + 0x15210D0B, 0x0F254710, 0xC2011400, 0x41824002, + 0xFDAF0A62, 0x0F154363, 0x081F2005, 0x47100664, + 0x220A474A, 0xF00B2400, 0xA640270C, 0x148627CA, + 0x244622CA, 0x270AF743, 0x24002640, 0x240224C0, + 0x205324D1, 0x21530218, 0x77522211, 0x944125CC, + 0x0D21F405, 0x700E1621, 0xC201F01B, 0x41224042, + 0xFDAF0A12, 0x40104363, 0x25CC7752, 0xF2119601, + 0x4042C201, 0x09FE4103, 0x4363FDAF, 0x20050813, + 0x05E40819, 0x2600210A, 0x4010458A, 0x200CF00A, + 0x25CAA5C0, 0xF7461506, 0x2500210A, 0x25C0200A, + 0x26610817, 0x30141410, 0xF547262F, 0x2542F204, + 0xF0032054, 0xC003708E, 0x007E082D, 0x2507252F, + 0x41C3D8C8, 0x0007021C, 0x434242C2, 0x0440240A, + 0x0400250A, 0x0400260A, 0x04C0270A, 0xFE6F0832, + 0x35401C00, 0x08178E00, 0x0D170481, 0x96012010, + 0x0440080F, 0x2500250A, 0x0DFDF012, 0x1410A011, + 0x202F3015, 0x431084C2, 0x716EF404, 0x2500250A, + 0x00012079, 0x2005C005, 0xF20C807E, 0xC00271C6, + 0xA000260C, 0x14441E02, 0xFFE506AA, 0x14821E00, + 0xC0A64002, 0x341B1404, 0x78E0C6DA, 0x44CBC0E6, + 0x12D98000, 0x8C204028, 0x7100244A, 0x70AD70CD, + 0x20A8708D, 0x091B0240, 0x7185030F, 0x000075C3, + 0x702C8000, 0x900345CB, 0x706DC000, 0x6892F015, + 0x10812800, 0x79647D85, 0x1F8C2505, 0x00009038, + 0x25059480, 0x903B1F8D, 0x2406C000, 0x7C6410CF, + 0x2C0179E5, 0x0C43108B, 0xB5200031, 0x708C1600, + 0x00258000, 0x1600EC88, 0x8000708C, 0xEC140040, + 0xBE0CDE07, 0x28007E05, 0x6E52108C, 0x22057C64, + 0x90000F81, 0x91200000, 0x0F8D2205, 0xC0009003, + 0x79857966, 0x4061B520, 0x78E0C4C6, 0x1CFCC2FA, + 0xC1ADB6C8, 0x4210C71D, 0x70801600, 0x00148000, + 0x21C0200A, 0x41384150, 0x700F70EE, 0x31801C2C, + 0x31401C04, 0x31001C28, 0x013E081B, 0x1600C349, + 0x80007080, 0x080F001E, 0x710F003F, 0x05400C5A, + 0x97C44018, 0x20C02242, 0x0175082F, 0x0D8297A1, + 0xE815FE4F, 0x800040C3, 0x88411222, 0x0A1F8800, + 0x790F0004, 0x27147104, 0x19241041, 0x790F05C4, + 0x80450AF3, 0x0ADBF003, 0x2178A050, 0xD80930D2, + 0x30F10911, 0xD80AC040, 0x3240234A, 0xF003C040, + 0x0842706F, 0x0E360380, 0xD8C8FCAF, 0xFCAF0E3E, + 0x7056970E, 0x900446D3, 0x40C33DD0, 0x01D09004, + 0x200226CA, 0x3031080D, 0x2004258A, 0x2002258A, + 0x2538C01C, 0x704E1393, 0x800044D3, 0xC04C1222, + 0x30002150, 0x40C3C045, 0x28F00000, 0x2001211F, + 0x201F781B, 0x60382000, 0x4063C043, 0x0184209F, + 0x6038C103, 0x0F812000, 0x1A3C8000, 0x800070C3, + 0xC0481A3E, 0xC042720C, 0x30802178, 0xC1477204, + 0x710CC046, 0x45CBC044, 0xC2CC9007, 0x20300A1D, + 0x0FC7208A, 0x732EB500, 0x15C41D04, 0x0819C005, + 0x97C800B1, 0xF009BE07, 0x712E70CD, 0x15C41D00, + 0xF003B502, 0x1400BE08, 0x14012090, 0x202F208B, + 0x0B930407, 0x43A21024, 0x70811600, 0x12D98000, + 0x002E097F, 0x10012714, 0x038B2840, 0x1F822305, + 0x3ED49004, 0xB90A9132, 0x04412105, 0xC109B220, + 0x000021F4, 0x30300829, 0x0A1960D8, 0x79102030, + 0x08002155, 0x0FCF218A, 0x8FCF208C, 0xF009F7C8, + 0x8002218C, 0xF785702C, 0x003E2080, 0x23054100, + 0xB0201580, 0xE815CC20, 0x712CD840, 0x15C41D00, + 0x03E009E6, 0x15C41D04, 0x70801600, 0x00088000, + 0xD8407414, 0x20CAD944, 0x1DF40041, 0x71069004, + 0xCC20F1B5, 0xC106E827, 0x20032D01, 0x00412800, + 0x1400633B, 0x0B3F2081, 0x16001044, 0x80007088, + 0x782F12D9, 0x102E0827, 0x2005B80E, 0x90040F82, + 0x9200029C, 0x05C41A00, 0x0F8C2004, 0x1FFE0000, + 0xB80DCC20, 0xBC807C05, 0x7124B280, 0x0BD7782F, + 0x78709005, 0xFCAF082E, 0x7076702C, 0x14B7F26F, + 0x14012088, 0x8F05208B, 0x208E1400, 0x268AE82E, + 0x7BCF0FC7, 0x10C40BC5, 0x10CE084D, 0x0F82231F, + 0x0A3C0000, 0xC008C407, 0x621A645C, 0xC1004063, + 0x00450835, 0xE988C101, 0x06812300, 0x0081111C, + 0x00400819, 0x7001248A, 0x41404189, 0x018020A8, + 0x00151904, 0x11941904, 0x11842480, 0x01842280, + 0xF1E77104, 0xF1D771C5, 0x128D265F, 0x7ACF7563, + 0x10840B69, 0x10AE085F, 0x416344A9, 0x0957C000, + 0xC0010005, 0x2200E887, 0x101C0680, 0x09410080, + 0x788F0000, 0x7002248A, 0x000E209F, 0x0F832000, + 0xC1448000, 0x20A8C00C, 0x1B0201C0, 0x1B040014, + 0x225F0015, 0x60F80500, 0x3030080D, 0x18347834, + 0xF0060FC5, 0x23F4C30A, 0xB07A0083, 0x71247185, + 0xE50AF1D6, 0xF1CD71C5, 0x0A7E706E, 0x1400FC4F, + 0x14012090, 0x262F2080, 0x08771407, 0x714E03A4, + 0x70801600, 0x12D98000, 0x03AE0863, 0x13912E40, + 0xC000456B, 0x10050D57, 0xE888C001, 0x16802600, + 0x0080101C, 0x10000D43, 0x12802D40, 0x20CA7337, + 0x20050021, 0x20050440, 0x90040F80, 0xC10B01D0, + 0x0FF87034, 0x9000FD61, 0x1502265F, 0x7034C104, + 0x800041C3, 0x7AB4BE24, 0x6159F204, 0xF005B100, + 0x19506159, 0x71A50004, 0x7106F1D5, 0xC102F1C3, + 0xC1427724, 0x702C7034, 0xFFE2056E, 0x1400C144, + 0x202F2091, 0x200C2447, 0x012EA000, 0x1600000D, + 0x80007081, 0x211112D9, 0xF28D8400, 0x2295215E, + 0xC000466B, 0x010A7610, 0xC0010006, 0x2000E887, + 0x101C2680, 0x0EA10080, 0x205F1000, 0x40C32501, + 0xBE248000, 0x03832114, 0x6315607A, 0x01121250, + 0xE82E8F05, 0xDB3F9724, 0x48319701, 0x29049707, + 0x78300001, 0x023E41C3, 0x42000002, 0x000120BC, + 0xFBEF0816, 0x201F4350, 0x00002F81, 0xC0030A3C, + 0x40C16119, 0x0184209A, 0x21156119, 0x200004C0, + 0x80000F81, 0x70C31A3C, 0x1A3E8000, 0x23650A33, + 0x0FC7228A, 0x05C41800, 0xF016B140, 0x23640A29, + 0x79D461F9, 0x082D911A, 0x00000F81, 0x2200FFFF, + 0xE0FF2340, 0x1934F70A, 0x700C05C4, 0xB1A0F00A, + 0x04841800, 0xF1A771C5, 0x2080781D, 0xB11A003F, + 0x78109728, 0x75104D12, 0x0480200E, 0x23832500, + 0x004B2A04, 0x28047C6F, 0x23CA0040, 0x7A101025, + 0x02C8212F, 0x80640AD1, 0x215F4081, 0x209F0181, + 0x6119000E, 0x800040C3, 0x6038C144, 0xB0219721, + 0x90609721, 0x00C50907, 0x7165B020, 0x1401F1EA, + 0x71262080, 0xC0ADF167, 0x341B1404, 0x78E0C6DA, + 0x47CBC2FA, 0x12228000, 0x240A8FC0, 0x250A2180, + 0x260A2140, 0x47702100, 0x41384058, 0x8F014110, + 0x03840899, 0x800040C3, 0x880012D9, 0x03AE0889, + 0x1105704E, 0x700E2080, 0x27F4E883, 0x265A2390, + 0x11051293, 0xE81D2080, 0x000040C3, 0x791B28F0, + 0x3002211F, 0x3041201F, 0x78CCB822, 0x611A6159, + 0x209A4042, 0x621A0184, 0x800040C3, 0x60591A3C, + 0x91016215, 0x0345081B, 0x700C70AD, 0x0B82F009, + 0x4062FF6F, 0x40624508, 0xFF6F0BA6, 0x60B941A1, + 0x24C22614, 0x7502793D, 0x71467102, 0x2514B220, + 0xB1A024C1, 0x04012000, 0x24C02414, 0x0A977166, + 0xB020A2B4, 0xF1B571C5, 0x78E0C6DA, 0x800041C3, + 0x89011222, 0x71108920, 0x07CD20E0, 0x29407822, + 0x71040382, 0x7000240A, 0x030020A8, 0x0F812205, + 0x01D09004, 0x72C39100, 0x40000000, 0xB100E020, + 0x78E07EE0, 0x0343236F, 0x800041C3, 0x93000458, + 0x208CDA08, 0xD8088059, 0x02A520CA, 0x9300B100, + 0x8059208C, 0x20CAD808, 0xB10102A5, 0x208C9300, + 0xD8088059, 0x02A520CA, 0x9300B102, 0x8059208C, + 0x02A522CA, 0xB1437FE0, 0xC1A2C3EE, 0x42104728, + 0x0C0D2055, 0x0D124020, 0x702CFD6F, 0x40424010, + 0x090E702C, 0xDACAFBAF, 0x208A71CD, 0xB5C20016, + 0x20041AC2, 0x0C15208A, 0x1600B500, 0x80007080, + 0x20440009, 0x710C8091, 0x00A120CA, 0x22431AC6, + 0x03200A1A, 0x20021AC9, 0x22408D24, 0xADC82403, + 0x200D2178, 0x424240E1, 0x71AC708C, 0xFEEF0BDA, + 0x12C546A1, 0x22402081, 0x22402202, 0x40E12603, + 0x71AC708C, 0xFEEF0BC2, 0x47CB46A1, 0x12228000, + 0x8F018FC0, 0x03840841, 0x238D2214, 0x0C9AC180, + 0x9500FD6F, 0x0C929504, 0xC181FD6F, 0x0BBAC080, + 0x712C0120, 0xFE2F090E, 0xB500C080, 0x0BAAC081, + 0x712C0120, 0xFE2F08FE, 0xB504C081, 0x76108F01, + 0xF7A471C5, 0x05000CE2, 0x70148FC0, 0x2040740C, + 0x20CA2413, 0x204001E2, 0x1AC72491, 0x8F012002, + 0x03A4085F, 0x13102E40, 0x265A70AD, 0x2D401503, + 0x22051202, 0xC8080402, 0x41C37A05, 0x00009004, + 0x04402205, 0x04C22205, 0xB8027342, 0x78257BB4, + 0x01051000, 0x1B206A12, 0x78250144, 0x01041000, + 0x1B70740C, 0x41C30104, 0x000401C7, 0x0FD242C1, + 0x43A1FDEF, 0x0DB771A5, 0x71C59254, 0xC7CEF1D1, + 0x40C3C0F1, 0x12208000, 0xC8088880, 0x7885BC0C, + 0x0F802005, 0x0FD80003, 0x05200F3A, 0xC808702C, + 0x6C127C05, 0x0F802005, 0x0364900C, 0x7FE0C0D1, + 0x00051800, 0xD9FFD838, 0x1803B89F, 0x18FC0052, + 0x18018042, 0x18160052, 0x18010052, 0xA8200052, + 0x7FE0A823, 0x78E0A824, 0xD9FFD83A, 0x1803B89F, + 0x18FC0052, 0x18018042, 0x18160052, 0x18010052, + 0xA8200052, 0x7FE0A823, 0x78E0A824, 0x200AC2E8, + 0x47682100, 0x45284648, 0x0135080B, 0xBA0E4200, + 0x0A0FF00D, 0x700C03F1, 0xBA0EDA1F, 0x41C3F008, + 0x00010030, 0xFB8F0C22, 0xBA92704C, 0x900040C3, + 0x22053A90, 0x74040001, 0x2205B1A0, 0x74040001, + 0x2205B1C0, 0x74040001, 0xB1E07845, 0x04041800, + 0x78E0C6C8, 0x4110C2EE, 0x230A4040, 0x220A2140, + 0x45682100, 0xFEAF0BAE, 0x46084030, 0xFEAF0BA6, + 0x470840A1, 0xFEAF0B9E, 0x45084042, 0xFEAF0B96, + 0x09214062, 0x092D2090, 0x09472050, 0x42222031, + 0x901C42C3, 0x41C3006C, 0xF8A89007, 0xF011B2C0, + 0x901C42C3, 0xB2C000EC, 0x900741C3, 0xF009F928, + 0x901C42C3, 0xB2C000AC, 0x900741C3, 0xB2E2F8E8, + 0xB102B1A0, 0x84041AD4, 0x840419D8, 0x41C3C6CE, + 0x0001002F, 0xFBAF0B72, 0xC6CE700C, 0x45CBC5E1, + 0x006C901C, 0x10141D04, 0x900744CB, 0x1D3CF8A8, + 0x1C041054, 0x1C3C1094, 0x1D0410D4, 0xB5201014, + 0x10941C04, 0xB51EB460, 0x10441D40, 0x1C40B45E, + 0xC4C210C4, 0x1600C2E2, 0x90307100, 0x45CB0200, + 0x4FC48001, 0x1A11DAB0, 0x206D3003, 0x40C30081, + 0x04A88000, 0x40A1A820, 0xFB6F0E26, 0x42C3702C, + 0xFFFC7FFF, 0x10802504, 0x2000B822, 0x00050F81, + 0x12688000, 0x20790600, 0x1A680000, 0x1A090058, + 0xC6C23002, 0x0FBAC3EC, 0xC1A1FBEF, 0x800040D3, + 0x205410D4, 0x70CD280F, 0x254270AD, 0x08111700, + 0x160001D5, 0x80007080, 0xE8130131, 0x14032532, + 0x1700700C, 0x762C1084, 0x254A704C, 0x08FE03C0, + 0x70CCFC6F, 0xD922700C, 0xFC6F0BE6, 0x71A5704C, + 0x98F40DCB, 0x700C71E5, 0xFC6F0892, 0xDD25712C, + 0xBD9F714E, 0x702C722E, 0x8D40720E, 0x7A058D1B, + 0x20402A00, 0x200FB802, 0x7F4B004F, 0x0E6AF21B, + 0x40C10060, 0x0F3AE817, 0x252FFBCF, 0x700C03C7, + 0x704C762C, 0x244ADBD0, 0x08A20300, 0x70CCFC6F, + 0xD922700C, 0xFC6F0B8A, 0x700C704C, 0xFC6F083E, + 0x208D712C, 0x712C277F, 0x25FF218D, 0xD98271CD, + 0xB99F70CD, 0x800047CB, 0x712E1220, 0x04801101, + 0x0140206C, 0x0E002045, 0x8900C060, 0x0140206C, + 0x0E002045, 0x30021C01, 0x206C8901, 0x20450140, + 0x1C020E00, 0x89023002, 0x0140206C, 0x0E002045, + 0x30021C03, 0x790F700C, 0x00B50979, 0xE906AF00, + 0xE8888D1B, 0xF034710C, 0x70148D00, 0xF230700C, + 0x20402900, 0xFEAF0826, 0x0E96780F, 0x702CFBCF, + 0x8D60720E, 0x7B058D1B, 0x20402900, 0x200FB802, + 0x7A6B0042, 0x8F60F20F, 0x252FC080, 0x704C0087, + 0x0440244A, 0x787470CC, 0x700C602B, 0xFC2F0FDE, + 0x208D762C, 0x712C2A7F, 0xD922700C, 0xFC6F0AC2, + 0x700C704C, 0xFC2F0F76, 0x8F00712C, 0xF1C57104, + 0xFE6F0FCA, 0xB7C0730C, 0x78E0C7CC, 0x0FDEC0F1, + 0x208A00E0, 0x7910041F, 0x0A96700C, 0x704CFC6F, + 0x7EE0C0D1, 0x4508C2E2, 0xB813D841, 0x744CD907, + 0x708C706C, 0x0F8670AC, 0x70CCFC2F, 0xFC4F0A2A, + 0xD90740A1, 0x706C744C, 0x70AC708C, 0xFC2F0F6E, + 0x09FE70CC, 0x40A1FC4F, 0x744CD907, 0x708C706C, + 0x0F5A70AC, 0x70CCFC2F, 0xD907D880, 0x744CB893, + 0x708C706C, 0x0F4670AC, 0x70CCFC2F, 0x78E0C6C2, + 0x800042C3, 0x8A401225, 0x0042223C, 0x16007854, + 0x80007082, 0x22110121, 0x21448000, 0x20F90040, + 0x7FE00022, 0x002120F8, 0x4608C2E4, 0x800040C3, + 0x88001225, 0x203C4528, 0x0CAE0040, 0x41C10060, + 0x710C7014, 0x038120CA, 0xFFE10FB8, 0xC6C441A1, + 0x0927682B, 0x71140175, 0x71011600, 0x00148000, + 0x210B710C, 0x00008F80, 0xF2034008, 0x782D7EE0, + 0x207A7FE0, 0x700C0000, 0xF1FAF3F0, 0x4220C0F1, + 0x2144B923, 0xBAC50601, 0x81006119, 0xFB6F0F3E, + 0xB8C08121, 0x7FE0C0D1, 0x00002078, 0x2482C3EC, + 0x45083708, 0x087AC087, 0x41A1FF2F, 0xC18240A1, + 0xFD2F0E46, 0x31C22440, 0xC7CCE802, 0x30801407, + 0x00B00811, 0x080F72CD, 0x704E00F0, 0xF00370CD, + 0x702E714E, 0xC080C182, 0x42A179D5, 0xFFAF091A, + 0x080FC387, 0xC7200444, 0x14024110, 0x76523110, + 0xF63277C5, 0xA03009C7, 0x1D82750C, 0x2580141C, + 0x700C1084, 0xC7CCADE0, 0xC1A2C3E6, 0x70AD4708, + 0x800146CB, 0xC5414D7C, 0x0071080D, 0xD864C540, + 0xF066B600, 0xB606D8C8, 0x080FF062, 0xE8890050, + 0xB808D87F, 0xD87FF003, 0xC040B810, 0xD9FFF006, + 0x0FA6700C, 0xB910FB6F, 0x10710F0D, 0x26F44E1C, + 0xF0041340, 0x034020F4, 0x0882B802, 0x7810FC6F, + 0xD907D841, 0xDA08B813, 0x708C706C, 0x0DCE70AC, + 0x70CCFC2F, 0x742C700C, 0xFC6F08B6, 0xC080714C, + 0x080E41E1, 0x724CFC6F, 0xD914700C, 0xFC6F08A2, + 0x706C714C, 0x4060D907, 0xB892744C, 0x70AC708C, + 0xFC2F0D9A, 0x160070CC, 0x80007080, 0x0811000C, + 0x700C003E, 0x087AD914, 0x714CFC6F, 0xD907D880, + 0xDA08B893, 0x708C706C, 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0x2B407825, 0x20051201, + 0x90040F80, 0x908002DC, 0x6038C092, 0x60797095, + 0x20C58900, 0xF4030082, 0x71657846, 0x7106A900, + 0x700EF1AB, 0x08DD8F01, 0x42A10364, 0x03FA41C3, + 0x0ADE0001, 0x740CFD6F, 0x09B9702E, 0x00002F85, + 0x218B0800, 0x1C0CA803, 0x1C083400, 0xF4123400, + 0x28002156, 0x21822941, 0x0F802004, 0xFFC00000, + 0x41C3B826, 0x000203FB, 0x0AA66869, 0x740CFD6F, + 0x70CCDB08, 0xC48270CD, 0x64DC700C, 0x00892653, + 0x7100244A, 0x200A736D, 0x1C001440, 0x20A81003, + 0x2D4004C0, 0xC2921201, 0x2841623A, 0x710510C1, + 0x29016229, 0x71250241, 0x2900B9C0, 0x776502C1, + 0x26527825, 0x74260086, 0x238D71C5, 0xAC0007FF, + 0x3087140D, 0x3085140B, 0x3086140C, 0x3084140A, + 0x1409C222, 0x140E3083, 0x140F3081, 0xC1403080, + 0x03FC41C3, 0xC0410008, 0xFD6F0A26, 0xF1A7740C, + 0x03FD41C3, 0x0A1A0000, 0x740CFD6F, 0xF19471A5, + 0x08318F20, 0x78220064, 0xC8086861, 0x06C02005, + 0x70C0240A, 0x20A86852, 0xC08A0380, 0x004320F4, + 0x03802940, 0x71247845, 0xB89CB892, 0xB060B89F, + 0x02000F22, 0x03FE41C3, 0x09D60000, 0x740CFD6F, + 0x42D3700C, 0x00009000, 0x202FC046, 0xC0498648, + 0x1600F2F2, 0x80007080, 0x0817000C, 0x700C00FE, + 0xFBAF0CBA, 0xD80F712C, 0xFC6F0E5A, 0x700CD90F, + 0xFBAF0CAA, 0x8FC0712C, 0x76108F01, 0x002D01AA, + 0x2440D80F, 0x27143C17, 0x17002397, 0x70142100, + 0x2614F4C9, 0x80007395, 0x2E40048C, 0x24401301, + 0x15003E11, 0x21052100, 0x00010F98, 0x200500B7, + 0x21050600, 0xB80206C1, 0x23912114, 0x04802005, + 0x2490224F, 0xC8089040, 0x78254350, 0x20841900, + 0x2005B802, 0xC0902010, 0x21141000, 0x03962014, + 0x21001600, 0x0B3FE80E, 0x740C2031, 0x03FF41C3, + 0x42C10002, 0x091A4382, 0x1F00FD6F, 0xF0932045, + 0x20110B23, 0x7014CA07, 0x20CAD812, 0xC10903E1, + 0x00610813, 0x740C702C, 0xFD6F08F6, 0x710CB99A, + 0x2453C046, 0x24AD214D, 0x740C2982, 0x040141C3, + 0x42C10004, 0x44A14382, 0xFD6F08D6, 0x04C0250A, + 0x20812440, 0x20056916, 0xCA070353, 0xD8227014, + 0x072120CA, 0x004508C3, 0x08B3C006, 0x16000010, + 0x80007080, 0x29090008, 0xF2518014, 0x040241C3, + 0x089E0000, 0x740CFD6F, 0xD90FD80F, 0xFC6F0D46, + 0x23441800, 0x02000DCE, 0x41C3740C, 0x00030403, + 0x706C42C1, 0xFD6F087A, 0x160044A1, 0x80007080, + 0x0817000C, 0x700C00FE, 0xFBAF0B72, 0xD80F712C, + 0xFC6F0D12, 0x700CD90F, 0xFBAF0B62, 0x1500712C, + 0x20052100, 0xB8020600, 0x04802005, 0x19009000, + 0xE8132004, 0x21842C40, 0x2405740C, 0x41C30344, + 0x00030404, 0x438242C1, 0xFD6F0826, 0x21041800, + 0x20451F00, 0x740CF017, 0x040541C3, 0x42C10003, + 0x080E706C, 0x44A1FD6F, 0x41C343B1, 0x00000406, + 0xFAEF0D06, 0x1800700C, 0x110024C4, 0x1E002100, + 0x71C52004, 0x0C9EF12A, 0xD90FFC6F, 0x02200D26, + 0xF10D7727, 0x1E00C007, 0x901C7004, 0xC0080510, + 0x70041E00, 0x0508901C, 0xFE4F0816, 0x702CC004, + 0xFC6F09AE, 0x41C3704C, 0x00000407, 0xFD2F0FB2, + 0x0A7E750C, 0xC005FDEF, 0x32112480, 0x341B1404, + 0x78E0C6DA, 0xC1A4C3E8, 0x800046CB, 0x8EA11220, + 0x40D371ED, 0x4E748001, 0x40027014, 0x7FB8D912, + 0x083EF209, 0x400202C0, 0x0D4AD912, 0xDA800060, + 0x09B6F003, 0x0EFA0240, 0xC08002E0, 0x0BDAC080, + 0xD912FDEF, 0x259F8E00, 0x209F12C1, 0x704C0582, + 0x708CC380, 0x6F12651D, 0x250078E5, 0x0A7E1401, + 0x780F04A0, 0x000040C3, 0x0B5A4E20, 0x702C00E0, + 0x78E0C7C8, 0x2482C3F2, 0x44103104, 0x702CC081, + 0xFAAF0F3E, 0x0004228A, 0x800045CB, 0x8D401220, + 0x20502479, 0x22102040, 0xA0432442, 0x41C3750C, + 0x00030150, 0xFD2F0EFA, 0x0400240A, 0x24408DA0, + 0xC8083081, 0x7D05BD0C, 0xFCAF0A82, 0x46084082, + 0x1F802505, 0x00D90003, 0x0E6AD940, 0x43100460, + 0x02200BBE, 0x1402BE68, 0x7FD03102, 0x41E14082, + 0x0BEA41F1, 0x4250FB2F, 0xD955E806, 0x0BBA700C, + 0xB912FAEF, 0x22002840, 0x7D0570CD, 0x800047CB, + 0x25050484, 0x00031F95, 0x7DD000D8, 0x9FC3258C, + 0x40A2F712, 0x04600E1E, 0x0B7641A1, 0x40820200, + 0x0BAA4122, 0x4242FB2F, 0x61B9C181, 0x8F00A900, + 0xF1ED661E, 0x0DFE40A2, 0x702C0460, 0x20802B40, + 0xB89C70AD, 0x0B4AB89F, 0xB0A00220, 0x015741C3, + 0x0E4E0000, 0x740CFD2F, 0x21C22042, 0x41C3740C, + 0x00020158, 0xFD2F0E3A, 0x8F804302, 0x7200244A, + 0x706C704C, 0x030020A8, 0x659EC081, 0x224E60A9, + 0x714401C0, 0x290045C9, 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0x0F802005, 0xC3EC9007, + 0x00451800, 0x41C3F006, 0x0000034D, 0xFA8F0B8A, + 0x74041E00, 0xC2509007, 0xB802C808, 0x0F802005, + 0xC02C903B, 0x00851800, 0x78E0C6C8, 0xC1A2C3F2, + 0xB99FD925, 0x1C068900, 0x891B3002, 0x30021C07, + 0x800040C3, 0x88201224, 0x8822C161, 0x30421C05, + 0x88038821, 0x30421C02, 0xFEAF0896, 0x30021C03, + 0x70ED4110, 0x218121AD, 0x0FA9714E, 0x2A001465, + 0x70CD23D5, 0x0E99C806, 0x24401005, 0x60C83180, + 0xA000250B, 0x2714F242, 0x700E1380, 0x20142A00, + 0x30802440, 0x03932032, 0x60CDC081, 0x0B6D78AF, + 0x78CF2024, 0xFF6F0EF2, 0x6E3479EF, 0x800042C3, + 0xE81311DE, 0x20402040, 0x03C32116, 0x6D817910, + 0x61596179, 0x03021920, 0x0408212F, 0x61596179, + 0x03421920, 0x232FF016, 0x79F60408, 0x16006179, + 0x80007080, 0x240B0121, 0x6D01A000, 0xF2066159, + 0x00021920, 0xF005A9A0, 0x1920A900, 0x40020342, + 0x204072A5, 0xF1CC0050, 0xF1B671C5, 0xF1AF71E5, + 0x78E0C7D2, 0xDB24C2E6, 0x800042C3, 0xBB9F1224, + 0x00031A00, 0xE0078B00, 0x00C12841, 0x69898B1C, + 0xE80FAA81, 0x791DC805, 0x70801600, 0x003F8000, + 0xB9C6E007, 0xAA22B823, 0x68C96038, 0x4689F003, + 0x12B5AA22, 0x788F008D, 0xAAC37104, 0x7000240A, + 0x20A8770C, 0x71040180, 0x100D250F, 0x42C378CF, + 0x12D98000, 0x0064081B, 0x7822AAA0, 0x240A7104, + 0x20A87000, 0x250F0180, 0x7124104D, 0x70ADAAA0, + 0x800044CB, 0x0D4311DA, 0x408910B5, 0x706D70CD, + 0x0B3179AF, 0x70751095, 0x20CA4060, 0x80000F82, + 0x88E0003F, 0xFF6F0DE2, 0xE80578CF, 0xB8236F07, + 0x4F1FF003, 0x1802B824, 0x71C51012, 0xF1EB7165, + 0x71A57185, 0xC6C6F1E1, 0x0A22C0F1, 0xC0D10100, + 0x700C7FE0, 0xE9058840, 0x001F0A0B, 0xBAE07EE0, + 0x88217DE0, 0xF78AE1C0, 0x20E07354, 0x218007CD, + 0xA821003F, 0xF0086A21, 0x7CE07054, 0x08012154, + 0x6A29A821, 0xA8207FE0, 0x0443216F, 0x11FE8940, + 0x229F8101, 0x790C041F, 0x00802905, 0x71047FE0, + 0x2482C3F4, 0x16003302, 0x80007080, 0xB8C30004, + 0x800047CB, 0x205F1220, 0x41C30B16, 0x0000013F, + 0x2700702E, 0x18081580, 0x0C360001, 0xD80AFCEF, + 0xFF8F0EB6, 0x800042D3, 0x202F1138, 0x24400448, + 0x24403181, 0x08823142, 0x2440FEAF, 0x701431C3, + 0x1407F4E3, 0x0F763080, 0x1A00FD6F, 0x14052043, + 0x712C3080, 0xFDAF0966, 0x70AD4310, 0x712C4062, + 0x0F62704C, 0x1A00FFAF, 0x14062342, 0xC1823080, + 0x716C724C, 0x0A0A708C, 0x4010FAAF, 0x702CC083, + 0xFA6F0BEE, 0x258ADA80, 0x708E2002, 0x8F2070CD, + 0x0507222F, 0x0CD64062, 0xC540FF6F, 0xC1804002, + 0x716C724C, 0xFAAF09DA, 0x1401708C, 0x20533080, + 0xF20681BE, 0x60D8C083, 0x00431800, 0x258D7186, + 0x71C52A7F, 0x740C8F60, 0x014141C3, 0x0B820002, + 0x4202FCEF, 0xDE8070AD, 0x41C3C083, 0x00010142, + 0x0B6E60AA, 0x740CFCEF, 0x1E3F268D, 0x41C371A5, + 0x00000143, 0xFCEF0B5A, 0x248A740C, 0x77AD7002, + 0x776D700C, 0x20A8776C, 0xC1830740, 0x610977B5, + 0xE0FFF207, 0xE914F202, 0x6829E906, 0xE98FF005, + 0xF00E4508, 0x2302D97F, 0x49B210CC, 0x25CA7291, + 0x21CA10CC, 0x43A102CC, 0x77AD4328, 0x77747104, + 0x77B5F404, 0xF404DE7F, 0x46694568, 0x41A18F60, + 0x21B94EB0, 0x207F0FFF, 0x78240100, 0x014541C3, + 0x0FF60002, 0x4202FA6F, 0x41C366B8, 0x00030146, + 0x00942844, 0x42A1740C, 0x0AD643C1, 0x240AFCEF, + 0x8F200500, 0x843E2105, 0x26144620, 0x70022040, + 0x180860F8, 0xF20B0502, 0x2011081D, 0x00510E19, + 0x75021E00, 0x004E8000, 0x1E00F013, 0x80007502, + 0xF00F0033, 0x20510813, 0x00110E0F, 0x75021E00, + 0x00348000, 0x1E00F005, 0x80007502, 0x242F004F, + 0x250A0507, 0x245F0400, 0x20540140, 0x78300C81, + 0x02822845, 0x209E4040, 0x60380DBF, 0x014741C3, + 0x7B100005, 0xFCEF0A5A, 0x4062750C, 0x0946702C, + 0x1A00FDEF, 0x71262043, 0x0448202F, 0x061E7414, + 0x40C3FFC5, 0x12D88000, 0x00431800, 0x78E0C7D4, + 0x88606038, 0xA8607B45, 0x0083104B, 0x184B7B45, + 0x109600C2, 0x7B450083, 0x00C21896, 0x008310E1, + 0x7FE07A65, 0x008218E1, 0x2482C3EA, 0x266F3206, + 0xC0801243, 0xFF2F0812, 0x10901600, 0x800140C3, + 0x88404E77, 0x7A058813, 0x30811403, 0x30801416, + 0x78477825, 0x01BE080B, 0x0C2E700C, 0x256F03C0, + 0x150016C3, 0x081110C0, 0xC0800032, 0x0DAAD913, + 0xDAF3FB6F, 0x3BC02456, 0xFD6F0D16, 0x20D02053, + 0x3BC02456, 0x02A00946, 0xC080D90B, 0xDA45D910, + 0xFFEF0F72, 0x30112440, 0x3BC02456, 0x02A0092E, + 0x2456D946, 0x09263BC0, 0xD94702A0, 0x3BC02456, + 0x02A0091A, 0x2456D948, 0x09123BC0, 0xD94902A0, + 0x3BC02456, 0x02A00906, 0xCA0ED94A, 0x47CB704C, + 0x12208000, 0x00050A31, 0x2B01205F, 0x0F832232, + 0x04788000, 0x79557322, 0x673F7144, 0xAB208F28, + 0x1B968F2A, 0x8F290042, 0x00421B4B, 0x1BE18F2B, + 0xF1E70042, 0x3BC22456, 0x712CC080, 0x08BEDBFF, + 0x708C0460, 0xD910C080, 0xFB6F0CFE, 0x8D00DABC, + 0x005E0815, 0x08118E00, 0xC080017F, 0x0ED6D910, + 0xDA40FFEF, 0x02A0088A, 0x3BC02456, 0x3BC02456, + 0xFD6F0D66, 0xC027D910, 0x017F0819, 0xD91CC080, + 0xFFEF0EB2, 0x2456724C, 0x0D4E3BC0, 0xD91CFD6F, + 0x3BC22456, 0x702CC080, 0x0862DBFF, 0x708C0460, + 0x080F8D00, 0x8E00005E, 0x0ADCB8E5, 0x08A2FEC1, + 0x0A8EFCCF, 0x8D00FACF, 0xF29EB8E1, 0xB8E58E00, + 0x096AF49A, 0x0882FD8F, 0xD8100280, 0x0FC2D940, + 0xDA0FFB2F, 0x762C700C, 0xFB2F0ED6, 0x8F20714C, + 0x0582219F, 0x100017BC, 0x88216038, 0x00DF090D, + 0x20538814, 0xF23580FE, 0x2400702C, 0x00003F80, + 0x087E012C, 0xDA4BFA6F, 0x3A002456, 0x02A00816, + 0x00831800, 0x0B56700C, 0x712CFB2F, 0xFACF0A22, + 0x02800826, 0x752C700C, 0xFB2F0E86, 0x40C3714C, + 0x3A980000, 0x00600C4E, 0x0D0A742C, 0x710C0120, + 0x3F802400, 0x012C0000, 0x02800966, 0x000340C3, + 0x0C320D40, 0xD9080060, 0x01200D5A, 0xD810710C, + 0x0F2E702C, 0xDA0FFB2F, 0x762C700C, 0xFB2F0E42, + 0x700C714C, 0x704CD932, 0x708C706C, 0x0B3E73AC, + 0x70CCFB2F, 0xD933700C, 0x706CDA20, 0x73AC708C, + 0xFB2F0B2A, 0x700C70CC, 0x0E16762C, 0x714CFB2F, + 0xD938D811, 0xFB2F0EEA, 0x700CDA0F, 0x0E02D907, + 0x714CFB2F, 0xD930700C, 0x706C704C, 0x73AC708C, + 0xFB2F0AFA, 0x700C70CC, 0x704CD931, 0x708C706C, + 0x0AEA73AC, 0x70CCFB2F, 0x762C700C, 0xFB2F0DD2, + 0x0F42714C, 0x700C0240, 0xFB2F0A82, 0x0FC2712C, + 0xF027FD8F, 0xDA20D825, 0x706CB89F, 0x70CC708C, + 0x881B8820, 0xD90B7825, 0x00452053, 0xFB2F0AAE, + 0x700C700C, 0x724CD928, 0x708C706C, 0x0A9E73AC, + 0x70CCFB2F, 0xD907700C, 0x706CDA1E, 0x70AC708C, + 0xFB2F0A8A, 0x700C70CC, 0xFB2F0A32, 0x702C712C, + 0x70441E00, 0xC200901F, 0x70801600, 0x00968000, + 0x011E0815, 0xB802C808, 0x0F802005, 0xC0049007, + 0x00451800, 0x900840C3, 0xB02001B8, 0x1CC3266F, + 0x8E00B036, 0xF01AE89E, 0x1600E908, 0x80007080, + 0xE88B0040, 0xF011710C, 0x70801600, 0x00258000, + 0x700C7014, 0x710CF209, 0x0A327838, 0x780FFD6F, + 0xFB8F0986, 0x68218F00, 0x792FAF20, 0x809409CD, + 0xFD6F0A1A, 0x70AD730C, 0x8E20B7A0, 0x0C82E984, + 0x8E200240, 0x900740C3, 0xB0A0C2CC, 0xE989B0A2, + 0x71001600, 0x00108000, 0x09F07114, 0x0F820242, + 0x08DAFF0F, 0xC7CAFD8F, 0x78E07EE0, 0x7FE0700C, + 0x00C420AB, 0x1CFCC2FA, 0xC1A2B6C8, 0xC8084608, + 0x006E41C3, 0xB8020002, 0x0F802005, 0x200C900C, + 0x78BD90A0, 0x70901600, 0x00048000, 0x004F2044, + 0x10432544, 0x42E1D80A, 0xFCAF0E36, 0x20534078, + 0xC04020C0, 0xC200EF8A, 0x006F41C3, 0x0E220001, + 0xD80AFCAF, 0x000003E5, 0xB802C808, 0x0F802005, + 0x140C9000, 0x30310821, 0x01131000, 0x10C02D41, + 0x1AC125AD, 0x0F832084, 0x60B8742C, 0x0380205A, + 0xF004E038, 0x732CD870, 0x6038710E, 0x1E007017, + 0x90037404, 0x1E00D878, 0x90077404, 0x02F4F87C, + 0xC0410022, 0x02EC70D5, 0x710C0021, 0x01000AA6, + 0x45CBC808, 0xC400900F, 0x14CE2550, 0xB802726D, + 0x03412005, 0x190078C5, 0x180002C4, 0x099E02C4, + 0xD81E0060, 0x36091208, 0x702E700D, 0x70CC71EC, + 0x00100F11, 0x70801600, 0x00258000, 0xF053E888, + 0x70801600, 0x00408000, 0x001008A7, 0x00052752, + 0x3000264A, 0x33002E40, 0x70C0704C, 0x200572EF, + 0x0E090244, 0xEAB830D1, 0x31310E17, 0x8080270B, + 0x1600F207, 0x80007081, 0x095D0025, 0x0E1B0050, + 0x220B3131, 0xF2098140, 0x70811600, 0x00408000, + 0x0051090F, 0x2678F020, 0x794B3141, 0x215AF41C, + 0x41C32503, 0x12E08000, 0x71266A94, 0x43C36179, + 0x0FF10000, 0x43C3B166, 0x05248000, 0x1908639A, + 0x82E30003, 0x22058241, 0xA1E40102, 0x6462A141, + 0xA1407A05, 0x31FF278D, 0x2640714C, 0x0E79305E, + 0x46C3B194, 0x70000000, 0x193E238D, 0x40C370EC, + 0x12D98000, 0x00841000, 0x43C371CC, 0x05448000, + 0x022E0C6B, 0x72AC700C, 0x00072E00, 0x02002014, + 0x244AB80C, 0x20057180, 0x4308025F, 0x3000264A, + 0x088020A8, 0x310C2E40, 0x89086399, 0x8000270B, + 0x215AF218, 0x40C32502, 0x12E08000, 0x60587126, + 0x000042C3, 0xB0460FF1, 0x81218143, 0x07C12105, + 0x01821808, 0x6461A021, 0x02C12105, 0xA020A044, + 0x305E2640, 0x04BF258D, 0x7105710C, 0x91140895, + 0x41C34022, 0x00010069, 0x024120BC, 0xFA6F094A, + 0x21424222, 0x42D3A03C, 0x12E48000, 0x2344F20B, + 0x22402042, 0xD9F12140, 0x014020A8, 0x1814A822, + 0x706D0092, 0x79EDDFF1, 0xFE2F0862, 0x71654022, + 0x14310B11, 0x702C4022, 0x01A00A56, 0x706DDA10, + 0x7F0D6F01, 0x94120FE3, 0x702C4022, 0x01A00A42, + 0x21424261, 0xF20DA03C, 0x2006710C, 0x224004C1, + 0x20A82140, 0x180201C0, 0x181403C3, 0x706D0052, + 0x4022DF0F, 0xFE2F0816, 0x716541E1, 0x14310B11, + 0x712C4022, 0x01A00A0A, 0x706DDA10, 0x7F0D6F09, + 0x9C3F278C, 0x4022F62F, 0x09F6712C, 0x426101A0, + 0x2030098F, 0x230A708E, 0x702F3440, 0x350F215A, + 0x23D32200, 0x20D51308, 0x23F10D1F, 0x20D61309, + 0x14822730, 0xDB0F740C, 0x006441C3, 0x0B720003, + 0x240AFCAF, 0x268C0580, 0xF40DAC7F, 0x14822730, + 0x43A2740C, 0x006541C3, 0x0B560003, 0x248AFCAF, + 0x26000C7F, 0x27302540, 0x28441482, 0x13040097, + 0x252F2080, 0xE80705C5, 0x41C3740C, 0x00040066, + 0x740CF005, 0x006741C3, 0x43A20004, 0xFCAF0B22, + 0x0580240A, 0x238D7127, 0x1B06313F, 0x402225C2, + 0x04200BE2, 0xC808702C, 0x2005B802, 0x78C50341, + 0x05041900, 0x05041800, 0x0120084A, 0xC808710C, + 0x7D05B802, 0x1D007E05, 0x1E001045, 0xF0061045, + 0x74041E00, 0xC02C9003, 0x0260083E, 0x4008710C, + 0x00200ECA, 0x45CBD80D, 0xE008900F, 0x255070CD, + 0xB5C014CB, 0x13841B00, 0x00200E4E, 0x1D00C001, + 0x08231404, 0x1B003031, 0xC8081404, 0x40C36832, + 0xC400900F, 0x00022105, 0x7825B8B3, 0xB0C0B2C0, + 0x40C3F00C, 0xC02C9003, 0xB8AFB0C0, 0x70451E00, + 0x802C9001, 0x00451800, 0x1E0070CD, 0x90037384, + 0x1E00D878, 0x90077384, 0x0FCEF87C, 0x40010220, + 0x45CBD820, 0x03E09008, 0x00200DEE, 0x10451D00, + 0x0DE6D820, 0xB5C00020, 0xD80AC200, 0x007041C3, + 0x0A3E0002, 0x4303FCAF, 0x1404C0A2, 0xC6DA341B, + 0x1CFCC2F8, 0x2482B6C8, 0x44303902, 0xB910D9AB, + 0x30001C84, 0x4670740C, 0xFCAF0A16, 0xD9204550, + 0x89A0B99F, 0x11002553, 0x8961A900, 0x01002353, + 0xA9017BA5, 0x813E2353, 0x808C11F7, 0x11002453, + 0x800219F7, 0x808211F8, 0x01002253, 0x800219F8, + 0x1901F405, 0x19000043, 0x7A850043, 0x813E2253, + 0x19F8F405, 0x19F78043, 0x0E1D8043, 0x740C2030, + 0x20710E23, 0x09BAD92B, 0xB912FCAF, 0x712E700F, + 0xF01070EE, 0x09AAD9AD, 0xB910FCAF, 0x710F70EE, + 0xD957F007, 0xFCAF099A, 0x71EEB911, 0x722E700F, + 0xBD9FDDEE, 0x15328DC0, 0x70D5109B, 0x0ECA40D1, + 0x23CA03A0, 0x1C8C3022, 0xE8123000, 0x740CD9AF, + 0xFCAF096E, 0xD825B910, 0x8840B89F, 0x00412244, + 0xA8204250, 0x274488FB, 0xA83B1041, 0x740CD90B, + 0xFCAF094E, 0x8D00B914, 0x120C4182, 0x20793085, + 0x14840006, 0x42A23000, 0x0D8A43C2, 0x240AFBEF, + 0x160006C0, 0x80007080, 0x081B000B, 0xD9B1003E, + 0x091E740C, 0xB910FCAF, 0x41A240E2, 0xFDAF0C7A, + 0x20054203, 0x148C35C0, 0x1C883001, 0x78253000, + 0x0051085F, 0xE8AD8D00, 0x740CD959, 0xFCAF08F2, + 0x2479B911, 0x40E22003, 0x42A2702C, 0x0440240A, + 0x01200EBE, 0x46084370, 0x40E2E88A, 0x42A2712C, + 0x0EAE4362, 0x240A0120, 0x46080440, 0x740CD9B3, + 0xFCAF08BE, 0x40E2B910, 0x0C1E41A2, 0x4203FDAF, + 0xFE2F0DE6, 0x709640C1, 0xFB2209A4, 0x0F1740A2, + 0x740C2030, 0x089AD92D, 0xB912FCAF, 0x04800AE6, + 0xD9B5F057, 0xFCAF088A, 0x120CB910, 0x24793081, + 0x20782003, 0x40032004, 0x04A00806, 0xCA0C42A2, + 0x060A212F, 0x00002078, 0x084D7825, 0xD840003F, + 0xB89F700E, 0x88C0722E, 0x808010E5, 0x0E237E05, + 0x4002142E, 0x70931600, 0x00048000, 0xFBEF0C5A, + 0x4200712C, 0x4162700C, 0xFCEF0B62, 0x218D4302, + 0x710E2C7F, 0x740CD95B, 0xFCAF0826, 0x09DEB911, + 0x40A2FB2F, 0x0343206F, 0x10C29020, 0x09330700, + 0x0C2F0004, 0x16002011, 0x80007100, 0x09230188, + 0x0E9E0005, 0x2005FC8F, 0x08170600, 0xD9B70071, + 0x0FEE740C, 0xB910FC6F, 0xFB2F0ABE, 0x8D0040A2, + 0xF47C7114, 0x7014CA06, 0x700CF278, 0x20300C15, + 0x30001C90, 0xFC8F0E6A, 0x710CE804, 0x30001C90, + 0x708E1600, 0x12228000, 0x16007DCF, 0x80007080, + 0x08C51223, 0x40C30344, 0x12D98000, 0x08B58800, + 0x40A2036E, 0x0260092E, 0x702E41A1, 0x30001CA0, + 0x300014A0, 0x046E0897, 0x706E720C, 0x30001C94, + 0xB89FD825, 0x881B8820, 0x710C7905, 0x04C02800, + 0x200FB802, 0x782B04C0, 0x1490F231, 0x40C33010, + 0x28F00000, 0x231F791B, 0x201F2002, 0xB8222041, + 0x436278AA, 0x6219623A, 0x209A4022, 0x704C0184, + 0x41E26038, 0x800070C3, 0x1C981A3C, 0x24793000, + 0x1C9C2000, 0x14983000, 0x0B623000, 0x149C0460, + 0x14983004, 0x41E23000, 0x3004149C, 0x0B4E714C, + 0x43620460, 0x710E7016, 0x1494F3D3, 0x716E3000, + 0x08817704, 0x1C948031, 0x71263000, 0xA2940965, + 0xF19C71C5, 0x0100099A, 0x3000148C, 0x026E7014, + 0x0C0A0001, 0x24790380, 0x1C05200E, 0x40633002, + 0x42C141E2, 0xFE2F0A3A, 0xD917C380, 0x0EC2740C, + 0xB913FC6F, 0x30001488, 0x256FE81A, 0x700C1243, + 0x10901500, 0xFBEF0AC2, 0x4200712C, 0x4102700C, + 0xFCEF09CA, 0x8DA0706C, 0x0AAE710C, 0x712CFBEF, + 0x700C4200, 0x09B641A1, 0x716CFCEF, 0x2744DD40, + 0xBD9F1080, 0xAD0070F6, 0x20802244, 0x90021DE5, + 0x09DAF27E, 0x710CFD2F, 0x800046CB, 0x8E221B3C, + 0x140C714C, 0x782A3100, 0x61199620, 0x0EB6710C, + 0x21ADFA6F, 0x40C30883, 0x25788000, 0x140C8842, + 0x7A2A3101, 0x710C9020, 0x724C6159, 0xFA6F0E96, + 0x088321AD, 0xFD2F0996, 0x40C3720C, 0x2FB48000, + 0x140C8842, 0x7A2A3101, 0x710C9020, 0x714C6159, + 0xFA6F0E72, 0x088321AD, 0x800040C3, 0x884239F0, + 0x3101140C, 0x90207A2A, 0x6159710C, 0x0E56724C, + 0x21ADFA6F, 0x09560883, 0x730CFD2F, 0x3085120C, + 0x14844182, 0x42A23000, 0x708C43C2, 0xFBEF0A26, + 0xD9B971CC, 0xB910740C, 0x0DC6ADE0, 0x1DE5FC6F, + 0x40C39482, 0x12228000, 0x008810B7, 0x88608841, + 0x01007350, 0x0835000D, 0x244A10EE, 0x700C7280, + 0x050020A8, 0x209A68A1, 0x231A0184, 0x00000F81, + 0x60380A3C, 0x800041C3, 0x603C442C, 0x60D860D1, + 0x8802B420, 0x40A1AC02, 0xF1E47164, 0x3085120C, + 0x14844182, 0x42A23000, 0x708C43C2, 0x09B671CC, + 0x700EFBEF, 0x740CD95D, 0xADE0B911, 0xFC6F0D52, + 0x94821DE5, 0x3081120C, 0x42A24003, 0x0CD243C1, + 0x708C0460, 0x212FCA0C, 0x2078060A, 0x78250000, + 0x001F0845, 0x15E58DE0, 0x72AD9080, 0x0F237F05, + 0x4002142E, 0x708E1600, 0x00048000, 0xFBEF092A, + 0x4200712C, 0x41C1700C, 0xFCEF0832, 0x258D4302, + 0x710E1C7F, 0x740CD9BB, 0xFC6F0CF6, 0x0EAEB910, + 0x40A2FAEF, 0x0343206F, 0x10C29020, 0x09390700, + 0x0C350004, 0x16002011, 0x80007100, 0x09290188, + 0x0B6E0005, 0x2005FC8F, 0x081D0600, 0xD92F0071, + 0x0CBE740C, 0xB912FC6F, 0xFAEF0F8E, 0xF00440A2, + 0x04400F02, 0x30001488, 0x256FE819, 0x700C1243, + 0x08B68DC0, 0x712CFBEF, 0x710C4200, 0x0FBE41C1, + 0x706CFCAF, 0x710C8DA0, 0xFBEF089E, 0x4200712C, + 0x41A1710C, 0xFCAF0FA6, 0x2480716C, 0x14043902, + 0xC6D8341B, 0x68614200, 0x7054CA08, 0x20AA7B19, + 0x081700C4, 0x23CA003F, 0x720C0021, 0x00C420AB, + 0x20AB710C, 0x0B1100C4, 0x16000415, 0x901C7100, + 0xF01B0490, 0x010420AA, 0x0A1B7A12, 0x24AA00E5, + 0x21AA1144, 0x08FF0104, 0x4B508044, 0x114424AA, + 0x6078F002, 0x010421AA, 0x20E17110, 0x22AA07C6, + 0x0CF50144, 0x7EE09080, 0x0443226F, 0x8A004300, + 0x0A0F239A, 0x00802079, 0x12FE6822, 0x78398100, + 0x70002E05, 0x4240000F, 0xFFEF077D, 0x00002B05, + 0x0826C0F1, 0x0F720000, 0xC0D1FFCF, 0x78E07EE0, + 0x4328C0F1, 0x00200812, 0x7071702C, 0x7FE0C0D1, + 0x02C520CA, 0x0343226F, 0x000370D3, 0x92600D41, + 0x0F8628C5, 0x86A00001, 0x00C620DA, 0x052628C5, + 0x00C520DA, 0x0F8528C5, 0x8480001E, 0x69818A62, + 0x71046078, 0x00C02805, 0x800043C3, 0x8B601138, + 0x12FBEB0D, 0x0A178082, 0x43C300DF, 0x121E8000, + 0xEA058B40, 0x8B817A2C, 0x74107C4C, 0x20CA7FE0, + 0x78E0030D, 0x0DBAC2EE, 0x2053FDCF, 0x206D00C1, + 0x50160900, 0x43D3782A, 0x003F8000, 0x13005015, + 0x13012080, 0xE9112081, 0x029741C3, 0x083A0000, + 0x2079FA2F, 0xCA140000, 0x20811300, 0x206CB802, + 0x61190080, 0xD953F011, 0x00002078, 0xFA2F081A, + 0x1600B913, 0x80007081, 0xC8060024, 0x0091080B, + 0x781DC805, 0x7A2F5015, 0x807E2153, 0x00832A41, + 0x23C0BA23, 0x21530062, 0x1A028080, 0x22C03002, + 0xD80A0062, 0x029941C3, 0x1A010002, 0x0AD230C2, + 0x1A00FC6F, 0x226F3082, 0x41C320C3, 0x0006029B, + 0x20801200, 0xD87FB8E2, 0x01E220CA, 0x30021A03, + 0x1205D80A, 0x12002486, 0x120C2107, 0x120A2085, + 0x13012104, 0x0A9A2083, 0x121FFC6F, 0x121F2082, + 0xB8E02080, 0xDE66F2AB, 0x02A447CB, 0xBE9F0005, + 0x41E1D80A, 0x948616FC, 0x948516FC, 0x10841600, + 0x908316FC, 0x908216A6, 0xFC6F0A66, 0x2640BAC3, + 0x8E6C160D, 0x10861500, 0x1401274F, 0x908515FC, + 0x15F8D80A, 0x16A69084, 0x0A469082, 0xBAC3FC6F, + 0x14102540, 0x10008D64, 0x274F2086, 0x10FC144D, + 0xD80AA085, 0xA08410F8, 0x16A641A1, 0x0A229082, + 0xBAC3FC6F, 0x240F2040, 0x20831004, 0x14861710, + 0x1401254F, 0x908517EC, 0x17E8D80A, 0x16A69084, + 0x09FE9082, 0xBAC3FC6F, 0x948617FC, 0x1700D80A, + 0x41C31085, 0x000502A8, 0x908417FC, 0x17F84030, + 0x16A69083, 0x09DA9082, 0xBAC3FC6F, 0x150D2740, + 0x15008F68, 0x204F1086, 0x15FC2401, 0xD80A9085, + 0x908415F8, 0x908216A6, 0xFC6F09B6, 0x2540BAC3, + 0x8D64140F, 0x10861700, 0x2441204F, 0x908517FC, + 0x17F8D80A, 0x16A69084, 0x09969082, 0xBAC3FC6F, + 0x120D2740, 0x15008F64, 0xD80A1084, 0x908216A6, + 0x02AB41C3, 0x097A0003, 0xBAC3FC6F, 0x10861510, + 0x2481204F, 0x1085150C, 0x1508D80A, 0x8D641084, + 0x908216A6, 0xFC6F095A, 0x151CBAC3, 0xD80A1085, + 0x10841518, 0x02AD41C3, 0x8D740004, 0x908216A6, + 0xFC6F093E, 0x121FBAC3, 0xB8E12080, 0xDE67F2A8, + 0x02AE45CB, 0xBE9F0005, 0x41A1D80A, 0x948616FC, + 0x948516FC, 0x14841618, 0x908316E4, 0x9082168D, + 0xFC6F090E, 0x16FCBAC3, 0x254F9486, 0x16001401, + 0xD80A1085, 0x908416FC, 0x908316F8, 0x90821691, + 0xFC6F08EE, 0x2640BAC3, 0x8E68150D, 0x10861500, + 0x15FCD80A, 0x41C39085, 0x000502B0, 0x908415F8, + 0x16914030, 0x08CA9082, 0xBAC3FC6F, 0x140F2540, + 0x17008D64, 0x204F1086, 0x17FC2401, 0xD80A9085, + 0x908417F8, 0x90821691, 0xFC6F08A6, 0x2740BAC3, + 0x8F64140D, 0x10861500, 0x2441204F, 0x908515FC, + 0x15F8D80A, 0x41309084, 0x90821691, 0xFC6F0882, + 0x2540BAC3, 0x8D64140F, 0x10861700, 0x2401214F, + 0x908517FC, 0x17F8D80A, 0x16919084, 0x08629082, + 0xBAC3FC6F, 0x140D2740, 0x15088F64, 0x204F1486, + 0x15F4248F, 0xD80A9085, 0x908415F0, 0x169141E1, + 0x083E9082, 0xBAC3FC6F, 0x10841500, 0x15FCD80A, + 0x41C39083, 0x000302B5, 0x90821691, 0xFC6F0822, + 0x1510BAC3, 0x274F1086, 0x150C1441, 0xD80A1085, + 0x10841508, 0x16918D64, 0x08069082, 0xBAC3FC6F, + 0x1085151C, 0x1518D80A, 0x41C31084, 0x000402B7, + 0x16918D74, 0x0FEA9082, 0xBAC3FC2F, 0x20801301, + 0xF2ABB8E0, 0xD80ADE68, 0x41C3BE9F, 0x000502B8, + 0x16FC4030, 0x16FC9486, 0x16009485, 0x16FC1084, + 0x16A49083, 0x0FBA9082, 0xBAC3FC2F, 0x160F2640, + 0x17008E6C, 0x204F1086, 0x17FC2401, 0xD80A9085, + 0x908417F8, 0x908216A4, 0xFC2F0F96, 0x2740BAC3, + 0x8F64140D, 0x10861500, 0x2441204F, 0x908515FC, + 0x15F8D80A, 0x41309084, 0x908216A4, 0xFC2F0F72, + 0x2540BAC3, 0x8D64140F, 0x14861710, 0x2401214F, + 0x908517EC, 0x17E8D80A, 0x16A49084, 0x0F529082, + 0xBAC3FC2F, 0x948617FC, 0x2481204F, 0x10851700, + 0x17FCD80A, 0x40309084, 0x908317F8, 0x908216A4, + 0xFC2F0F2E, 0x2740BAC3, 0x8F68150D, 0x10861500, + 0x2401204F, 0x908515FC, 0x15F8D80A, 0x16A49084, + 0x0F0E9082, 0xBAC3FC2F, 0x140F2540, 0x17008D64, + 0x204F1086, 0x17FC2441, 0xD80A9085, 0x908417F8, + 0x908216A4, 0xFC2F0EEA, 0x2740BAC3, 0x8F64120D, + 0x10841500, 0x16A4D80A, 0x41C39082, 0x000302BF, + 0xFC2F0ECE, 0x1510BAC3, 0xD80A1086, 0x1085150C, + 0x02C041C3, 0x15080005, 0x8D641084, 0x908216A4, + 0xFC2F0EAE, 0x151CBAC3, 0xD80A1085, 0x10841518, + 0x02C141C3, 0x8D740004, 0x908216A4, 0xFC2F0E92, + 0x1301BAC3, 0xB8E12080, 0xDE69F2AA, 0x02C245CB, + 0xBE9F0005, 0x41A1D80A, 0x948616FC, 0x948516FC, + 0x14841618, 0x908316E4, 0x9082168B, 0xFC2F0E62, + 0x16FCBAC3, 0x254F9486, 0x16001401, 0xD80A1085, + 0x908416FC, 0x908316F8, 0x9082168F, 0xFC2F0E42, + 0x2640BAC3, 0x8E68150D, 0x10861500, 0x02C447CB, + 0x15FC0005, 0xD80A9085, 0x908415F8, 0x168F41E1, + 0x0E1E9082, 0xBAC3FC2F, 0x14102540, 0x10008D64, + 0x274F2086, 0x10FC1401, 0xD80AA085, 0xA08410F8, + 0x9082168F, 0xFC2F0DFA, 0x2040BAC3, 0x10042411, + 0x11002083, 0xBF912086, 0xA08511FC, 0x11F8D80A, + 0x41E1A084, 0x9082168F, 0xFC2F0DD6, 0x2140BAC3, + 0x1104240D, 0x15002083, 0x274F1086, 0x15FC1401, + 0xD80A9085, 0x908415F8, 0x9082168F, 0xFC2F0DB2, + 0x2540BAC3, 0x8D64140F, 0x14861708, 0x02C845CB, + 0x17F40005, 0xD80A9085, 0x908417F0, 0x168F41A1, + 0x0D8E9082, 0xBAC3FC2F, 0x10841700, 0x17FCD80A, + 0x41C39083, 0x000302C9, 0x9082168F, 0xFC2F0D72, + 0x1710BAC3, 0x254F1086, 0x170C1441, 0xD80A1085, + 0x10841708, 0x168F8F64, 0x0D569082, 0xBAC3FC2F, + 0x1085171C, 0x1718D80A, 0x41C31084, 0x000402CB, + 0x168F8F74, 0x0D3A9082, 0xBAC3FC2F, 0x71001600, + 0x02009030, 0xB82271ED, 0x10002706, 0x30021A08, + 0x21001200, 0x0F85082B, 0x0A6B0000, 0x244AC808, + 0x68527200, 0x20A8700C, 0x22050340, 0x70C30001, + 0x40000000, 0x0F812105, 0x004C9038, 0x0BAAB1E0, + 0x46CBFE0F, 0xC1DC901F, 0x1443256F, 0x73C41E00, + 0x04A0901C, 0x73C41E00, 0xC294900B, 0x10051E00, + 0x41C3740C, 0x000102CE, 0xFC2F0CC6, 0x0BD68D40, + 0x8D00FAAF, 0x02CF41C3, 0x0CB60000, 0x750CFC2F, + 0x120AB6F2, 0x08152100, 0x16000050, 0x80007080, + 0xB8E40004, 0x010109F4, 0x70801600, 0x01148000, + 0x0CEC7014, 0x16000182, 0x80007080, 0x205300F4, + 0xF20B80FE, 0x813E206C, 0x208CF207, 0xF7068FC2, + 0x1A20B825, 0xC6CE301C, 0x301D1A20, 0x78E0C6CE, + 0x0E3EC2E2, 0x40C3FA0F, 0x0BB80000, 0xFFEF0886, + 0x252F702C, 0xF20D9007, 0xD907700C, 0x706C704C, + 0x73AC708C, 0xFA6F0F96, 0x258C70CC, 0xD8801E3F, + 0x704CD907, 0x708C706C, 0x0F8273AC, 0x70CCFA6F, + 0x0F2A700C, 0x712CFA6F, 0x78E0C6C2, 0x1CFCC2FA, + 0x2482B6C8, 0xC0413C09, 0x70C01600, 0x001F8000, + 0x00320817, 0x0E06DE51, 0xC0010020, 0x3C092480, + 0x341B1404, 0x740CC6DA, 0x0BE6BE13, 0x41C1FC2F, + 0x3F002456, 0x70901600, 0x12238000, 0x708D1600, + 0x12228000, 0x0BEA702C, 0xDA90F9AF, 0x3A802456, + 0x0BDE702C, 0xDA90F9AF, 0x70921600, 0x001F8000, + 0x21402244, 0x1401264F, 0xF9EF08AE, 0x01402079, + 0x20402244, 0x20912244, 0x2244C044, 0xC0432100, + 0x0442242F, 0x740CC303, 0x41C3C204, 0x0003028A, + 0xFC2F0B7E, 0xC808BB22, 0x2005B802, 0x90380F80, + 0x90000008, 0xB8C2C049, 0x0050080D, 0x80B10871, + 0xF003720C, 0xC045710C, 0xC04278BB, 0x2014710C, + 0x226D0400, 0x41C32902, 0x0001028B, 0x740CC048, + 0x0B3E70ED, 0x4450FC2F, 0x01A00B2E, 0xC001C001, + 0x01E00CC2, 0x2F4079EF, 0x45101310, 0x0DCB70AD, + 0x2D40236E, 0x275A120E, 0x26051500, 0x726E140E, + 0x78B4704E, 0x800170C3, 0x18004DAC, 0x43420405, + 0x238C2200, 0x0201239F, 0xC8084CAA, 0x1488275A, + 0x42C37905, 0x00009004, 0x2455B902, 0x79453C0B, + 0x10CB2300, 0x01061100, 0x2300C18C, 0x6179120B, + 0x14032440, 0x134B2314, 0x71017865, 0x1B00B802, + 0x78451184, 0x100079B4, 0x740C0105, 0x01441900, + 0x028C41C3, 0x42420005, 0x0AA643E1, 0x44A1FC2F, + 0x20510C41, 0x000040C3, 0x271A0A3C, 0xB8021001, + 0x2000221F, 0x40A16119, 0x0184209A, 0xC8086119, + 0x210078C5, 0x80000F82, 0xB8021B40, 0x800071C3, + 0x20056D20, 0x90040F80, 0x90000320, 0xB100B200, + 0x2BFE238D, 0x71A5714E, 0x92540D37, 0x0F2371E5, + 0x244A9114, 0xD8987140, 0x903B43DB, 0x20A8C000, + 0x20050200, 0x740406C1, 0x00C51900, 0x20B10C11, + 0x20412478, 0x000047CB, 0xF00586B0, 0x000047CB, + 0x2940265C, 0xE90520C0, 0x000147CB, 0x20523694, + 0xC04A0100, 0xFCAF0DFA, 0xDE25700C, 0xBE9F716E, + 0x029040DB, 0xC8080005, 0x2005B802, 0x903B0F80, + 0x0B11C008, 0x228A2071, 0x18002802, 0xF0060045, + 0x2902228A, 0x01451800, 0x30171428, 0xC808708E, + 0x7140244A, 0x20A84242, 0x22050440, 0xE2100001, + 0x2105B902, 0x210506C3, 0x903B0F81, 0x1B00C004, + 0x190005C4, 0x160005C4, 0x80007080, 0x08110001, + 0xDD6400BF, 0x708D1600, 0x01208000, 0xE88BC003, + 0xD80FC201, 0x716C742C, 0x70AC44A1, 0xFB6F0DD6, + 0xC00470CC, 0xC201E88A, 0x742CD80F, 0x44A1706C, + 0x0DC270AC, 0x70CCFB6F, 0x70AE720C, 0xC047C046, + 0x8E3B8E00, 0x710C7905, 0x05402800, 0x200FB802, + 0x782B0540, 0x740CF2A6, 0x028D41C3, 0x42620003, + 0x093E43E2, 0x240AFC2F, 0x16000540, 0x80007091, + 0x16001222, 0x80007080, 0x210C1223, 0x0124A000, + 0x40C3000D, 0x12D98000, 0x20118800, 0xF2888440, + 0x0AA2C001, 0x212F01E0, 0x700E0447, 0x2448262F, + 0xC00BC04B, 0x042E08F3, 0x1408252F, 0xE8ABC004, + 0xE8B4C003, 0x41C240A2, 0x7F6042A1, 0x4118706C, + 0x4103740C, 0x43A24222, 0x0400240A, 0x05C0250A, + 0xFC2F08CE, 0x0640260A, 0x41C240A2, 0x7F6042A1, + 0x4508716C, 0x3401204F, 0x4222740C, 0x240A43A2, + 0x250A0400, 0x08AA05C0, 0x46A1FC2F, 0x164D2509, + 0x40A2F01F, 0x42A141C2, 0x706C7F60, 0x740C4508, + 0x028E41C3, 0xF00C0005, 0x41C240A2, 0x7F6042A1, + 0x4508716C, 0x41C3740C, 0x0005028F, 0x43A24222, + 0x0400240A, 0x05C0250A, 0xFC2F0866, 0x43A246A1, + 0x248C215A, 0x0201239F, 0x3A802456, 0x60986078, + 0x04012014, 0x3F002456, 0x91406078, 0x03650A17, + 0x20146098, 0x42A10400, 0x1800B1A0, 0x40E205C4, + 0x20F4F003, 0xC2400400, 0x0008272F, 0x41C3740C, + 0x00070292, 0x432242A2, 0x0400240A, 0x05C0250A, + 0xFC2F080E, 0x710646A1, 0xA254080B, 0xF16B7126, + 0x71AEC007, 0x70147704, 0xF54CC047, 0x274C71E6, + 0x061EA800, 0x8E00FFC5, 0x79058E3B, 0x2800710C, + 0xB8020500, 0x0500200F, 0xF24C782B, 0x70901600, + 0x12228000, 0x70801600, 0x12238000, 0x04240877, + 0x40C34082, 0x12D98000, 0x08678800, 0x212F042E, + 0x09420407, 0xC00101E0, 0x2495205A, 0x70AD4610, + 0x236E0E49, 0x2500210A, 0x3A802456, 0x2201219F, + 0x70A27022, 0x034020F4, 0x700CE88A, 0x029341C3, + 0x42820003, 0x0C824302, 0x44A1F9AF, 0x2500205A, + 0x200078B4, 0x80010F81, 0x24564DAC, 0x70223F00, + 0x20F470A2, 0xB1000340, 0x0DB971A5, 0x71069254, + 0xC301F1C2, 0x000042C3, 0x0D9EBA68, 0x414203E0, + 0x718EC006, 0x08537704, 0xC0468031, 0x230CC005, + 0x0536A000, 0x7166FFE5, 0xC00170CD, 0x01E008B6, + 0x2E4079CF, 0x43101311, 0x0B7970AD, 0x2D40236E, + 0x704C1210, 0x24502005, 0x4340724E, 0x148C265A, + 0x0201239F, 0x3C002455, 0x04082200, 0x900447CB, + 0x20400000, 0x44A11481, 0x20006078, 0xC808030B, + 0x23F47905, 0xB9021349, 0x190079E5, 0x20400244, + 0x78251401, 0x029441C3, 0xB8020005, 0xC08C7F05, + 0x43C16078, 0x24F4641C, 0xB7001340, 0x24F4740C, + 0x0EAE1345, 0x23F4FBEF, 0x228D1346, 0x714C247F, + 0x0D8B71A5, 0x71C59254, 0x91140E73, 0x0882C001, + 0x712C03A0, 0x7A0FC008, 0x780FC002, 0x00040A29, + 0x6832C808, 0xB8C4C002, 0x7825B80E, 0x0F832005, + 0x00089038, 0xB300C009, 0x7104C002, 0x780FC042, + 0x80050AE5, 0x70801600, 0x01648000, 0xF42BB8E6, + 0x70801600, 0x001F8000, 0x00FF0839, 0x41C3740C, + 0x00000295, 0xFBCF0E3A, 0x256FC201, 0xD80F1A43, + 0x716C742C, 0xFF6F0BFE, 0x12051D00, 0xD80FC201, + 0x0BF2742C, 0x706CFF6F, 0xB88FD808, 0xF00BB500, + 0x029641C3, 0x0E0A0000, 0x740CFBEF, 0xFAEF0F7A, + 0x020DC001, 0x78E0FFCF, 0x1CFCC2FA, 0xC1BFB6C8, + 0xC8084410, 0x2005B802, 0x90380F80, 0x90000008, + 0x1600C043, 0x80007080, 0xC1030164, 0xC046B9C2, + 0x800040C3, 0x88601222, 0x00700911, 0x72348841, + 0x00220320, 0xF003720C, 0xC044710C, 0xC00671AD, + 0x780D7D54, 0xC0497F7B, 0x88002044, 0xF40EC047, + 0x7140244A, 0x20A8D898, 0x20050280, 0x903B0F81, + 0x7404C000, 0x00C51900, 0x01600D7E, 0xD8254082, + 0x33C7232F, 0x712FB89F, 0x881B8820, 0x20787825, + 0x710400C0, 0x78AFC048, 0x202FC041, 0xC0043647, + 0x02347013, 0x40820025, 0x752CC808, 0x2005B802, + 0x903B0F80, 0x0815C008, 0xC1453071, 0xDEA0712C, + 0x730CB020, 0xF009C040, 0x01451800, 0xDEA4740C, + 0x760CC040, 0x70ADC045, 0x7510C008, 0x000601F2, + 0x2578C007, 0x20791017, 0x27040000, 0x20782017, + 0x27043040, 0x0F1F2017, 0x244A2071, 0xD8987140, + 0x024020A8, 0x0F812005, 0xC000903B, 0x19007404, + 0x08DE0005, 0x710CFCAF, 0x30041400, 0x2347262F, + 0x218AD8C8, 0x43820004, 0x000042C3, 0x250ABA68, + 0x70CC0580, 0x02A0083E, 0xC0064250, 0x800140D3, + 0x08434DAC, 0x244000FF, 0x74AE3B13, 0x2400210A, + 0x41224062, 0xF96F0CB2, 0x2340DA14, 0x258D2513, + 0x21402EBF, 0x14142511, 0xD8C83004, 0x0004218A, + 0x43824242, 0x0580250A, 0x02600FFA, 0xC28B70CC, + 0x42C3F004, 0xBF648000, 0x244A746C, 0x20A87280, + 0x100002C0, 0x12022101, 0x60380500, 0x1802781D, + 0x238C2014, 0x084A0D7F, 0x700CFCAF, 0x0E424082, + 0x702C0360, 0x706E70F6, 0xF28570AE, 0x7140244A, + 0x20A8D998, 0x21050280, 0x903B0F80, 0x7424C000, + 0x04C41800, 0xF07773AE, 0x244AC808, 0x20057140, + 0x41C10342, 0x038020A8, 0x00402205, 0xB802E110, + 0x0F832005, 0xC000903B, 0xC042700C, 0x00051B00, + 0x30041400, 0x142440C1, 0xD9103006, 0x0FFF26BF, + 0x000042C3, 0x43822950, 0x02600F5A, 0x0580250A, + 0x2540203C, 0x26C0200A, 0xC001C04A, 0x04040895, + 0x212FC002, 0x20790402, 0xB9C60000, 0x00922840, + 0x0D524082, 0x702E01A0, 0x230C2840, 0x24055020, + 0x43C11342, 0x00482205, 0x20412044, 0x010B2140, + 0x22C50955, 0x04AE0849, 0x10C12005, 0x903842C3, + 0xB9020000, 0x00892105, 0x11061100, 0x270BC10A, + 0xF216A040, 0x29812140, 0xB9027985, 0x26537A25, + 0x091D00C1, 0x120003F1, 0x0F150107, 0x274000F0, + 0x19000041, 0xB2201184, 0x10051900, 0x7126E310, + 0xF1D87146, 0x7106C002, 0x00002052, 0xF1B7C042, + 0x202F7166, 0x0D1524C7, 0x71A5A405, 0x05CFF106, + 0x7127FFEF, 0x03600D1A, 0xC001712C, 0x06C40827, + 0x6852C808, 0x11002753, 0xB80E71E5, 0x20057845, + 0x90380F81, 0xC0030008, 0x79EFB100, 0x08E9C001, + 0x16008045, 0x80007080, 0x08590164, 0x1600019F, + 0x80007080, 0x083B001F, 0x740C00FF, 0x028641C3, + 0x0ADE0000, 0x256FFBCF, 0xD80F1A43, 0x4282742C, + 0x08A2716C, 0x1D00FF6F, 0xD80F1205, 0x4282742C, + 0xFF6F0892, 0xD808706C, 0xB500B88F, 0x41C3F00A, + 0x00000287, 0xFBEF0AAA, 0x0C1E740C, 0x4082FAEF, + 0x1404C0BF, 0xC6DA341B, 0x200AC2F6, 0x80010F80, + 0x20A78000, 0x200A0849, 0x80010F80, 0x20A78000, + 0x200A0949, 0x80010F80, 0x20A77000, 0x200A0809, + 0x80010F80, 0x20A77000, 0x200A0909, 0x00080F80, + 0x20296000, 0x206F0000, 0x100020C3, 0x701420C0, + 0x000B072C, 0x800047CB, 0x8F00019A, 0x1600E886, + 0x80007080, 0xE812019B, 0x00C420AA, 0x003F0811, + 0x20AB720C, 0x710C00C4, 0x00C420AB, 0x010420AA, + 0x20AA5031, 0x50320144, 0x19C3266F, 0x70451E00, + 0x0080900C, 0x903045CB, 0x16EF03B8, 0x0D4E9481, + 0x950002E0, 0x000041D3, 0x0E962503, 0x1E00FC6F, + 0x0E961444, 0x41C30080, 0x00000325, 0xFBEF09E2, + 0x0D2ED80A, 0x40C3FA0F, 0xA6350000, 0x902446CB, + 0xB60020A8, 0x0304208A, 0xD80AB602, 0x032741C3, + 0x09BE0001, 0x4222FBEF, 0xD80A9542, 0x41C39560, + 0x00050328, 0x910415FC, 0x71051600, 0x03B89008, + 0xFBEF099E, 0x910615F8, 0xFDCF0B6E, 0xB802C808, + 0x0F802005, 0x002C9008, 0xCA079020, 0x01B5081B, + 0x00CC2184, 0x8084218C, 0x41C3F407, 0x00000329, + 0xF96F0E76, 0xCC1E700C, 0x08139620, 0x700C0060, + 0x032A41C3, 0x0E620000, 0xCC1FF94F, 0x08139622, + 0x700C0060, 0x032B41C3, 0x0E4E0000, 0x1600F94F, + 0x80007080, 0xB8E00185, 0x00C20C54, 0x1243256F, + 0x800042D3, 0x8D001138, 0x9566B8C3, 0x1A00B814, + 0x0B1A2043, 0x50300160, 0xFDCF098E, 0xFDCF09AE, + 0xBBE0C808, 0xB8024170, 0x0F802005, 0x003C900C, + 0x01141000, 0x1E00F28D, 0x90087045, 0x0DD60288, + 0x710C0020, 0x70801600, 0x00198000, 0x1600E893, + 0x80007080, 0x080D000D, 0x8D00005E, 0x011E0817, + 0xE8898F00, 0x70801600, 0x019B8000, 0x0E947014, + 0x0D66FA41, 0x0B42FF4F, 0xD933FECF, 0x08B2740C, + 0xB914FBEF, 0xFE0F0B22, 0xF9CF0A86, 0x742C700C, + 0xFA2F0EEE, 0x700C704C, 0xFA2F0BA2, 0x0DE6712C, + 0x700C0020, 0x70801600, 0x000D8000, 0x005E080D, + 0xB8E48D00, 0x01410F30, 0x1A43266F, 0xFBEF09A2, + 0x10451E00, 0xFB0F0B06, 0xFECF0A06, 0x01000E4E, + 0x233E0939, 0xD80A70ED, 0x033341C3, 0x08520000, + 0xBF8CFBEF, 0x70801600, 0x01848000, 0x20CA7014, + 0x1A0B0321, 0x08123002, 0xB6E0F9AF, 0xB80CD809, + 0x0DCAB600, 0xD80D0020, 0x03400C2E, 0xF9CF0A02, + 0x000040C3, 0x0C4E3A98, 0x702CFF6F, 0xD907780F, + 0x02022048, 0x706C700C, 0x70AC708C, 0xFA2F0B5E, + 0x700C70CC, 0xFA2F0B06, 0x0DC6712C, 0x710CFA4F, + 0x20031A00, 0xB600B88F, 0x00200D82, 0x0B3E700C, + 0x710CFC6F, 0x207E092B, 0x41C3D80A, 0x000002F1, + 0xFB8F0FCE, 0x1A43266F, 0x0A2E710C, 0x1E0001A0, + 0x720C1085, 0xB600B88F, 0x00200D52, 0x095D710C, + 0xD9BB20BE, 0x0FAAD80A, 0xB912FBAF, 0xFBCF0FAE, + 0x1A43266F, 0xFAEF0ABE, 0x11051E00, 0x41C3E80F, + 0x000002ED, 0xFBAF0F8A, 0x09EED80A, 0xD80901A0, + 0xB88F740C, 0x750CB600, 0x41C3F00E, 0x000002EE, + 0xFBAF0F6E, 0x09D2D80A, 0x700C01A0, 0xB88F740C, + 0x720CB600, 0x00000CF6, 0x000042D3, 0x21044000, + 0xF215A495, 0x02EF41C3, 0x0F460000, 0xD80AFBAF, + 0x1A43266F, 0x09A2D80C, 0x1E0001A0, 0x730C1484, + 0xB600B80E, 0x00200CC6, 0x2144D814, 0xF205A216, + 0x02E008EA, 0x0939710C, 0xD80A21BE, 0x02F741C3, + 0x0F0E0000, 0xDF40FBAF, 0xFD8F0FA2, 0x1A43266F, + 0xB6E0D80B, 0x01A00962, 0x30431A06, 0xB88FD840, + 0x0C8AB600, 0x760C0020, 0x30031A06, 0xF445262F, + 0x00030096, 0xF98F0EF6, 0xFAEF09FA, 0xE8094710, + 0x02F941C3, 0x0ECA0000, 0xD80AFBAF, 0x266FF03D, + 0xD95F14C3, 0x10931600, 0x0EB6B913, 0xD80AFBAF, + 0x12CF2640, 0xB700D880, 0xA0002351, 0x090AD80D, + 0x20CA01A0, 0x8E0002A1, 0x00BF0843, 0x218A70F6, + 0xD8FF0FC7, 0xFAEF0802, 0xCA0A703C, 0xD825E897, + 0xB89F706E, 0x88C072EE, 0x7E05881B, 0x14EE0E19, + 0x0A864062, 0x712CFB2F, 0x42008D20, 0x098E700C, + 0x4362FC2F, 0x2D3F278D, 0xD880716E, 0xB700B88F, + 0x00200BEA, 0x0D67D80A, 0x16002010, 0x80007080, + 0x08510164, 0xD92F013F, 0x0E36D80A, 0xB914FBAF, + 0x1A43266F, 0xF9AF0E46, 0x14841E00, 0x218A7014, + 0xD8FF0FC7, 0xFFAF0A0A, 0x730C703C, 0xB600B80E, + 0x00200BAA, 0x8D20D814, 0x704C700C, 0xFC2F092E, + 0x8D20706C, 0x714C700C, 0xFC2F0922, 0xF007716C, + 0xD80AD9CD, 0xFBAF0DEA, 0x096DB912, 0xD80A22BE, + 0x02FA41C3, 0x0DDA0000, 0x278AFBAF, 0x0DEE1010, + 0x4210F98F, 0x70801600, 0x01638000, 0xFA6F0E42, + 0x266F712C, 0x41421A43, 0x02600EFA, 0xD821B6E0, + 0xB600B80A, 0xE895CA0A, 0x70EDD825, 0x724EB89F, + 0x88DB8820, 0x0E157E25, 0x40E113EE, 0xFB2F09AA, + 0x0EAA712C, 0x41E1FBEF, 0x2DFF228D, 0x0B1E71ED, + 0xD80E0020, 0x2051092D, 0x70801600, 0x00198000, + 0x1600E897, 0x80007080, 0xE893011D, 0x033541C3, + 0x0D5E0000, 0xD80AFBAF, 0x01600FBE, 0xF009D808, + 0x213F0909, 0xF003710C, 0x0F3E700C, 0x09710140, + 0x704E213E, 0x20801000, 0x370E1223, 0x0D4EB8E2, + 0x22CAF9AF, 0x278A23E1, 0xE8831FC7, 0x0E51DFFF, + 0xD80A117E, 0x02FD41C3, 0x0D160000, 0x208AFB8F, + 0x266F0404, 0xB6001A43, 0x4142720C, 0x00200AEA, + 0x083242E1, 0xE80DFACF, 0x02FE41C3, 0x0CF20000, + 0x740CFBAF, 0x4142730C, 0x00200ACE, 0x40C342E1, + 0x81100000, 0x0A76B600, 0xD8160020, 0x20300EAD, + 0x40C3704E, 0x01888000, 0x103F9020, 0x70308700, + 0xF786700C, 0x00000F5A, 0x00002052, 0x30021A05, + 0x0E7A700C, 0x1A0C02A0, 0xCA053482, 0x700CE806, + 0x02A00E6A, 0x30431A0C, 0x20801000, 0x370E1223, + 0x0CAAB8E2, 0x22CAF9AF, 0x278A23E1, 0xE8831FC7, + 0x0E0DDFFF, 0x0F9E119E, 0xE808FA8F, 0xD80A732C, + 0xFBAF0C6E, 0xF022B918, 0x02FF41C3, 0x0C620000, + 0xD80AFBAF, 0x0204208A, 0x1A43266F, 0x710CB600, + 0x0A364142, 0x42E10020, 0x000040C3, 0xB6000908, + 0x4142700C, 0x00200A22, 0x40C342E1, 0x81080000, + 0x09CAB600, 0xD8180020, 0x227E0951, 0x41C3D80A, + 0x00000301, 0xFBAF0C1A, 0x2008228A, 0xF9AF0C2E, + 0x208F1000, 0x0F764010, 0x730CFC2F, 0x700CBFE2, + 0x1A43266F, 0x03E120CA, 0x0CE24102, 0x1E000220, + 0xD8411484, 0xB600B809, 0xE885CA0A, 0xFBEF0CCA, + 0x097A8D00, 0xD8090020, 0xE829CA0A, 0x70EDD825, + 0x720EB89F, 0x88DB8820, 0x0E297E25, 0x40E113EE, + 0xFAEF0FD6, 0x8D20712C, 0x710C4200, 0x0EDE43E1, + 0x4250FBEF, 0x700C8D20, 0x0ED24242, 0x43E1FBEF, + 0x2B7F208D, 0x0C8271ED, 0x8D00FBEF, 0x70801600, + 0x00008000, 0x0EACB8E5, 0x0982FC02, 0x0923FECF, + 0x8D002050, 0x0C012044, 0x0C100913, 0x017F0809, + 0xF003700C, 0x0C4A710C, 0x0ED202C0, 0x0CBE0100, + 0xC8080080, 0x2005B802, 0x900F0F80, 0x1800C03C, + 0x08DE0504, 0x700C0160, 0x00000DF6, 0xD80AD967, + 0xFBAF0B3E, 0x0E96B913, 0x700CFC2F, 0x02A00F6A, + 0x700CD807, 0x00C420AB, 0xF0007FFF, 0x02800C82, + 0x4308C2E6, 0x730C71AD, 0x900F46CB, 0x0EAAC028, + 0xB6A0FF2F, 0x900847CB, 0x97000288, 0x0B3DB8A1, + 0xB7001031, 0x900F41C3, 0x40C3C298, 0x3FFF0000, + 0x19E8B1A0, 0x20508004, 0x40C30341, 0xC2249007, + 0x1600B020, 0x80007082, 0x2253000C, 0xF205817E, + 0x00051804, 0xB022F002, 0xFF2F0E5E, 0xD81FD80D, + 0x135C1FAC, 0xFF2F0E52, 0x10051E00, 0x78E0C6C6, + 0x4308C2E4, 0xFF2F0E42, 0x70ADD81F, 0x900846CB, + 0x740C03E0, 0xFF2F0E32, 0x1654B6A0, 0x206C9700, + 0xB8810040, 0x10300B0B, 0x901C1E54, 0x700CC6C4, + 0x900F41C3, 0xB88CC280, 0x40C3B100, 0xC2249007, + 0xB0A2B0A0, 0xC6C4B1AC, 0x4608C2E4, 0x70801600, + 0x00128000, 0x8203208C, 0x02AE0E8C, 0x0EFA40C1, + 0x0BDE0040, 0x0B26FECF, 0xCA110080, 0x800145CB, + 0x25164FC4, 0x0B4A1000, 0xB0C0FAEF, 0x30821211, + 0xA5017D56, 0x0F0A6A01, 0x1A11FAAF, 0x0C663002, + 0xC6C40280, 0x1CFCC2FA, 0x2482B6C8, 0x41583304, + 0x4310C141, 0x702CC08E, 0xF92F0A26, 0x708EDA50, + 0x35001C34, 0x35001C30, 0x35001C2C, 0xFBEF087E, + 0x35001C28, 0x21350B27, 0x2353C042, 0x730C20C1, + 0x21787839, 0xB8C000DB, 0x202FC043, 0x26F004C5, + 0x80007000, 0xC04410C4, 0x700CF007, 0xB890706F, + 0x4063C044, 0x2350C043, 0x21842000, 0xC0473004, + 0x46D3720C, 0x12218000, 0x800047D3, 0xC045C144, + 0x458AD825, 0x718EB89F, 0x881B8820, 0x2C007905, + 0xB8022340, 0x0350200F, 0xA040200B, 0x00210408, + 0x0CEA730C, 0x1E00FC2F, 0xC0042342, 0x0E2A78A5, + 0xC04602A0, 0xC8084110, 0x7825C106, 0x208916B8, + 0x20881602, 0x008B2840, 0x20811601, 0x1064086D, + 0x096540A1, 0x2940106E, 0x215A0380, 0x2005050C, + 0xC78E02C0, 0x7280244A, 0x0F832005, 0x00009000, + 0x679F700C, 0x080020A8, 0x30310911, 0x06822100, + 0x0082121C, 0x0080082F, 0x30300B0B, 0x02422079, + 0x2078F003, 0xEA8F0242, 0x0271080D, 0x9340C68E, + 0xF009B749, 0x02822840, 0x7A65669E, 0x92407E14, + 0x7104B640, 0xF1CC7124, 0x3005140C, 0xC28C4162, + 0x708CC38A, 0xFC6F0C12, 0x40C370CC, 0x12DC8000, + 0x21798020, 0x40A13002, 0x09CA4340, 0x4250FE2F, + 0x30300B73, 0x1407262F, 0x0CCE710C, 0x41C1FC2F, + 0x00800A0A, 0x38812455, 0xDA084022, 0x44C14362, + 0x3C052440, 0x0480260A, 0x089A71EC, 0x2455FB6F, + 0xDA23388F, 0xBA0A40E2, 0xF92F08A6, 0xC301702C, + 0x1408D808, 0x41623004, 0x2440704C, 0x260A3C05, + 0x70EC0480, 0xFB6F0C52, 0x2455C740, 0x082A3880, + 0x702CFB6F, 0x0C72700C, 0x41C1FC2F, 0x00C00E3E, + 0x2455F029, 0x40223881, 0x4362DA08, 0x244044C1, + 0x260A3C05, 0x71EC0480, 0xFB6F083A, 0x388F2455, + 0x40E2DA23, 0x084ABA0A, 0x702CF92F, 0xD808C301, + 0x30041408, 0x704C4162, 0x3C052440, 0x0480260A, + 0x0BF670EC, 0xC740FB6F, 0x38802455, 0xFB2F0FCA, + 0x1601702C, 0x16022091, 0x210C2080, 0x025CA000, + 0x40C3000D, 0x12D98000, 0x20118800, 0x02468440, + 0x29400021, 0xC0062315, 0x05402005, 0xC049700E, + 0x2280215A, 0x0917C048, 0x21003031, 0x101C2680, + 0x200C0080, 0x0214A000, 0x0B0D0001, 0x20793030, + 0xF0042240, 0x22402078, 0x02007014, 0xC2080002, + 0x229A7202, 0x2232000E, 0x80000F83, 0xEB14C444, + 0x00700B2B, 0x05C02234, 0x0B1772E2, 0x922100F1, + 0xDE809282, 0x4E924913, 0x00A20B17, 0x42104291, + 0xF0074628, 0x70CD704E, 0xDE80F003, 0x215A4210, + 0xC08E2501, 0xC007603A, 0x040F22F4, 0x00B1080F, + 0xC08C4058, 0x044020F4, 0x0812F00A, 0x40E1FBAF, + 0xC08C4708, 0xFBAF0806, 0x044020F4, 0x4F10661E, + 0x20024EF1, 0x72760480, 0x20CA4608, 0x26CA0045, + 0x0B411046, 0x12082030, 0x0BB73609, 0x28402071, + 0x47CB220B, 0x00009000, 0x154B2305, 0x124B2305, + 0x1F812305, 0x006A0001, 0xB90261B9, 0x03C82105, + 0x1F812305, 0x00680001, 0xB90261B9, 0xF0787F25, + 0x220B2840, 0x900042C3, 0x23050000, 0x7BD0154B, + 0x124B2305, 0x23057810, 0x00011F81, 0x61B90068, + 0x7F4569F2, 0x21099720, 0x230500CE, 0x00011F81, + 0x61B9006A, 0x2105B902, 0x10000088, 0x21091101, + 0x23050000, 0xB9021341, 0x0F822105, 0x00489004, + 0x0F812105, 0x00409004, 0x16009240, 0x80007083, + 0x0B8D00EF, 0x91200030, 0xB9C6BAC6, 0x21CC72D1, + 0x005E838D, 0x0A59000D, 0x4A760065, 0x0B2DF029, + 0x210520B1, 0x28401541, 0x43C32202, 0x00009000, + 0x21057945, 0x00010F82, 0x62BA0060, 0x0F812105, + 0x00630001, 0xF00EBA02, 0x0F822105, 0x00190001, + 0x7AB4B981, 0xBA02B985, 0x43C3B990, 0x00009000, + 0xB2C07A65, 0xB90261B9, 0xF0277965, 0x621C4976, + 0xF705E4FE, 0xE4FF611C, 0x090FF78A, 0x228700A5, + 0x4A700FC1, 0x2187F004, 0x49700FC1, 0x1F812305, + 0x006C0001, 0x42C361B9, 0x00009000, 0xB7C0B902, + 0xB1C07945, 0x1F812305, 0x006E0001, 0x180061B9, + 0xB9021004, 0xB1007945, 0x41C3C009, 0x00009000, + 0x340320F4, 0x02402005, 0x2270080D, 0x2840B802, + 0x78452282, 0xB0607825, 0x204C7106, 0x05DAA280, + 0x05A7FFC5, 0x7126FFEF, 0x20110B1D, 0x71001600, + 0x00C49004, 0x0002204F, 0x900741C3, 0xB140C0C4, + 0xB100B8A0, 0x7704C005, 0x03D87014, 0xC045FFE2, + 0x33042480, 0x341B1404, 0x78E0C6DA, 0x70801600, + 0x000D8000, 0x08002044, 0xB8257FE0, 0xC1A4C3E4, + 0x70CDDD37, 0x1501BD9F, 0xC0621480, 0x14801501, + 0x30021C09, 0x14801501, 0x30021C0A, 0x14801501, + 0x30021C0B, 0x14801501, 0x1501C063, 0x1C0D1480, + 0x15013002, 0x1C0E1480, 0x15143002, 0x1C0F1480, + 0xC0823002, 0x022141C3, 0x60CB0002, 0x0D02740C, + 0x42C1FB6F, 0x0EEF71C5, 0x15019214, 0xC0601480, + 0x14801501, 0x30021C01, 0x14801501, 0x30021C02, + 0x14801501, 0x30021C03, 0x14801501, 0x8D00C061, + 0x30021C05, 0x1C068D01, 0x8D023002, 0x1C0770AD, + 0xC0803002, 0x022241C3, 0x60AB0002, 0x0CB2740C, + 0x42A1FB6F, 0x0DEF71A5, 0xC7C49214, 0x46CBC2E6, + 0x04628000, 0x800045CB, 0x08131A20, 0x470802FF, + 0x20539600, 0xF41180BE, 0x950AF00D, 0xB50AB880, + 0x20538E00, 0xF20780BE, 0xA503700C, 0xA501A502, + 0x0E22A500, 0x262FF94F, 0x0008F3C5, 0xC6C60004, + 0x20538E00, 0xF20780BE, 0xA503700C, 0xA501A502, + 0x0E02A500, 0xC6C6F94F, 0x46A8C2EA, 0x40704788, + 0x0CDA4548, 0x4130FB6F, 0x2281215F, 0x25CAE589, + 0x60381221, 0x229F7A0F, 0x2200000E, 0x20000400, + 0x80000F81, 0x8960C444, 0x0B1D710C, 0x78B800F0, + 0x00700B3F, 0x0B5178CB, 0x78CB00B0, 0x78CBEB83, + 0xC6CAF22C, 0xF3FF78CB, 0x2180205F, 0x40C3621A, + 0xC1448000, 0x9340621B, 0x78429301, 0x93027C10, + 0x7A504F12, 0x10850C1B, 0xB300B3E1, 0xF3EBF009, + 0x2180205F, 0x70C36058, 0xC1468000, 0x1900B0E0, + 0xC6CA0083, 0x205FF5DF, 0x19002180, 0x605800C3, + 0x800070C3, 0xF00AC148, 0x2180205F, 0x00431900, + 0x70C36058, 0xC1448000, 0xC6CAB0E0, 0xC1A6C3F2, + 0x44104530, 0xF2B27014, 0x230A70ED, 0x25142500, + 0x244023D2, 0x21143511, 0x120023D1, 0x20532100, + 0x19010141, 0x702C2042, 0x1900B826, 0x0EBA2002, + 0x4022FE6F, 0x21001204, 0x34102440, 0x23D02014, + 0x01412053, 0x20421801, 0xB826702C, 0x20021800, + 0xFE6F0E96, 0x40224002, 0x0DB24102, 0x724C0060, + 0x2100120A, 0x7EF4C683, 0x01412053, 0x712CAE21, + 0xAE00B826, 0xFE6F0E72, 0x120E40C1, 0xC5822100, + 0x20537DF4, 0xAD210141, 0xB826712C, 0x0E5AAD00, + 0x40A1FE6F, 0x41A140C1, 0x00600D72, 0x1101724C, + 0xE0C02080, 0xD940F704, 0xF0044910, 0x003F2080, + 0x31812440, 0xA90061F9, 0x20801001, 0xF705E0C0, + 0x4910D940, 0x2080F003, 0xC181003F, 0xA90061F9, + 0xE0C08E01, 0xD940F704, 0xF0044910, 0x003F2080, + 0x30812440, 0xA90061F9, 0xE0C08D01, 0xD940F704, + 0xF0044910, 0x003F2080, 0x63F9C380, 0x238D71E5, + 0xA900227E, 0x7500240A, 0x708D70AD, 0x704C706D, + 0x054020A8, 0x30802440, 0x22086088, 0x13010001, + 0x21080480, 0x24400002, 0x60883180, 0x10012308, + 0x6088C081, 0x21087185, 0x270A000B, 0xC3830540, + 0x32042440, 0x35052440, 0x34062440, 0x24147BB4, + 0x25140344, 0x26140345, 0x78AF0346, 0xFA2F0812, + 0x71A54161, 0x95040DDB, 0x78E0C7D2, 0x1CFCC2FA, + 0x2482B6C8, 0x1C473D08, 0xC0413058, 0x36001447, + 0x30981C48, 0x800042C3, 0x1C081224, 0x08293100, + 0x1C490070, 0x144730D8, 0xE89F3600, 0x70801600, + 0x00258000, 0x00C02078, 0x00971200, 0xC0407104, + 0xF0118A01, 0x70801600, 0x00408000, 0x00412078, + 0x00971202, 0x7314C140, 0x20CAC000, 0xC04000A1, + 0x1C468A03, 0xC2013018, 0x41C3740C, 0x000200BD, + 0xFB6F09AE, 0xC001C300, 0x02D07014, 0xD9200021, + 0x0BC3216F, 0x780A8900, 0x301C1A1C, 0x780A8901, + 0x301C1A1D, 0x7014C000, 0x0021052C, 0x40DB708E, + 0x0A3C0000, 0x2619271F, 0x394F2456, 0x33102440, + 0x800043DB, 0x27801A3C, 0x20801084, 0x706E2084, + 0x36D92100, 0x30181C45, 0x7001248A, 0x218AC083, + 0x1A0D0FC7, 0x20A834C2, 0xB0210180, 0x00151804, + 0x39402456, 0x248AD9FF, 0x228A7001, 0x18000FC7, + 0x1C8627C3, 0x1C88351C, 0x20A8305C, 0xB0410180, + 0x00151804, 0x25C0210A, 0x3F802400, 0x02280000, + 0x17C31F00, 0x00051800, 0x1446B022, 0x08CF3600, + 0xC0830464, 0x36001448, 0x0447212F, 0x01200A86, + 0x34581A0B, 0xC04270AE, 0x08A9C002, 0x211A054E, + 0x1A0C2600, 0x231A3558, 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0x80007080, 0x0811000B, + 0x40A100BF, 0x0220091E, 0xC6C240A1, 0xFCEF0FC2, + 0xC6C2702C, 0x1600C2E6, 0x8000708E, 0x47280008, + 0xF8EF0CCE, 0x700C4508, 0x744CD907, 0x708C706C, + 0x0E3A70AC, 0x70CCF92F, 0x10802678, 0x08DA781B, + 0x68C2F96F, 0x700CEF11, 0x724CD907, 0x708C706C, + 0x0E1A70AC, 0x74CCF92F, 0x752C704C, 0x238A4040, + 0xB8950004, 0x704CF01B, 0x4040752C, 0x0004238A, + 0x708CB895, 0x0DF645A1, 0x70CCF92F, 0xD92B74ED, + 0x42C1BF98, 0x706C40E1, 0x45A1708C, 0xF92F0DDE, + 0x40E170CC, 0x42C1D92B, 0x708C706C, 0x0DCE45A1, + 0x70CCF92F, 0xD92BD841, 0x42C1B812, 0x708C706C, + 0x0DBA45A1, 0x70CCF92F, 0xD907700C, 0x706C744C, + 0x70AC708C, 0xF92F0DA6, 0x0280264A, 0xD907706C, + 0x744C4060, 0x708CB88F, 0x0D9270AC, 0x70CCF92F, + 0xD907700C, 0x706CDA08, 0x70AC708C, 0xF92F0D7E, + 0x080E70CC, 0x700CF94F, 0x744CD907, 0x708C706C, + 0x0D6A70AC, 0x70CCF92F, 0x78E0C6C6, 0x2482C3F0, + 0x42103403, 0x38002455, 0x702C4330, 0xF86F0A12, + 0x40C3DA50, 0xF0B00000, 0xB415448B, 0x73044899, + 0xB409B42F, 0x0A812057, 0x000040C3, 0x1C66FF74, + 0x21573004, 0x1C5A09C0, 0xB86E3004, 0x30041C42, + 0xB41BB863, 0x000140C3, 0xC049F0BA, 0x710C686E, + 0xB88EDA07, 0x30841C5C, 0x30841C44, 0xB45C71AD, + 0x03422342, 0x40C3B408, 0xFFB50001, 0x2080C043, + 0xC2400339, 0x1C6ADA40, 0x20403084, 0xC05B0802, + 0x6843C258, 0xB4237704, 0x41C3C04F, 0xFE030000, + 0x70801600, 0x00088000, 0x00802079, 0x30441C4E, + 0x30041C40, 0xB41D702C, 0xC255B802, 0x000742C3, + 0xB417F004, 0xB42EC808, 0xB425B42B, 0x30441C70, + 0x30441C64, 0x30441C5E, 0x30441C58, 0x30441C52, + 0x30441C4C, 0x6B4BC252, 0x30441C46, 0x2005B43A, + 0x000E0F81, 0xC15EF00B, 0x09412254, 0xC3467825, + 0x30041C72, 0xC24CB830, 0x1C74702C, 0x700C3004, + 0x706C704C, 0xB4B0B4B6, 0xB4A4B4AA, 0x33441C68, + 0x33441C50, 0xB4B1B4B4, 0x30851C04, 0x30851C7C, + 0xFCEF0A7E, 0x33441C76, 0x000042C3, 0x700C5555, + 0x4340722C, 0x09E24440, 0x4540FCEF, 0x094EC080, + 0xD97E0260, 0x0D6ED80F, 0xD90FF9EF, 0x900741D3, + 0x1900F804, 0x47CB2105, 0x12228000, 0x6832C808, + 0x2105D880, 0x90070F82, 0xB200FC48, 0x0F822105, + 0xFC4C9007, 0x2105B200, 0x90070F82, 0xB200FC40, + 0x0F822105, 0xFC449007, 0x2D00B200, 0xB8021480, + 0x200F8F40, 0x8F01048E, 0x00A4082B, 0xBA0E7842, + 0x240A7104, 0x20A87000, 0x210503C0, 0x72C30080, + 0x40000000, 0x0F802005, 0x057C9004, 0xBB8A9060, + 0x0C62B060, 0x09DEFC0F, 0x242F0000, 0xD8552387, + 0x704CD955, 0x0E5E706C, 0x240A0060, 0x40820500, + 0xFFEF0D26, 0xD860702C, 0xF92F0B22, 0x208A712C, + 0x40D30FC7, 0xC2CC9007, 0x20041800, 0x20041804, + 0x71001600, 0x02C09004, 0x0C002045, 0xA00418F4, + 0xA34418F8, 0x8F008F81, 0x10240C43, 0x2840D9AC, + 0x244A0388, 0x706D7240, 0x20A8704C, 0x0B1305C0, + 0x20002031, 0x111C0681, 0x0A190081, 0x20050040, + 0x210512C1, 0x90040F81, 0x916001D0, 0xB160E320, + 0x10102380, 0x71047144, 0x46CBF1E0, 0x01068000, + 0xD8538E40, 0x0DCE4340, 0x240A0060, 0x8E000500, + 0x8FA0E81C, 0x08258F01, 0x8E000344, 0x00A00916, + 0x2D4079AF, 0x21051381, 0x90040F81, 0xB1003830, + 0x75108F01, 0xF7B371A5, 0x0FC7218A, 0x900740C3, + 0x1800F834, 0xB0220005, 0x0C5E4082, 0x712CFFEF, + 0x000042C3, 0x700CAC53, 0x4340722C, 0x085A4440, + 0x4540FCEF, 0x0BEED80F, 0xD90FF9EF, 0xDD2870CD, + 0x0A3AD808, 0x712CF92F, 0x108B1701, 0x0B578F00, + 0xD90F1024, 0x03892840, 0x7240244A, 0x708D700D, + 0x07C020A8, 0x20310B11, 0x06812000, 0x0081111C, + 0x10400C29, 0x12412005, 0x210570CD, 0x90040F82, + 0x210502DC, 0x90040F81, 0x924001D0, 0xEA069160, + 0x08032354, 0xB1604648, 0x10102080, 0x71047185, + 0x0B82F1D7, 0xD80FF9EF, 0x133F258C, 0x10002678, + 0x02DD41C3, 0x0BC20001, 0x4242F86F, 0x38002455, + 0x0F9E712C, 0x704CFFAF, 0x0ABE4042, 0x712CFA2F, + 0x0F002054, 0x38012455, 0x706C714C, 0x70AC708C, + 0x0260081E, 0x40C34588, 0xF8309007, 0x73441E00, + 0xC29C9007, 0xA34418F8, 0x73441E00, 0x0004901C, + 0x23441900, 0xB0A2B0A0, 0x0020080A, 0xC7D0B0A4, + 0xD820C2E2, 0x900B45CB, 0x09EEC280, 0x1D00FE6F, + 0x1D001045, 0xC6C21005, 0x1CFCC2FA, 0x2482B6C8, + 0x41DB3002, 0xC17C9007, 0x901C43D3, 0x190004A8, + 0x42103005, 0x20551B5C, 0xC8084338, 0x800041C3, + 0xDA6C04B8, 0x71AD702E, 0x2005B802, 0x180004C0, + 0x0E160045, 0xC085F82F, 0x702C700C, 0x0FA2704C, + 0x706CFCAF, 0x722C700C, 0x706C704C, 0x0F0A708C, + 0x70ACFCAF, 0x0E76C085, 0xD96C0220, 0xFACF0BC2, + 0x0A92D80F, 0xD90FF9EF, 0xFF8F0B1A, 0x40C3D90A, + 0x4E748001, 0x00200E8A, 0x40024010, 0x09AAD90A, + 0x704CF96F, 0xD90A4002, 0xFDEF0B8A, 0x4002DA59, + 0x00200E6E, 0x4002D92E, 0x098ED92E, 0x704CF96F, + 0x0E5E4002, 0xD9120020, 0xD9124002, 0xF96F097A, + 0x0D1EDAEF, 0xC0810060, 0x09FEC081, 0xD90AFB6F, + 0x09F6C081, 0xD92EFB6F, 0x09EEC081, 0xD912FB6F, + 0x800047CB, 0x41421220, 0x219F8F00, 0x704C02C1, + 0x0582209F, 0x708CC381, 0x2D006119, 0xB8021480, + 0x200F7102, 0x6D12048D, 0x7E0F78A5, 0x087E40C1, + 0x40D90220, 0x0F824002, 0xD90AFFAF, 0x0F7A4002, + 0xD912FFAF, 0x0F724002, 0xD92EFFAF, 0x700C7DAF, + 0x704C702C, 0x0B4E706C, 0x44A10060, 0x098A710C, + 0x712C0060, 0x0CB640A1, 0x702C01E0, 0x02D341C3, + 0x0CFE0000, 0x740CFAAF, 0x0802D860, 0x712CF92F, + 0xFC8F0B6E, 0x8F228F03, 0x00640829, 0x68417822, + 0x03802940, 0x7080240A, 0x030020A8, 0x0F812005, + 0x01D09004, 0x70C39140, 0x40000000, 0xB140BAC5, + 0x712C700C, 0xF8EF0FC6, 0x3FC11C00, 0x0966D80F, + 0xD90FF9EF, 0x0C5640A1, 0x712C01E0, 0x0FC7208A, + 0x900746CB, 0xB600C2CC, 0xB602D9B5, 0x1EF8D881, + 0xD8309004, 0x1EF4B912, 0x0C869004, 0x740CFAAF, + 0x40A1DDFF, 0x461045B1, 0x700C44B1, 0xF8EF0F7E, + 0x8F03712C, 0x08618F22, 0x70EE0064, 0x29407822, + 0x7104038C, 0x7000240A, 0x07C020A8, 0x2405C280, + 0x90041F80, 0x900002DC, 0x2079623A, 0x8A000003, + 0x7865781B, 0x2053AA00, 0x240580BE, 0x90041F80, + 0x904001D0, 0x2254F205, 0x71EE0802, 0x7124B040, + 0x000074C3, 0x14034000, 0xC5203096, 0x30951402, + 0x30941401, 0x08BED80F, 0xD90FF9EF, 0x41C3740C, + 0x000402D5, 0x438242A1, 0x0540240A, 0xFAAF0BF2, + 0x0580250A, 0x090B7126, 0x0F732E15, 0x41C3A011, + 0x000002D7, 0xF86F08E2, 0x20002778, 0x740CD95B, + 0xFAAF0BCE, 0x8F03B913, 0x082D8F22, 0x78220064, + 0x29406841, 0x240A0380, 0x20A87080, 0x20050380, + 0x90040F81, 0x914001D0, 0x000070C3, 0x22554000, + 0xB1400802, 0xB6A070AD, 0x0A16B6A2, 0x1EF4FCAF, + 0x700C9344, 0x00200D42, 0xD881712C, 0x02D941C3, + 0x1EF80000, 0x0B7A9004, 0x740CFAAF, 0x0E7ED840, + 0x712CF8EF, 0x712C4063, 0xFFAF0C56, 0x8F23724C, + 0x09238F02, 0x79020024, 0x240A7124, 0x20A87040, + 0x23F402C0, 0x23143001, 0x21803002, 0x7104003E, + 0x4042B220, 0xF9EF0F52, 0x48C8712C, 0x7825C808, + 0x714C4163, 0x708C706C, 0x02200CB6, 0xD92071AC, + 0x900740C3, 0xB0A0C29C, 0x22C1229F, 0x804418EC, + 0x834418EC, 0x73441E00, 0xC164900B, 0x93441EF8, + 0x30451900, 0xB802C808, 0x04C12005, 0xFFEF0C96, + 0x8F00B1A0, 0x209F704C, 0xC3810582, 0x7042708C, + 0x04012000, 0x01E00E16, 0xCA004003, 0x10250D31, + 0x138C2D40, 0x7240244A, 0x702C704C, 0x038020A8, + 0x2405716C, 0x7B381080, 0x0F802005, 0x02F89004, + 0x00102280, 0xB0607124, 0xF1E971A5, 0x30022480, + 0x341B1404, 0x78E0C6DA, 0x4408C0F1, 0x2084880B, + 0xAC0B01C2, 0xB8A38C01, 0x1600AC01, 0x800070C0, + 0x080F000D, 0x8C130012, 0x03002046, 0x0A8EAC13, + 0xE808F88F, 0xB8858C0D, 0x8C03AC0D, 0xAC03B887, + 0xF98F0D4A, 0x8C15E807, 0xAC15B8A5, 0xB8868C03, + 0xD840AC03, 0x10831C14, 0x8C0DAC10, 0xAC0DB8A4, + 0x20458C11, 0xAC110E00, 0x206C8C12, 0xAC120080, + 0x20448C1C, 0xAC1C0300, 0x10801429, 0xC0D1B8C4, + 0x1C297FE0, 0x78E01002, 0x40C3C5E1, 0x04988000, + 0xE9328820, 0xA840704C, 0x0A5DCA00, 0x2A400025, + 0x244A0381, 0x706C7240, 0x090020A8, 0x00802216, + 0x20006078, 0x80010F8D, 0x6B124FA0, 0x20057825, + 0x90040F80, 0x90800200, 0x0B13AD80, 0xB0600231, + 0x22008D80, 0x181C0680, 0x2B400302, 0x718D0280, + 0x7C787825, 0x20057164, 0x90040F80, 0xB08002F8, + 0xF1D47144, 0x78E0C4C2, 0xC1A2C3E6, 0x900042C3, + 0x92800184, 0x903841C3, 0x246C0184, 0x91601140, + 0x236CB200, 0xB1000140, 0x9202722D, 0xB8C891A2, + 0x704CB280, 0x44CBBDC8, 0x05A48000, 0xC241B160, + 0xB1014183, 0xC808B1A0, 0x10832415, 0x30062440, + 0x70AD720D, 0xF41C7AAB, 0x13412415, 0x7E0583C1, + 0x79C58123, 0x2105B902, 0x90030F8E, 0xB99CC000, + 0x91E0B99F, 0x134124F4, 0xC1817F26, 0x034B21F4, + 0x008126F4, 0x02C12900, 0xB62079E5, 0x193F208D, + 0x218D71AD, 0x714C16FF, 0x2042C805, 0xF20E803C, + 0xD99C700C, 0x028020A8, 0x0F822005, 0x03649004, + 0x000070C3, 0xB2204000, 0x9661468B, 0x41C3740C, + 0x00020071, 0x08EA96A0, 0x42A1FAAF, 0xDC7FC808, + 0x2553BC09, 0x68321202, 0x0F832105, 0x20289024, + 0x21059300, 0x90240F81, 0x7884202C, 0x008D2005, + 0x78849100, 0x7845B3A0, 0x740CB100, 0x007241C3, + 0x08AE0001, 0x9640FAAF, 0x78E0C7C6, 0xDC25C808, + 0x43C3BC9F, 0x12248000, 0x21056832, 0x90070F80, + 0x2105C408, 0x90040F81, 0x91200408, 0x305C1A23, + 0x0F812104, 0xFF9F0000, 0x8C00B020, 0x8B01E818, + 0x082D8B20, 0x78220064, 0x240A7104, 0x20A87000, + 0x29400400, 0x26140380, 0x80007042, 0x2005049C, + 0x90040F80, 0x9000028C, 0xB2007124, 0x70148C1B, + 0x8B037CE0, 0x71108B22, 0x07CD20E0, 0x71047822, + 0x7000240A, 0x03C020A8, 0x03802940, 0x70422614, + 0x049C8000, 0x0F802005, 0x028C9004, 0x71249000, + 0x7EE0B200, 0x45CBC2E8, 0x12228000, 0x40108DC0, + 0x085B8D01, 0x40C30384, 0x12D98000, 0x084B8800, + 0x79CF03AE, 0x0060097E, 0x44084002, 0x2E40C808, + 0x244A1382, 0x68327280, 0x702C7A25, 0x054020A8, + 0x104E0C25, 0x1500265A, 0x20007834, 0x80010F83, + 0x29404E24, 0x78450280, 0x0F802005, 0x03209004, + 0xB3009000, 0x71C57124, 0xC6C8F1D4, 0x706CC808, + 0x6852726D, 0xE808710C, 0x70801600, 0x00258000, + 0xF020E888, 0x70801600, 0x00408000, 0x7CE07014, + 0x7180244A, 0x058020A8, 0x03802B40, 0x800044CB, + 0x784519AC, 0x20057C74, 0x90000F81, 0x912001C0, + 0x0F802005, 0x01B49000, 0x7164B420, 0xB40E9000, + 0x238DDB07, 0x700C16FF, 0x78E07EE0, 0x21006038, + 0x80000F83, 0x88401880, 0x2100AB40, 0x80000F83, + 0x104B18CB, 0xAB400082, 0x0F832100, 0x19168000, + 0x00821096, 0x800071C3, 0xAB401961, 0x008010E1, + 0xA9007FE0, 0x2142EA1E, 0x7CE0803C, 0x064020A8, + 0x04831001, 0x04811001, 0x04821001, 0x7B25B908, + 0x04811001, 0x7945B908, 0x7965B910, 0xB99CB902, + 0x9120B99F, 0x00521801, 0x1801B928, 0xF0200052, + 0x803C2142, 0x072220E8, 0x04831001, 0x04811001, + 0x04821001, 0x7B25B908, 0x04811001, 0x7945B908, + 0x04821001, 0x7965B910, 0x2105B902, 0x90030F83, + 0x1001C000, 0xB9080481, 0xB3207945, 0x78E07EE0, + 0x7915793B, 0x0F802100, 0x04588000, 0xB0407FE0, + 0x40C34100, 0x12DA8000, 0xE8898800, 0x70801600, + 0x00088000, 0x01110807, 0x7FE0793B, 0x78E07830, + 0xE0C04100, 0xD840F704, 0xF0044831, 0x003F2180, + 0x782F7FE0, 0x24056892, 0x90071F80, 0x1800C2D4, + 0x40C30005, 0x12228000, 0x88608841, 0x20E07350, + 0x4A7007CD, 0x7104BB0E, 0x7000240A, 0x030020A8, + 0x10C02405, 0x000073C3, 0x20054000, 0x90040F80, + 0xB02002D4, 0x78E07EE0, 0x0443206F, 0x800042C3, + 0x8820121E, 0x0703219F, 0x810010FE, 0x01031A01, + 0x77046038, 0x00402805, 0xAA007FE0, 0xC1A4C3E4, + 0x800145CB, 0x46084E74, 0x40A17034, 0xF20BD912, + 0xFFCF0E8E, 0xD91240A1, 0xFDAF0B9A, 0x714CDA10, + 0x0806F004, 0x704CFF8F, 0x41C3C808, 0x0504901C, + 0x7825B802, 0xC080B040, 0x00200D36, 0x804519A4, + 0x0A16C080, 0xD912FB2F, 0x702C40A1, 0x43C1C280, + 0x01E00D2A, 0xC7C4708C, 0x70CDC0E6, 0x800042C3, + 0x1E001222, 0x90077384, 0x8AE1FED4, 0x1047232F, + 0x0F638A60, 0x2B4010E4, 0x238C038D, 0xF4169FC3, + 0x1F822505, 0x3ED49004, 0x023F091D, 0x2300B200, + 0x121C0682, 0xBA0A0082, 0x25057D45, 0x90041F82, + 0xB2C002D4, 0xF1E77164, 0x4028702D, 0x08F9704C, + 0x0AF59010, 0x202F8275, 0xF7499202, 0x124C2505, + 0x1F8C2405, 0x02D49004, 0x2180B400, 0x71441010, + 0xC4C6F1EF, 0x0FB2C2E2, 0x4408F92F, 0x1843256F, + 0x09679520, 0x41C30050, 0x12218000, 0x800043C3, + 0x0C1B0458, 0x894010F1, 0x15307B55, 0x93401081, + 0x9321E909, 0x00422208, 0x2450F005, 0x79551001, + 0x621B6172, 0x6852C808, 0x0F802205, 0x0034901C, + 0xC805B060, 0x803C2042, 0x700CF20D, 0x02C020A8, + 0x00012205, 0x000070C3, 0xB9924000, 0xB99FB99C, + 0x0E42B160, 0xC6C2FF8F, 0xC808C2E6, 0x120570AD, + 0x706C3608, 0x1202212F, 0x800046CB, 0x68920458, + 0x02250B51, 0x233DD940, 0xB99F024B, 0x20798900, + 0x23040002, 0x26F4908F, 0xF20613C2, 0x00D10817, + 0xF0079623, 0x808111E5, 0x00D1090B, 0x22089622, + 0x26140042, 0x716413C1, 0xB142B140, 0x13412405, + 0x75C3B992, 0x40000000, 0xB99FB99C, 0xF1DAB140, + 0x96219600, 0xF92F0ED2, 0x000C2108, 0x60985020, + 0x2105B902, 0x901C0F81, 0xB1000034, 0x78E0C6C6, + 0xC1A4C3E6, 0xC0804708, 0x00200B96, 0xC0804528, + 0xFB2F0876, 0x46CBD918, 0x4E748001, 0xD91840C1, + 0x0020096A, 0x78BD42E1, 0x800041C3, 0xB8C01220, + 0x209F8920, 0x704C02C1, 0x0582219F, 0x708CC380, + 0x6D126119, 0x61D978A5, 0x01A00F02, 0xC7C6780F, + 0x4528C2E4, 0xF86F0D9A, 0x700C4608, 0x724C762C, + 0x244A43C1, 0x45A10780, 0xF8AF0F02, 0x700C70CC, + 0x09EED922, 0x704CF8EF, 0x0EA2700C, 0x712CF8AF, + 0x78E0C6C4, 0x900742C3, 0xB200C2E4, 0xB2227FE0, + 0xC1A4C3E8, 0xC0804010, 0x0B064548, 0x47280020, + 0xAFC3208C, 0x800146CB, 0xF20C4E74, 0x28C02054, + 0xC080790F, 0xFAEF0FD2, 0x40C14030, 0xF02C4102, + 0x0FC6C080, 0xD946FAEF, 0x0FBEC080, 0xD947FAEF, + 0x0FB6C080, 0xD948FAEF, 0x0FAEC080, 0xD949FAEF, + 0x0FA6C080, 0xD94AFAEF, 0xD94640C1, 0x0020089E, + 0x40C142E1, 0x0896D947, 0x42E10020, 0xD94840C1, + 0x0020088A, 0x40C142E1, 0x0882D949, 0x42E10020, + 0xD94A40C1, 0x00200876, 0x79BD42E1, 0x800040C3, + 0x88001220, 0x209FB9C0, 0x704C0582, 0x02C1219F, + 0x708CC380, 0x6D126119, 0x61D978A5, 0x01A00E0E, + 0xC7C8780F, 0xDB1FC0F1, 0xC8084100, 0x2085BB0B, + 0xDA0B08C1, 0x0AEA708C, 0x4128FC2F, 0xC8084600, + 0x09012085, 0xDA0B4121, 0xFC2F0AD6, 0xC0D1718C, + 0x40C07FE0, 0xC8084100, 0x08C12085, 0x238ADA09, + 0x02BD0008, 0x708CFC2F, 0x184B6038, 0xA8400082, + 0x00821896, 0x18E17FE0, 0x78E00082, 0x45CBC2E2, + 0x04588000, 0x0FA2E806, 0x700CFFEF, 0xC6C2B504, + 0xFFEF0F96, 0xC6C29504, 0x4528C2E4, 0xF86F0C32, + 0x700C4608, 0x724C762C, 0x248A43C1, 0x45A10141, + 0xF8AF0D9A, 0x700C70CC, 0x0886D922, 0x704CF8EF, + 0x0D3A700C, 0x712CF8AF, 0x78E0C6C4, 0xDD25C2E2, + 0x901C41C3, 0xBD9F01C8, 0x1480151B, 0x15C6B100, + 0x0BD29480, 0xB102FF6F, 0x08359500, 0x00000F84, + 0xC8080C81, 0x40C36852, 0x0C50902C, 0x22059020, + 0x90240F8C, 0x9062201C, 0x71046917, 0xB4006B37, + 0x0F802205, 0x20209024, 0xB0207124, 0x78E0C6C2, + 0x4588C2EA, 0x47484668, 0x0BA64030, 0x4110F86F, + 0x800140C3, 0x88604E88, 0xBBC5700C, 0xDA22762C, + 0x0500244A, 0x0D0645A1, 0x70CCF8AF, 0x762C700C, + 0x4322DA22, 0x0840244A, 0x0CF245A1, 0x70CCF8AF, + 0x700CDA22, 0x4302762C, 0x45A14440, 0xF8AF0CDE, + 0x700C70CC, 0xDA22762C, 0x244A43E1, 0x45A107C0, + 0xF8AF0CCA, 0x700C70CC, 0xDA22762C, 0x244A43C1, + 0x45A10800, 0xF8AF0CB6, 0x700C70CC, 0xF8AF0C5E, + 0xC6CA712C, 0xD925C2E6, 0x8900B99F, 0x7F0589FB, + 0x000540C3, 0x0D6ECC60, 0x752CFDEF, 0xFE2F0CD6, + 0x0B0E4608, 0xBFC1F84F, 0xD90C700C, 0x706CDA20, + 0x45E1708C, 0xF8AF0C76, 0x40C370CC, 0x1D4C0000, + 0xFDEF0D42, 0x60DD722C, 0x262F700C, 0xD9070347, + 0x706C704C, 0x0C56708C, 0x70ACF8AF, 0x920D2D41, + 0x700CF20D, 0x704CD907, 0x708C706C, 0x0C3E70AC, + 0x268AF8AF, 0x258C0FC3, 0x700C1DFF, 0x744CD910, + 0x708C706C, 0x0C2645E1, 0x70CCF8AF, 0x0387262F, + 0xD907700C, 0x706C704C, 0x0C12708C, 0x70ACF8AF, + 0x920D2E41, 0x700CF20D, 0x704CD907, 0x708C706C, + 0x0BFA70AC, 0x268AF8AF, 0x258C0FC3, 0xD8801DFF, + 0x704CD907, 0x708C706C, 0x0BE270AC, 0x70CCF8AF, + 0x0B8A700C, 0x712CF8AF, 0x78E0C6C6, 0xA023772C, + 0xA021A022, 0xA0207FE0, 0x4628C2E4, 0x21534508, + 0x710C0142, 0xF7EF0C1A, 0xBE23702C, 0x16022644, + 0x8540655D, 0xA5007845, 0x78258501, 0xC6C4A501, + 0x700CC0F1, 0x0E8AD910, 0x714CF8AF, 0x702CD810, + 0xF8AF0E7E, 0x700C714C, 0x0E76D90A, 0x714CF8AF, + 0x7EE0C0D1, 0x752C700C, 0xF8AF0665, 0x78E0714C, + 0x0FAAC0F1, 0x208AF8AF, 0x40C30B04, 0x04888000, + 0xF8AF0FAA, 0x710C9000, 0x1E00702C, 0x901C7004, + 0x0B2204C4, 0x700CF8AF, 0x000040C3, 0x0C06C350, + 0xD90FFDEF, 0x7EE0C0D1, 0x901C41C3, 0x190004C4, + 0x11C00005, 0xE87F8100, 0x800519BC, 0x000040C3, + 0x03E11388, 0x702CFDEF, 0x4030C2F0, 0x41004508, + 0x800040C3, 0x88C01220, 0x02C1219F, 0x47CB40C1, + 0x4E758001, 0x0582209F, 0x67386119, 0x710C882F, + 0x080F78B8, 0xB8022030, 0x00D4216C, 0x2145F003, + 0x095E0154, 0x200FF86F, 0x087B0351, 0x40822030, + 0x12C1259F, 0x1582269F, 0x01012085, 0x2447222F, + 0x700C7B0F, 0xDA22762C, 0x0400244A, 0x250A65DD, + 0x67BE0480, 0x13D32532, 0x10901613, 0xF8AF0A9E, + 0x234470CC, 0xF20CA213, 0x700C65EB, 0xDA22762C, + 0x250A718C, 0x0A860480, 0x70CCF8AF, 0x20D02053, + 0x20B1080D, 0x08F87076, 0xF00DF841, 0x700C8E73, + 0xDA22762C, 0x0500244A, 0x0480250A, 0xF8AF0A5E, + 0x244F70CC, 0x252F2183, 0x7B6F0447, 0x762CD880, + 0x244ADA22, 0x0A460400, 0x70CCF8AF, 0x09EE700C, + 0x712CF8AF, 0x71001600, 0x00068000, 0x000070D3, + 0x41C3257F, 0x57300005, 0x000340C3, 0x20CAD090, + 0x0AE2004D, 0x702CFDEF, 0x78E0C6D0, 0x88945020, + 0x69528801, 0x0F812205, 0xC054900F, 0x00C0206D, + 0x0F832205, 0xC02C903B, 0x2205B100, 0x90070F81, + 0x2444C1F0, 0xBCC11300, 0x2478B100, 0x783B1001, + 0x2205B300, 0x90070F80, 0x7FE0C3EC, 0x78E0B020, + 0x215FC0E4, 0x44CB0A03, 0x113A8000, 0x647970CD, + 0x63959141, 0x0E237D04, 0x231510A5, 0x61990381, + 0x08139123, 0x79DB006E, 0x00412314, 0x91226199, + 0x71C57D25, 0x40A1F1F1, 0x78E0C4C4, 0x901C44CB, + 0x16000004, 0x90047102, 0x94203804, 0x900743C3, + 0xBAA0F804, 0x7A05B9A0, 0xB3407825, 0x7FE0B400, + 0x00051B04, 0xE81EC2E2, 0x740CD9BF, 0xFA2F0E02, + 0x700CB912, 0xD92572AD, 0x8940B99F, 0x7A25893B, + 0x7918712C, 0x210FB902, 0x794B0001, 0x09FAF206, + 0x712CF9AF, 0xFB8F091A, 0x1BFF258D, 0xC6C2710C, + 0x02FB41C3, 0x0DCA0000, 0xD80AFA2F, 0x1A43256F, + 0xFC2F0E5A, 0x14051D00, 0x081ED807, 0x1A060020, + 0xD8103043, 0x30031A06, 0xB500B88F, 0xFEAF0B3E, + 0xC6C2740C, 0xC1B6C3F6, 0xD8404608, 0x1000B89F, + 0x0ABA0095, 0x10E50160, 0x70148092, 0x20CAD80C, + 0x267C01A2, 0x1A0B1393, 0x2E013002, 0x00007380, + 0x20443679, 0x0E150051, 0x230411F1, 0x16002453, + 0x80007080, 0xE88D0161, 0x73146E0B, 0x000D0212, + 0x70801600, 0x01608000, 0x02067014, 0x0DC20001, + 0x712CF8EF, 0x23524708, 0x26792001, 0x782B11C0, + 0x708EDDFF, 0x0D46F407, 0xE805F80F, 0x1FC7258A, + 0x088A718E, 0x730CFAEF, 0x08336E0B, 0x26790135, + 0x26791141, 0x200410C0, 0x6E0D0050, 0x00B5082D, + 0x09A6702C, 0x70140140, 0x70801600, 0x01818000, + 0x21CA742C, 0xE88F01E2, 0xE687F00F, 0xE68CF2E5, + 0x00E10B50, 0xF00E40A1, 0x70801600, 0x01828000, + 0x1A0BE803, 0x78F03002, 0x430242A1, 0xFD8F0A96, + 0x1381267D, 0x20002178, 0x24952505, 0x00122105, + 0x70EE70AD, 0x800040D3, 0x72F61220, 0x00260124, + 0xA5C02511, 0x40E2F28B, 0x08AE4162, 0x1801F9AF, + 0x08B22342, 0x4610FBAF, 0x702CC082, 0xF7AF0CA2, + 0x0FEADA50, 0x730CFAAF, 0x13950ED3, 0x03802025, + 0xF024F019, 0xF063F027, 0xF061F061, 0xF05FF05F, + 0xF037F025, 0xF042F004, 0xF002F059, 0x79F078AF, + 0x0AF64282, 0x43C10020, 0x13500E9B, 0x12D00E8B, + 0x78AFF04D, 0xFF6F0DF6, 0x700CC182, 0xF8EF0D8A, + 0x710C712C, 0xF027712C, 0x08EE78AF, 0xC18201E0, + 0x08E2F03D, 0x78AF01E0, 0x78AFF039, 0x714CC180, + 0x0B52706C, 0x4110FBAF, 0xC1804022, 0x716C714C, + 0x30011C04, 0xFBAF0B3E, 0x30011C00, 0x78AFF027, + 0xFF6F09EE, 0x700C4182, 0xF8EF0D3E, 0x710C702C, + 0x0D36702C, 0xF01BF8CF, 0x70801600, 0x00098000, + 0x78AFB8E3, 0x0CFEF404, 0xF0070040, 0x428279F0, + 0x00200A66, 0x1600DB0B, 0x80007080, 0x080F017C, + 0xCC22001E, 0x1A227104, 0x730C301C, 0xFAAF0F0E, + 0x20031800, 0xE88BCA0A, 0x70811600, 0x00048000, + 0x40427BAF, 0xFA6F0EB6, 0x71A542C2, 0xF16F71E6, + 0x12D00E0B, 0x13500E13, 0x1600F00E, 0x80007080, + 0x0815017C, 0x1600001E, 0x80007080, 0xB8E60001, + 0xF8C20A6C, 0x70801600, 0x00018000, 0x0970B8E6, + 0x40C1F8E2, 0x70031E00, 0x000F8000, 0x1600C7D6, + 0x80007080, 0xE8070163, 0xF203E68D, 0x05F2E68A, + 0x1600FFC1, 0x80007080, 0xB8E20001, 0x05EB70ED, + 0x27CAFFEF, 0x0E4E13E1, 0x2079F90F, 0x28400000, + 0x16000256, 0x80007080, 0xE8040183, 0x30021A0B, + 0x23562605, 0xBD9FDDF4, 0x08338D00, 0x085A005F, + 0xE8150140, 0x02DF41C3, 0x0AE60000, 0x740CFA2F, + 0x10901500, 0x204F702C, 0x42C22040, 0x78F0AD00, + 0xFDAF08A2, 0x1D00726C, 0x78F01402, 0x42C2702C, + 0xFFEF05FD, 0x78E0726C, 0xC1A1C3F4, 0x43304550, + 0xFAEF081A, 0x70CD4210, 0x800040D3, 0x22531138, + 0x708E204D, 0x800047CB, 0x0B351220, 0x18002030, + 0x16002382, 0x80007080, 0x0825001B, 0x708E007E, + 0xFCEF0B56, 0x8F404042, 0x750C4410, 0x017741C3, + 0x43420003, 0xFA2F0A6A, 0x0500240A, 0x41624042, + 0x0DD2704C, 0x2578FCEF, 0x71561096, 0x000341C3, + 0xC80808D8, 0x082221D6, 0x8F207825, 0x7825B90C, + 0x016009D2, 0x7DD0D940, 0xE5FF708D, 0x002D00A8, + 0x11C0234A, 0x2005C808, 0x8F000301, 0x7825B80C, + 0x0F802005, 0x00D80003, 0x016009AA, 0x238D41A1, + 0x24561D3F, 0x0EFA180C, 0x40C2FECF, 0x734CC180, + 0x708C4362, 0xF7EF082A, 0x1400702E, 0x25553009, + 0xD8071803, 0x10C82D41, 0x2006BB23, 0x244A034B, + 0x20A871C0, 0x29010900, 0x29401440, 0xB8C02142, + 0x02CC2800, 0x209F8F00, 0x70A20803, 0x70016058, + 0x79858820, 0x2140A820, 0x29012200, 0x71261000, + 0x2800B8C0, 0x8F0002C1, 0x0803209F, 0x621A70A2, + 0x88406278, 0xA8207945, 0x800040C3, 0x88000484, + 0xF1AB661E, 0x7885C808, 0x0F802005, 0xF0D80003, + 0x01600912, 0x238D702C, 0x24561E3F, 0x0E62180C, + 0x4042FECF, 0x085E702C, 0x1800FB2F, 0x40822043, + 0x78E0C7D4, 0x2482C3F8, 0x46503617, 0x47104130, + 0x3F802400, 0x03800000, 0xDA78702C, 0xF7AF0962, + 0x30C01CD4, 0x2400702C, 0x00003F80, 0x09520308, + 0xDA78F7AF, 0x2400702C, 0x00003F80, 0x09420290, + 0xDA78F7AF, 0x300014D4, 0x0819704E, 0x700F02B1, + 0x70981600, 0x000C8000, 0x30012084, 0x31982841, + 0x300514D4, 0x42E2740C, 0x01D641C3, 0x43220005, + 0x0580240A, 0xFA2F08EA, 0x0600260A, 0x702C710C, + 0x05D32800, 0xF96F0CF2, 0x084B40E2, 0x1CD83031, + 0xC0823000, 0xFBEF0FC6, 0x14C841E2, 0x42C33101, + 0x00009038, 0x7905C808, 0x7945B902, 0x216D9120, + 0x14CA0A10, 0x78253101, 0x01D741C3, 0xB8020002, + 0x92007A05, 0x206D4202, 0x740C0A0D, 0xFA2F0892, + 0x14D443A1, 0x2B403000, 0x0F122093, 0x2079FA2F, + 0x1C5A034E, 0x16003018, 0x80007080, 0x206D0009, + 0x70140940, 0x30001CE0, 0x006120CA, 0x30001CE0, + 0x300014D4, 0x03510815, 0xB802C808, 0x0F802005, + 0xC234903B, 0x00451800, 0x0CFE7FDB, 0x230F0120, + 0x1CDC25D4, 0x24003000, 0x00003F80, 0x702C0218, + 0xF7AF084E, 0x45D3DA78, 0x12228000, 0x303008BD, + 0x1E00DA60, 0x90077484, 0x1E00C17C, 0x901C7045, + 0xC80804A8, 0x800041C3, 0xB8020EAB, 0x0F802005, + 0x0504901C, 0x00451800, 0x70C51E00, 0xC164900B, + 0xF76F0FF6, 0x3E402455, 0x3E402455, 0x01A0086E, + 0x710CD960, 0xFFAF0C52, 0x212F712C, 0x700C0507, + 0x09DA704C, 0x4330F9EF, 0xF82F0CF6, 0x43104062, + 0x20801501, 0x20821500, 0x00A408C3, 0x27407842, + 0x6821280C, 0x240AC808, 0x20A87040, 0x2A4007C0, + 0x24000301, 0x00003F83, 0x61990210, 0x79057B54, + 0xB992B902, 0xB99FB99C, 0xB3209120, 0x8005218C, + 0x003C238A, 0x00CD21C0, 0x3F832400, 0x02080000, + 0x71447B54, 0xF03BB320, 0x308714D1, 0x2507232F, + 0x308314CC, 0x3E412455, 0x04C0240A, 0x32052440, + 0x308214CF, 0x0580260A, 0xF9AF0F4A, 0x300014DC, + 0x308714D1, 0x3F812400, 0x01840000, 0x308314CD, + 0x04C0240A, 0x34052440, 0x0580260A, 0x308214CF, + 0xF9AF0FB2, 0x300014DC, 0x36001440, 0x30181C68, + 0x308014E9, 0x710CE80B, 0x34801CEC, 0x1C63B890, + 0x1CF03498, 0x1C643000, 0xBD083018, 0xE70D6E06, + 0x2447212F, 0x33581C5B, 0x22102840, 0x1C5D70AD, + 0x1C5E3018, 0x1C5C33D8, 0x145E3418, 0x75103600, + 0x000604A0, 0x3600145D, 0x790E78A2, 0x300014E0, + 0x00012908, 0xF048262F, 0x7017F4AD, 0x40C3F2AD, + 0x0E9C8000, 0x68346508, 0x212F7825, 0x0C4E0507, + 0x780FFFAF, 0xF86F0E36, 0x0E42D8C8, 0x202FF86F, + 0x150104C8, 0x1C602081, 0x15003498, 0x09352080, + 0x1C5F0024, 0x79023498, 0x240A7124, 0x20A87040, + 0x28400480, 0x21050381, 0x90040F82, 0x24003DD0, + 0x00003F81, 0x21F40208, 0x71040001, 0xB220E120, + 0xFECF0B92, 0x0AFED80F, 0xD90FF92F, 0x0086208A, + 0x900746CB, 0xB600C2C4, 0x096AD840, 0x712CF86F, + 0x20811501, 0x20801500, 0x00240931, 0x71247902, + 0x7040240A, 0x048020A8, 0x03812840, 0x3F832400, + 0x017C0000, 0x21057B14, 0x90040F82, 0x922001D0, + 0xB3207104, 0xB220E120, 0xFECF0B3A, 0x0AA6D80F, + 0xD90FF92F, 0x712CD882, 0x091AB600, 0xD840F86F, + 0x208E1500, 0x20801501, 0x03A40877, 0x0DAA78AF, + 0x4010F9CF, 0x13802E40, 0x0F8F2005, 0x01D09004, + 0x3F802400, 0x017C0000, 0x20F49720, 0x78220380, + 0x88012054, 0x0023000E, 0x26024420, 0x00007001, + 0xD840FFC0, 0x483142C1, 0x3F802400, 0x02180000, + 0x430278B6, 0xB02078D4, 0x01DC41C3, 0x0D820003, + 0x740CF9EF, 0x3F802400, 0x02100000, 0x038020F4, + 0x1501B700, 0x76102080, 0xFFE5079C, 0x0AA671C5, + 0x71A5FECF, 0x702CF143, 0x3F802400, 0x05880000, + 0xF76F0D6E, 0x702CDA50, 0x3F802400, 0x05380000, + 0xF76F0D5E, 0x702CDA50, 0x3F802400, 0x04E80000, + 0xF76F0D4E, 0x702CDA50, 0x3F802400, 0x04980000, + 0xF76F0D3E, 0x702CDA50, 0x3F802400, 0x04480000, + 0xF76F0D2E, 0x702CDA50, 0x3F802400, 0x03F80000, + 0xF76F0D1E, 0x14D4DA50, 0x08773000, 0x6D340371, + 0x3600145B, 0x254E7905, 0x20051300, 0x145C004B, + 0x78103601, 0xB80479A5, 0x36091208, 0x15007825, + 0x7E3B2081, 0x43C3710D, 0x00009038, 0x034F2940, + 0x20811501, 0x10482014, 0x13A40857, 0x124C2705, + 0x310214C8, 0x10082796, 0x14D871C5, 0x61593001, + 0xB9027985, 0xB1007965, 0x310214CA, 0x300114D8, + 0x79856159, 0x7965B902, 0x02C41900, 0x40C3F1E6, + 0x0E9C8000, 0x14D46508, 0x68343002, 0x212F7825, + 0x0A190507, 0x780F02B1, 0xFF8F0A12, 0x0886F003, + 0x268AFB4F, 0xF0051FC7, 0xFF8F089A, 0x14CCDE7F, + 0x24553081, 0xC2823E40, 0xF9AF0B56, 0x3E4F2455, + 0x300014DC, 0x14CCE825, 0x42E23081, 0x2440C382, + 0x14CF3604, 0x250A3080, 0x70CC0580, 0xC74170EC, + 0xFBAF0CEE, 0x2455C640, 0x41E23E40, 0x2400704C, + 0x00003F84, 0x24000588, 0x00003F85, 0x24000538, + 0x00003F86, 0x09BE04E8, 0xC386FBEF, 0x081AF024, + 0x14D00200, 0x222F3087, 0x14CC0507, 0x43223081, + 0x3604145A, 0x32052440, 0x308014CF, 0x0580260A, + 0xF9AF0FB6, 0x2400C740, 0x00003F81, 0x24000588, + 0x00003F82, 0x24000538, 0x00003F83, 0x0C6204E8, + 0xC086FB2F, 0x308114CD, 0x3F802400, 0x01840000, + 0x3F8F2400, 0x01840000, 0xF9AF0AA6, 0x14DCC284, + 0xE8283000, 0x308114CD, 0xC38442E2, 0x38042440, + 0x308014CF, 0x0580250A, 0x71EC70CC, 0x0C42C741, + 0xC640FBAF, 0x240041E2, 0x00003F80, 0x714C0184, + 0x3F842400, 0x04980000, 0x3F852400, 0x04480000, + 0x3F862400, 0x03F80000, 0xFBEF090A, 0xF025C388, + 0x01C00F66, 0x308714D0, 0x0507222F, 0x308114CD, + 0x145A4322, 0x24403604, 0x14CF3405, 0x260A3080, + 0x0F060580, 0xC740F9AF, 0x3F812400, 0x04980000, + 0x3F822400, 0x04480000, 0x3F832400, 0x03F80000, + 0xFB2F0BAE, 0x1501C088, 0x14CE2087, 0x15003084, + 0x74F0208C, 0xFFED058E, 0x245A706D, 0x24001286, + 0x00003F8F, 0x24000308, 0x00003F8E, 0x7FB60380, + 0x7F947EB6, 0x218A7E94, 0xD97F1FC1, 0x11250B6D, + 0x9040210C, 0x20310E11, 0x16802400, 0x0080101C, + 0x10000B55, 0x11882300, 0x3F802400, 0x05380000, + 0x020220F4, 0x3F802400, 0x04E80000, 0x020020F4, + 0x96004853, 0xB6006078, 0x3F802400, 0x04480000, + 0x020220F4, 0x3F802400, 0x03F80000, 0x020020F4, + 0x97407842, 0x7810621A, 0x02492009, 0x20097870, + 0xB7400041, 0xF1CC7165, 0x9700F745, 0x4121B600, + 0xF407F007, 0x96209700, 0x804408F5, 0x2400F1F9, + 0x00003F80, 0x78B60290, 0x71857894, 0xF1A3B020, + 0x30300847, 0x3E402455, 0x74841E00, 0xC164900B, + 0x6832C808, 0x901C40C3, 0x79050504, 0x04841900, + 0x18A4D920, 0x40C38484, 0xC17C9007, 0x00451800, + 0x74841E00, 0xFED49007, 0x005C1886, 0xFF2F0B96, + 0x049C1886, 0x09B2F005, 0x14CCF9AF, 0x15003081, + 0x40C3208F, 0x07070707, 0x30181C5F, 0x20801501, + 0x3F8E2400, 0x017C0000, 0x02507710, 0x41E2002D, + 0x70AD66FE, 0x708E714E, 0x70CE706E, 0x3600145D, + 0x790E78A2, 0x300014E0, 0x00012908, 0xF048262F, + 0x081DF434, 0x42E13030, 0x3F802400, 0x02180000, + 0x20F478B6, 0x210A03D0, 0xF01B2400, 0x3F802400, + 0x03800000, 0x41C378B6, 0x000401E5, 0x20F443A1, + 0x240003D1, 0x00003F80, 0x78B60290, 0x0440250A, + 0x03D020F4, 0x095A740C, 0x240AF9EF, 0x200C0400, + 0xF705A580, 0x0B21F410, 0xAEA02445, 0x260A718E, + 0x230A2400, 0x714E2440, 0x145E71A5, 0x0D813600, + 0xF00D9004, 0x20300C13, 0xA580200C, 0xA4C121CC, + 0x206122C0, 0x708EF3F2, 0x202FF1F0, 0x68290487, + 0x300014E0, 0x8E00790C, 0x783D7914, 0x7D0FAE00, + 0x300014D4, 0xF48AE08D, 0x41C3740C, 0x000301E6, + 0x43A142E1, 0xF9EF08EA, 0x04C0240A, 0x41C3740C, + 0x000201E7, 0x08DA42E1, 0x43A1F9EF, 0x37041222, + 0x01E841C3, 0x202F0003, 0x42E10100, 0x43A178F6, + 0x800170C3, 0xB0A04D44, 0xF9EF08B6, 0x14C8740C, + 0x2F403101, 0x12081348, 0x254E360B, 0x14D81306, + 0x23053000, 0x60381203, 0x3601145C, 0x46CB7865, + 0x00009038, 0x79A5B802, 0x01022E40, 0x7A2578C5, + 0x1F892000, 0x10000000, 0x2305B040, 0x14C8124C, + 0x14D83100, 0x60383001, 0xB8027885, 0xB04078C5, + 0x310014CA, 0x300114D8, 0x6D346038, 0x145B7865, + 0xB8023603, 0x01832305, 0x7B2578C5, 0x14CAB060, + 0x14D83101, 0x60383000, 0xB8027885, 0xB06078C5, + 0x70801600, 0x017C8000, 0x001F08AB, 0x70801600, + 0x00098000, 0x013F089F, 0x15CB2305, 0x903840C3, + 0x23051540, 0xBC02120C, 0x10012405, 0x2305B140, + 0xB9021241, 0x000D2105, 0x08002054, 0x79057C05, + 0xB460B540, 0xF037B160, 0xF9AF0FBE, 0x460840A1, + 0x300014D4, 0x02B1081F, 0x0837740C, 0xD8403030, + 0x01E941C3, 0x20020003, 0x740C04C4, 0x43A142E1, + 0x41C3F017, 0x000301EC, 0x43A142E1, 0xF9AF0FB2, + 0x04C0240A, 0x41C3740C, 0x000201ED, 0x740CF00F, + 0x01EA41C3, 0x42E10003, 0x240A43A1, 0x0F9204C0, + 0x740CF98F, 0x01EB41C3, 0x42E10002, 0xF9AF0F82, + 0x05AD43C1, 0x71E5FFEF, 0x3F802400, 0x017C0000, + 0x016009D2, 0x300214D4, 0x30310897, 0x0B7A40E2, + 0x702CF92F, 0x4210D939, 0x0F56B913, 0x740CF9AF, + 0x20901500, 0x24132240, 0x24922240, 0x1407272F, + 0x20801501, 0x03E40863, 0x13112F40, 0x275F70AD, + 0xC0821501, 0x43A142E1, 0x740C603E, 0x41C37EB4, + 0x000401C9, 0x11051620, 0xF9AF0F16, 0x11041670, + 0x12012D40, 0x2105C808, 0x43C30441, 0x00009004, + 0x71A57825, 0x04812005, 0x04C02005, 0x96306952, + 0xB8027A65, 0x7865B220, 0x11011670, 0x92740DB3, + 0x7106B020, 0x0C1EF1CC, 0x0CC2FE8F, 0xC7D8FF0F, + 0x1CFCC2FA, 0x2482B6C8, 0x40103D06, 0xDA78702C, + 0x3F802400, 0x013C0000, 0xC1504528, 0xC14EC14F, + 0xC14CC14D, 0xC14AC14B, 0xF72F0EC6, 0x2455C149, + 0x702C3C40, 0xF72F0EBA, 0x2455DA78, 0x702C3880, + 0xC548DA3C, 0xF72F0EAA, 0xC093C547, 0x0EA2702C, + 0xDA3CF72F, 0xC552712C, 0x70441E00, 0x04A8901C, + 0xC546C808, 0x6852C545, 0x0F802205, 0x0504901C, + 0x2205B020, 0x90040F80, 0x90000090, 0x0F832205, + 0xC0909007, 0xB888C042, 0x1600B300, 0x80007083, + 0x16000004, 0x80007080, 0x0811017C, 0x2205001E, + 0x903B0F80, 0xB020C234, 0x040E2900, 0x7FCFBBC3, + 0x40E1752C, 0xF9EF0D7E, 0x44D3C343, 0x12228000, + 0x208D1400, 0x35112440, 0x20801401, 0x03640841, + 0x160040E1, 0x80007080, 0x083112D9, 0x4002036E, + 0xFBEF0A12, 0xE81241A1, 0x742C78AF, 0xFEAF0D86, + 0x42004202, 0x23402114, 0x41C343A1, 0x000201A7, + 0x0DCEB040, 0x750CF9AF, 0xF1E071A5, 0xF9EF0D26, + 0x1400762C, 0x706F208D, 0x20801401, 0x0364084D, + 0x16006E12, 0x80007080, 0x083D12D9, 0x4002036E, + 0xFBEF09C2, 0xE81841A1, 0x20F4C085, 0x08290340, + 0x78AF0071, 0x0D2E742C, 0x4202FEAF, 0x750C4708, + 0x41C342E1, 0x000201A8, 0xF9AF0D76, 0x0F0943A1, + 0x716F11D1, 0xF1DA71A5, 0x78CF7E05, 0xF7EF09EE, + 0xC044C040, 0x060640C3, 0xC0510606, 0x2005C808, + 0x14B70400, 0xB8022097, 0x0F802005, 0x15409038, + 0x01181000, 0x1401D80D, 0x2084208F, 0xC041300C, + 0x20831400, 0x35C7212F, 0xDEC0C808, 0x040B2005, + 0x10C40F9B, 0x30EE0993, 0x2B40C591, 0x65690342, + 0x06002105, 0x4E31B904, 0x22057905, 0x284002C0, + 0x22960088, 0x20050008, 0x90381F80, 0xB0201540, + 0x20056568, 0xB8040601, 0x79054E10, 0x02C02205, + 0x42C36892, 0x15809038, 0x1F802405, 0x15409038, + 0x6568B020, 0x06012005, 0x4E10B804, 0x20057905, + 0xB0201080, 0x65687A85, 0x06012005, 0x4E10B804, + 0x702C7825, 0xC08DB200, 0xB0207874, 0x7874C08F, + 0xC08BB020, 0xB0207874, 0x7874C089, 0x30300B0B, + 0x1800B020, 0x71640045, 0x70CDF1B4, 0x1F802632, + 0x0E9C8000, 0x78256834, 0x08BAC100, 0x780FFF6F, + 0xF82F0C0A, 0x0C16D8C8, 0xC004F82F, 0x0F96700C, + 0x712CF7EF, 0x089EC100, 0x700CFF6F, 0x0BB6C000, + 0xD91AF9EF, 0x704E72AE, 0x20100A0F, 0x70801600, + 0x00408000, 0x212FE827, 0x40020480, 0xFBEF0856, + 0x46104130, 0x20532140, 0x41227014, 0x04C121CA, + 0x742C782F, 0xFEAF0BBE, 0xC5924202, 0x75224708, + 0xB5004102, 0xFC2F0D12, 0xE80D4042, 0x23CA70D6, + 0x202F2441, 0x742C04C7, 0xFEAF0B9A, 0x78E54202, + 0x258DB500, 0x714E253F, 0xF9AF0BBE, 0x140078CF, + 0x4110208D, 0x20801401, 0x01347510, 0x2111002D, + 0xF294B340, 0x208F1403, 0x0FEA4002, 0x41A1FBAF, + 0x1342273C, 0x21F4C192, 0x2078008C, 0x781B0000, + 0x38822455, 0x73046862, 0x10C12C01, 0x21447C19, + 0x255A0043, 0xC09313C1, 0x6119623A, 0x61D862DA, + 0x2444AA60, 0xA8401042, 0x78B4C08B, 0x09299020, + 0x438900E0, 0xC08FB060, 0x902078B4, 0xB0806981, + 0x178C255A, 0x3F802400, 0x013C0000, 0x78346098, + 0x04441800, 0x78B4C089, 0x09239020, 0xB0400080, + 0x78B4C08D, 0x69819020, 0x255AB080, 0x2455178C, + 0x60983C40, 0x18007834, 0x0E910444, 0xC18F13B1, + 0x910079B4, 0x0050083D, 0x7074E88F, 0x1783255A, + 0x0E7F208A, 0x3F812400, 0x013C0000, 0x01E120CA, + 0xB1006179, 0xEB8EF00E, 0xB1606861, 0x1783255A, + 0x3F812400, 0x013C0000, 0x79146179, 0x01C51900, + 0x78B4C08D, 0xE9179020, 0x32C22305, 0x16CB2304, + 0x10032378, 0xF41A7A6B, 0x00700931, 0xB0406941, + 0x1782255A, 0x3C402455, 0x78346058, 0x01C51800, + 0x7054F00C, 0x1782255A, 0x0E7F208A, 0x3C412455, + 0x01E120CA, 0xB1006159, 0xF16671A5, 0xE68F71C5, + 0xFFC5061C, 0x41C3750C, 0x000101B4, 0xF9AF0A92, + 0x41C34202, 0x000001B5, 0xF9AF0A86, 0x70AD740C, + 0x0A56DE0F, 0x78AFF9AF, 0x41C34200, 0x000101B6, + 0xF9AF0A6E, 0x268D740C, 0x71A51DFF, 0x01B741C3, + 0x0A5E0000, 0x740CF9AF, 0x20911400, 0x215FC693, + 0x245523CD, 0x66BE3880, 0x1401651D, 0x0F71208F, + 0x740C1464, 0x01B841C3, 0x0A360001, 0x4222F9AF, + 0x42B1DF0F, 0x24821201, 0x01B941C3, 0x0A220001, + 0x740CF9AF, 0x1E3F278C, 0x740CD9DD, 0xF9AF0A12, + 0x740CB911, 0x01BB41C3, 0x0A060001, 0x4222F9AF, + 0x42D1DF0F, 0x24821201, 0x01BC41C3, 0x09F20001, + 0x740CF9AF, 0x1E3F278D, 0x41C3740C, 0x000001BD, + 0xF98F09DE, 0xE50FE60F, 0xF1C97126, 0x208D1400, + 0x13640FAB, 0x42A14FB0, 0x240A7104, 0x20A87000, + 0x096D0E40, 0xC08F30AE, 0x008120F4, 0x00B40925, + 0x0783225A, 0x3F802400, 0x013C0000, 0x20146078, + 0x98800041, 0x814111FE, 0x2C44643C, 0xB0201081, + 0x20F4C08D, 0x2455008C, 0x60783C40, 0x10B40C17, + 0x20149820, 0x14FE030C, 0x6199914C, 0x00812944, + 0x2400B020, 0x00003F8C, 0xC087013C, 0x10C32435, + 0x7854792E, 0x2B44633B, 0xB0200081, 0xC6877144, + 0x091F7EB4, 0x740C336E, 0x11441600, 0x41C34202, + 0x000301C1, 0xF9AF093A, 0x140143A1, 0x72C5208F, + 0x71A575F1, 0x1400F7AF, 0x0F99208D, 0xC1871364, + 0x79B44FB0, 0x240A7104, 0x42A17000, 0x034020A8, + 0x308E0913, 0x080B9900, 0xB8830052, 0x7813F002, + 0x7224B100, 0xF0367144, 0x270479B8, 0x262F2040, + 0xF22DF007, 0x70801600, 0x017C8000, 0xC08FE809, + 0x034020F4, 0xC08DE808, 0x034020F4, 0x2706E804, + 0xF01D2057, 0xC287C191, 0x22F561B9, 0x0A190342, + 0x890001F2, 0x03310815, 0x700C7104, 0x01C241C3, + 0xF00A0001, 0x7704E804, 0xF009A900, 0x41C3700C, + 0x000101C3, 0xF72F0DA2, 0x140142A1, 0x71A5208F, + 0x93650F99, 0xC001712C, 0x262F7704, 0xC041F007, + 0x262FF205, 0x034CF5C7, 0x1600FFC2, 0x80007080, + 0x0895017C, 0x1400001E, 0x0F8D2081, 0xC8081044, + 0x903841CB, 0x160015C0, 0x80007088, 0x200512D9, + 0x4F30040B, 0x240A7104, 0x20A87000, 0x08670D80, + 0xC491106E, 0x034D2940, 0x2205642A, 0x6A740600, + 0x4A76DAC0, 0x25057E05, 0x687212C0, 0x10082596, + 0x02402305, 0x6428B0C0, 0x060E2005, 0x4A10B804, + 0x25057E05, 0x68B212C0, 0x12402505, 0x6428B0C0, + 0x060E2005, 0x4A10B804, 0x21547E05, 0x7B051800, + 0xB3C078A5, 0x2305642B, 0xBB04060C, 0x7A857A62, + 0x7124B040, 0x716E70ED, 0xEF08724E, 0x70801600, + 0x00408000, 0x00100879, 0x40027EFB, 0xFBAF0BE6, + 0xC18741C1, 0x894079D4, 0xE8058922, 0x7D4569B4, + 0x6AB4F003, 0x710C7D25, 0x0B1278F8, 0x780FFA2F, + 0x2347212F, 0x4202750C, 0x01C541C3, 0x43E10003, + 0xF96F0F8E, 0x0440240A, 0x0BCAC100, 0x4022FF2F, + 0x205FC003, 0x60D80B00, 0x70827002, 0x20300815, + 0x0B27A8B6, 0x1E002010, 0x80007342, 0xF00800F7, + 0x20100B21, 0x73421E00, 0x00F28000, 0x228D71ED, + 0x706E2FFE, 0x1E00F00A, 0x80007342, 0xF0060101, + 0x73421E00, 0x00FC8000, 0xFA2F0AA2, 0xC808730C, + 0x2005B802, 0x90070F81, 0xC002C090, 0x2480B100, + 0x14043D06, 0xC6DA341B, 0x1CFCC2FA, 0xC1A5B6C8, + 0x702CC140, 0x0D5AC044, 0xC000F9AF, 0x1443256F, + 0x8D00C043, 0x900747CB, 0x2078C2C0, 0xD90F0100, + 0xE030B802, 0x0B9EB700, 0xD80FF8AF, 0x71AED9FF, + 0x208A700E, 0xB7320FC7, 0x15441F28, 0x94041FDC, + 0xB708B706, 0x15441F04, 0x7054C200, 0x093E711C, + 0x710CFF2F, 0xFACF0ADE, 0x1097150E, 0x720C776E, + 0x800046CB, 0x46D31220, 0x12D98000, 0x34041C0A, + 0x34041C08, 0x8E00C041, 0xD840E803, 0xD825F002, + 0x2D00B89F, 0xB9022401, 0x040D210F, 0x7D0B8800, + 0x40C3F2A1, 0x12DC8000, 0x40028020, 0x0F76C200, + 0xC300FBEF, 0x7DAFC203, 0x0872700C, 0x41A1F96F, + 0xF78F083E, 0x702C700C, 0xF92F0BB2, 0x450842A1, + 0xF7EF0DEA, 0x0DF6D8C8, 0x78B0F7EF, 0x329B2440, + 0x32192440, 0x341B2300, 0x34192100, 0x70AD700F, + 0x6892C808, 0x1F802405, 0xC034901F, 0x8E23B0A0, + 0x09338E02, 0x79020024, 0x20831600, 0x28406941, + 0x240A0381, 0x20A87080, 0x0B1303C0, 0x2405002E, + 0xBA921042, 0xBA9FBA9C, 0x7104B2A0, 0x000071C3, + 0x09864000, 0xD814FD2F, 0xFE8F0F8A, 0x712CC004, + 0xF7EF08EA, 0x8E027810, 0x4110704E, 0x03942840, + 0x083F8E03, 0xD80F0464, 0x20801600, 0x044E0827, + 0x2F802405, 0x02F49004, 0x22059000, 0xE88B2012, + 0x41C3740C, 0x0003024B, 0x43224202, 0xF96F0DA2, + 0x712644A1, 0x2F942400, 0x40000000, 0x0A46F1E2, + 0xD90FF8AF, 0x3011082D, 0x20310A33, 0x15C02500, + 0x7A10702C, 0x0EEE4002, 0x4150FEEF, 0x712C4002, + 0xFEEF0EE2, 0x1B004222, 0x23083342, 0xF0062353, + 0x20110A0B, 0x33421900, 0x71A5710F, 0x98D40D25, + 0x41C34003, 0x00010250, 0xF72F0A4E, 0x0F164202, + 0xC001F90F, 0x7704710E, 0xC0417014, 0x202FF54D, + 0x41C304CA, 0x00000252, 0xF72F0A2E, 0x202FB83F, + 0x43C304C7, 0x01328000, 0x140B70E2, 0x2049308D, + 0xC0220881, 0x140A4832, 0x49103080, 0x00802009, + 0xAB02AB00, 0x6852C808, 0x30801409, 0x0F8C2205, + 0xC034901F, 0x4834B420, 0x200949B0, 0xAB010300, + 0x8E03AB03, 0x08378E62, 0x786200E4, 0x038D2B40, + 0x40C36881, 0x12D98000, 0x240A88C0, 0x20A87300, + 0x0E1303C0, 0x220510EE, 0xB8920340, 0xB89FB89C, + 0x7164B020, 0x000075C3, 0x0E4A4000, 0x700CFE8F, + 0xB708B706, 0xC0A5B702, 0x341B1404, 0x78E0C6DA, + 0x1CFCC2FA, 0xC1BBB6C8, 0x710C4018, 0x01402800, + 0x2140250A, 0x160068B2, 0x80007080, 0x260A0162, + 0x44702100, 0x47304158, 0xB203208C, 0x31801C68, + 0xE899F403, 0xE809F009, 0xBD41208C, 0xBF8220CC, + 0x00700000, 0x2050F20F, 0x204A3080, 0x208C21C0, + 0xF40D8802, 0x70801600, 0x01648000, 0x80802053, + 0x0CAEF205, 0x712CF82F, 0x26424010, 0x250F20C0, + 0x212F1553, 0x08232007, 0x706F0135, 0x40C3790D, + 0x0FA08000, 0x02022040, 0x004D20F4, 0x005222F4, + 0xBB8E736C, 0x736CF006, 0x000045CB, 0x704EFFFF, + 0x44CB710C, 0xFE030000, 0xB60A468B, 0x000041C3, + 0xB604F0B0, 0x1C5C6943, 0x276F3004, 0x1C441443, + 0xB61C3004, 0x6C0AB610, 0x40C3B60F, 0xFFB50001, + 0xB969B629, 0x2258B643, 0xC0400B02, 0x000140C3, + 0x1C4EFE04, 0x24403084, 0xB63B1282, 0xB662489A, + 0x000743C3, 0xC058F004, 0x1C42B864, 0x42C33084, + 0xF0B40001, 0x6B0BC04C, 0x6A0BC049, 0x8F00C046, + 0x01002078, 0xB61AC152, 0xB617B962, 0xE030B802, + 0xB60BC14F, 0xD966C080, 0x33041C5A, 0x31C51C50, + 0x31C51C2C, 0x36C41C2A, 0x36C41C10, 0x1C0AC243, + 0x1C6436C4, 0x1C5E36C4, 0x1C5836C4, 0xC35536C4, + 0x36C41C52, 0x36C41C4C, 0x36C41C46, 0x36C41C40, + 0x36C41C3A, 0x31851C28, 0x30851C22, 0x00E00BAE, + 0x30C51C1C, 0x4142D80F, 0x43424242, 0xFB6F0BD2, + 0x0480240A, 0x722C700C, 0x706C704C, 0x0C1A44A1, + 0x45A1FB6F, 0x14C7262F, 0x12012D41, 0x704C78AF, + 0x0922706C, 0x44C1FF2F, 0x2102217D, 0x0407212F, + 0xFE2F0E96, 0x40C240C1, 0xF8AF0B12, 0x45CB41A2, + 0x4DAC8001, 0x0B2B43B1, 0x212F3135, 0x0C5606C7, + 0x4082FF2F, 0x7280244A, 0x20A8702C, 0x080B0240, + 0x1D00004E, 0x72A515C4, 0x71677124, 0x0F9FF1ED, + 0x46EA2030, 0xB203208C, 0x4082F406, 0x00E00C82, + 0xF010702C, 0xBC01208C, 0x40C2F406, 0x01600846, + 0xF0084182, 0x410340A2, 0x08CE4223, 0x706C0160, + 0xBC01208C, 0x76F2F205, 0xFE610EBC, 0x0EBA4082, + 0x4082FE6F, 0x2A102354, 0x2382222F, 0x456A702E, + 0x21350945, 0x0447212F, 0xFF2F0BDA, 0x704C4082, + 0x02950A2D, 0x008E081D, 0x20832033, 0xE90DC11A, + 0x00520B0B, 0x79C29520, 0x9520B520, 0xB5207142, + 0x714472A5, 0x0BF7F1EE, 0xF1F68013, 0x22902040, + 0xF1E07126, 0xA0310A71, 0x208C464A, 0xF407B203, + 0x0BEE4082, 0x702C00E0, 0x208CF00F, 0xF407BC01, + 0x0FB240C2, 0x41820120, 0x40A2F007, 0x42234103, + 0x01600836, 0x704C706C, 0x900741C3, 0x1924C29C, + 0x706C0015, 0x70841E00, 0xFED49007, 0x708C8F00, + 0x01002078, 0x1904B802, 0xD80F0014, 0xB144B140, + 0x1E00B146, 0x90077084, 0x1E00F804, 0x901F7084, + 0x0A5EC004, 0x702CFB6F, 0x1404C0BB, 0xC6DA341B, + 0x1CFCC2FA, 0xC1BAB6C8, 0x41C34510, 0x000003DD, + 0xF96F097E, 0x730C740C, 0x900741DB, 0x70EEC17C, + 0xF9EF0CDA, 0x30051900, 0xFEEF095E, 0x0D5240A2, + 0x710CF9EF, 0x45CBD840, 0x4E748001, 0xD90BB89F, + 0x10E588E0, 0x0A0A8090, 0x40A1FEEF, 0x0A0240A1, + 0xD911FEEF, 0xD90BC808, 0xB802DAF7, 0x0F802005, + 0x00B89038, 0xC0409000, 0xF7EF0D0E, 0x40A140A1, + 0x0D06D911, 0xDAF8F7EF, 0xD91140A1, 0xFC6F0EE6, + 0x089E724C, 0xC096FF2F, 0x0D7EC096, 0xD90BF9EF, + 0x0D76C096, 0xD911F9EF, 0x800046CB, 0x8E001220, + 0x209F704C, 0xC3960582, 0x60B9708C, 0x00A00C1E, + 0x2705750C, 0x40DB141B, 0x4EBF8001, 0x30F10B1F, + 0x30CF2378, 0x704C8E00, 0x0582209F, 0x708CC396, + 0x06012000, 0x00A00BF6, 0x6F01D80A, 0x903B46D3, + 0xC041C0B8, 0x000042C3, 0xC808BA68, 0x718C43A2, + 0x70CC70AC, 0x68324350, 0x2105D870, 0xB1000581, + 0x0C02D8C8, 0x218AFFEF, 0x44D30004, 0x4DAC8001, + 0x32112440, 0x800047CB, 0x220A12D9, 0x24402500, + 0x0F413210, 0xD8C82135, 0x082D8F00, 0x212F05EE, + 0x09F205C7, 0x40A2FF2F, 0x7280244A, 0x4342708D, + 0x20A84202, 0x080B0280, 0x9320030E, 0x7264B220, + 0x71857244, 0x25122240, 0x25102040, 0xF1E371E6, + 0x0004218A, 0x43A24262, 0x70AC708C, 0x0B9670CC, + 0x704EFFEF, 0x2500200A, 0x21350A45, 0x8F0040A2, + 0x04AE0831, 0x0487212F, 0xFF2F099A, 0x244A40A2, + 0x706D7280, 0x442A4302, 0x030020A8, 0x02CE080F, + 0x94209340, 0x793D6159, 0x7264B320, 0x71657285, + 0x25102040, 0x25112140, 0xF1E07146, 0x00E009C2, + 0xD870702C, 0x43A2D910, 0x000042C3, 0x718C2950, + 0x70CC70AC, 0xFFEF0B2E, 0xD8704050, 0x4202D910, + 0x708C43A2, 0x0B1E70AC, 0x70CCFFEF, 0xB802C808, + 0x05812005, 0xB100C000, 0x09DE40A1, 0xD90BFE6F, + 0x09D640A1, 0xD911FE6F, 0xFEEF0F16, 0xC096C096, + 0xF9EF0BF6, 0xC096D90B, 0xF9EF0BEE, 0x8E00D911, + 0x209F704C, 0xC3960582, 0x60B9708C, 0x00A00A9E, + 0x0B1D750C, 0x704C30F1, 0x209F8E00, 0xC3960582, + 0x2000708C, 0x0A860601, 0xD80A00A0, 0x45CB70CD, + 0xBF648000, 0x0E61C001, 0x252F1025, 0xD8C80387, + 0x0004218A, 0x43A24262, 0x0A9A728C, 0x70CCFFEF, + 0x2500200A, 0x093D702E, 0x8F002115, 0x046E082B, + 0x0447212F, 0xFF2F089E, 0x244A40A2, 0x708D7280, + 0x41A14302, 0x024020A8, 0x030E0809, 0xB1409340, + 0x72247264, 0x20407185, 0xE5142510, 0xF1E57126, + 0xF1D271C5, 0x08CA40A2, 0x712C00E0, 0xF9EF0AC2, + 0x1900700C, 0xC0BA3045, 0x341B1404, 0x78E0C6DA, + 0x1CFCC2FA, 0x2482B6C8, 0xC1443F17, 0xC08D4318, + 0x0ECE702C, 0xDA14F6AF, 0x0E0A750C, 0xD918F96F, + 0x800041DB, 0x11001222, 0x0ABA3081, 0x700CFB6F, + 0x00012052, 0x30801100, 0x742C6038, 0x704C7E0F, + 0xFE2F0E22, 0x206D40C1, 0x740C01CD, 0x41C342A1, + 0x0002033B, 0xF92F0E6A, 0xED8A43C1, 0x033D41C3, + 0x0E5E0000, 0xD80AF92F, 0x000007A9, 0x1243266F, + 0xF86F0982, 0x148F16F4, 0x750CC04C, 0xF96F0DA6, + 0x1100702C, 0x0A5E3081, 0x700CFB6F, 0x00012052, + 0x30801100, 0x742C6038, 0x704C7D0F, 0xFE2F0DC6, + 0x206D40A1, 0x41C301C0, 0x0002033C, 0xC04243A1, + 0x0E0E740C, 0xC202F92F, 0xB802C808, 0x0F812005, + 0xC0909007, 0x0F802005, 0x00909004, 0xB8899000, + 0xC004B100, 0x00002079, 0xC045E008, 0x7014C00C, + 0x20CAC005, 0xC04502A2, 0xC0438E00, 0x10801639, + 0x730C7014, 0xF219C046, 0xC003C102, 0x700C790B, + 0x20CAC048, 0xC04800E2, 0x70801600, 0x017B8000, + 0x001E081B, 0xC003C102, 0xD807790B, 0x20CAC046, + 0xC0460122, 0x700CF003, 0xC004C048, 0x2FC3268A, + 0x208A7014, 0xDE250FC7, 0x200226CA, 0xBE9FC106, + 0xBFC3C008, 0x700E6038, 0xC74A702E, 0xC007C047, + 0xA000210C, 0x002D0210, 0xC10272AE, 0x2440220A, + 0x790BC003, 0xF20E700C, 0x220AC006, 0x210C2440, + 0x700CA000, 0x1418F7C6, 0xC0063012, 0x0440200E, + 0x21012A40, 0x22056852, 0x7A052052, 0x68B66834, + 0x728E7945, 0x706E7D25, 0x8E204262, 0x716E8E1B, + 0x2B007825, 0xB9022081, 0x0081210F, 0xF211790B, + 0x202F7F2F, 0x08FE0487, 0x41E1FEEF, 0xC003C102, + 0xF207790B, 0xD8FF79AF, 0xFEEF097A, 0x248C42E1, + 0x160029BF, 0x80007080, 0x08130001, 0x244A00BF, + 0x16000FC0, 0x80007084, 0x40630120, 0x42C2702C, + 0x70AC726C, 0x091E70CC, 0x70EEF8AF, 0x230A720F, + 0x8E2025C0, 0x71EE8E1B, 0x2F007905, 0xB80224C0, + 0x04C0200F, 0xF2A3782B, 0x000045D3, 0x231F28F0, + 0x11022540, 0x2D41308D, 0x251F2095, 0x671F154F, + 0x30801105, 0x03640839, 0x44D3704E, 0x1A3C8000, + 0x0A27C005, 0xC0042005, 0x2500E887, 0x101C1680, + 0x0A0F0080, 0x0A7E2000, 0x24000060, 0x248023C0, + 0x71462184, 0x77A2F1EE, 0xF1E471A5, 0xC103C202, + 0xF2397A2B, 0x308D1102, 0x036408E3, 0x10522544, + 0x30801103, 0x0354203C, 0xC00570ED, 0x10050F4F, + 0xE888C004, 0x16802500, 0x0080101C, 0x10000F3B, + 0x30061410, 0x7BF079B0, 0x704C4062, 0x0822718C, + 0x71ACF7EF, 0x42624122, 0x0802219A, 0x229FC393, + 0x61790401, 0x245F6159, 0x623A2A02, 0x2501225F, + 0x7AF4623A, 0x71E5B200, 0x1105F1D9, 0x71A53080, + 0x708EF1CC, 0x20950C77, 0x20100C09, 0xF0038E1B, + 0xE8338E00, 0x20100C0B, 0x30921104, 0x1102F003, + 0x24783092, 0xE8852000, 0x308F1105, 0x1103F003, + 0xC305308F, 0x14104062, 0x41423006, 0x718C42E1, + 0xF7AF0FAE, 0x412270AC, 0x219A4262, 0xC3930802, + 0x0401229F, 0x30061410, 0x2A0D245A, 0x70AC728C, + 0xC3056179, 0x4142623A, 0x42E1655D, 0x0F82B500, + 0x4062F7AF, 0x7186B50A, 0x208CF1C6, 0x05F334FD, + 0x7126FFEF, 0x242FC005, 0x40A22000, 0x800043DB, + 0xC04B0025, 0x30811300, 0x3080131B, 0x710C7905, + 0x04002800, 0x200FB802, 0x782B0400, 0x702EF2AB, + 0x01527136, 0x090D000D, 0x131B2010, 0xF0043080, + 0x30801300, 0xF29D7014, 0x2214704E, 0x7156244F, + 0x002D012E, 0x702CC08D, 0xF6AF0B26, 0x24004282, + 0x00003F93, 0x231605EC, 0x70CD2413, 0x24532315, + 0x24932314, 0xC003C102, 0xF236790B, 0x79EF70AD, + 0x0B7A7AAF, 0x710CF92F, 0xE988C104, 0x16812700, + 0x0081111C, 0x10400D47, 0x230A41C1, 0x219A1400, + 0xC2930802, 0x1401239F, 0x2A0C215A, 0x2503225A, + 0x7261623A, 0x61796299, 0x000121F4, 0x78B4C08D, + 0x0A1B9040, 0xB0200045, 0x3F802400, 0x054C0000, + 0x60987061, 0x7BB4631B, 0x71A5B3C0, 0x0DA3C005, + 0xF0199004, 0x410240C1, 0x0802209A, 0x219FC293, + 0x60580401, 0x215A6038, 0x61192A01, 0x2500225A, + 0x14346110, 0x090F3101, 0x1B000005, 0x1C342384, + 0xC0073004, 0x07607610, 0x71C5FFE5, 0xC003C102, + 0xF21F790B, 0xC68D70AD, 0xE888C004, 0x16802700, + 0x0080101C, 0x10000D1F, 0xE88D9600, 0x41C3700C, + 0x00040343, 0x43224202, 0x0480240A, 0xF6AF0F1A, + 0x71A545A1, 0x0DD5C005, 0x72C59024, 0x1434F00E, + 0xE88C3100, 0x41C3700C, 0x00030344, 0x43224202, + 0xF6AF0EF6, 0x0480240A, 0x71E57146, 0x7126F169, + 0x258DF158, 0x710E22BD, 0x710C704E, 0x1300C049, + 0x131B3081, 0x79053080, 0x2800710C, 0xB8020480, + 0x0480200F, 0x02F4782B, 0xC0470021, 0xD9504042, + 0xF72F0A12, 0x200A734C, 0x24003480, 0x00003F80, + 0x209F054C, 0x70AE3401, 0x30182000, 0x02CC71B6, + 0x0D0D000D, 0x131B2010, 0xF0043080, 0x30801300, + 0x02AE7014, 0x710C0021, 0x05402800, 0xF9AF0CDE, + 0x252F780F, 0x40421540, 0xFB2F0D8A, 0x471041A1, + 0xC003C102, 0xF2C0790B, 0x20002752, 0x700E708E, + 0x23512200, 0x08FBC052, 0xDB0820B5, 0x2007C012, + 0x790F0400, 0x215F700C, 0x653E0502, 0x43484330, + 0x082BC105, 0x796F0065, 0xE988C104, 0x16812600, + 0x0081111C, 0x00400811, 0x30812034, 0x71917C6F, + 0x004523CA, 0x71047244, 0xC006F1EC, 0x708DC208, + 0x00032109, 0x3F802400, 0x05EC0000, 0x04802016, + 0x05402015, 0x04C02014, 0xC005B060, 0x7000240A, + 0x050020A8, 0xE888C004, 0x16802600, 0x0080101C, + 0x10000C15, 0x32C02000, 0x79629020, 0x00820907, + 0xB020C108, 0x71857265, 0x72CE70ED, 0x244A6F72, + 0x702C7100, 0x20A870CD, 0x40420640, 0x3F822400, + 0x054C0000, 0x0401209F, 0x255A6058, 0x621A2A02, + 0x2500235F, 0x20F46058, 0x783B00C2, 0x71647124, + 0x00002A00, 0x27147E05, 0xC207140F, 0x79CF78EF, + 0xFEAF0CF2, 0xC00A7A4F, 0x0B00205F, 0x71ED78F5, + 0x70237022, 0x253F268D, 0x7106A8DE, 0x4042F185, + 0x2A02255A, 0x0401209F, 0x3F812400, 0x054C0000, + 0x621A6038, 0xE886C004, 0x05041A24, 0x05041A10, + 0xE886C00C, 0x05041A26, 0x05041A12, 0x0F1B8A30, + 0x12242030, 0xB8020080, 0x8A127905, 0x7825B804, + 0x00811226, 0xB902F008, 0x12267905, 0xB8040080, + 0x8A327825, 0x7E0569D6, 0x79CFC007, 0x0C767A0F, + 0x740CFEAF, 0x205FC00A, 0x60B80B00, 0x70237042, + 0x0382182E, 0x3F802400, 0x05EC0000, 0x04802016, + 0x05402015, 0x20300F0D, 0x880290E0, 0xF004B804, + 0xBF049001, 0xC0077F05, 0x23C7242F, 0x0BA6790F, + 0x4082FEAF, 0x2140C00A, 0x205F3890, 0x21400B00, + 0x21403991, 0x42A23B93, 0x240A4342, 0x651D0500, + 0x21007542, 0x2032334E, 0xAEF22346, 0x3A8F2140, + 0x1085161E, 0x23472132, 0x233267A9, 0xC1402340, + 0x034541C3, 0xC0410008, 0xF8EF0F66, 0x0D27740C, + 0x8E322030, 0xE81EC009, 0x1E00C003, 0x80007042, + 0xC10200FB, 0xF23D790B, 0x40C38E3E, 0x01718000, + 0xC009F029, 0xC003E81B, 0x70421E00, 0x00F18000, + 0x790BC102, 0x8E3EF22D, 0x800040C3, 0xF01B0167, + 0x1E00C003, 0x80007042, 0xC1020100, 0xF221790B, + 0x40C38E3E, 0x01768000, 0xC003F00D, 0x70421E00, + 0x00F68000, 0x790BC102, 0x8E3EF213, 0x800040C3, + 0x1801016C, 0x20320052, 0x18012341, 0x21320052, + 0xA8202341, 0xA82167A9, 0x23412332, 0x2040A822, + 0x053D3A18, 0x71A6FFEF, 0x714EC00B, 0xC04B7704, + 0x700C7014, 0xFFE204EA, 0x0A22C049, 0x730CF9AF, + 0x3F172480, 0x341B1404, 0x78E0C6DA, 0x09FEC0F1, + 0x710CF9AF, 0x030541C3, 0x0E960000, 0xD80AF8EF, + 0x030641C3, 0x42C30001, 0x25030000, 0xF8EF0E82, + 0x740CD80A, 0x030741C3, 0x714C0004, 0x738C726C, + 0xF8EF0E6E, 0x740C74AC, 0x030841C3, 0x704C0004, + 0x123444C3, 0x45C3ABCD, 0xEF12ABCD, 0xF8EF0E52, + 0x09AADB07, 0x700CF9AF, 0x00200A7E, 0x700CD807, + 0x00C420AB, 0xF0007FFF, 0x2079C2E6, 0x4708000E, + 0x256F4E18, 0xB5001A43, 0x10002752, 0xF82F0946, + 0x30021A06, 0x41C3E808, 0x000002F6, 0xF8EF0E12, + 0xF018D80A, 0xEF05D80A, 0xB912D9BD, 0x41C3F004, + 0x000002F5, 0xF8CF0DFA, 0xF90F0C96, 0xEF86E802, + 0x085678DB, 0x7404FEEF, 0x084E78DB, 0x7304FEEF, + 0x40C370F5, 0x8009FFFF, 0x006120C2, 0x30031A06, + 0xD8FDB500, 0xFD6F0B66, 0x00E120CA, 0x78E0C6C6, + 0x7FE0710C, 0x00C420AB, 0x1E00710C, 0x900C7004, + 0x7EE00088, 0x7014C2F6, 0x42C3C808, 0x01238000, + 0x901C43C3, 0x404804B0, 0x0F8122CA, 0x01248000, + 0x008B2840, 0x23056BA4, 0xDF3F10C1, 0x23058A40, + 0x91001343, 0xBF08E50C, 0x12CD2505, 0x938078E4, + 0x784595C0, 0x2404B100, 0x7EE413C0, 0x7AC57845, + 0xB540B300, 0x901C41D3, 0x100004E4, 0x21401080, + 0x16002215, 0x80007081, 0x48350124, 0x14402305, + 0x254090C0, 0x25CE2116, 0x26531021, 0x23051181, + 0x23051542, 0x25001583, 0x92209057, 0x01131300, + 0x01902153, 0x001A4230, 0x23530024, 0x25002194, + 0x000E943E, 0x25000024, 0x0022953E, 0x752C0003, + 0x0A06700C, 0xB913F6AF, 0x6832C808, 0x05832105, + 0x05422105, 0x04402105, 0x7EE44328, 0x23D22204, + 0x15C12605, 0x23502000, 0x2305B020, 0x901C1F80, + 0x270404E8, 0x758214CF, 0x2005B020, 0x7DE52480, + 0xB3A0B200, 0x78E0C6D6, 0x4628C2E4, 0x16004508, + 0x90307100, 0x1A2103BC, 0xE909301C, 0x10710E3D, + 0x724C700C, 0x30831A07, 0x258CF020, 0x004E9804, + 0x258C0029, 0x00629FC3, 0x258C002C, 0x258C9002, + 0xF23D9004, 0x9404258C, 0x258CF23D, 0xF44F9804, + 0x1A07754C, 0xF00A3143, 0x030241C3, 0x096A0001, + 0x42C1F6AF, 0x30821207, 0x41C3D80A, 0x00030303, + 0x0C4E43A1, 0x44C1F8EF, 0x258CC6C4, 0xF6D597C8, + 0x9808258C, 0x258CF223, 0xF2259848, 0x9F800D97, + 0xE9010000, 0xF223F02B, 0x9402258C, 0x714CF427, + 0x30431A07, 0x258CF1E2, 0xF21D9844, 0x9408258C, + 0xDA07F41D, 0x31C31A07, 0x734CF1D8, 0x30C31A07, + 0x744CF1D4, 0x31031A07, 0xDA08F1D0, 0x32031A07, + 0xDA09F1CC, 0x32431A07, 0x704CF1C8, 0x30031A07, + 0x764CF1C4, 0x31831A07, 0xDA0AF1C0, 0x32831A07, + 0x78E0F1BC, 0x8FC3208C, 0x0821F209, 0x41C301D1, + 0x0470901C, 0x00451900, 0x41C3F006, 0x0470901C, + 0x01051900, 0x00051900, 0x903041C3, 0xB10000C8, + 0x0020001D, 0x00051904, 0x903041C3, 0xB10000C8, + 0xB104B830, 0x00200009, 0x00051904, 0x903041C3, + 0x91000010, 0x801F08FF, 0x0B822155, 0x080F9200, + 0x1A0408B1, 0x1ACE0045, 0x9100005D, 0x801E08FF, + 0x78E07EE0, 0x70801600, 0x01078000, 0x01002044, + 0xB8227FE0, 0x0343226F, 0x0500120E, 0x000070D3, + 0x700C0C80, 0x07C520E0, 0x050112E0, 0xF60BE1FF, + 0x02032142, 0x00940B23, 0x0430092B, 0xF20FE1C0, + 0x218CF014, 0xF20B8002, 0x8010218C, 0x091DF211, + 0x00000F81, 0x8A004000, 0x8A00F007, 0x0080206D, + 0x8A00F004, 0xB8C0781D, 0x20797FE0, 0x8A000000, + 0x00C0206D, 0x78E0F1FA, 0x70801600, 0x00058000, + 0x20797FE0, 0x78E00000, 0x0F8EC0F1, 0xE809FFCF, + 0x70801600, 0x00F48000, 0x710CB8E4, 0x700CF402, + 0x7EE0C0D1, 0x216FC0F1, 0x890005C3, 0x700CB8E6, + 0x895AF208, 0x00811135, 0x73347945, 0xFFC10FCC, + 0x7EE0C0D1, 0x0F43216F, 0xB8E18900, 0x7CE0700C, + 0x810011E8, 0x7000263C, 0x0C7F0000, 0x78E07EE0, + 0x4300C0F1, 0x70801600, 0x00018000, 0x013F0825, + 0x0EA64428, 0xD808FFEF, 0xFFEF0ED2, 0x232F4060, + 0xF20880C8, 0xFFEF0EC6, 0x14001404, 0x0F3F238C, + 0x7EE0C0D1, 0x44CBC5E1, 0x28F00000, 0x030D201F, + 0x786A789B, 0x0184229F, 0x2C4160BB, 0x782A1080, + 0x605C6078, 0x800042C3, 0x22561A3E, 0x64080800, + 0x10012415, 0x60336A0A, 0x0A256152, 0x700C00E4, + 0x1F812434, 0x1B408000, 0x21CC7230, 0xF78880C6, + 0x4A314970, 0x79307810, 0x00002109, 0x78E0C4C2, + 0x1600C2E8, 0x80007101, 0x47C3000A, 0x18000000, + 0x21044010, 0x248A01C1, 0x27507001, 0x700D0307, + 0x70CC702D, 0x70CD70ED, 0x706D704C, 0x20A8708D, + 0x20150101, 0x906023C0, 0x087B9001, 0x631D00E4, + 0x6B014873, 0x7D0C73C0, 0x00462340, 0x21007034, + 0x20DA1349, 0x20D503C1, 0xF22D1001, 0x01E10915, + 0x8C07208B, 0x271A780C, 0x621A1003, 0xF0237E75, + 0x083BF20D, 0xDB08023F, 0x8003208B, 0x262FF213, + 0xDB07F005, 0x01A323CA, 0x204BF011, 0xF2078300, + 0x736CB8E3, 0x00A123CA, 0x781DF009, 0x00432044, + 0xB8E5F005, 0x23CA756C, 0x647C0121, 0x23157BEC, + 0x71E510CB, 0x00300E4B, 0x2905D8C9, 0x21781180, + 0x71F00003, 0x767D729D, 0x26CA7074, 0x20CA0081, + 0x71041381, 0x118D2805, 0xFFEF0E42, 0xE8897E1D, + 0xBD2271A5, 0x1FC0257C, 0x25CA7014, 0x18821FE1, + 0x2080239C, 0x18002084, 0x700C2342, 0x41C3C6C8, + 0x00020215, 0x08EA4201, 0x4321F8EF, 0x021641C3, + 0x08DE0000, 0xD8C9F8EF, 0xC6C8730C, 0x42C3C2E4, + 0x12208000, 0x8A404300, 0x02C1239F, 0x0582229F, + 0x2232627A, 0x80010F8D, 0x714C4E86, 0xE9047A18, + 0x12012585, 0x0A8A6A12, 0x2005F6EF, 0x252F008E, + 0x700C0387, 0xDA22762C, 0x244A43A1, 0x0BEE0480, + 0x70CCF72F, 0xD907D880, 0x706C724C, 0x70AC708C, + 0xF72F0BDA, 0x700C70CC, 0xF72F0B82, 0xC6C4712C, + 0xB80243E3, 0x0F822005, 0x00009000, 0xFE6F09E6, + 0x7B204020, 0x78E0B200, 0x4608C2E6, 0x70801600, + 0x00088000, 0x72AD7214, 0x0A264728, 0x25CAF6EF, + 0x0E461161, 0x0A02F70F, 0x0819F6CF, 0x700C003F, + 0x704CD907, 0x708C706C, 0x0B8270AC, 0x70CCF72F, + 0x752CD809, 0x704CB813, 0x0008238A, 0x45C1708C, + 0xF72F0B6A, 0xD80C70CC, 0x42A1D92B, 0x708C706C, + 0x0B5A45C1, 0x70CCF72F, 0xD92BD80C, 0x706C42A1, + 0x45C1708C, 0xF72F0B46, 0xEF0670CC, 0xD80C6D41, + 0xF005D92B, 0xD92BD80C, 0x706C42A1, 0x45C1708C, + 0xF72F0B2A, 0x708C70CC, 0x4788D92B, 0xBF9242A1, + 0x40E1726C, 0x0B1645C1, 0x70CCF72F, 0xD92BD80C, + 0x726C42A1, 0x45C1708C, 0xF72F0B02, 0x700C70CC, + 0x744CD907, 0x708C706C, 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0x00050078, 0x240A4362, + 0x45C10400, 0xF8AF0E4A, 0x0500260A, 0x13310E1B, + 0x3083120E, 0x0407202F, 0xFB2F0F3E, 0x0487212F, + 0xDA22E803, 0x6B09F00A, 0x2538DA22, 0x23781001, + 0x20052000, 0x7AC0807E, 0x4382710C, 0x04C02800, + 0x683244C1, 0x782570CC, 0x272F762C, 0x700C2007, + 0xF72F095A, 0x05C0250A, 0x13310E79, 0x1487262F, + 0x0EF64003, 0x41C1FB2F, 0x244FE823, 0x740C21D4, + 0x41C34222, 0x00050079, 0x240A4362, 0x254A0400, + 0x0DCE0300, 0x260AF8AF, 0x0B130500, 0x704C2030, + 0x7704CA0E, 0x10000D07, 0x700CDA22, 0x4382762C, + 0x0300244A, 0x05C0250A, 0xF72F0902, 0x400370CC, + 0xFB2F0EA6, 0xE88E41C1, 0x742C700C, 0xF72F0BE2, + 0x0B11704C, 0x700C2030, 0x0BD6702C, 0x704CF72F, + 0x71667146, 0x74A6F187, 0xF17E71A5, 0x74367126, + 0xFFE506DA, 0xF045E72C, 0x704E740F, 0x72EEC080, + 0x04802015, 0x70AD70AE, 0x040020F4, 0x2005781B, + 0x00040F93, 0x0E4D1000, 0x240A2030, 0x25002580, + 0x80002F95, 0x70ED1228, 0x2B00225A, 0x1F822732, + 0x04788000, 0x007A41C3, 0x78F50002, 0x04002014, + 0x200E2532, 0x0D1A740C, 0x43C1F8AF, 0x71E578AF, + 0x71A57062, 0xB89CB802, 0x248DB89F, 0xA0C02A3F, + 0x26FF278D, 0x0D1571AE, 0x78AF103E, 0xB8027062, + 0xB89FB89C, 0x04441800, 0x30BF208D, 0xC0047146, + 0x72047106, 0xF10AC044, 0x901C40C3, 0xB02001F8, + 0x804418F0, 0x78E0C7DA, 0x716EC2F4, 0x23064010, + 0x16002013, 0x80007080, 0x70140131, 0x2740224A, + 0x2100240A, 0x46504570, 0x0E864628, 0x22CAF6AF, + 0x70AD25A1, 0x011C7552, 0x40A20026, 0x1F912532, + 0x06188000, 0x092A4122, 0x2632FAEF, 0x08BD144F, + 0x0D1B0010, 0x700C1131, 0x744CD910, 0x708C706C, + 0x0400250A, 0xF6EF0FC6, 0x700C70CC, 0x704C762C, + 0x240A43E1, 0x250A0440, 0x0FB20400, 0x70CCF6EF, + 0xD922700C, 0xF72F0A9A, 0x0D85704C, 0x0E191755, + 0x1F08734E, 0x16000000, 0x80007080, 0x085D00CA, + 0xF034001F, 0x734F0E55, 0x00000006, 0x14110D61, + 0x800040C3, 0x88201222, 0x203C8803, 0x0D1A0040, + 0x4162FB2F, 0x0F96E81A, 0xD8FAFBAF, 0x700C7910, + 0xF72F0A4E, 0x274F704C, 0x700C11C3, 0x704C762C, + 0x0440240A, 0x0400250A, 0xF6EF0F42, 0x700C70CC, + 0x0A2ED922, 0x704CF72F, 0x0F62D8FA, 0x7910FB8F, + 0x0A1E700C, 0x704CF72F, 0xF19671A5, 0x0C41EDFE, + 0x8E012010, 0x00DF080D, 0x20538E14, 0xF21880FE, + 0x0EBA700C, 0x712CF6EF, 0xF68F0D86, 0x000040C3, + 0x0FC23A98, 0xD908FC2F, 0xFE6F0CE6, 0x40C340C1, + 0x0D400003, 0xFC2F0FAE, 0xF1E0D908, 0xF1D7D8C8, + 0xD941700C, 0xF72F09CA, 0x700C704C, 0xF6EF0E7E, + 0x0E41712C, 0x8E1C2010, 0x015E0831, 0xF68F0D42, + 0x20452053, 0xD919D880, 0xDB85744C, 0x0EAE708C, + 0x70CCF6EF, 0x0E56700C, 0x712CF6EF, 0x005B40C3, + 0x0F628D80, 0x702CFC2F, 0x09EE700C, 0x4102F8EF, + 0x78E0C6D4, 0x716EC2F6, 0x23064010, 0x16002013, + 0x80007080, 0x70140131, 0x2740224A, 0x2140240A, + 0x2100250A, 0x47504670, 0x0BD24628, 0x22CAF96F, + 0x0CDE25A1, 0x0AE2F68F, 0x70ADFE4F, 0x012A7552, + 0x40C20026, 0x1F912532, 0x06188000, 0x0F824122, + 0x2632FAAF, 0x7014144F, 0x0D11F285, 0x700C2030, + 0x091ED91E, 0x714CF72F, 0x11310D55, 0x762C700C, + 0xF72F090E, 0x700C714C, 0x704CD92C, 0x708C706C, + 0x0400250A, 0xF6EF0E06, 0x700C70CC, 0x704CD92D, + 0x708C706C, 0x0400250A, 0xF6EF0DF2, 0x700C70CC, + 0x08DE762C, 0x714CF72F, 0x41E14022, 0xF72F09B2, + 0x25424202, 0x08451600, 0xF0500154, 0x41E14022, + 0xF72F099E, 0xED234202, 0x14D00D31, 0x94110DE7, + 0x800040C3, 0x88201222, 0x203C8803, 0x0B5A0040, + 0x4162FB2F, 0x700CE867, 0x0896762C, 0x714CF72F, + 0x11C1274F, 0xF1DC4022, 0x70801600, 0x00CA8000, + 0x003E0859, 0xD91E700C, 0x0C47F025, 0x8E012010, + 0x00DF080D, 0x20538E14, 0xF21B80FE, 0xFE4F09D6, + 0x0D1A700C, 0x712CF6EF, 0xF68F0BE6, 0xFE4F09EA, + 0x000040C3, 0x0E1E3A98, 0xD908FC2F, 0xFE6F0B42, + 0x40C340C1, 0x0D400003, 0xFC2F0E0A, 0x700CD908, + 0x082ED918, 0x714CF72F, 0x762C700C, 0xF72F0822, + 0x71A5714C, 0x098EF16C, 0x700CFE4F, 0xF6EF0CCE, + 0x0F5B712C, 0x8E1C2010, 0x015E084B, 0xF68F0B92, + 0xFE4F0996, 0xD925700C, 0xDB85704C, 0x250A708C, + 0x0CFA0400, 0x70CCF6EF, 0xD926700C, 0xDB85704C, + 0x70AC708C, 0xF6EF0CE6, 0x094A70CC, 0x700CFE4F, + 0xF6EF0C8A, 0x40C3712C, 0x8D80005B, 0xFC2F0D96, + 0x710C702C, 0xF8EF0822, 0x09B64102, 0xC6D6F98F, + 0x47CBC2EA, 0x02FE8000, 0x10911700, 0xF92F0CBE, + 0x40C3730C, 0x11388000, 0xE80B8800, 0x70801600, + 0x00018000, 0x02002044, 0x00002078, 0x700CF002, + 0x0E36D911, 0xB913F62F, 0x207E090B, 0x0D5AD820, + 0x09EAFF8F, 0x8FA1F94F, 0x10901700, 0xF6AF0AF2, + 0x10022589, 0xFE4F08F2, 0x70CDED1B, 0x1F802600, + 0x03808000, 0xDA0F8820, 0xF72F0826, 0x80801080, + 0x762C700C, 0xF6EF0F3A, 0x258D714C, 0x71C51CBF, + 0xFE4F08A2, 0x0BE6700C, 0x712CF6EF, 0x0896F003, + 0x080FFE4F, 0xD822207E, 0xFF8F0CFE, 0x0912F1D5, + 0x090DF98F, 0xD821207E, 0xFF8F0CEE, 0x78E0C6CA, + 0x43C3C5E1, 0x04628000, 0x93034008, 0xF042242F, + 0x7A1DF215, 0x2200706D, 0x00040F8C, 0x20A81000, + 0x201503C0, 0x716512C2, 0x924192A0, 0x7D45BA10, + 0xBA9C6C52, 0xBA9F7185, 0x6038A2A0, 0x9300B303, + 0xB3006038, 0x78E0C4C2, 0x1CFCC2FA, 0x4710B6C8, + 0xB89FD840, 0x2100240A, 0x45504378, 0x00991000, + 0x10E54630, 0x700E8098, 0x716E724E, 0x24002B00, + 0x2004722E, 0xB80206CF, 0x040E200F, 0x70AD4003, + 0xF23078EB, 0x23402B00, 0xF92F0B92, 0x40C3780F, + 0x11388000, 0xE8188800, 0x70801600, 0x00018000, + 0x00FF0825, 0x259F4002, 0x209F1582, 0x42C202C1, + 0x708C43A2, 0x0500250A, 0x651975E2, 0xFFEF0CCA, + 0xF01078CF, 0x259F4002, 0x209F1582, 0x42C202C1, + 0x240A43A2, 0x75E20500, 0x0B126519, 0x78CFFFEF, + 0x218D4023, 0x71AD243F, 0x20BF228D, 0x0B2E710E, + 0x730CF92F, 0x341B1404, 0x78E0C6DA, 0x4568C3E6, + 0x47284648, 0xB0091CF8, 0x30011C04, 0x30C21C01, + 0xF6EF0D9A, 0x2578C360, 0x41C11000, 0x6841781B, + 0xF6EF0D3E, 0x0D86C080, 0x40E1F6EF, 0x0A8E700C, + 0x712CF6EF, 0x78E0C7C6, 0x2945C2E4, 0x4608018B, + 0x0D3D70AD, 0x8E0112C5, 0x8E228E40, 0x7A05B808, + 0xB8088E03, 0xB8107825, 0x00812005, 0x8E448E05, + 0xB8087734, 0xF2077845, 0xB99CB902, 0xB100B99F, + 0x0AD6F003, 0x76C5FC0F, 0xF1E571A5, 0x78E0C6C4, + 0x7034C2E4, 0x800041C3, 0xF22712E0, 0x00C1110A, + 0x7180244A, 0x7B31C808, 0x2144B923, 0x68520401, + 0x22057965, 0x90030F8C, 0x7B2FD580, 0x0F812205, + 0xD5849003, 0x800042C3, 0xB4600548, 0x20A8B160, + 0x12100300, 0x79050401, 0x2105B902, 0x90030F81, + 0xB160C000, 0x2042F017, 0xF215803C, 0x20A86944, + 0x120604C0, 0xB8020400, 0x0F832005, 0x00009000, + 0x04C0120E, 0xB8237911, 0x04002044, 0x780F7825, + 0x720CB300, 0x900345CB, 0x46CBD478, 0xF07C9007, + 0x10C51D00, 0xFC2F0A32, 0x10C51E00, 0x900F41C3, + 0x2150E008, 0x710C04C2, 0x01451900, 0x01451A00, + 0xB200B100, 0xB600B500, 0x78E0C6C4, 0x42C3C0E6, + 0x12228000, 0x40288A81, 0x0C518AA0, 0x43001364, + 0x00022479, 0xE20970B4, 0x22CAC808, 0x20050062, + 0x221F00CE, 0x2D40034B, 0x240A130F, 0x7FC57080, + 0x20A8706C, 0x2B400440, 0x70B40200, 0x20F478C0, + 0x78E512C1, 0xB8027164, 0xB8927165, 0xB89FB89C, + 0x7591B020, 0xF7A971A5, 0x78E0C4C6, 0x4010C2E8, + 0x800046CB, 0x47CB1222, 0x4DAC8001, 0x2754E903, + 0x8EA01F0F, 0x08578E01, 0xD8C80364, 0x800040C3, + 0x880012D9, 0x036E0843, 0x0F7A79AF, 0x4002FE2F, + 0xC8084408, 0x13822D40, 0x7280244A, 0x700C6832, + 0x20A87A25, 0x0C2104C0, 0x255A100E, 0x61F91501, + 0x000321F4, 0x02812840, 0x21057945, 0x90040F81, + 0xB1600320, 0x71A57104, 0x09A2F1D6, 0xC6C8FC0F, + 0x718EC2F4, 0x2C004610, 0x16002040, 0x80007093, + 0xB8020004, 0x200F4230, 0x0AAF0051, 0x235302F0, + 0xE28A20D3, 0x700EF4B4, 0x081372AE, 0x16002010, + 0x80007080, 0x08890040, 0x272F0010, 0x40421400, + 0xFAAF0982, 0x260041E1, 0x42C323C1, 0x0E9C8000, + 0x89218960, 0x6149634D, 0x6914E804, 0xF0047D05, + 0x7D25BD04, 0x2800710C, 0x08A20400, 0x780FF92F, + 0x750C7EAF, 0x41C34242, 0x000301D3, 0x0D224302, + 0x44C1F86F, 0x0447212F, 0xFE2F0AC2, 0x235F40C1, + 0x60F82B00, 0x70C37042, 0x123C8000, 0x20300A15, + 0x0CC7A8A0, 0x1E002010, 0x80007342, 0xF008017E, + 0x20100CCB, 0x73421E00, 0x017D8000, 0x258D710E, + 0x708E2DFE, 0x700EF064, 0x081372AE, 0x16002010, + 0x80007080, 0x08890040, 0x272F0010, 0x40421400, + 0xFAAF08E2, 0x260041E1, 0x42C323C1, 0x0E9C8000, + 0x89218960, 0x6149634D, 0x6914E804, 0xF0047D05, + 0x7D25BD04, 0x2800710C, 0x08020400, 0x780FF92F, + 0x750C7EAF, 0x41C34242, 0x000301D4, 0x0C824302, + 0x44C1F86F, 0x0447212F, 0xFE2F08BA, 0x235F40C1, + 0x60F82B00, 0x70C37042, 0x12388000, 0x20300A15, + 0x0C31A8A0, 0x1E002010, 0x80007342, 0xF00800F7, + 0x20100C35, 0x73421E00, 0x00F28000, 0x258D710E, + 0x708E2DFE, 0x1E00F014, 0x80007342, 0xF0100180, + 0x73421E00, 0x01018000, 0x1E00F00A, 0x80007342, + 0xF006017F, 0x73421E00, 0x00FC8000, 0x70801600, + 0x00408000, 0x730CE803, 0x710CF002, 0xF8CF0F6E, + 0x78E0C6D4, 0xC1A8C3E6, 0x1243276F, 0x800145CB, + 0x8FC04E74, 0x1756712C, 0x20441080, 0x09B60202, + 0x40A1FBAF, 0xD91440A1, 0xF6EF0FBE, 0x178A704C, + 0x40A11082, 0x099EBAC3, 0xD914FBAF, 0xF8EF0F22, + 0x0B4EC084, 0xC080FE2F, 0x082EC080, 0xD910F92F, + 0x08358F17, 0x40C3001E, 0x12D88000, 0xE8148800, + 0x41C3BEC3, 0x12288000, 0x1B00265F, 0x6119602A, + 0x1DA28902, 0x89011002, 0x10021D57, 0xAD4C8903, + 0x10021DED, 0xD91040A1, 0xF6EF0F5E, 0x40A1DAFB, + 0x0942D910, 0xDA41FBAF, 0x702C40A1, 0xDBFFC284, + 0xFFEF0AFA, 0x40A1708C, 0x092AD910, 0x744CFBAF, + 0x702C40A1, 0x0BDEC280, 0x716CF72F, 0x78E0C7C6, + 0x78E07EE0, 0x1CFCC2FA, 0x2482B6C8, 0x46303604, + 0x0F46702C, 0x4318F7AF, 0x451071AD, 0x16C02D00, + 0xF9EF0DE2, 0x0DEA68F2, 0x4210F9EF, 0x8E82208C, + 0x238A70CD, 0xF7062F83, 0xF9CF0DD6, 0x08932054, + 0x70831600, 0x00048000, 0x750CBBC3, 0x41C34263, + 0x0002040D, 0xF86F0AEA, 0x16D0270F, 0x41C3D82E, + 0x0E010001, 0xB70F478B, 0xB709D895, 0xB890D897, + 0x41C3C155, 0x012A0007, 0x2154C040, 0xB86C0942, + 0xC043C149, 0xC808E115, 0xC2466989, 0x00422005, + 0x7224B755, 0xBA30C24F, 0xB7567905, 0xC14C6C49, + 0x00812005, 0x03032005, 0x30441C42, 0x1C44B930, + 0x6A2E3044, 0x20057905, 0x00010F80, 0xB73B00FB, + 0xB703B930, 0xB73CB830, 0xB704D90F, 0x714CC080, + 0x31C51C50, 0x33441C4E, 0xB7AAB7B0, 0x1C58B7C2, + 0x1C523384, 0x1C4C3384, 0x1C463384, 0x1C403384, + 0xB7DD3384, 0xB7D7B7DA, 0xB7D1B7D4, 0xB7CBB7CE, + 0xB7C5B7C8, 0xFDEF0B32, 0x1600C352, 0x80007083, + 0x245512D9, 0x244A3801, 0x700C7200, 0x33801C8C, + 0x33801C88, 0x33801C84, 0x33801C80, 0x040020A8, + 0x0B137A1D, 0x2605008E, 0x90381F82, 0x9240012C, + 0x7224B140, 0x000076C3, 0x71044000, 0x1643276F, + 0x20448F00, 0xF2068202, 0x70851E00, 0xC3789007, + 0x41C3700C, 0xC25C9007, 0x800046CB, 0x1E001222, + 0x901C7004, 0x1E000004, 0x90077004, 0xB100F804, + 0x1964EA99, 0xD9400205, 0x900740C3, 0xB020C2C4, + 0x8E41B0A8, 0x0A778E20, 0x7A5B0064, 0x70402614, + 0x048C8000, 0x00412217, 0x09B66942, 0x702CF5EF, + 0x1600F02D, 0x80007082, 0x72540008, 0x901C43C3, + 0x42C30000, 0xF8009007, 0x1964F406, 0xB3000004, + 0xF006B200, 0x01051964, 0xB2A0B3A0, 0x8E008E21, + 0x0024092B, 0x71247902, 0x7040240A, 0x03C020A8, + 0x06812000, 0x70022614, 0x048C8000, 0x0081111C, + 0x21787104, 0xB9080001, 0xD8AAB220, 0x70041E00, + 0xC0B89007, 0xF64F0B0A, 0x0407202F, 0xC057D907, + 0x145CD841, 0xB8133005, 0x706C744C, 0x0C6E708C, + 0x70CCF6AF, 0xD907700C, 0x706CDA08, 0x70AC708C, + 0xF6AF0C5A, 0x145C70CC, 0xD8803005, 0xD907B893, + 0x706C744C, 0x0C46708C, 0x70CCF6AF, 0x0BEE700C, + 0x712CF6AF, 0x000040C3, 0x0CFA1388, 0x752CFBEF, + 0xD9FF710C, 0xFB6F0986, 0x216F704C, 0x40D32443, + 0x048C8000, 0x20801100, 0x01012078, 0x7424B902, + 0x180AB806, 0x20892042, 0x41C30E43, 0x000103E3, + 0x740C6846, 0xF86F089A, 0x20841808, 0x6872C808, + 0x901C40C3, 0x23050504, 0xB1A00001, 0x0F812305, + 0x04FC901C, 0x834418A4, 0x0F802305, 0x04DC901C, + 0x11009000, 0x0A1B2082, 0xB8C500B1, 0x02C2204F, + 0x8F20B140, 0x00FE0925, 0x0301204F, 0x204FF009, + 0xB1400302, 0x09158F20, 0x204F00FE, 0x23050341, + 0x901C0F80, 0xB02004F4, 0x0F802305, 0xC3EC9007, + 0x71051E00, 0xC12C903B, 0x088EB0A0, 0x710CFB2F, + 0xB802C808, 0x0F812005, 0x00949004, 0x1C909120, + 0x8F203040, 0x00DE091B, 0x0F812005, 0xC0949007, + 0x30001490, 0x0080206C, 0x00C02045, 0x1600B100, + 0x80007080, 0x22440126, 0xB8E22051, 0xF9A20C48, + 0x21004063, 0x42D32491, 0x0FB08000, 0x3A402455, + 0x28012240, 0x0FD2DA72, 0x2344F5AF, 0x40C32054, + 0xF0A70000, 0x30041C66, 0x000140C3, 0xC058FF74, + 0x0004208A, 0x30041C6A, 0x100AD972, 0x1C682080, + 0xB8063344, 0x30041C64, 0xFFEF0822, 0x3A402455, + 0x204B8F00, 0xF4068E00, 0x0812C098, 0xD90CFFEF, + 0xD90FD80F, 0x24CD2400, 0xF76F0C2A, 0x27912140, + 0x204B8F00, 0xF4088E00, 0xF84F0D46, 0x0E924063, + 0x712CFF6F, 0x78AFC217, 0x0447212F, 0xFB2F0BDA, + 0x8F404118, 0x8E00224B, 0x0A67F20B, 0x700C00FF, + 0x041441C3, 0x0C420001, 0x026FF5CF, 0x41C30000, + 0x0000040F, 0xF82F0F2A, 0xD861740C, 0x900745CB, + 0xB808C29C, 0xB500712C, 0xF6AF0A22, 0xD941D808, + 0x0004208A, 0xB500B914, 0xF82F0F06, 0x1600740C, + 0x80007080, 0xB8E20001, 0x002201FA, 0x1008DD0A, + 0x09FA2100, 0x712CF6AF, 0x1EFF258C, 0x41C3F0F8, + 0x00000411, 0xF82F0EDA, 0x710C740C, 0xF6AF09DE, + 0x2455712C, 0x41423A40, 0xF5AF0ECE, 0x2455DA10, + 0x22403940, 0x0EC22401, 0xDA10F5AF, 0x8E20700C, + 0xC05EC05F, 0xC05CC05D, 0x082F8E01, 0x78220064, + 0xC8086841, 0x7080240A, 0x20A86872, 0x294003C0, + 0xC2980380, 0x7A357865, 0x0F802005, 0x00A89004, + 0x71249000, 0x700CA200, 0xF6AF0982, 0x8E01712C, + 0x2001258A, 0x082F8E20, 0x78220064, 0xC8086861, + 0x70C0240A, 0x20A86852, 0x294003C0, 0x78450380, + 0x0F832005, 0x00A89004, 0x3A402455, 0x71244820, + 0x0FE2B300, 0x700CFD4F, 0xF6AF0942, 0x8EA0712C, + 0x08D98E01, 0x2D400364, 0xD8891391, 0x2F922105, + 0x01C89004, 0x20041A00, 0xFBEF09AE, 0x20F4D808, + 0x24552340, 0x23153A53, 0x24552353, 0x26153956, + 0x41C32356, 0x00050412, 0xB80242A1, 0x04402005, + 0x3E112454, 0x0F802005, 0x01CC9004, 0x21159000, + 0x1A002351, 0x20442005, 0x43660058, 0x1600740C, + 0x260A2017, 0x11000600, 0x240A2012, 0x250A05C0, + 0x0DBE0480, 0x4470F82F, 0x3011081B, 0x20330A17, + 0x20402740, 0x00F5080B, 0x71EE714E, 0x2F84F003, + 0x081D2FBF, 0x0A193010, 0x27402072, 0x080D2040, + 0x774E00F5, 0xF00477EE, 0x2FBF2F84, 0x20310A19, + 0x30002078, 0x00002079, 0xB805791B, 0x00522142, + 0x04172042, 0x25D42400, 0x25C01E00, 0x24801900, + 0x1B0071A5, 0xF1962500, 0x2DBD258C, 0x096A4063, + 0x702CF7AF, 0x00100883, 0x8E408E21, 0x00A40941, + 0x0A832040, 0x7942C808, 0x240A7124, 0x20A87040, + 0x2A400600, 0x7C05030C, 0x10C12405, 0x2105B902, + 0x90040F8D, 0x6C320000, 0x0F8C2105, 0x00A89004, + 0xB5209420, 0x4941C198, 0xB4207144, 0xFD0F0A46, + 0x1008F01B, 0x08062100, 0x712CF6AF, 0x0C224063, + 0x702CFF6F, 0x702C40C2, 0xFD2F0DD6, 0x2540724C, + 0xC8082A95, 0x05402005, 0x704C41C2, 0x708C706C, + 0xFFAF0E5E, 0x0E6E71AC, 0x70CDFD4F, 0x900745CB, + 0x4063C29C, 0xFAAF0F2E, 0x41C3B5C0, 0x00000415, + 0xF82F0CAE, 0x700C740C, 0x0D62702C, 0x704CFB2F, + 0xB5D4B5D2, 0x08218F00, 0xC80800DE, 0x2005B802, + 0x90070F81, 0x1490C094, 0xB1003000, 0x73841E00, + 0xC3789007, 0xF60F0E5A, 0x752C700C, 0xF6AF0AC2, + 0x700C714C, 0xF66F0F76, 0x0CCE712C, 0x700CFAEF, + 0xF60F0E3E, 0xD907700C, 0x706C744C, 0x70AC708C, + 0xF66F0FAA, 0x708C70CC, 0x3005145C, 0x732C4080, + 0x4223B890, 0x01032841, 0xF66F0F92, 0xD88070CC, + 0x744CD907, 0x708C706C, 0x0F8270AC, 0x70CCF66F, + 0x0F2A700C, 0x712CF66F, 0xFD0F095A, 0xFD4F0DB6, + 0xD90FC080, 0xFDAF0D02, 0x1600704C, 0x8000708C, + 0x245512D9, 0x244A3801, 0x700C7200, 0x040020A8, + 0x0C137A1D, 0x9140108E, 0x1F832605, 0x012C9038, + 0x7224B340, 0x000076C3, 0x71044000, 0x36042480, + 0x341B1404, 0x78E0C6DA, 0x2482C3F4, 0x228A3102, + 0x10822084, 0x2033070F, 0x250A048E, 0x46702100, + 0x43304450, 0xFF6F08D6, 0xE8084110, 0x710478CF, + 0x2049B822, 0xF0050FCE, 0x10320E45, 0x2648700E, + 0x40D11000, 0x780F7104, 0x7000240A, 0x034020A8, + 0x0407202F, 0x20002115, 0x09139020, 0x900103C5, + 0x10050F0B, 0x700E7706, 0x0892F006, 0x7014FF4F, + 0x206220C0, 0xDD3FE6BF, 0xF01DF6C2, 0xD940E6C0, + 0x45C96E01, 0x004B20CA, 0x240A78C2, 0x20A87000, + 0x21150300, 0x90202340, 0x03C50911, 0x0F0D9001, + 0x71A51005, 0xF007DD3F, 0xFF4F0852, 0x25C27014, + 0x084A1062, 0xE809FF4F, 0x24802132, 0x79026D32, + 0x04022018, 0x4DD1F004, 0x14022602, 0x7E2F78CF, + 0x200C2115, 0x4F109400, 0x94017B10, 0x7F4F78E2, + 0x081A7810, 0x2009FF6F, 0x701400CD, 0x138E2709, + 0xFF6F080A, 0x106225C0, 0x40A17014, 0x138125CA, + 0x710CF213, 0x20300B0F, 0x30431C05, 0x704C712C, + 0x702CF003, 0x0E2A42A2, 0xC380F9AF, 0x3100140C, + 0x710478CA, 0x7CB0B822, 0x0C177B10, 0x24892030, + 0x0E1B1FC3, 0x0B272051, 0xD9592071, 0x0E17F016, + 0x0B232051, 0xD93E2071, 0x0B17F010, 0xD9552071, + 0x0B17F00C, 0xD93A2071, 0xD957F008, 0xD953F006, + 0xD93CF004, 0xD938F002, 0x6909B99F, 0xC2608840, + 0x0A0DC220, 0x23890325, 0xC4200FC3, 0x8900A880, + 0xC020C060, 0x00C50807, 0xA960C320, 0x78E0C7D4, + 0x1600C2EA, 0x8000708E, 0x71141222, 0xDD75D870, + 0x25CA4130, 0x16001001, 0x80007080, 0x08771223, + 0x16000384, 0x80007080, 0x086712D9, 0x79CF03AE, + 0xFDEF0BA2, 0x46004022, 0x742D70EC, 0x702C720D, + 0x03822114, 0xBA0CC808, 0x27157845, 0x702C0042, + 0x02450937, 0x00AE0E2D, 0x7B0561BB, 0x2305BB02, + 0x90380F8C, 0x265A0000, 0x7B541503, 0x0F8B2334, + 0x4DAC8001, 0x800043C3, 0x23F40F60, 0xB46002C3, + 0x71447124, 0x712CF1E6, 0x173F208D, 0x71C5752D, + 0xC6CAF1C3, 0x1CFCC2FA, 0x44D3B6C8, 0x12228000, + 0x14014018, 0x14002080, 0x200C2090, 0x011AA000, + 0x4748002D, 0x0C172140, 0x000E45D3, 0x21400000, + 0x21400816, 0x21540402, 0x21050819, 0x2705055B, + 0x26052557, 0x25052556, 0x46CB2095, 0x00009000, + 0x800041C3, 0x892012D9, 0x040E09D5, 0x2513205A, + 0x800145CB, 0x7F604DAC, 0x23402334, 0x23512840, + 0x21055020, 0x75622612, 0x26C22205, 0xB9027945, + 0xB10079C5, 0x95017F60, 0x25422205, 0x79455020, + 0x79C5B902, 0x7F60B100, 0x22059502, 0x50202582, + 0xB9027945, 0xB10079C5, 0x95037F60, 0x25D22205, + 0x21055020, 0xB9020481, 0xB10079C5, 0x95047F60, + 0x26112100, 0x21964100, 0xC8082008, 0x26C22105, + 0xB8027845, 0xB02078C5, 0x95057F60, 0x25422105, + 0x79455020, 0x79C5B902, 0x7F60B100, 0x21059506, + 0x50202582, 0xB9027945, 0xB10079C5, 0x95077F60, + 0x25C22105, 0x79455020, 0x79C5B902, 0x7F60B100, + 0x21059508, 0x50202651, 0x04412105, 0x2105B902, + 0x90380F81, 0xB1000000, 0x20801401, 0xA000200C, + 0xFFE50720, 0x14047106, 0xC6DA341B, 0x1CFCC2FA, + 0x2482B6C8, 0x45683902, 0xC0414730, 0x700C700E, + 0x31001C90, 0x30801C8C, 0xEB05C040, 0xF80F0EF2, + 0x41DBC040, 0xC0C49007, 0xFF2F0D72, 0x30451900, + 0x30021C0D, 0x702C710C, 0x0BA642A1, 0xC382F9AF, + 0xD825726F, 0x8820B89F, 0x7905881B, 0x2800710C, + 0xB8020400, 0x0400200F, 0x0252782B, 0x16000001, + 0x8000708D, 0x16001222, 0x80007080, 0x75101223, + 0x000D023A, 0x800040C3, 0x880012D9, 0x83402011, + 0x00210224, 0x097E79AF, 0x148CFDEF, 0x1C983000, + 0x20143000, 0x70CD2340, 0x0F962000, 0x04708000, + 0x13002D40, 0x30001C94, 0x30001498, 0x83802011, + 0x40C3F2EF, 0x28F00000, 0xC1017A1B, 0x200B201F, + 0x794AB822, 0x251A40C9, 0x44CB1003, 0x1B3C8000, + 0x1184209A, 0x3089140D, 0x61787161, 0x64197001, + 0x89026097, 0x10300919, 0x14149142, 0x782A3101, + 0xB8227104, 0x10112700, 0xF0044748, 0x4150671F, + 0x12012E40, 0x30001494, 0xC8087905, 0xC0017905, + 0x0412214F, 0xE80A4330, 0x09717361, 0x23001030, + 0x60980200, 0xF0379002, 0x20110F23, 0x1A00255A, + 0x201478D5, 0x20000400, 0x80000F81, 0x70C3BEC4, + 0xC0048000, 0x04441900, 0x2455B0E0, 0x09463A01, + 0x78F0F96F, 0xE807CA05, 0x3A002455, 0xFB2F0A6A, + 0x09AE41E2, 0xE808FC8F, 0x20811600, 0xFB2F0A5A, + 0x3A002455, 0x24002205, 0x2005B802, 0x90000F8F, + 0x24550048, 0xF0773A00, 0x60906419, 0x60388922, + 0x09027810, 0x2455F96F, 0x24003A01, 0x00003F81, + 0x08F2009E, 0x78F0F96F, 0xE806C000, 0x3100149E, + 0x30041CA0, 0xE80ECA05, 0x3A002455, 0xFB2F0A0A, + 0x240041E2, 0x00003F80, 0x09FE009E, 0x41E2FB2F, + 0xFC8F093E, 0x1600E80F, 0x09EE2081, 0x2455FB2F, + 0x24003A00, 0x00003F80, 0x09DE009E, 0x1600FB2F, + 0xCA052081, 0x091AE887, 0x08A1FC8F, 0x24550030, + 0x24553A00, 0x24003A00, 0x00003F81, 0x724C009E, + 0xFD0F08DA, 0x20310F37, 0x3A002455, 0x1A15255A, + 0x800044D3, 0x2515C004, 0x25142395, 0x0F022415, + 0x2400F7EF, 0x1C002554, 0x25002004, 0x80002F80, + 0x1CA0BEC4, 0x180023C4, 0x22050444, 0xBF02240F, + 0x1F922705, 0x00489000, 0xF7EF0ECA, 0x3A002455, + 0x1A00BF86, 0xBF9C2004, 0x3F802400, 0x009E0000, + 0x0EB2BF9F, 0xB700F7CF, 0x30001490, 0x2B40E809, + 0x20052080, 0x90040F80, 0x18000320, 0x71C50444, + 0x0618E689, 0xF008FFC5, 0x3F812400, 0x009E0000, + 0xF1B8714C, 0xFFEF05C3, 0x238D71A5, 0x710E337B, + 0x30051900, 0x39022480, 0x341B1404, 0x78E0C6DA, + 0x1600C3F2, 0x80007091, 0x0AD20004, 0x2482FF2F, + 0x1C053102, 0x710C3002, 0x704C712C, 0xF9AF0902, + 0x2153C380, 0x718E20D1, 0x726E700E, 0x47CB714E, + 0x12208000, 0xB89FD825, 0x881B8820, 0x2C007905, + 0xB8022400, 0x0400200F, 0xF2C1782B, 0x8F038FC2, + 0x017A7610, 0x40C3000D, 0x12D98000, 0x20118800, + 0xF2B38380, 0x13002E40, 0x30881405, 0x04012005, + 0x7825C808, 0x7280244A, 0x706D6892, 0x1F892405, + 0x00A09004, 0x0A0020A8, 0x000040C3, 0x68320A3C, + 0x201F78CC, 0x41C32042, 0x1B3C8000, 0x4061621A, + 0x0184209A, 0x1030080D, 0x60386058, 0xF0069002, + 0x6030611B, 0x60788B62, 0x12710B0F, 0x12832B40, + 0x10041900, 0x7B85F007, 0x0F832305, 0x01E89004, + 0x7165B300, 0x70801600, 0x00EE8000, 0xF4757014, + 0x10100821, 0x6159622D, 0x140C8922, 0x782A3100, + 0x20047104, 0x00000F80, 0xB822FFFC, 0xF004651D, + 0x89A46159, 0x08118F05, 0x720C03A5, 0xF88F080E, + 0xF006710C, 0xF8AF0806, 0x700C710C, 0x4002AF00, + 0xFA2F08B2, 0x451041C1, 0x08AA4002, 0x41C1FA2F, + 0x2B01215F, 0x00002078, 0x7404B802, 0x8F006119, + 0x00002114, 0x700279AF, 0xA8A860F8, 0x20002578, + 0x0CC26841, 0x4002F5EF, 0x20300D17, 0xE8118F00, + 0x20100A3B, 0x73421E00, 0x00508000, 0xE810F02A, + 0x20100A35, 0x73421E00, 0x00FA8000, 0x0A33F022, + 0x1E002010, 0x80007342, 0xF01C0035, 0x20100A2D, + 0x73421E00, 0x00F08000, 0x1E00F014, 0x80007342, + 0xF0100051, 0x73421E00, 0x00FF8000, 0x1E00F00A, + 0x80007342, 0xF0060036, 0x73421E00, 0x00F58000, + 0xF86F0F5A, 0x71C5730C, 0x704EF143, 0x2D3C238D, + 0xC7D2710E, 0x7A00244A, 0x800040C3, 0x20A8C444, + 0x180001C0, 0x20800003, 0x7EE0000E, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DMAC_TRANS_DCCM[] = { + 0x00000000, 0x21500030, 0x00044004, 0x00006000, + 0x00FF56DF, 0x00020000, 0x07000000, 0x08010000, + 0x00000000, 0x00000110, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x10000000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0xD0D00000, 0xDDDDD0D0, + 0x8686DDDD, 0x54548686, 0xB4B45454, 0x2E2EB4B4, + 0x00002E2E, 0x28280000, 0x28282828, 0x00002828, + 0x2E060000, 0x0C0C2E06, 0x10100C0C, 0x02021010, + 0x00000202, 0x00000000, 0x77770000, 0x00007777, + 0x00000000, 0x00000000, 0x24240000, 0x00002424, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x60600000, 0x00006060, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x0000001F, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x57000001, 0x0000004F, 0x00000000, 0x00000000, + 0x00000100, 0x00000000, 0x001E001E, 0x00FF00FF, + 0x000F6E0A, 0x0005000F, 0x00000000, 0x00000000, + 0x005C0032, 0x00E000B6, 0x0164013A, 0x01E801BE, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01000000, 0x00000000, + 0x00000000, 0x00000000, 0x06400C80, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x050B0000, + 0x00000006, 0x00000000, 0x00000000, 0x08080808, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x010CA635, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000004, 0x00000000, 0x00040000, + 0x00000000, 0x00000000, 0x180F0E0C, 0x4746451E, + 0x004A4948, 0x01000000, 0x00000000, 0x00000000, + 0x00000000, 0x00040000, 0x00000001, 0x00000000, + 0x00000000, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0002F059, 0xFFB50003, + 0x00000001, 0x0001F0B5, 0xF0B30001, 0x00000001, + 0x0001F0B4, 0xF0B00000, 0x00300001, 0x0007F003, + 0xF0040000, 0x00000007, 0x0001FE03, 0xFE040000, + 0x00000001, 0x0007F011, 0xFE210000, 0x00000001, + 0x0001F0B1, 0xFFBE0182, 0x00000001, 0x0001F0BE, + 0xF0A70001, 0x00000001, 0x0001F0A2, 0x00790002, + 0x00400002, 0x00000308, 0x00000560, 0x00000000, + 0x80000DB4, 0x00000309, 0x00000561, 0x00000001, + 0x80000DC5, 0x000E0305, 0x000E0205, 0x00000003, + 0x80000DD6, 0x000E0300, 0x000E0200, 0x00000003, + 0x80000E3C, 0x000E0301, 0x000E0201, 0x00000003, + 0x80000E4F, 0x000E0302, 0x000E0202, 0x00000003, + 0x80000E62, 0x000E0303, 0x000E0203, 0x00000003, + 0x80000E75, 0x000E0304, 0x000E0204, 0x00000002, + 0x80000E88, 0x01FF01FF, 0x000E0000, 0x00000000, + 0x00000063, 0x00000064, 0x00000660, 0x00000000, + 0x80000D87, 0x00000661, 0x00000001, 0x80000DA5, + 0x000E00F0, 0x00000003, 0x80000DE7, 0x000E00F1, + 0x00000003, 0x80000DF8, 0x000E00F2, 0x00000003, + 0x80000E09, 0x000E00F3, 0x00000003, 0x80000E1A, + 0x000E00F4, 0x00000002, 0x80000E2B, 0x000E00F5, + 0x00000003, 0x80000D96, 0x02011210, 0x1C0A1403, + 0x0B112E29, 0x1916150D, 0x180F0E0C, 0x453A131E, + 0x49484746, 0x02006E4A, 0x00000100, 0x02150028, + 0x0085000A, 0x00000000, 0x02150001, 0x0085042B, + 0x0001010B, 0x00020000, 0x0640042B, 0x0190010B, + 0x00010002, 0x06400002, 0x01900855, 0x00030215, + 0x00030001, 0x0ABE0855, 0x02B00215, 0x00010004, + 0x0ABE0004, 0x02B00C80, 0x00050320, 0x00040002, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00280000, + 0x00050215, 0x00000043, 0x00010000, 0x042B0215, + 0x00850043, 0x00000001, 0x042B0001, 0x00850640, + 0x000200C8, 0x00010001, 0x08550640, 0x010B00C8, + 0x00010003, 0x08550002, 0x010B0ABE, 0x00040158, + 0x00020001, 0x0C800ABE, 0x01900158, 0x00010005, + 0x0C800002, 0x01900E95, 0x000601D3, 0x00030001, + 0x10AB0E95, 0x021501D3, 0x00010007, 0x10AB0003, + 0x021512C0, 0x00080258, 0x00030002, 0x157C12C0, + 0x02B00258, 0x00020009, 0x157C0004, 0x02B01770, + 0x000A02EE, 0x00040002, 0x19001770, 0x032002EE, + 0x0002000B, 0x19000004, 0x03201D4C, 0x000C03AA, + 0x00050003, 0x21551D4C, 0x042B03AA, 0x0003000D, + 0x21550006, 0x042B2580, 0x000E04B0, 0x00070003, + 0x02150028, 0x0085000A, 0x00040004, 0x00010001, + 0x00030001, 0x02150004, 0x0085042B, 0x0004010B, + 0x00000006, 0x00020002, 0x00050003, 0x0640042B, + 0x0190010B, 0x00080006, 0x00030001, 0x00040002, + 0x06400006, 0x01900855, 0x00080215, 0x0002000A, + 0x00030004, 0x00070004, 0x0ABE0855, 0x02B00215, + 0x000E0008, 0x00070001, 0x00040004, 0x0ABE0008, + 0x02B00C80, 0x000A0320, 0x00030010, 0x00040009, + 0x00080004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00280000, 0x00050215, + 0x00020043, 0x00000002, 0x00010000, 0x00030002, + 0x042B0215, 0x00850043, 0x00030002, 0x00010000, + 0x00020001, 0x042B0003, 0x00850640, 0x000300C8, + 0x00010004, 0x00010002, 0x00030002, 0x08550640, + 0x010B00C8, 0x00050004, 0x00020001, 0x00020002, + 0x08550004, 0x010B0ABE, 0x00040158, 0x00010007, + 0x00020004, 0x00040002, 0x0C800ABE, 0x01900158, + 0x00080005, 0x00050002, 0x00020002, 0x0C800004, + 0x01900E95, 0x000601D3, 0x00020009, 0x00030005, + 0x00050002, 0x10AB0E95, 0x021501D3, 0x000B0006, + 0x00070002, 0x00020003, 0x10AB0005, 0x021512C0, + 0x00070258, 0x0003000C, 0x00030008, 0x00050002, + 0x157C12C0, 0x02B00258, 0x000E0008, 0x00090003, + 0x00020004, 0x157C0006, 0x02B01770, 0x000902EE, + 0x0004000F, 0x0004000A, 0x00060002, 0x19001770, + 0x032002EE, 0x00100009, 0x000B0004, 0x00020004, + 0x19000006, 0x03201D4C, 0x000B03AA, 0x00050013, + 0x0005000D, 0x00070002, 0x21551D4C, 0x042B03AA, + 0x0016000C, 0x000F0005, 0x00020006, 0x21550008, + 0x042B2580, 0x000E04B0, 0x00060018, 0x00070010, + 0x00090002, 0x02150028, 0x0085000A, 0x00060006, + 0x00000006, 0x00000000, 0x00060001, 0x02150007, + 0x0085042B, 0x0008010B, 0x00080008, 0x00000000, + 0x00020000, 0x00090007, 0x0640042B, 0x0190010B, + 0x000A000A, 0x0001000C, 0x00030001, 0x00080002, + 0x0640000A, 0x01900855, 0x000C0215, 0x000E000E, + 0x00040002, 0x00030004, 0x000B0008, 0x0ABE0855, + 0x02B00215, 0x00100010, 0x00030012, 0x00050003, + 0x000A0004, 0x0ABE000E, 0x02B00C80, 0x00120320, + 0x00140014, 0x00070005, 0x00040007, 0x000E000A, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00280000, 0x00050215, + 0x00030043, 0x00030003, 0x00000000, 0x00010000, + 0x00040003, 0x042B0215, 0x00850043, 0x00040004, + 0x00000004, 0x00000000, 0x00040001, 0x042B0005, + 0x00850640, 0x000500C8, 0x00050005, 0x00010001, + 0x00010002, 0x00050004, 0x08550640, 0x010B00C8, + 0x00070006, 0x00010007, 0x00020002, 0x00040002, + 0x08550006, 0x010B0ABE, 0x00080158, 0x00090008, + 0x00020002, 0x00020003, 0x00070005, 0x0C800ABE, + 0x01900158, 0x000A0009, 0x0003000A, 0x00040004, + 0x00050002, 0x0C800007, 0x01900E95, 0x000A01D3, + 0x000C000B, 0x00040003, 0x00030005, 0x00080005, + 0x10AB0E95, 0x021501D3, 0x000D000C, 0x0004000E, + 0x00060005, 0x00060003, 0x10AB0009, 0x021512C0, + 0x000D0258, 0x000F000E, 0x00060005, 0x00030007, + 0x00090006, 0x157C12C0, 0x02B00258, 0x0010000F, + 0x00060011, 0x00080007, 0x00060004, 0x157C000A, + 0x02B01770, 0x001002EE, 0x00130011, 0x00070006, + 0x00040009, 0x000B0007, 0x19001770, 0x032002EE, + 0x00120011, 0x00070014, 0x000A0008, 0x00070004, + 0x1900000B, 0x03201D4C, 0x001403AA, 0x00180016, + 0x00090007, 0x0005000B, 0x000E0009, 0x21551D4C, + 0x042B03AA, 0x00190017, 0x0008001A, 0x000B000A, + 0x000A0006, 0x21550010, 0x042B2580, 0x001904B0, + 0x001D001C, 0x000B0008, 0x0007000C, 0x0012000B, + 0x00000A05, 0x50000000, 0x446B6C63, 0x6F434143, + 0x43416564, 0x63500030, 0x43446B6C, 0x646F4341, + 0x53514465, 0x6C635000, 0x4143446B, 0x65646F43, + 0x00314341, 0x6B6C6350, 0x4F444344, 0x65736666, + 0x30434174, 0x6C635000, 0x4443446B, 0x7366664F, + 0x43417465, 0x63500031, 0x43446B6C, 0x66664F44, + 0x44746573, 0x50005351, 0x446B6C63, 0x6F434143, + 0x71446564, 0x00306E4C, 0x6B6C6350, 0x43414344, + 0x4465646F, 0x316E4C71, 0x6C635000, 0x4143446B, + 0x65646F43, 0x6E4C7144, 0x63500032, 0x43446B6C, + 0x646F4341, 0x4C714465, 0x5000336E, 0x446B6C63, + 0x6F434143, 0x71446564, 0x00346E4C, 0x6B6C6350, + 0x4F444344, 0x65736666, 0x4C714474, 0x5000306E, + 0x446B6C63, 0x664F4443, 0x74657366, 0x6E4C7144, + 0x63500031, 0x43446B6C, 0x66664F44, 0x44746573, + 0x326E4C71, 0x6C635000, 0x4443446B, 0x7366664F, + 0x71447465, 0x00336E4C, 0x6B6C6350, 0x4F444344, + 0x65736666, 0x4C714474, 0x0000346E, 0x04050607, + 0x00010203, 0x0C0B0A09, 0xB50F0E0D, 0x000001FF, + 0x01F0B500, 0xB3000100, 0x000001F0, 0x01F0B400, + 0xB0000100, 0x300001F0, 0x07F00300, 0x04000000, + 0x000007F0, 0x01FE0300, 0x04000000, 0x000001FE, + 0x07F01100, 0x21000000, 0x000001FE, 0x01FFBE00, + 0xBE000000, 0x010001F0, 0x01F0A700, 0xA2000000, + 0x020001F0, 0x02007900, 0x00004000, 0x0001008B, + 0xF05F0000, 0x00000001, 0x0001FFB5, 0xF0B30001, + 0x01FF0001, 0x0001F0B4, 0xF0B001FF, 0x00300001, + 0x0007F003, 0xF0040000, 0x00000007, 0x0001FE03, + 0xFE040000, 0x00000001, 0x0007F011, 0xFE210000, + 0x00000001, 0x0001F0B1, 0xF0A70002, 0x00000001, + 0x000E000F, 0x000C000D, 0x000A000B, 0x00080009, + 0x00060007, 0x00040005, 0x00020003, 0x00000001, + 0x00110010, 0x00130012, 0x00150014, 0x00170016, + 0x00190018, 0x001B001A, 0x001D001C, 0x001F001E, + 0xEF77DBB7, 0xFBDFF7BD, 0xBDDFB76F, 0xBDFFBDEF, + 0x00000200, 0x00000200, 0x00000200, 0x00000200, + 0x00000010, 0x00000010, 0x00000010, 0x00000010, + 0x0001FFB5, 0xF0B30001, 0x00000001, 0x0001F0B4, + 0xF0B90000, 0x00010001, 0x0001F0BA, 0xF0B10001, + 0x00020001, 0x0007F003, 0xF0040000, 0x00000007, + 0x0001FE03, 0xFE040000, 0x00000001, 0x0007F011, + 0xFE210000, 0x00000001, 0x0007F010, 0xFE200002, + 0x00020001, 0x0007F01B, 0xF01CFFFF, 0xFFFF0007, + 0x0001FE2A, 0xFE2BFFFF, 0xFFFF0001, 0x00020079, + 0xFFB50040, 0x00010001, 0x0001F0B3, 0xF0B40000, + 0x00000001, 0x0001F0B9, 0xF0BA0001, 0x00010001, + 0x0001F0B1, 0xF0B00002, 0x00300001, 0x0007F003, + 0xF0040000, 0x00000007, 0x0001FE03, 0xFE040000, + 0x00000001, 0x0007F011, 0xFE210000, 0x00000001, + 0x0007F010, 0xFE200002, 0x00020001, 0x0007F01B, + 0xF01CFFFF, 0xFFFF0007, 0x0001FE2A, 0xFE2BFFFF, + 0xFFFF0001, 0x00020079, 0x00000040, 0x08840884, + 0x00000020, 0x00010010, 0x00010012, 0x0001007A, + 0x00010028, 0x00060000, 0x50005000, 0x02008050, + 0x00000000, 0x00060080, 0x3C5A5555, 0x00600000, + 0x00000000, 0x00000000, 0x00000070, 0x00000075, + 0x00000026, 0x000000A0, 0x000000A1, 0x000000A4, + 0x000000A5, 0x0A030201, 0x0E0D0C0B, 0x1413120F, + 0x18171615, 0x1E1C1A19, 0x2221201F, 0x2E292825, + 0x4746453A, 0x004A4948, 0x00000000, 0x00000000, +}; + +static const u32 DMAC_TRANS_ACSM[] = { + 0x0000C028, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0000C858, 0x00100000, 0x0000E088, 0x00100000, + 0x0000E038, 0x00100000, 0x0000C858, 0x00100000, + 0x0000C088, 0x00100000, 0x00000000, 0x00000000, + 0x0000C028, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0000C858, 0x00100000, 0x0000E208, 0x00100000, + 0x0000E038, 0x00100000, 0x0000C858, 0x00100000, + 0x0000C208, 0x00100000, 0x00000000, 0x00000000, + 0x0000C040, 0x00100000, 0x00000000, 0x00100000, + 0x0000C068, 0x00100000, 0x00000000, 0x00000000, + 0x0000C2F0, 0x00100000, 0x00000000, 0x00000000, + 0x0000C370, 0x00100000, 0x00000000, 0x00000000, + 0x0000D2D8, 0x00100000, 0x0000E008, 0x00100000, + 0x00000000, 0x7B000000, 0x00000000, 0x00000000, + 0x0000C0F0, 0x00100000, 0x0000CFD8, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D058, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D0D8, 0x00100000, + 0x0000C088, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D158, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x6B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00402C, 0x04000001, 0x08004050, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x08034050, 0x00000000, + 0x00000000, 0x1F000000, 0x00000000, 0x08000000, + 0x00000000, 0x04000000, 0x0000407C, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000001, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00802C, 0x04100001, 0x08008050, 0x00100000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x08038050, 0x00100000, + 0x00000000, 0x1F000000, 0x00000000, 0x08000000, + 0x00000000, 0x04000000, 0x0000807C, 0x00100000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000001, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00402C, 0x00000001, 0x08004050, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08034050, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08034050, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08004050, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x08000000, + 0x00000000, 0x00000000, 0x0000407C, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x1C000000, + 0x0D00802C, 0x00100001, 0x08008050, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08038050, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08038050, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08008050, 0x00100000, + 0x00000000, 0x1B000000, 0x00000000, 0x08000000, + 0x00000000, 0x00000000, 0x0000807C, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x4B000000, 0x00000000, 0x28000000, + 0x0D00402C, 0x00000001, 0x08035198, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08035218, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x08000000, + 0x00000000, 0x00000000, 0x0000407C, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x0D00802C, 0x00100001, 0x08039198, 0x00100000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08039218, 0x00100000, + 0x00000000, 0x1B000000, 0x00000000, 0x08000000, + 0x00000000, 0x00000000, 0x0000807C, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x04000000, + 0x0000D2D8, 0x00100000, 0x0000E008, 0x00100000, + 0x00000000, 0x7B000000, 0x00000000, 0x00000000, + 0x0000C0F0, 0x00100000, 0x0000CFD8, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D058, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D0D8, 0x00100000, + 0x0000C088, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D158, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x6B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00402C, 0x04000001, 0x08004050, 0x00000000, + 0x00000000, 0x04000000, 0x08034050, 0x00000000, + 0x00000000, 0x4F000000, 0x00000000, 0x08000000, + 0x0000407C, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x1F000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000001, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00802C, 0x04100001, 0x08008050, 0x00100000, + 0x00000000, 0x04000000, 0x08038050, 0x00100000, + 0x00000000, 0x4F000000, 0x00000000, 0x08000000, + 0x0000807C, 0x04100000, 0x00000000, 0x00000000, + 0x00000000, 0x1F000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000001, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00402C, 0x00000001, 0x08004050, 0x00000000, + 0x00000000, 0x00000000, 0x08034050, 0x00000000, + 0x00000000, 0x00000000, 0x08034050, 0x00000000, + 0x00000000, 0x00000000, 0x08004050, 0x00000000, + 0x00000000, 0x4B000000, 0x00000000, 0x08000000, + 0x0000407C, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x1C000000, + 0x0D00802C, 0x00100001, 0x08008050, 0x00100000, + 0x00000000, 0x00000000, 0x08038050, 0x00100000, + 0x00000000, 0x00000000, 0x08038050, 0x00100000, + 0x00000000, 0x00000000, 0x08008050, 0x00100000, + 0x00000000, 0x4B000000, 0x00000000, 0x08000000, + 0x0000807C, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x28000000, + 0x0D00402C, 0x00000001, 0x08035198, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08035218, 0x00000000, + 0x00000000, 0x4B000000, 0x00000000, 0x08000000, + 0x0000407C, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00802C, 0x00100001, 0x08039198, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08039218, 0x00100000, + 0x00000000, 0x4B000000, 0x00000000, 0x08000000, + 0x0000807C, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x6B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DATA_A[] = { + 0x00000001, 0x00000019, 0x0000002E, 0x00000043, + 0x0000005B, 0x00000070, 0x00000085, 0x0000009D, + 0x000000B2, 0x000000C7, 0x000000DF, 0x000000F4, + 0x00000109, 0x00000113, 0x00000115, 0x00000119, +}; + +static const u32 DATA_B[] = { + 0x00000018, 0x0000002D, 0x00000042, 0x0000005A, + 0x0000006F, 0x00000084, 0x0000009C, 0x000000B1, + 0x000000C6, 0x000000DE, 0x000000F3, 0x00000108, + 0x00000112, 0x00000114, 0x00000118, 0x0000011A, +}; + +static const u32 ACSM_0[] = { + 0x0000C9D8, 0x00000000, 0x0000C808, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C958, 0x00000000, 0x0000C608, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C0D8, 0x00000000, 0x0000E848, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C158, 0x00000000, 0x0000EEC8, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C1D8, 0x00000000, 0x0000C348, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C558, 0x00000000, 0x0000EA08, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C5D8, 0x00000000, 0x0000DA48, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x000048D8, 0x00000000, 0x00004308, 0x00000000, + 0x000088D8, 0x00000000, 0x00009708, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000CA58, 0x00000000, 0x0000C108, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000CB58, 0x00000000, 0x0000C008, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000D4D8, 0x00000000, 0x0000F008, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000DD58, 0x00000000, 0x0000C008, 0x00000000, +}; + +static const u32 ACSM_123[] = { + 0x0000C9D8, 0x00000000, 0x0000C008, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C958, 0x00000000, 0x0000C008, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C0D8, 0x00000000, 0x0000E808, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C158, 0x00000000, 0x0000EA88, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C1D8, 0x00000000, 0x0000C308, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C558, 0x00000000, 0x0000EA08, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C5D8, 0x00000000, 0x0000C008, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x000048D8, 0x00000000, 0x00004008, 0x00000000, + 0x000088D8, 0x00000000, 0x00009408, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000CA58, 0x00000000, 0x0000C108, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000CB58, 0x00000000, 0x0000C008, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000D4D8, 0x00000000, 0x0000F008, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000DD58, 0x00000000, 0x0000C008, 0x00000000, +}; + +static const u32 DATA_C[] = { + 0x00000000, 0x000000FE, 0x000000A8, 0x0000F040, + 0x0000F040, 0x00000000, 0x0000FFFF, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DATA_3_1[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x0000084F, + 0x0000084F, 0x0000082B, 0x0000082B, 0x0000084F, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00001810, 0x00001810, 0x00000428, 0x0000192C, + 0x0000181C, 0x0000181C, 0x00000434, 0x00003938, + 0x00001808, 0x00001808, 0x00000420, 0x00001124, +}; + +static const u32 DATA_3_2[] = { + 0x000040A0, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x0000024E, 0x0000004E, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0000024E, 0x0000004E, 0x0000006F, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DATA_3_3[] = { + 0x00000086, 0x00000190, 0x00000A69, 0x00000058, + 0x0000001B, 0x00000000, 0x00000043, 0x00000000, + 0x00000017, 0x0000004F, 0x00000006, 0x00000006, + 0x0000000E, 0x00000068, 0x00000000, 0x00000000, +}; + +static const u32 DATA_3_4[] = { + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000009, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x0000001C, 0x0000071C, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000077, 0x00000707, 0x00000030, 0x00003300, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000099, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DATA_3_5[] = { + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000009, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x0000001C, 0x0000071C, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000077, 0x00007777, 0x00000030, 0x00003300, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000099, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DMAC_TRANS_PIE[] = { + 0x3f7ab480, 0x00016420, 0x00000400, 0x00000000, + 0x80000480, 0x00000fc0, 0x04000c00, 0x00000000, + 0x84000480, 0x00000c00, 0x04000800, 0x00000000, + 0x84000080, 0x00000c00, 0x000001e0, 0x00000000, + 0x80068200, 0x0000400f, 0x00008d40, 0x00000000, + 0xa0000480, 0x00002420, 0x04000400, 0x00000000, + 0x9c001ca0, 0x00001c04, 0xa8000880, 0x00001c06, + 0x80010080, 0x00001c04, 0x04000400, 0x00000000, + 0x80010480, 0x00001c04, 0x04000800, 0x00000000, + 0x00000040, 0x00006000, 0xa0000080, 0x00002420, + 0x00001020, 0x00000000, 0x00001020, 0x00000000, + 0x00001020, 0x00000000, 0x00003020, 0x00000000, + 0x80000080, 0x00001c04, 0xa8000880, 0x00001c06, + 0x80010880, 0x00001c04, 0x04000400, 0x00000000, + 0x80010c80, 0x00001c04, 0x04000800, 0x00000000, + 0x00001020, 0x00000000, 0x00002c20, 0x00000000, + 0x00002c20, 0x00000000, 0x00002c20, 0x00000000, + 0x80000080, 0x00001c04, 0x000001e0, 0x00000000, + 0xa8000480, 0x00001c04, 0x04000400, 0x00000000, + 0x40004200, 0x00004000, 0x00011140, 0x00000000, + 0xc80038a0, 0x00001c01, 0xcc003ca0, 0x00001c01, + 0xa40000a0, 0x00001c06, 0xa8001c80, 0x00001c06, + 0x80051080, 0x00001c04, 0x04000400, 0x00000000, + 0x80051480, 0x00001c04, 0x04000800, 0x00000000, + 0x00000840, 0x00006000, 0x80000080, 0x00001c04, + 0xcc000080, 0x00001c01, 0xa8001c80, 0x00001c06, + 0x80051880, 0x00001c04, 0x04000400, 0x00000000, + 0x80051c80, 0x00001c04, 0x04000800, 0x00000000, + 0x00000840, 0x00006000, 0x80000080, 0x00001c04, + 0xc8000080, 0x00001c01, 0xcc003ca0, 0x00001c01, + 0xa8001c80, 0x00001c06, 0x80052080, 0x00001c04, + 0x04000400, 0x00000000, 0x80052480, 0x00001c04, + 0x04000800, 0x00000000, 0x00000840, 0x00006000, + 0x80000080, 0x00001c04, 0xc80038a0, 0x00001c01, + 0x54000091, 0x00018fc0, 0x54000091, 0x00014fc0, + 0xf0000091, 0x000187c1, 0xf0000091, 0x000147c1, + 0x08000611, 0x00001800, 0x00013d71, 0x00000000, + 0x04000911, 0x0001a420, 0x04001000, 0x00000000, + 0x00000a11, 0x00001800, 0x00017551, 0x00000000, + 0x00014571, 0x00000000, 0x00000611, 0x00001800, + 0x00017571, 0x00000000, 0x24000491, 0x0001e420, + 0x000021d1, 0x00000000, 0x00001031, 0x00000000, + 0x00001031, 0x00000000, 0x00002c31, 0x00000000, + 0xa8000091, 0x00001c06, 0x80016891, 0x00001c04, + 0x04000400, 0x00000000, 0x80016c91, 0x00001c04, + 0x04000800, 0x00000000, 0x00000851, 0x00006000, + 0x80000091, 0x00001c04, 0xa8000080, 0x00001c04, + 0x04000800, 0x00000000, 0x000001e0, 0x00000000, + 0xa8000080, 0x00001c06, 0x80012880, 0x00001c04, + 0x04000400, 0x00000000, 0x80012c80, 0x00001c04, + 0x04000800, 0x00000000, 0x00000840, 0x00006000, + 0x80000080, 0x00001c04, 0x000001e0, 0x00000000, + 0x00080200, 0x0000400e, 0x0001b540, 0x00000000, + 0x00020200, 0x0000400e, 0x0001b540, 0x00000000, + 0x80068200, 0x0000400f, 0x30000cc0, 0x000007c4, + 0x000001e0, 0x00000000, 0x00100600, 0x00000010, + 0x2c0004c0, 0x000003c0, 0x8c0028a0, 0x00017bc1, + 0xa0000480, 0x00002420, 0x04000400, 0x00000000, + 0x8c0014a0, 0x000143c1, 0xa0000080, 0x00002420, + 0x78000480, 0x000003d8, 0x7c000480, 0x000007f8, + 0x08000080, 0x00000fe0, 0x08000080, 0x000007e0, + 0x00080600, 0x00000008, 0x000004c0, 0x00014fc4, + 0x000004c0, 0x000147c4, 0x00002420, 0x00000000, + 0x08000480, 0x00000fe0, 0x08000480, 0x000007e0, + 0x00000080, 0x00014fc4, 0x00000080, 0x000147c4, + 0x78000080, 0x000003d8, 0x7c000080, 0x000007f8, + 0x8c002ca0, 0x00017bc1, 0xa0000480, 0x00002420, + 0x04000400, 0x00000000, 0x8c0018a0, 0x000143c1, + 0xa0000080, 0x00002420, 0x2c000080, 0x00000000, + 0x2c000080, 0x00000040, 0x2c000080, 0x00000080, + 0x2c000080, 0x000000c0, 0x2c000080, 0x00000100, + 0x2c000080, 0x00000140, 0x00200600, 0x00000020, + 0x2c0000c0, 0x000001c0, 0x2c0000c0, 0x00000200, + 0x2c0000c0, 0x00000240, 0x2c0000c0, 0x00000280, + 0x2c0000c0, 0x000002c0, 0x2c0000c0, 0x00000300, + 0xc4000880, 0x000007c0, 0x04000400, 0x00000000, + 0x0c000480, 0x00000fc4, 0x04002000, 0x00000000, + 0x0c000480, 0x000007c4, 0x04002000, 0x00000000, + 0x0c000080, 0x00000fc4, 0x0c000080, 0x000007c4, + 0xc4000080, 0x000007c0, 0x04000400, 0x00000000, + 0xe0000480, 0x00000803, 0x04002000, 0x00000000, + 0x04000600, 0x00000400, 0x265a58c0, 0x000187c8, + 0x58000080, 0x000007c0, 0x04000400, 0x00000000, + 0xe0000080, 0x00000803, 0x04002000, 0x00000000, + 0x000001e0, 0x00000000, 0x50000080, 0x00001c01, + 0x40000480, 0x00002c0c, 0xc4000080, 0x000007c0, + 0x2c000080, 0x000007c2, 0x8c200080, 0x00000fc2, + 0x00200600, 0x00000020, 0x880c0080, 0x00000c02, + 0x880c00c0, 0x00000c42, 0x247ffc80, 0x000007c2, + 0x281ffc80, 0x000007c2, 0x04000400, 0x00000000, + 0x800c0080, 0x00000fc2, 0x04000800, 0x00000000, + 0x98000480, 0x00000fc2, 0x28000480, 0x00000fc0, + 0x04001000, 0x00000000, 0x80fffc80, 0x00000fc2, + 0x30000080, 0x000007c4, 0x00010600, 0x00000001, + 0x0002fd40, 0x00000000, 0x80068200, 0x0000400f, + 0x00030160, 0x00000000, 0x0001a1c0, 0x00000000, + 0xe0000480, 0x00000803, 0x04001c00, 0x00000000, + 0x28000080, 0x00000fc0, 0x88000480, 0x00000802, + 0x04000400, 0x00000000, 0x5c000080, 0x000007c2, + 0x02000600, 0x00000200, 0x2c0010c0, 0x00003bc1, + 0x2c001880, 0x00003bc1, 0x18001880, 0x00003bc1, + 0x1c001880, 0x00003bc1, 0x20001880, 0x00003bc1, + 0x24001880, 0x00003bc1, 0x28001880, 0x00003bc1, + 0x00020200, 0x0000400e, 0x00036d40, 0x00000000, + 0x40004600, 0x00000000, 0x00035940, 0x00000000, + 0x04000900, 0x0001a420, 0x04001000, 0x00000000, + 0x40004a00, 0x00000000, 0x0c0010e0, 0x00001800, + 0x0c0000c0, 0x00001800, 0x04000480, 0x00001800, + 0x04000800, 0x00000000, 0x08000480, 0x00001800, + 0x04000800, 0x00000000, 0x000001e0, 0x00000000, + 0x9c000cb1, 0x00001c01, 0x9c0010b1, 0x00001c03, + 0x24000091, 0x00001c01, 0x00000051, 0x00004000, + 0x00039531, 0x00000000, 0x40001a01, 0x00000000, + 0x00039561, 0x00000000, 0x24000081, 0x00001c01, + 0x00000041, 0x00004000, 0x000001e0, 0x00000000, + 0x84000900, 0x0000241c, 0xc0014200, 0x0000c001, + 0x0003ad40, 0x00000000, 0x04001000, 0x00000000, + 0x2c0008a0, 0x00000802, 0x000001e0, 0x00000000, + 0x40000480, 0x00002c0c, 0x04000400, 0x00000000, + 0x04000080, 0x00002c00, 0x04000400, 0x00000000, + 0x00020200, 0x0000400e, 0x00044540, 0x00000000, + 0x40004600, 0x00000000, 0x040004c0, 0x00001800, + 0x080004c0, 0x00001800, 0x00044540, 0x00000000, + 0x08000080, 0x00001800, 0x04000400, 0x00000000, + 0x04000080, 0x00001800, 0x00000081, 0x00001800, + 0x04000400, 0x00000000, 0x88000480, 0x00000802, + 0x04000800, 0x00000000, 0x0c000900, 0x00001800, + 0x04001000, 0x00000000, 0x00010a00, 0x00000001, + 0x00042140, 0x00000000, 0x0c000c80, 0x00001800, + 0x00000020, 0x00000000, 0x00000020, 0x00000000, + 0x0c000880, 0x00001800, 0x00000020, 0x00000000, + 0x0c000080, 0x00001800, 0x00044920, 0x00000000, + 0x0c001c80, 0x00001800, 0x00001020, 0x00000000, + 0x00001020, 0x00000000, 0x0c001880, 0x00001800, + 0x00001020, 0x00000000, 0x00001020, 0x00000000, + 0x00001020, 0x00000000, 0x0c001080, 0x00001800, + 0x00044920, 0x00000000, 0x00000080, 0x00001800, + 0x00200600, 0x00000020, 0x0004a160, 0x00000000, + 0x18000080, 0x00003bc1, 0x1c000080, 0x00003bc1, + 0x20000080, 0x00003bc1, 0x24000080, 0x00003bc1, + 0x28000080, 0x00003bc1, 0x2c000880, 0x00003801, + 0x2c001080, 0x00003841, 0x2c000880, 0x00003881, + 0x2c001080, 0x000038c1, 0x2c000880, 0x00003901, + 0x2c001080, 0x00003941, 0x2c000880, 0x00003981, + 0x2c001080, 0x000039c1, 0x02000600, 0x00000200, + 0x2c0010c0, 0x00003bc1, 0x58000080, 0x000003cf, + 0x5c000080, 0x000003cf, 0x5c000880, 0x000000cf, + 0x5c000880, 0x0000028f, 0x00052d20, 0x00000000, + 0x18000080, 0x00003801, 0x18000080, 0x00003841, + 0x18000080, 0x00003881, 0x18000080, 0x000038c1, + 0x1c000080, 0x00003801, 0x1c000080, 0x00003841, + 0x1c000080, 0x00003881, 0x1c000080, 0x000038c1, + 0x20000080, 0x00003801, 0x20000080, 0x00003841, + 0x20000080, 0x00003881, 0x20000080, 0x000038c1, + 0x24000080, 0x00003801, 0x24000080, 0x00003841, + 0x24000080, 0x00003881, 0x24000080, 0x000038c1, + 0x28000080, 0x00003841, 0x28000080, 0x000038c1, + 0x2c000880, 0x00003801, 0x2c001080, 0x00003841, + 0x2c000880, 0x00003881, 0x2c001080, 0x000038c1, + 0x02000600, 0x00000200, 0x2c0010c0, 0x00003bc1, + 0x58000080, 0x0000000f, 0x5c000080, 0x0000000f, + 0x58000080, 0x0000004f, 0x5c000080, 0x0000004f, + 0x58000080, 0x0000008f, 0x5c000080, 0x0000008f, + 0x58000080, 0x000000cf, 0x58000080, 0x0000010f, + 0x5c000080, 0x0000010f, 0x58000080, 0x0000014f, + 0x5c000080, 0x0000014f, 0x20000080, 0x00002bcc, + 0x00053d31, 0x00000000, 0x40001a00, 0x00000000, + 0x00053d60, 0x00000000, 0x040030a0, 0x00002c00, + 0x88000080, 0x00000802, 0x5c1ffc80, 0x000007c2, + 0x00800600, 0x00000080, 0xbc000900, 0x00016c0c, + 0x040000c0, 0x00002424, 0x040080e0, 0x00002424, + 0x04000000, 0x00000000, 0x98000095, 0x00002c0c, + 0x9c000095, 0x00002c0c, 0x98001cb5, 0x00002c0c, + 0x9c0020b5, 0x00002c0c, 0x98000095, 0x00002c0c, + 0x9c000095, 0x00002c0c, 0x40000095, 0x00002c0c, + 0x00000605, 0x00002000, 0x400000c5, 0x00002c0c, + 0x800004c5, 0x00002c0c, 0x800000c5, 0x00002c0c, + 0x040000e5, 0x00002c00, 0xbc0000e5, 0x00016c0c, + 0x04000000, 0x00000000, 0x9bfe00e5, 0x00002c0c, + 0x9ffe00e5, 0x00002c0c, 0x9bfe04e5, 0x00002c0c, + 0x9ffe04e5, 0x00002c0c, 0x9bfe00e5, 0x00002c0c, + 0x9ffe00e5, 0x00002c0c, 0x400004e5, 0x00002c0c, + 0x04000400, 0x00000000, 0xbc0008a5, 0x00016c0c, + 0x000001e0, 0x00000000, 0xe8030c80, 0x00001c01, + 0x04000400, 0x00000000, 0xe8000080, 0x00001c01, + 0x000001e0, 0x00000000, 0x88000080, 0x00000802, + 0x04000c00, 0x00000000, 0x0000cc80, 0x00000808, + 0x1c000480, 0x00000fc1, 0x1c000080, 0x00000fc1, + 0x1c000480, 0x000007c1, 0x1c000080, 0x000007c1, + 0x00000080, 0x00000808, 0x50000080, 0x00001c01, + 0xb8000480, 0x00000801, 0x04000400, 0x00000000, + 0x00040600, 0x00000004, 0x598000e0, 0x000007c0, + 0x28000480, 0x00000fc0, 0x04001000, 0x00000000, + 0xe0000080, 0x00000803, 0x04001400, 0x00000000, + 0x88000880, 0x00000802, 0x00000c20, 0x00000000, + 0x40004600, 0x00000000, 0x00062160, 0x00000000, + 0x1c000880, 0x00000fc1, 0x1c000080, 0x00000fc1, + 0x1c000880, 0x000007c1, 0x1c000080, 0x000007c1, + 0x04003c00, 0x00000000, 0x00040600, 0x00000004, + 0x00064140, 0x00000000, 0x0001bdc0, 0x00000000, + 0x28000080, 0x00000fc0, 0x80000080, 0x00000fc2, + 0x98000080, 0x00000fc2, 0x24000080, 0x000007c2, + 0x28000080, 0x000007c2, 0x883c0080, 0x00000fc2, + 0x80040200, 0x0000400f, 0x00067940, 0x00000000, + 0x00080200, 0x0000400e, 0x00067940, 0x00000000, + 0xe4000480, 0x00000801, 0x04000800, 0x00000000, + 0xe4000080, 0x00000801, 0x04000800, 0x00000000, + 0xe8030c81, 0x00001c01, 0x04000800, 0x00000000, + 0xe8000081, 0x00001c01, 0x04000400, 0x00000000, + 0x40001a01, 0x00000000, 0x0006a541, 0x00000000, + 0xa0000481, 0x00002420, 0x04000400, 0x00000000, + 0x40003201, 0x00000000, 0x0006c541, 0x00000000, + 0x0006a561, 0x00000000, 0x00001c21, 0x00000000, + 0xa0000081, 0x00002420, 0x04000400, 0x00000000, + 0x00020601, 0x00000002, 0xe8030cc1, 0x00001c01, + 0x04000800, 0x00000000, 0xe80000c1, 0x00001c01, + 0x04000400, 0x00000000, 0xa0000081, 0x00002420, + 0x04000400, 0x00000000, 0xe8030c91, 0x00001c01, + 0x04000800, 0x00000000, 0xe8000091, 0x00001c01, + 0x04000400, 0x00000000, 0xa8000480, 0x00001c04, + 0x04000400, 0x00000000, 0x18000081, 0x0001e420, + 0x40006611, 0x00000000, 0x0006f551, 0x00000000, + 0x000021d1, 0x00000000, 0xa0000491, 0x00002420, + 0x04000400, 0x00000000, 0x540020b1, 0x00014fc0, + 0xf00024b1, 0x000147c1, 0xa0000091, 0x00002420, + 0x000001e0, 0x00000000, 0xa8000080, 0x00001c06, + 0x80013080, 0x00001c04, 0x04000400, 0x00000000, + 0x80013480, 0x00001c04, 0x04000800, 0x00000000, + 0x04001c00, 0x00000000, 0x80000080, 0x00001c04, + 0x00000420, 0x00000000, 0xa8000080, 0x00001c06, + 0x80013880, 0x00001c04, 0x04000400, 0x00000000, + 0x80013c80, 0x00001c04, 0x04000800, 0x00000000, + 0x04001c00, 0x00000000, 0x80000080, 0x00001c04, + 0x000001e0, 0x00000000, 0x20000086, 0x0001c7c4, + 0x9e000480, 0x000007c2, 0xc4060080, 0x000007c2, + 0xd4000480, 0x000007c2, 0xe4000480, 0x000007c2, + 0x9c003080, 0x00001c04, 0x7c000080, 0x0001c7c1, + 0x88000c80, 0x000007c2, 0x64000c80, 0x00000801, + 0x90000880, 0x000007c2, 0xec0ffc80, 0x000007c2, + 0xec000080, 0x000007c2, 0xf8000080, 0x000007fe, + 0xf8000480, 0x000007c2, 0xf8000480, 0x000007d2, + 0xa8001080, 0x00001c06, 0x80014880, 0x00001c04, + 0x04000400, 0x00000000, 0x80014c80, 0x00001c04, + 0x04000800, 0x00000000, 0x00000840, 0x00006000, + 0x80000080, 0x00001c04, 0xf8000080, 0x000007c2, + 0xf8000080, 0x000007d2, 0xec0ffc80, 0x000007c2, + 0xec000080, 0x000007c2, 0xf8000480, 0x000007c6, + 0xf8000480, 0x000007d6, 0xa8001080, 0x00001c06, + 0x80015080, 0x00001c04, 0x04000400, 0x00000000, + 0x80015480, 0x00001c04, 0x04000800, 0x00000000, + 0x00000840, 0x00006000, 0x80000080, 0x00001c04, + 0xf8000080, 0x000007c6, 0xf8000080, 0x000007d6, + 0x64000880, 0x00000801, 0x00001420, 0x00000000, + 0xc4000480, 0x000007c0, 0x04001000, 0x00000000, + 0xc4000080, 0x000007c0, 0x04000600, 0x00000400, + 0x24c8c8c0, 0x000147c8, 0x80000480, 0x00000802, + 0x04000400, 0x00000000, 0x80000080, 0x00000802, + 0x90000080, 0x000007c2, 0x98000c80, 0x000007c2, + 0xa8001080, 0x00001c06, 0x80015880, 0x00001c04, + 0x04000400, 0x00000000, 0x80015c80, 0x00001c04, + 0x04000800, 0x00000000, 0x00000840, 0x00006000, + 0x80000080, 0x00001c04, 0x04000800, 0x00000000, + 0x98000080, 0x000007c2, 0x88000080, 0x000007c2, + 0x64000080, 0x00000801, 0x7c000480, 0x0001c7c1, + 0xe4000480, 0x00000801, 0x04000800, 0x00000000, + 0xe4000080, 0x00000801, 0x04000800, 0x00000000, + 0x00001820, 0x00000000, 0x90000480, 0x000007c2, + 0xa8001080, 0x00001c06, 0x80016080, 0x00001c04, + 0x04000400, 0x00000000, 0x80016480, 0x00001c04, + 0x04000800, 0x00000000, 0x00000840, 0x00006000, + 0x80000080, 0x00001c04, 0x04000800, 0x00000000, + 0x80000480, 0x00000802, 0x04000400, 0x00000000, + 0x80000080, 0x00000802, 0x90000080, 0x000007c2, + 0x04000800, 0x00000000, 0xe4000480, 0x00000801, + 0x04000800, 0x00000000, 0xe4000080, 0x00000801, + 0x04000800, 0x00000000, 0xa8000080, 0x00001c04, + 0x50000480, 0x00001c01, 0x20000486, 0x0001c7c4, + 0x000001e0, 0x00000000, 0x80008600, 0x00000000, + 0x0008d560, 0x00000000, 0x80000480, 0x00000802, + 0x04000400, 0x00000000, 0x80000080, 0x00000802, + 0x04000400, 0x00000000, 0xe4000480, 0x00000801, + 0x04000800, 0x00000000, 0xe4000080, 0x00000801, + 0xa8000080, 0x00001c04, 0xb8000080, 0x00000801, + 0x04000800, 0x00000000, 0x00001080, 0x000033c2, + 0x50000480, 0x00001c01, 0xb4000080, 0x00002400, + 0x88000481, 0x00000c00, 0x24000480, 0x00001c01, + 0x000001e0, 0x00000000, 0x40000480, 0x00002c0c, + 0x2c000080, 0x000007c2, 0x8c000080, 0x00000fc2, + 0x00200600, 0x00000020, 0x880c0080, 0x00000c02, + 0x880c00c0, 0x00000c42, 0x247ffc80, 0x000007c2, + 0x281ffc80, 0x000007c2, 0x04000400, 0x00000000, + 0x98000480, 0x00000fc2, 0x28000480, 0x00000fc0, + 0x04001000, 0x00000000, 0x80fffc80, 0x00000fc2, + 0x04000400, 0x00000000, 0xe0000480, 0x00000803, + 0x04002000, 0x00000000, 0x28000080, 0x00000fc0, + 0x50000080, 0x00001c01, 0x00000480, 0x00001800, + 0x0c000080, 0x00001800, 0x5c000080, 0x000007c2, + 0x04000080, 0x00002c00, 0x02000600, 0x00000200, + 0x2c0010c0, 0x00003bc1, 0x2c001880, 0x00003bc1, + 0x18001880, 0x00003bc1, 0x1c001880, 0x00003bc1, + 0x20001880, 0x00003bc1, 0x24001880, 0x00003bc1, + 0x28001880, 0x00003bc1, 0x20000880, 0x00002bcc, + 0x040030a0, 0x00002c00, 0x24000080, 0x00001c01, + 0xb4000480, 0x00002400, 0x00000040, 0x00004000, + 0x00000020, 0x00000000, 0x00000020, 0x00000000, + 0x88000c80, 0x00000c00, 0x80000080, 0x00000fc0, + 0x04000c00, 0x00000000, 0x88000480, 0x00000802, + 0x000001e0, 0x00000000, 0x00001880, 0x000033c2, + 0x000009c1, 0x00000000, 0x9c000d11, 0x00001c01, + 0x04001011, 0x00000000, 0x9c001111, 0x00001c03, + 0x04001011, 0x00000000, 0x9c000091, 0x00001c01, + 0x9c000091, 0x00001c03, 0x0009dd21, 0x00000000, + 0xb8000480, 0x00000801, 0x04000800, 0x00000000, + 0x80068200, 0x0000400f, 0x0009d540, 0x00000000, + 0x000091c0, 0x00000000, 0x000181c0, 0x00000000, + 0x0002a5c0, 0x00000000, 0x000371c0, 0x00000000, + 0x000399c0, 0x00000000, 0x0003b1c0, 0x00000000, + 0x0005cdc0, 0x00000000, 0x40004200, 0x00000000, + 0x6001c0e0, 0x00002425, 0x00080200, 0x0000400e, + 0x000a2140, 0x00000000, 0x000a0531, 0x00000000, + 0x00070dc0, 0x00000000, 0x80008600, 0x00000000, + 0x000a2140, 0x00000000, 0x00074dc2, 0x00000000, + 0x80068200, 0x0000400f, 0xc40004c0, 0x000007c0, + 0x04001000, 0x00000000, 0xc40000c0, 0x000007c0, + 0x40006611, 0x00000000, 0x000a6951, 0x00000000, + 0x80068211, 0x0000400f, 0x000a6951, 0x00000000, + 0x00080211, 0x0000400e, 0x000a4151, 0x00000000, + 0x80008611, 0x00000000, 0x000a4d71, 0x00000000, + 0x00001031, 0x00000000, 0x00001031, 0x00000000, + 0x00002c31, 0x00000000, 0xa8000091, 0x00001c06, + 0x80016891, 0x00001c04, 0x04000400, 0x00000000, + 0x80016c91, 0x00001c04, 0x04000800, 0x00000000, + 0x00000851, 0x00006000, 0x80000091, 0x00001c04, + 0x24000091, 0x0001e420, 0x0008adc0, 0x00000000, + 0x00000000, 0x00000000, 0x0008f5c0, 0x00000000, + 0x24000480, 0x00001c01, 0x00000400, 0x00000000, + 0x50000080, 0x00001c01, 0x9c000d00, 0x00001c01, + 0x04001000, 0x00000000, 0x9c001100, 0x00001c03, + 0x04001000, 0x00000000, 0x9c000080, 0x00001c01, + 0x9c000080, 0x00001c03, 0x00001880, 0x000033c2, + 0xb8000480, 0x00000801, 0x04000c00, 0x00000000, + 0x24000491, 0x0001e420, 0xa8000080, 0x00001c06, + 0x80012880, 0x00001c04, 0x04000400, 0x00000000, + 0x80012c80, 0x00001c04, 0x04000800, 0x00000000, + 0x00000840, 0x00006000, 0x80000080, 0x00001c04, + 0x2c000080, 0x000007c2, 0x8c200080, 0x00000fc2, + 0x00200600, 0x00000020, 0x883c0080, 0x00000c02, + 0x883c00c0, 0x00000c42, 0x98000480, 0x00000fc2, + 0x28000480, 0x00000fc0, 0x04001000, 0x00000000, + 0x80fffc80, 0x00000fc2, 0x247ffc80, 0x000007c2, + 0x281ffc80, 0x000007c2, 0x04000400, 0x00000000, + 0xe0000480, 0x00000803, 0x28000080, 0x00000fc0, + 0x00800600, 0x00000080, 0x040000c0, 0x00002424, + 0x040080e0, 0x00002424, 0x400004e2, 0x00002c0c, + 0x04000800, 0x00000000, 0x400000e2, 0x00002c0c, + 0x04000800, 0x00000000, 0x800004e0, 0x00002c0c, + 0x800000e0, 0x00002c0c, 0x00000605, 0x00002000, + 0x400004c2, 0x00002c0c, 0x04000800, 0x00000000, + 0x400000c2, 0x00002c0c, 0x04000800, 0x00000000, + 0x800004c0, 0x00002c0c, 0x800000c0, 0x00002c0c, + 0x04000c00, 0x00000000, 0x24000080, 0x00001c01, + 0x10000200, 0x00005000, 0x000b5540, 0x00000000, + 0x00000040, 0x00004000, 0x28000480, 0x00000fc0, + 0x04001000, 0x00000000, 0xe0000080, 0x00000803, + 0x04000800, 0x00000000, 0x28000080, 0x00000fc0, + 0x80000080, 0x00000fc2, 0x98000080, 0x00000fc2, + 0x24000080, 0x000007c2, 0x28000080, 0x000007c2, + 0xe4000480, 0x00000801, 0x04000800, 0x00000000, + 0xe4000080, 0x00000801, 0x04000800, 0x00000000, + 0xa8000480, 0x00001c04, 0xe8030c80, 0x00001c01, + 0x04000800, 0x00000000, 0xe8000080, 0x00001c01, + 0x04000400, 0x00000000, 0x9c000ca0, 0x00001c01, + 0x9c0010a0, 0x00001c03, 0x000a0520, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DRAM_H__ */ diff --git a/include/dbsc5.h b/include/r8a779g0-dbsc5.h similarity index 100% rename from include/dbsc5.h rename to include/r8a779g0-dbsc5.h diff --git a/include/r8a78000-dbsc5.h b/include/r8a78000-dbsc5.h new file mode 100644 index 00000000000..7954f5b0761 --- /dev/null +++ b/include/r8a78000-dbsc5.h @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#ifndef __INCLUDE_DBSC5_H__ +#define __INCLUDE_DBSC5_H__ + +/* The number of channels X5H has */ +#define DRAM_CH_CNT 16 +/* The number of slices X5H has */ +#define SLICE_CNT 2 +/* The number of chip select X5H has */ +#define CS_CNT 2 + +struct renesas_dbsc5_board_config { + u32 bdcfg_phyvalid; + u32 bdcfg_tx_drv; + u32 bdcfg_tx_ffc; + u32 bdcfg_rx_odt; + u8 bdcfg_rx_dfe; + u8 bdcfg_tx_odt; + u8 bdcfg_tx_ntodt; + u8 bdcfg_tx_dfe; + u8 bdcfg_rx_dca; + u8 bdcfg_rx_drv; + u32 bdcfg_rx_emphasis; + u8 bdcfg_tx_dca; + u8 bdcfg_ca_vref; + u32 bdcfg_rx_vref; + u32 bdcfg_rx_vref_step; + u32 bdcfg_tx_vref; + u8 bdcfg_rfm_chk; + + /* Board parameter about channels */ + struct { + /* + * 0x00: 4Gb dual channel die / 2Gb single channel die + * 0x01: 6Gb dual channel die / 3Gb single channel die + * 0x02: 8Gb dual channel die / 4Gb single channel die + * 0x03: 12Gb dual channel die / 6Gb single channel die + * 0x04: 16Gb dual channel die / 8Gb single channel die + * 0x05: 24Gb dual channel die / 12Gb single channel die + * 0x06: 32Gb dual channel die / 16Gb single channel die + * 0x07: 24Gb single channel die + * 0x08: 32Gb single channel die + * 0xFF: NO_MEMORY + */ + u8 bdcfg_ddr_density[CS_CNT]; + /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ + u32 bdcfg_ca_swap; + /* SoC dqsX([1][0]) -> MEM dqsY: */ + u8 bdcfg_dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + u32 bdcfg_dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + u8 bdcfg_dm_swap[SLICE_CNT]; + } ch[DRAM_CH_CNT]; +}; + +#endif /* __INCLUDE_DBSC5_H__ */ From 28f675023da174b1b4817266cac7bcf3ffb6d908 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 10 Jun 2026 20:20:59 +0200 Subject: [PATCH 50/65] arm: dts: renesas: Enable DBSC5 on R-Car R8A78000 X5H Cortex-M33 RSIP port Bind the DBSC5 DRAM controller driver on boot in board_early_init_r(), which brings up the DBSC5 DRAM controller and its PHY and which enables access to DRAM present on this system. Add default boot command which loads additional bootloader components from HF and UFS storage into SRAM and DRAM, and starts those components on SCP and AP core 0. The system is then capable of reaching U-Boot on the AP core 0. Specifically, the following components are loaded: - SCP firmware, 384 kiB from HF offset 0x4c0000 to SCP STCM - TFA BL31, 256 kiB from UFS0 offset 0x5000 * 4 kiB sectors to DRAM 0x8c200000 - TEE, 2 MiB from UFS0 offset 0x5200 * 4 kiB sectors to DRAM 0x8c400000 - U-Boot, 1 MiB from UFS0 offset 0x7200 * 4 kiB sectors to DRAM 0x8c300000 - IPL parameters table is generated at DRAM address 0x8c100000 Enable pstore command support to allow dumping kernel console from pstore/ramoops, which is convenient for debugging. Use as follows: => pstore set 0x80000000 0x10000 0x400 0x8000 0 0 0 => pstore display console Signed-off-by: Marek Vasut --- .../dts/r8a78000-ironhide-cm33-u-boot.dtsi | 10 ++++ arch/arm/mach-renesas/Kconfig.rcar5 | 1 + board/renesas/common/gen5-cm33.c | 49 +++++++++++++++++++ configs/r8a78000_ironhide_cm33_defconfig | 8 ++- include/configs/rcar-gen5-common.h | 42 +++++++++++++++- 5 files changed, 108 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi index 2d4cdbac62a..356f633135d 100644 --- a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi @@ -65,10 +65,20 @@ syscon = <&ctl>; }; + ram@b8940000 { /* RT-VRAM */ + compatible = "renesas,r8a78000-rtvram"; + reg = <0 0xb8940000 0 0xf000>; + }; + scp@c1340000 { compatible = "renesas,r8a78000-rproc"; reg = <0 0xc1340000 0 0x80000>; }; + + ram@e9800000 { /* DBSC5 */ + compatible = "renesas,r8a78000-dbsc"; + reg = <0 0xe9800000 0 0x1000000>; + }; }; &cpg { diff --git a/arch/arm/mach-renesas/Kconfig.rcar5 b/arch/arm/mach-renesas/Kconfig.rcar5 index fcca3811241..33ad8522f07 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar5 +++ b/arch/arm/mach-renesas/Kconfig.rcar5 @@ -2,6 +2,7 @@ if RCAR_GEN5 config RCAR_64_RSIP bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)" + select LMB_ARCH_MEM_MAP select SKIP_RELOCATE_CODE select TMU_TIMER help diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c index e07db9817f2..f06df824019 100644 --- a/board/renesas/common/gen5-cm33.c +++ b/board/renesas/common/gen5-cm33.c @@ -904,6 +904,24 @@ static void mfis_unprotect(void) writel(MFIS_CODEVALUE, MFIS_WPCNTR); } +/** + * rsip_write_reg() - Write RSIP control register + * @reg: Register to write + * @val: Value to set in the register + */ +static void rsip_write_reg(const u32 reg, const int val) +{ + for (;;) { + writel(RSIP_CTL_PROT0PCMD_WREN, RSIP_CTL_PROT0PCMD); + writel(val, reg); + writel(~val, reg); + writel(val, reg); + + if (readl(RSIP_CTL_PROT0PS) != RSIP_CTL_PROT0PS_ERR) + break; + } +} + /** * rsip_irq_setup() - Configure RSIP interrupts */ @@ -1353,6 +1371,26 @@ int mach_cpu_init(void) return 0; } +int board_early_init_r(void) +{ + u32 remaptmp = readl(RSIP_CTL_ESICREMAP0); + struct udevice *dev; + int ret; + + /* Remap DDR PHY during DRAM init. */ + rsip_write_reg(RSIP_CTL_ESICREMAP0, 0xe0000000); + + /* Start DBSC5 */ + ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e9800000", &dev); + if (ret) + printf("DBSC5 init failed: %d\n", ret); + + /* Restore remapping. */ + rsip_write_reg(RSIP_CTL_ESICREMAP0, remaptmp); + + return 0; +} + /** * board_debug_uart_init() - Initialize all HSCIF */ @@ -1407,3 +1445,14 @@ void __weak reset_cpu(void) writel(RST_KCPROT_DIS, RST_RESKCPROT0); writel(0x1, RST_SWSRES1A); } + +/** + * lmb_arch_add_memory() - Add memory to LMB + * + * Add the window to a subset of 32bit DRAM are into LMB, + * to make it possible to TFTP into it. + */ +void lmb_arch_add_memory(void) +{ + lmb_add(0x60000000, 0x40000000); +} diff --git a/configs/r8a78000_ironhide_cm33_defconfig b/configs/r8a78000_ironhide_cm33_defconfig index dda096634b5..7ea3ae993ba 100644 --- a/configs/r8a78000_ironhide_cm33_defconfig +++ b/configs/r8a78000_ironhide_cm33_defconfig @@ -17,9 +17,14 @@ CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET=0xa0000000 CONFIG_ARCH_CPU_INIT=y CONFIG_BAUDRATE=1843200 -CONFIG_BOOTCOMMAND="" +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_BOOTCOMMAND="run rsip_ipl_boot_ca0" CONFIG_BOUNCE_BUFFER=y CONFIG_CMD_IMI=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x80000000 +CONFIG_CMD_PSTORE_RECORD_SIZE=0x400 +CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x8000 CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_UFS=y CONFIG_DM_DMA=y @@ -37,6 +42,7 @@ CONFIG_PHY_R8A78000_MP_PHY=y CONFIG_PHY_TI_DP83869=y CONFIG_POWER_DOMAIN=y CONFIG_RAM=y +CONFIG_RAM_RENESAS_DBSC5=y CONFIG_REMOTEPROC_RENESAS_RSIP=y CONFIG_RENESAS_ETHER_SWITCH=y CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index 5ff2a76fc05..a0c05521c85 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -26,10 +26,50 @@ #if defined(CONFIG_RCAR_64_RSIP) #define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CFG_SYS_TIMER_RATE (133333333 / 4) -#endif +/* Environment setting */ +#define CFG_EXTRA_ENV_SETTINGS \ + "rsip_ipl_params_base=0x8c100000\0" \ + "rsip_ipl_params_optee=0x8c100088\0" \ + "rsip_ipl_params_uboot=0x8c100030\0" \ + "rsip_ipl_optee_ep=0x8c400000\0" \ + "rsip_ipl_tfa_ep=0x8c200000\0" \ + "rsip_ipl_uboot_ep=0x8e300000\0" \ + "rsip_ipl_params_write=" \ + "base ${rsip_ipl_params_base} ; " \ + "mw 0x00 0 0x9e ; " /* Clear the area */ \ + "mw 0x00 0x00300103 ; " /* type, version, size */ \ + "mw 0x20 0x${rsip_ipl_params_uboot} ; " /* U-Boot descriptor */ \ + "" \ + "base ${rsip_ipl_params_uboot} ; " \ + "mw 0x00 0x00580101 ; " /* type, version, size */ \ + "mw 0x04 0x00000001 ; " /* attr */ \ + "mw 0x08 ${rsip_ipl_uboot_ep} ; " /* U-Boot entry point */ \ + "mw 0x10 0x000003c5 ; " /* SPSR */ \ + "" \ + "base ${rsip_ipl_params_optee} ; " \ + "mw 0x00 0x00580201 ; " /* type, version, size */ \ + "mw 0x04 0x00000008 ; " /* attr */ \ + "mw 0x08 ${rsip_ipl_optee_ep} ; " /* OPTEE-OS entry point */ \ + "mw 0x10 0x000003c5 ; " /* SPSR */ \ + "" \ + "base 0\0" \ + "rsip_ipl_boot_ca0=" /* Start TFA BL31, OPTEE-OS, U-Boot on Cortex-A720AE core 0 */ \ + "scsi scan && " /* Scan for UFS devices */ \ + "rproc init && " /* Start remoteproc */ \ + "rproc load 0 0x344c0000 0x60000 && " /* Load SCP from HF */ \ + "rproc start 0 && " /* Start SCP */ \ + "scsi read ${rsip_ipl_uboot_ep} 0x7200 0x100 && " /* Load U-Boot from UFS */ \ + "scsi read ${rsip_ipl_optee_ep} 0x5200 0x200 && " /* Load OPTEE-OS from UFS */ \ + "scsi read ${rsip_ipl_tfa_ep} 0x5000 0x40 && " /* Load TFA BL31 from UFS */ \ + "run rsip_ipl_params_write && " /* Write entry point descriptors */ \ + "rproc load 13 ${rsip_ipl_tfa_ep} 4 && " /* Set up Cortex-A720AE Core 0 */ \ + "rproc start 13\0" /* Start Cortex-A720AE Core 0 */ + +#else /* Environment setting */ #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" +#endif #endif /* __RCAR_GEN5_COMMON_H */ From 79f3e2f8be956575afb339a26325fcd4b15ff1e6 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Thu, 11 Jun 2026 16:08:57 +0200 Subject: [PATCH 51/65] Makefile: let 'make clean' remove files created by DEVICE_TREE_DEBUG Originally, 'make DEVICE_TREE_DEBUG=1' only generated extra output on the console. But since 6cdd7597a2f ("kbuild: Produce diff between base DT and U-Boot augmented DT if DEVICE_TREE_DEBUG=1"), that has also left behind lots of files that clutter the repo and are hard to get rid of manually. Make sure that a 'make clean' will remove those files, and add them to .gitignore. Signed-off-by: Rasmus Villemoes Reviewed-by: Marek Vasut --- .gitignore | 3 +++ Makefile | 1 + 2 files changed, 4 insertions(+) diff --git a/.gitignore b/.gitignore index d57d3be0291..0e09715cc60 100644 --- a/.gitignore +++ b/.gitignore @@ -16,6 +16,9 @@ *.dtb *.dtbo *.dtb.S +*.dtb.clean.dts +*.dtb.diff +*.dtb.full.dts *.elf *.exe *.fit diff --git a/Makefile b/Makefile index 4e5c1dd6a1c..46ecced8daa 100644 --- a/Makefile +++ b/Makefile @@ -2611,6 +2611,7 @@ clean: $(clean-dirs) \( -name '*.[aios]' -o -name '*.ko' -o -name '.*.cmd' \ -o -name '*.ko.*' -o -name '*.su' -o -name '*.pyc' \ -o -name '*.dtb' -o -name '*.dtbo' -o -name '*.dtb.S' -o -name '*.dt.yaml' \ + -o -name '*.dtb.clean.dts' -o -name '*.dtb.full.dts' -o -name '*.dtb.diff' \ -o -name '*.dwo' -o -name '*.lst' \ -o -name '*.su' -o -name '*.mod' -o -name '*.usyms' \ -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ From fae363f2cff9ffc258afee3801184879899c5767 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 3 Jun 2026 08:19:46 +0200 Subject: [PATCH 52/65] configs: phycore_am62x_a53_defconfig: Enable fastboot Enable USB fastboot support for downloading and flashing images via the fastboot protocol. Signed-off-by: Wadim Egorov --- configs/phycore_am62x_a53_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index e990d556531..ddf53b481cd 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -108,6 +108,9 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y @@ -169,7 +172,6 @@ CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_DFU=y # CONFIG_WATCHDOG is not set # CONFIG_WATCHDOG_AUTOSTART is not set From 78d5f8cb50090a2888df284564f43f4ebfbf663c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Jun 2026 14:48:48 +0800 Subject: [PATCH 53/65] usb: tcpm: fix inverted poll condition in tcpm_pd_transmit() The read_poll_timeout() macro breaks out of its loop when the condition evaluates to true. The current code uses "!tx_complete" as the condition, which means it exits immediately when tx_complete is false (i.e., transmission has NOT completed yet), rather than waiting for completion. Fix the condition to "tx_complete" so that the poll loop waits until the TCPC signals transmission success/failure/discard before proceeding. Without this fix, tcpm_pd_transmit() returns before the TCPC has finished transmitting, causing the PD state machine to proceed with stale tx_status values. Fixes: 1db4c0ac77e3 ("usb: tcpm: add core framework") Reviewed-by: Neil Armstrong Signed-off-by: Peng Fan --- drivers/usb/tcpm/tcpm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c index 3061b466d7c..d6c0be82333 100644 --- a/drivers/usb/tcpm/tcpm.c +++ b/drivers/usb/tcpm/tcpm.c @@ -207,7 +207,7 @@ static int tcpm_pd_transmit(struct udevice *dev, */ timeout_us *= 5; ret = read_poll_timeout(tcpm_transmit_helper, tx_complete, - !tx_complete, false, timeout_us, dev); + tx_complete, false, timeout_us, dev); if (ret < 0) { dev_err(dev, "TCPM: PD transmit data failed: %d\n", ret); return ret; From a1d74f409fd56c0c8be091f764f317414df40aaf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 Jun 2026 05:36:05 +0200 Subject: [PATCH 54/65] doc: board: renesas: Document Renesas RZ/N1D and RZ/N1S as arm The RZ/N1D and RZ/N1S contain Cortex-A7 core, which is 32bit ARM core. Document the SoC as 32bit ARM instead of aarch64. Fixes: a5b9f959439b ("doc: renesas: add Renesas board docs") Signed-off-by: Marek Vasut Reviewed-by: Heinrich Schuchardt --- doc/board/renesas/renesas.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst index fedfeed42e3..1c94456eaed 100644 --- a/doc/board/renesas/renesas.rst +++ b/doc/board/renesas/renesas.rst @@ -231,13 +231,13 @@ Renesas is a SoC solutions provider for automotive and industrial applications. * - :doc:`RZ/N1 Family ` - Schneider RZ/N1D board - R9A06G032 (RZ/N1D) - - arm64 + - arm - rzn1_snarc_defconfig * - - Schneider RZ/N1S board - R9A06G033 (RZ/N1S) - - arm64 + - arm - rzn1_snarc_defconfig Build From 3b2190935b397360f3eea1902c796af3f935126a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Jun 2026 23:47:15 +0200 Subject: [PATCH 55/65] doc: board: renesas: Document Renesas Geist board support Document support for Renesas Geist development board based on Renesas R-Car M3Le (R8A779MD) SoC. Fixes: c8523795d796 ("arm64: dts: renesas: r8a779md: Add support for R-Car M3Le R8A779MD Geist") Signed-off-by: Marek Vasut --- doc/board/renesas/renesas.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst index 1c94456eaed..b145c2c6cfd 100644 --- a/doc/board/renesas/renesas.rst +++ b/doc/board/renesas/renesas.rst @@ -120,6 +120,12 @@ Renesas is a SoC solutions provider for automotive and industrial applications. - arm64 - rcar3_ulcb_defconfig + * - + - Geist + - R8A779MD (M3Le) + - arm64 + - r8a779md_geist_defconfig + * - - Eagle - R8A77970 (V3M) From 89b45e46ca20704e3bd9f4bd26f29a21cf8e72ac Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Jun 2026 23:47:16 +0200 Subject: [PATCH 56/65] doc: board: renesas: Document Renesas Gray Hawk board support Document support for Renesas Gray Hawk Single development board based on Renesas R-Car V4M (R8A779H0) SoC. Fixes: 53066deccbed ("ARM: renesas: Add Renesas R8A779H0 V4M Gray Hawk board code") Signed-off-by: Marek Vasut --- doc/board/renesas/renesas.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst index b145c2c6cfd..7673a3e4224 100644 --- a/doc/board/renesas/renesas.rst +++ b/doc/board/renesas/renesas.rst @@ -192,6 +192,12 @@ Renesas is a SoC solutions provider for automotive and industrial applications. - arm64 - r8a779g3_sparrowhawk_defconfig + * - + - Gray Hawk + - R8A779H0 (V4M) + - arm64 + - r8a779h0_grayhawk_defconfig + * - RZ/G2 Family - Beacon EmbeddedWorks RZ/G2M SoM - R8A774A1 (RZ/G2M) From 861be585cc1f922da68d3836a42e23e5ff49c3b6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Jun 2026 23:47:17 +0200 Subject: [PATCH 57/65] doc: board: renesas: Document Renesas Ironhide board support Document support for Renesas Ironhide development board based on Renesas R-Car X5H (R8A78000) SoC. Fixes: cf71963778ee ("arm64: dts: renesas: Add Renesas R-Car X5H R8A78000 Ironhide board code") Fixes: 9d47a5a4d560 ("arm: renesas: Add Renesas R-Car R8A78000 X5H Cortex-M33 RSIP port") Signed-off-by: Marek Vasut --- doc/board/renesas/renesas.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst index 7673a3e4224..fcfd51aa19c 100644 --- a/doc/board/renesas/renesas.rst +++ b/doc/board/renesas/renesas.rst @@ -198,6 +198,18 @@ Renesas is a SoC solutions provider for automotive and industrial applications. - arm64 - r8a779h0_grayhawk_defconfig + * - R-Car Gen5 + - Ironhide (Cortex-A720AE application core) + - R8A78000 (X5H) + - arm64 + - r8a78000_ironhide_defconfig + + * - + - Ironhide (Cortex-M33 RSIP boot core) + - R8A78000 (X5H) + - arm64 + - r8a78000_ironhide_cm33_defconfig + * - RZ/G2 Family - Beacon EmbeddedWorks RZ/G2M SoM - R8A774A1 (RZ/G2M) From 5150a86187657807a3de38c138ca281e6c1a6259 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Stehl=C3=A9?= Date: Mon, 15 Jun 2026 12:56:15 +0200 Subject: [PATCH 58/65] efi_selftest: fix guid comparison MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The `loaded image' efi selftest is comparing protocol GUIDs with the wrong polarity. This can be verified on the sandbox, where two protocols GUIDs are retrieved by the test from the image handle in the following order: 1. Loaded Image Device Path Protocol GUID 2. Loaded Image Protocol GUID The test matches on the first GUID, while it is in fact looking for the second one; fix the comparison polarity. Fixes: efe79a7c0de0 ("efi_selftest: test for loaded image protocol") Signed-off-by: Vincent Stehlé Cc: Heinrich Schuchardt Cc: Ilias Apalodimas Cc: Tom Rini Cc: Alexander Graf Reviewed-by: Heinrich Schuchardt --- lib/efi_selftest/efi_selftest_loaded_image.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/efi_selftest/efi_selftest_loaded_image.c b/lib/efi_selftest/efi_selftest_loaded_image.c index 5889ab12617..e0668f60ebd 100644 --- a/lib/efi_selftest/efi_selftest_loaded_image.c +++ b/lib/efi_selftest/efi_selftest_loaded_image.c @@ -60,8 +60,8 @@ static int execute(void) efi_st_printf("%u protocols installed on image handle\n", (unsigned int)protocol_buffer_count); for (i = 0; i < protocol_buffer_count; ++i) { - if (memcmp(protocol_buffer[i], &loaded_image_protocol_guid, - sizeof(efi_guid_t))) + if (!memcmp(protocol_buffer[i], &loaded_image_protocol_guid, + sizeof(efi_guid_t))) found = true; } if (!found) { From eb6f420836bb30e8c54c140f1bea3e2c88f5b201 Mon Sep 17 00:00:00 2001 From: Denis Mukhin Date: Sat, 20 Jun 2026 22:14:43 -0700 Subject: [PATCH 59/65] bootdev: fix typos Signed-off-by: Denis Mukhin Reviewed-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- include/bootdev.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/bootdev.h b/include/bootdev.h index 12c90c4ec1b..14f8a98633b 100644 --- a/include/bootdev.h +++ b/include/bootdev.h @@ -30,10 +30,10 @@ struct udevice; * generally very quick to access, e.g. less than 100ms * @BOOTDEVP_3_INTERNAL_SLOW: Internal devices which don't need scanning but * take a significant fraction of a second to access - * @BOOTDEVP_4_SCAN_FAST: Extenal devices which need scanning or bus + * @BOOTDEVP_4_SCAN_FAST: External devices which need scanning or bus * enumeration to find, but this enumeration happens quickly, typically under * 100ms - * @BOOTDEVP_5_SCAN_SLOW: Extenal devices which need scanning or bus + * @BOOTDEVP_5_SCAN_SLOW: External devices which need scanning or bus * enumeration to find. The enumeration takes significant fraction of a second * to complete * @BOOTDEVP_6_NET_BASE: Basic network devices which are quickly and easily @@ -327,7 +327,7 @@ int bootdev_hunt_and_find_by_label(const char *label, struct udevice **devp, * Bootdev scanners are used as needed. For example a label "mmc1" results in * running the "mmc" bootdrv. * - * @iter: Interation info, containing iter->cur_label + * @iter: Iteration info, containing iter->cur_label * @devp: New bootdev found, if any was found * @method_flagsp: If non-NULL, returns any flags implied by the label * (enum bootflow_meth_flags_t), 0 if none @@ -342,7 +342,7 @@ int bootdev_next_label(struct bootflow_iter *iter, struct udevice **devp, * This moves @devp to the next bootdev with the current priority. If there is * none, then it moves to the next priority and scans for new bootdevs there. * - * @iter: Interation info, containing iter->cur_prio + * @iter: Iteration info, containing iter->cur_prio * @devp: On entry this is the previous bootdev that was considered. On exit * this is the new bootdev, if any was found * Returns 0 on success (*devp is updated), -ENODEV if there are no more From 1f5c8eac2f299bd3a2fc748b068acbb4b90d592d Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 19 Jun 2026 11:38:29 +0300 Subject: [PATCH 60/65] efi_loader: fix memory leak in efi_var_collect Barebox has now ported some of the UEFI code. In the process they found some bugs. In this case when the variable buffer is too small, efi_var_collect() returns EFI_BUFFER_TOO_SMALL but doesn't free the allocated 'buf'. Fixes: 5f7dcf079de8c ("efi_loader: UEFI variable persistence") Signed-off-by: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt --- lib/efi_loader/efi_var_common.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c index d63c2d1b1cd..e51b21fe0b0 100644 --- a/lib/efi_loader/efi_var_common.c +++ b/lib/efi_loader/efi_var_common.c @@ -446,8 +446,10 @@ efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t * efi_status_t ret; if ((uintptr_t)buf + len <= - (uintptr_t)var->name + old_var_name_length) + (uintptr_t)var->name + old_var_name_length) { + free(buf); return EFI_BUFFER_TOO_SMALL; + } var_name_length = (uintptr_t)buf + len - (uintptr_t)var->name; memcpy(var->name, old_var->name, old_var_name_length); From 41c6b83c777788692640fa0f85a2381d8959f301 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Stehl=C3=A9?= Date: Tue, 9 Jun 2026 10:07:04 +0200 Subject: [PATCH 61/65] lib/efi_loader: fix block io revision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Revision field of the EFI_BLOCK_IO_PROTOCOL structure must be set to one of the two valid values [1], but this is not initialized in the efi_loader; fix it. Link: https://uefi.org/specs/UEFI/2.11/13_Protocols_Media_Access.html#efi-block-io-protocol [1] Signed-off-by: Vincent Stehlé Cc: Heinrich Schuchardt Cc: Ilias Apalodimas Cc: Tom Rini Reviewed-by: Heinrich Schuchardt --- lib/efi_loader/efi_disk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index f8a57539ec6..4a3ace3a304 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -305,6 +305,7 @@ static efi_status_t EFIAPI efi_disk_flush_blocks(struct efi_block_io *this) } static const struct efi_block_io block_io_disk_template = { + .revision = EFI_BLOCK_IO_PROTOCOL_REVISION3, .reset = &efi_disk_reset, .read_blocks = &efi_disk_read_blocks, .write_blocks = &efi_disk_write_blocks, From 60ff3d950996c2ea0bb744fd9c922a96abc65774 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Stehl=C3=A9?= Date: Thu, 11 Jun 2026 08:59:50 +0200 Subject: [PATCH 62/65] efi_selftest: fix use-after-free MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the `memory' efi selftest verifies the Devicetree memory reservation, it accesses the memory_map buffer after it has been freed with free_pool(). Move the verification earlier to fix this. Fixes: 34c96659ed57 ("efi_selftest: check fdt is marked as runtime data") Signed-off-by: Vincent Stehlé Cc: Heinrich Schuchardt Cc: Ilias Apalodimas Cc: Tom Rini Reviewed-by: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt --- lib/efi_selftest/efi_selftest_memory.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/lib/efi_selftest/efi_selftest_memory.c b/lib/efi_selftest/efi_selftest_memory.c index 7320964c129..450470ceedd 100644 --- a/lib/efi_selftest/efi_selftest_memory.c +++ b/lib/efi_selftest/efi_selftest_memory.c @@ -155,6 +155,15 @@ static int execute(void) EFI_RUNTIME_SERVICES_DATA) != EFI_ST_SUCCESS) return EFI_ST_FAILURE; + /* Check memory reservation for the device tree */ + if (fdt_addr && + find_in_memory_map(map_size, memory_map, desc_size, fdt_addr, + EFI_ACPI_RECLAIM_MEMORY) != EFI_ST_SUCCESS) { + efi_st_error + ("Device tree not marked as ACPI reclaim memory\n"); + return EFI_ST_FAILURE; + } + /* Free memory */ ret = boottime->free_pages(p1, EFI_ST_NUM_PAGES); if (ret != EFI_SUCCESS) { @@ -172,14 +181,6 @@ static int execute(void) return EFI_ST_FAILURE; } - /* Check memory reservation for the device tree */ - if (fdt_addr && - find_in_memory_map(map_size, memory_map, desc_size, fdt_addr, - EFI_ACPI_RECLAIM_MEMORY) != EFI_ST_SUCCESS) { - efi_st_error - ("Device tree not marked as ACPI reclaim memory\n"); - return EFI_ST_FAILURE; - } return EFI_ST_SUCCESS; } From ad90d1ec8b43aa3d7ec5790db5c5740472e47c96 Mon Sep 17 00:00:00 2001 From: Mattijs Korpershoek Date: Mon, 15 Jun 2026 14:29:28 +0200 Subject: [PATCH 63/65] doc: android: fastboot: Document halt behaviour It's possible to interrupt the fastboot command from the U-Boot shell using the Ctrl-c keybinding. Document this. Signed-off-by: Mattijs Korpershoek Reviewed-by: Sam Day --- doc/android/fastboot.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst index 19e2ee9d407..818b8815ebd 100644 --- a/doc/android/fastboot.rst +++ b/doc/android/fastboot.rst @@ -212,6 +212,11 @@ or initiate a reboot:: and once the client comes back, the board should reset. +It's possible to interrupt the fastboot command using Ctrl-c:: + + => fastboot usb 0 + Operation aborted. + You can also specify a kernel image to boot. You have to either specify the an image in Android format *or* pass a binary kernel and let the fastboot client wrap the Android suite around it. On OMAP for instance you From 661413904212a8ac96f13278a627ab3a38e54780 Mon Sep 17 00:00:00 2001 From: Francois Berder Date: Thu, 21 May 2026 19:52:39 +0200 Subject: [PATCH 64/65] serial: sh: Fix dev_read_addr error check dev_read_addr returns FDT_ADDR_T_NONE (-1) in case of error and not 0. Signed-off-by: Francois Berder Reviewed-by: Simon Glass Reviewed-by: Marek Vasut Tested-by: Marek Vasut # R-Car H3/M3-W/M3-N Salvator-X(S), H3/M3-W ULCB, V4H Sparrow Hawk, X5H Ironhide RSIP and CA720AE Signed-off-by: Marek Vasut # Update subject tags --- drivers/serial/serial_sh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index bc205234e24..7debff6cb3a 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -257,7 +257,7 @@ static int sh_serial_of_to_plat(struct udevice *dev) int ret; addr = dev_read_addr(dev); - if (!addr) + if (addr == FDT_ADDR_T_NONE) return -EINVAL; plat->base = addr; From f072620dc9ffda00b010783da27c41231c3a439b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 22 Jun 2026 16:22:08 -0600 Subject: [PATCH 65/65] Prepare v2026.07-rc5 Signed-off-by: Tom Rini --- Makefile | 2 +- doc/develop/release_cycle.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 46ecced8daa..503ac59e654 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2026 PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION* diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 1e3e179d77f..2f024905157 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -79,7 +79,7 @@ For the next scheduled release, release candidates were made on: * U-Boot |next_ver|-rc4 was released on Mon 08 June 2026. -.. * U-Boot |next_ver|-rc5 was released on Mon 22 June 2026. +* U-Boot |next_ver|-rc5 was released on Mon 22 June 2026. Please note that the following dates are planned only and may be deviated from as needed.