Pull request net-20260312.
net:
- Move network PHY under NETDEVICES
- s/DM_CLK/CLK/ in HIFEMAC_{ETH,MDIO}
- Add support for Airoha AN8811HB PHY
- airoha: PCS and MDIO support for Airoha AN7581 SoC
net-lwip:
- Fix issue when TFTP blocksize is >8192
- Adjust PBUF_POOL_SIZE/IP_REASS_MAX_PBUFS for better performance and
resource usage.
- Enable mii command for NET_LWIP
A number of network PHY drivers have Kconfig dependencies on various
network drivers under NETDEVICES. This is in addition to logical
dependencies of network PHYs needing network drivers. Resolve the
Kconfig problems by moving the network PHY lines to be after the network
devices, within the overall NETDEVICES guard.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>
TFTP transfers fail when tftpblocksize is set to 8192 or larger due to
insufficient buffer resources for IP fragment reassembly.
Calculate PBUF_POOL_SIZE and IP_REASS_MAX_PBUFS dynamically based on
CONFIG_TFTP_BLOCKSIZE using IP fragmentation boundaries (1480 usable
bytes per fragment at 1500 MTU). The pool size includes headroom for
TX, ARP, and protocol overhead, while ensuring PBUF_POOL_SIZE remains
greater than IP_REASS_MAX_PBUFS as required by lwIP.
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
The PBUF_POOL_BUFSIZE ends up being only 592 bytes, instead of 1514,
when PROT_TCP_LWIP Kconfig option is disabled. This results in a full
Ethernet frame requiring three PBUFs instead of just one.
This happens because the PBUF_POOL_BUFSIZE constant depends on the value
of a TCP_MSS constant, something that defaults to 536 when PROT_TCP_LWIP
is disabled.
PBUF_POOL_BUFSIZE = LWIP_MEM_ALIGN_SIZE(TCP_MSS + 40 + PBUF_LINK_HLEN)
Ensure that a full Ethernet frame fits inside a single PBUF by moving
the define of TCP_MSS outside the PROT_TCP_LWIP ifdef block.
Fixes: 1c41a7afaa ("net: lwip: build lwIP")
Acked-by: Jerome Forissier <jerome.forissier@arm.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
For enabling the clock driver we use symbol CONFIG_CLK.
Select this symbol for the HiSilicon Fast Ethernet Controller driver.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Don't imply non-existent symbols CONFIG_SIFIVE_CLINT and SPL_SIFIVE_CLINT.
MPFS boards neither use SPL nor do they run main U-Boot in M-mode.
So we don't need CONFIG_(SPL_)ACLINT either.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Under single core boot platform, the secondary cores won't enter the
u-boot spl. Therefore we move the pl2 driver from u-boot to the Opensbi.
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Jimmy Ho <jimmy.ho@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Tested on HiFive Unleashed and HiFive Unmatched, both SPIFlash and MMC boot.
Signed-off-by: Andreas Schwab <schwab@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
If we are using the legacy or the LWIP network stack,
should not influence our decision to provide command `mii`.
Let BOOT_DEFAULTS_CMDS imply MII if either of the network
stacks is available.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Current code just bind mt7531 mdio with it's driver, so mdio device may
not be probed and hense not usable.
This patch:
* Forces probing of mt7531 mdio for GDM1 port
* Renames the mt7531 mdio bus interface to 'mt7531-mdio'. We may have
multiple available MDIO, so the name 'mdio' isn't descriptive enough.
* Sets mdio bus for the GDM port device
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
It's not possible to disable PCS support just now, an7581 u-boot will not
compile. This patch fixes an issue.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Add required changes to call PCS function to configure the Serdes Port.
The Ethernet driver is adapted following Upstream Kernel node structure.
Function calling order is the same of Phylink upstream kernel.
With the PCS support, also add support for attaching PHY. With
"in-band-status" set in DT for the managed property, a rudimental
support for SFP module is present.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
A fix:
* Fixing compiling MT8195 due to some independent changes that were applied
around the same time as MT8195 support was merged. (CI would not have caught
this since we didn't have a defconfig until now).
And few small features:
* New defconfig for MT8395/Genio 1200 EVK.
* pinctrl support for MT8189-compatible SoCs.
pcs-airoha-common.o should not build unconditionally,
also make building rules looks better.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Add support for Airoha PCS driver present on AN7581 SoC.
This is needed to configure the Serdes port for the different PHY mode.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Call airoha_switch_init() before creating GDM instances, so if
allocation of GDM port fails, early created GDM instances will work
normally.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
We should not call airoha_fe_init() from GDM port independent code,
because it do a GDM specific things.
Makes airoha_fe_maccr_init() and airoha_fe_init() port dependent
and call them from airoha_eth_port_probe()
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Declare airoha_eth_port as U_BOOT_DRIVER(), fix airoha_alloc_gdm_port()
to lookup a driver instead of direct airoha_eth_port usage.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
In the case of an7581 possible GDM port id are: 1, 2 and 4.
Initialization of port GDM4 will lead to out of boundary writing
to gdm_port_str[] array.
Let's increase the array size by 1 to avoid it.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Rework the driver to support multiple GDM port. The driver is split to
main driver as a MISC driver with forced probe (by using the
DM_FLAG_PROBE_AFTER_BIND) and each GDM port register a ETH driver.
This permit a 1:1 implementation with the linux kernel driver and permit
to use the same exact DT nodes.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Instead of having duplicate priv struct for mdio-mt7531-mmio driver in
both driver and header, use the one exposed by the header directly.
This make sure we have consistent priv struct if the driver will be
updated in the future.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add minimal infrastructure to build SPL images with support for UFS
storage devices. This also pulls in SCSI support and charset functions,
which are dependencies of the UFS code.
With this, only a fixed offset is supported for loading the next image,
which should be specified in CONFIG_SPL_UFS_RAW_U_BOOT_SECTOR as the
number of 4096-byte sectors into the UFS block device.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://patch.msgid.link/20260120-rk3576-ufs-v5-1-0edb61b301b7@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Enable firmware TPM (fTPM) support via OP-TEE for K3 platforms with
MMC hardware. This provides TPM 2.0 functionality through
Microsoft's fTPM Trusted Application running in OP-TEE secure world,
using eMMC RPMB as persistent storage.
fTPM support in U-Boot provides the foundation for measured boot
and disk encryption use cases.
The ARM64 condition ensures these apply only to A53/A72 cores and the
MMC condition ensures fTPM is enabled only on platforms with eMMC
hardware support.
Signed-off-by: Shiva Tripathi <s-tripathi1@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
* The symbol for the x86 architecture is CONFIG_X86 and not CONFIG_x86.
* Correct the description. The partition type is called MBR.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
We removed configuration symbol CONFIG_DM_PCI with
commit 3232bdf0b3 ("pci: Drop DM_PCI").
Don't select it for TARGET_POMELO.
Fixes: b9d0f00a9d ("arm: add initial support for the Phytium Pomelo Board")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> says:
The disk_read() and disk_write() functions of the FAT driver use the
blk_dread() and blk_dwrite() respectively. The blk_* APIs read and write
to the devices in terms of the device block size. However, the FAT
driver reads in terms of the device block size (from fat_set_blk_dev and
read_bootsectandvi) and sector size in the rest of the places.
This causes buffer overflows or partial reads when the FAT sector size
is not equal to device block size. Fix this by using blk_dread in
fat_set_blk_dev and read_bootsectandvi instead of disk_read. And update
disk_read/disk_write to handle FAT sector size and block size mismatch.
Tested on
blksz | FAT sector size
------+----------------
4096 | 4096
512 | 512
4096 | 512
512 | 4096
CI test results
---------------
https://github.com/u-boot/u-boot/pull/871
All checks have passed
93 successful checks
No conflicts with base branch
Code size change info
---------------------
arm: (for 1/1 boards) all +32.0 text +32.0
qemu_arm : all +32 text +32
u-boot: add: 0/0, grow: 2/0 bytes: 24/0 (24)
function old new delta
read_bootsectandvi 420 432 +12
fat_set_blk_dev 204 216 +12
aarch64: (for 1/1 boards) all +12.0 rodata -8.0 text +20.0
qemu_arm64 : all +12 rodata -8 text +20
u-boot: add: 0/0, grow: 2/0 bytes: 20/0 (20)
function old new delta
read_bootsectandvi 408 420 +12
fat_set_blk_dev 204 212 +8
aarch64: (for 1/1 boards) all -2.0 data -8.0 rodata +6.0
qcom_qcs9100 : all -2 data -8 rodata +6
u-boot: add: 1/-1, grow: 8/-1 bytes: 708/-224 (484)
function old new delta
disk_rw - 628 +628
read_bootsectandvi 408 428 +20
fat_itr_root 500 520 +20
get_cluster 376 388 +12
set_contents 2076 2084 +8
fat_set_blk_dev 204 212 +8
static.set_fatent_value 536 540 +4
get_fatent 420 424 +4
fat_next_cluster 368 372 +4
disk_read 100 - -100
disk_write 132 8 -124
Link: https://lore.kernel.org/r/20260224035000.1617869-1-varadarajan.narayanan@oss.qualcomm.com
Enable FS_FAT_HANDLE_SECTOR_SIZE_MISMATCH to handle the different
combination of FAT sector size and device block size present in QCOM
platforms.
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
The disk_read() and disk_write() functions of the FAT driver use the
blk_dread() and blk_dwrite() respectively. The blk_* APIs read and write
to the devices in terms of the device block size. However, the FAT
driver reads in terms of the device block size (from fat_set_blk_dev and
read_bootsectandvi) and sector size in the rest of the places.
This causes buffer overflows or partial reads when the FAT sector size
is not equal to device block size. Fix this by using blk_dread in
fat_set_blk_dev and read_bootsectandvi instead of disk_read. And update
disk_read/disk_write to handle FAT sector size and block size mismatch.
Tested on
blksz | FAT sector size
------+----------------
4096 | 4096
512 | 512
4096 | 512
512 | 4096
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Booting into SPL using ramboot can take several seconds on some SoCs due
to the large size of the usb472 payload sent over USB to BootROM.
A large chunk of the usb472 payload, around 1-2 MiB, is padding used to
avoid overlapping when loading e.g. TF-A to 0x40000.
BootROM is likely wasting unnecessary time crc16 validating the padding
of the payload.
Place the FIT payload directly after SPL and memmove it to the expected
memory location, SPL_LOAD_FIT_ADDRESS, to avoid excessive padding and
help speed up ramboot.
Binman symbols are used to get the position and size of the FIT payload
that is initially loaded into DRAM by the BootROM.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The ATAGS set by Rockchip DDR init blob[1] specify DRAM banks above the
first addressable 4GiB which we haven't done in the mem_map for RK3588
yet.
For 4GiB DRAM, the 256MiB missing from the first addressable 4GiB (due
to MMIO) are accessible at the end of the 8GiB address space. For 8GiB,
4-8GiB address space is used for the additional 4GiB and the missing
256MiB are at the end of 12GiB address space. For 12, 4-12GiB and the
missing 256MiB at the end of 20GiB address space. For 16GiB, 4-~16GiB
with two holes (reasons unknown) around 16GiB and the missing 256MiB is
at the end of 20GiB address space. For 32GiB, 4-16~GiB with two holes
and then 16GiB to 32GiB address space (so likely missing 256MiB from
MMIO address space).
[1] https://gist.github.com/Kwiboo/1c020d37e3adbc9d0d79dc003d921977
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
