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rockchip: rk3588: include all addressable DRAM in memory map

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The ATAGS set by Rockchip DDR init blob[1] specify DRAM banks above the
first addressable 4GiB which we haven't done in the mem_map for RK3588
yet.

For 4GiB DRAM, the 256MiB missing from the first addressable 4GiB (due
to MMIO) are accessible at the end of the 8GiB address space. For 8GiB,
4-8GiB address space is used for the additional 4GiB and the missing
256MiB are at the end of 12GiB address space. For 12, 4-12GiB and the
missing 256MiB at the end of 20GiB address space. For 16GiB, 4-~16GiB
with two holes (reasons unknown) around 16GiB and the missing 256MiB is
at the end of 20GiB address space. For 32GiB, 4-16~GiB with two holes
and then 16GiB to 32GiB address space (so likely missing 256MiB from
MMIO address space).

[1] https://gist.github.com/Kwiboo/1c020d37e3adbc9d0d79dc003d921977

Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Quentin Schulz
2026-03-10 10:07:03 -06:00
committed by Tom Rini
parent 52877548d3
commit b107cfbb79
1 changed files with 18 additions and 0 deletions
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arch/arm/mach-rockchip/rk3588/rk3588.c
+18
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@@ -88,6 +88,24 @@ static struct mm_region rk3588_mem_map[] = {
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x100000000UL,
.phys = 0x100000000UL,
.size = 0x2fc000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x3fc500000UL,
.phys = 0x3fc500000UL,
.size = 0x3a00000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x400000000UL,
.phys = 0x400000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x900000000,
.phys = 0x900000000,
.size = 0x150000000,