The pinecube has an ethernet connector which uses the EMAC and internal
PHY of the chip. Enable it in the config.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Variables holding addresses are typically using the "long" C type in
U-Boot, to be easily compatible with both 32-bit and 64-bit builds.
The A133 DRAM driver is typically compiled for AArch64, so u64 is the
same type as unsigned long, but that breaks when compiling the DRAM
driver in AArch32 (for some experiments).
Fix the type to make the code more portable.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The first of the two Ethernet controllers in the Allwinner A527/T527 is
compatible to the MAC from the previous SoCs. Consequently the recent DT
update brought use the MAC node, using the A64 compatible string as the
fallback, which works out of the box.
Enable the sun8i-emac Ethernet driver in the defconfig for the Radxa and
the Avaota boards, so that kernels and other data can be loaded via
TFTP. Please note that only one of the Ethernet sockets will work, the
second MAC is not compatible, and needs a new U-Boot driver. The
X96QPro+ TV box unfortunately uses only this second EMAC, so Ethernet
cannot be used there at the moment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The name of the pin function was changed last minute in the DT, from
emac0 to gmac0.
Adjust the name we use in the pinctrl driver accordingly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The V3s (using co-packaged DRAM) runs at 360 MHz, which is specified in
the common platform Kconfig file. However the value for MACH_SUN8I will
be picked up instead due to ordering.
Re-order the defaults to have MACH_SUN8I_V3S before MACH_SUN8I and let
it select the correct default. Also update the LicheePi Zero Dock
defconfig to remove the value, which is now correctly selected.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
There is nothing special for u-boot in the V3/V3s device-tree files,
they are just copies of the upstream ones.
Remove the copies and switch to OF_UPSTREAM for supported boards.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
In order to set the BOOTFILE symbol we first need to have USE_BOOTFILE
be set, or some of the logic might not work as expected later on when
building. Second, defaults like this belong with the symbol itself.
Fixes: da595d236b ("include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile")
Signed-off-by: Tom Rini <trini@konsulko.com>
This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.
Highlights:
- Agilex7 M-series bring-up:
- Basic DT support and board initialization for Agilex7 M-series SoC and
SoCDK.
- New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
- Clock driver support for Agilex7 M-series.
- New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
- Improved SPL support: ASYNC interrupt enabling, system manager init
refactor, and cold scratch register usage.
- Updated firewall probing and watchdog support in SPL.
- Cleaned up DDR code, added secure region support for ATF, and improved warm
reset handling.
- Device Tree and config updates:
- Migration to upstream Linux DT layout for Agilex platforms.
- Consolidated socfpga_agilex_defconfig and removed deprecated configs.
- Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
- dwc_eth_xgmac and clk-agilex cleanup and improvements.
- Several coverity and style fixes.
Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody. This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.
Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318
Pull request efi-2025-10-rc2
Documentation:
* Describe running U-Boot as a pflash image on RISC-V QEMU
* Correct the description of the bootph-verify device-tree property
UEFI:
* In mkeficapsule fix a resource leak in read_bin_file()
* Support loading a Linux initial RAM disk with the bootefi command.
use the new email address for community work.
While at it, cleanup git shortlog output, by adding
fixes in .mailmap
Signed-off-by: Heiko Schocher <hs@nabladev.com>
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27314
- Several Smatch reported fixes.
- Enable the temperature command on imx8ulp-evk.
- Fix mx8mm_fracpll_tbl.
- Make optee packaging optional for imx8m.
- Reuse and export low_drive_freq_update() on imx9.
- Enable USB OTG ID pin pull up in SPL on dh-imx6.
This is for new platform enablement for Agilex7 M-series.
Add DDR driver for Agilex7 M-series. This driver is designed to support
DDR and HBM memory. The official HBM handoff is not ready yet, therefore
hardcoded handoff is used for HBM driver validation on mUDV board.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Add uibssm mailbox driver for Agilex7 M-series. HPS will interact with UIB
and HBM subsystem through software defined mailbox interface.
HPS can retrieve HBM memory interface calibration status, UIB
configuration, memory interfae configuration, trigger calibration and etc
with the list of supported mailbox command type and opcode.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file
using bootm command.
Change to use CONFIG_SPL_ATF to differentiate the bootfile of default
environment variable. We shouldn't use CONFIG_FIT because it is enabled
by default for U-Boot Proper.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Agilex7 M-series support has been added using upstream Linux DTS.
socfpga_agilex_socdk-u-boot.dtsi was updated to support both Agilex and
Agilex7 M-series platforms.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Migrate the legacy Agilex platform to use the upstream Linux device tree
configuration. This helps reduce maintenance overhead and aligns U-Boot
with the Linux kernel's DTS hierarchy and naming conventions.
This change improves consistency between U-Boot and Linux by removing
custom/legacy DTS handling and instead relying on the standardized
definitions provided by the upstream Linux DTS.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reorganize misplaced properties by moving board-common settings from
socfpga_agilex_socdk-u-boot.dtsi to socfpga_agilex-u-boot.dtsi to maintain
proper separation between common and board-level configurations.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
SPL checks for a magic word in the system manager's scratch
register to determine if an L2 reset has occurred. If detected,
SPL places all slave CPUs (CPU1–3) into WFI mode. The master
CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3
system register and also enters WFI mode.
This warm reset flow is handled entirely within the HPS. The
function `socfpga_sysreset_request()` triggers the warm
reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S`
handles the necessary initialization.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Agilex retrieves its clock manager address via probing its own clock
driver model during the SPL initialization.
Therefore, excluding Agilex from calling its clock driver in misc
driver to retrieve the clock manager address.
Once all SoC64 devices has been successfully transition to clock
driver model method, this implementation will be cleaned up.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
The DDR data rate must be set correctly in the DDRIOCTRL
register according to the Actual Clock Frequency (ACF) value.
By enabling the reading of ACF value from bit 18 of the boot
scratch register during initialization, the DDR data rate is
able to be configured accurately.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
The boot scratch cold reg 8 is shared between DBE, DDR init progress
update and Linux EDAC. This patch defines how the bits are used by
respective features above and their macro names used in U-Boot.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Setting up firewall regions based on SDRAM memory banks configuration
(up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space.
First 1 MiB (0 to 0xfffff) of SDRAM is configured as secure region,
other address spaces are non-secure regions. The ARM Trusted Firmware (ATF)
image is located in this first 1 MiB memory region. So, this can prevent
software executing at non-secure state EL0-EL2 and non-secure masters
access to secure region.
Add common function for firewall setup and reuse for all SoC64 devices.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
The base address of system manager can be retrieved
using DT framework through the system manager driver.
Enable system manager support for Agilex by probing the
system manager driver to initialize during SPL boot up.
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Refactor system manager initialization by searching for system manager
alias in Agilex5 device tree instead of manually passing node name to
the device model calling function
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Replace cm_wait_for_fsm() function with wait_for_bit_le32() function
which supports accurate timeout.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Asynchronous aborts were previously masked at SPL
entry.
To ensure early detection of system errors
such as ECC faults or bus errors, asynchronous aborts
should be explicitly unmasked by clearing the A-bit in
the DAIF register during Agilex SPL initialization.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
# Conflicts:
# arch/arm/mach-socfpga/spl_agilex.c
Enable backup for data section to support warm reset in Agilex SPL as
no SPL image would be reloaded in warm reset.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
For phyCORE-i.MX93 SoMs with i.MX93 parts running in VOLT_LOW_DRIVE mode
(SoCs with speed grade fuse set to 900 MHz) reduce usdhc clocks from 400
MHz to 266 MHz. Do this in board code since global imx9 board_fix_fdt()
is not used in case of phycore-imx93 board since commit d3b9b79968
("board: phytec: imx93: Add eeprom-based hardware introspection").
While at it, add a note to ft_board_setup() function to inform that
fixup for Linux device-tree is taken care by ft_system_setup() in imx9
global arch/arm/mach-imx/imx9/soc.c implementation.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Reuse and export low_drive_freq_update() function. This way global imx9
board_fix_fdt() doesn't duplicate code. While low_drive_freq_update()
can be reused on boards such as phyCORE-i.MX93 (TARGET_PHYCORE_IMX93)
which is not using the global imx9 board_fix_fdt() implementation.
While at it, make printout logic less verbose by only outputting on the
error condition and not on each successful clock fixup. Also drop now
invalid comment (low_drive_freq_update() now does fixup for internal and
kernel device-tree).
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
Update Agilex SPL code to implement device tree model
for firewall registers setup by using DTreg driver to
probe from device tree for the firewall settings instead
of calling firewall driver function.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Combine all MMC, NAND and QSPI configs into single defconfig which is named
as "socfpga_agilex_defconfig". This will be the default defconfig to use.
It supports booting from all three flashes using ARM Trusted Firmware (ATF)
as the secure runtime monitor.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Update the ARMv8 generic timer frequency register (cntfrq_el0)
with the actual hardware timer frequency (COUNTER_FREQUENCY_REAL).
The generic timer frequency was set to 0x200000000 during boot clk
which needs to be set to 0x400000000 when transition from boot clk
to PLL clk.
This will ensure that subsequent timer operations are based on the
correct frequency, ensuring accurate timekeeping.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
In dwxgmac_of_get_mac_mode there is a test for mac_mode which will
return if false. After this point mac_mode is guaranteed to be true so
there is no need to test for this. Remove that test.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
