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Merge tag 'u-boot-imx-master-20250808' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27314

- Several Smatch reported fixes.
- Enable the temperature command on imx8ulp-evk.
- Fix mx8mm_fracpll_tbl.
- Make optee packaging optional for imx8m.
- Reuse and export low_drive_freq_update() on imx9.
- Enable USB OTG ID pin pull up in SPL on dh-imx6.
This commit is contained in:
Tom Rini
2025-08-08 08:33:19 -06:00
parent 123cd77122 b6e2cfca1a
commit 7ef148daa4
14 changed files with 39 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/dts/imx8mm-u-boot.dtsi
+1 -6
View File
@@ -164,7 +164,6 @@
};
#endif
#ifdef CONFIG_OPTEE
tee: tee {
description = "OP-TEE";
type = "tee";
@@ -176,9 +175,9 @@
tee-os {
filename = "tee.bin";
optional;
};
};
#endif
binman_fip: fip {
arch = "arm64";
@@ -208,11 +207,7 @@
fdt = "fdt-SEQ";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
#ifdef CONFIG_OPTEE
loadables = "atf", "tee";
#else
loadables = "atf";
#endif
#endif
};
};
arch/arm/dts/imx8mn-u-boot.dtsi
+1 -6
View File
@@ -240,7 +240,6 @@
};
#endif
#ifdef CONFIG_OPTEE
tee: tee {
description = "OP-TEE";
type = "tee";
@@ -252,9 +251,9 @@
tee-os {
filename = "tee.bin";
optional;
};
};
#endif
binman_fip: fip {
arch = "arm64";
@@ -284,11 +283,7 @@
fdt = "fdt-SEQ";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
#ifdef CONFIG_OPTEE
loadables = "atf", "tee";
#else
loadables = "atf";
#endif
#endif
};
};
arch/arm/dts/imx8mp-u-boot.dtsi
+1 -6
View File
@@ -185,7 +185,6 @@
};
#endif
#ifdef CONFIG_OPTEE
tee: tee {
description = "OP-TEE";
type = "tee";
@@ -197,9 +196,9 @@
tee-os {
filename = "tee.bin";
optional;
};
};
#endif
@fdt-SEQ {
description = "NAME";
@@ -220,11 +219,7 @@
fdt = "fdt-SEQ";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
#ifdef CONFIG_OPTEE
loadables = "atf", "tee";
#else
loadables = "atf";
#endif
#endif
};
};
arch/arm/dts/imx8mq-u-boot.dtsi
+1 -6
View File
@@ -144,7 +144,6 @@
};
#endif
#ifdef CONFIG_OPTEE
tee: tee {
description = "OP-TEE";
type = "tee";
@@ -156,9 +155,9 @@
tee-os {
filename = "tee.bin";
optional;
};
};
#endif
fdt {
compression = "none";
@@ -180,11 +179,7 @@
fdt = "fdt";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
#ifdef CONFIG_OPTEE
loadables = "atf", "tee";
#else
loadables = "atf";
#endif
#endif
};
};
arch/arm/include/asm/arch-imx9/sys_proto.h
+1
View File
@@ -18,6 +18,7 @@ enum imx9_soc_voltage_mode {
void soc_power_init(void);
bool m33_is_rom_kicked(void);
int m33_prepare(void);
int low_drive_freq_update(void *blob);
enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
arch/arm/mach-imx/imx8m/clock_imx8mm.c
+6 -6
View File
@@ -55,16 +55,16 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
PLL_1443X_RATE(900000000U, 300, 8, 0, 0),
PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(900000000U, 300, 2, 2, 0),
PLL_1443X_RATE(800000000U, 200, 3, 1, 0),
PLL_1443X_RATE(750000000U, 250, 2, 2, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
PLL_1443X_RATE(266000000U, 400, 9, 2, 0),
PLL_1443X_RATE(400000000U, 400, 3, 3, 0),
PLL_1443X_RATE(266000000U, 266, 3, 3, 0),
PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
PLL_1443X_RATE(100000000U, 200, 3, 4, 0),
};
static int fracpll_configure(enum pll_clocks pll, u32 freq)
arch/arm/mach-imx/imx9/soc.c
+6 -23
View File
@@ -641,12 +641,10 @@ static int low_drive_fdt_fix_clock(void *fdt, int node_off, u32 clk_index, u32 n
return -ENOENT;
}
static int low_drive_freq_update(void *blob)
int low_drive_freq_update(void *blob)
{
int nodeoff, ret;
int i;
int nodeoff, ret, i;
/* Update kernel dtb clocks for low drive mode */
struct low_drive_freq_entry table[] = {
{"/soc@0/bus@42800000/mmc@42850000", 0, 266666667},
{"/soc@0/bus@42800000/mmc@42860000", 0, 266666667},
@@ -658,8 +656,8 @@ static int low_drive_freq_update(void *blob)
if (nodeoff >= 0) {
ret = low_drive_fdt_fix_clock(blob, nodeoff, table[i].clk,
table[i].new_rate);
if (!ret)
printf("%s freq updated\n", table[i].node_path);
if (ret)
printf("freq update failed for %s\n", table[i].node_path);
}
}
@@ -671,23 +669,8 @@ static int low_drive_freq_update(void *blob)
int board_fix_fdt(void *fdt)
{
/* Update dtb clocks for low drive mode */
if (is_voltage_mode(VOLT_LOW_DRIVE)) {
int nodeoff;
int i;
struct low_drive_freq_entry table[] = {
{"/soc@0/bus@42800000/mmc@42850000", 0, 266666667},
{"/soc@0/bus@42800000/mmc@42860000", 0, 266666667},
{"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667},
};
for (i = 0; i < ARRAY_SIZE(table); i++) {
nodeoff = fdt_path_offset(fdt, table[i].node_path);
if (nodeoff >= 0)
low_drive_fdt_fix_clock(fdt, nodeoff, table[i].clk,
table[i].new_rate);
}
}
if (is_voltage_mode(VOLT_LOW_DRIVE))
low_drive_freq_update(fdt);
return 0;
}
board/dhelectronics/dh_imx6/dh_imx6_spl.c
+5 -1
View File
@@ -49,6 +49,10 @@
(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define OTG_PAD_CTRL \
(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
@@ -509,7 +513,7 @@ int board_mmc_init(struct bd_info *bis)
/* USB */
static iomux_v3_cfg_t const usb_pads[] = {
IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(OTG_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
board/phytec/phycore_imx93/phycore-imx93.c
+9
View File
@@ -79,6 +79,10 @@ int board_fix_fdt(void *blob)
emmc_fixup(blob, &data);
/* Update dtb clocks for low drive mode */
if (is_voltage_mode(VOLT_LOW_DRIVE))
low_drive_freq_update(blob);
return 0;
}
@@ -86,5 +90,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
{
emmc_fixup(blob, NULL);
/**
* NOTE: VOLT_LOW_DRIVE fixup is done by the ft_system_setup()
* in arch/arm/mach-imx/imx9/soc.c for Linux device-tree.
*/
return 0;
}
configs/imx8ulp_evk_defconfig
+1
View File
@@ -57,6 +57,7 @@ CONFIG_CMD_READ=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_TEMPERATURE=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
drivers/clk/imx/clk-pll14xx.c
+1
View File
@@ -409,6 +409,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
default:
pr_err("%s: Unknown pll type for pll clk %s\n",
__func__, name);
kfree(pll);
return ERR_PTR(-EINVAL);
};
drivers/cpu/imx8_cpu.c
+4
View File
@@ -201,6 +201,10 @@ static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
__weak u32 get_cpu_temp_grade(int *minc, int *maxc)
{
if (minc && maxc) {
*minc = 0;
*maxc = 95;
}
return 0;
}
drivers/misc/imx8/scu_api.c
+1 -2
View File
@@ -1282,8 +1282,7 @@ int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data)
printf("%s, id:0x%x, access:%x, res:%d\n",
__func__, id, access, RPC_R8(&msg));
if (data)
*data = RPC_U32(&msg, 0U);
*data = RPC_U32(&msg, 0U);
return ret;
}
drivers/net/fec_mxc.c
+1
View File
@@ -1344,6 +1344,7 @@ static int fecmxc_probe(struct udevice *dev)
while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("FEC MXC: Timeout resetting chip\n");
ret = -ETIMEDOUT;
goto err_timeout;
}
udelay(10);