Add bootdev_hunt_fallthrough() test to verify that 'bootflow scan -l'
falls back to a lower-priority bootdev when a higher-priority hunter
fails.
Introduce a simple 'sandbox-bootdev' device for the test. The new
bootdev can be configured to produce an error at the hunting stage.
Introduce new host_set_flags_by_label() API and a flags field to
'host_sb_plat' to simulate a bootdev hunter failure for the test.
Adjust boot{dev,flow} tests which depend on bootdev hunters.
Signed-off-by: Denis Mukhin <dmukhin@ford.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently, default 'bootflow scan -lb' will stop booting the board if
any of higher-priority bootdevs fail to be hunted even if there are
bootdevs of lower priority.
For example, if the board has both NVMe (priority 4) and USB MSD devices
(priority 5), and if NVMe bootdev hunt fails (in the event of a bad NVMe
firmware update), USB (which may be a recovery bootdev) is never hunted
automatically, leaving the board at the U-Boot prompt (user intervention
is needed, e.g. something like 'bootflow scan usb' to hunt USB).
Fix bootdev_next_prio() to scan bootdevs at the lower priority level by
not exiting the scan loop early.
Keep the existing logging verbosity unchanged and rely on the failing
subsystem to provide a suitable diagnostic message.
Signed-off-by: Denis Mukhin <dmukhin@ford.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For IH_TYPE_KERNEL_NOLOAD, the entry point is given relative to the
image start, making 0 a valid default, and for IH_OS_EFI, it is ignored
altogether, so it may be preferable to omit it.
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The load address is ignored for IH_TYPE_KERNEL_NOLOAD. Instead of
failing the boot when none is set, it makes more sense to warn when it
*is* set.
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
`flush_start` must be set after `load` has been assigned.
Fixes: 69544c4fd8 ("bootm: Support kernel_noload with compression")
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable MAIN UART1 in the R5 SPL device tree to collect system SYSFW
debug traces during early boot.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
The upstream device tree changed the serial alias for MAIN UART1 from
serial3 to serial1. Update the board initialization code to match this
change by modifying the UCLASS_SERIAL sequence number lookup.
This ensures proper pin control configuration for the UART used by
system firmware (SYSFW).
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Fixes: d2edabfa8d ("arm: mach-k3: am642: Load SYSFW binary and config from boot media")
Reviewed-by: Bryan Brattlof <bb@ti.com>
Add the GigaDevice GD55LB02GF (256 Mo) similar to gd55lb02ge with
the same read path flags.
SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB do not match this chip's
status register layout: the GD55LB02GF uses a 5-bit block protect
field BP0..BP4 plus a CMP bit in SR2 for direction (see datasheet
"Status Register Block Protection").
The generic stm-lock helpers drive only BP0..BP2 and assume SR1
bit 5 is TB, but on this part SR1 bit 5 is BP3.
Enabling either flag would leave BP3..BP4 unmanaged or corrupt
BP3 on every lock op.
A proper support needs a vendor specific lock callback, it is out
of scope for this table update.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
Suggested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>
Commit 103b1e7ce8 ("bootm: bound-check OS index in
bootm_os_get_boot_func()") added a range check to the shared accessor so
an out-of-range OS id can no longer drive an out-of-bounds read of
boot_os[]. That accessor is reached by every image format, but only a
legacy uImage can deliver an unchecked value. bootm_find_os() takes the
raw 8-bit ih_os byte straight from image_get_os() for legacy images,
whereas the FIT path reaches the accessor only after fit_image_load()
has rejected any image whose os is not one of the supported types, and
the Android path hardcodes IH_OS_LINUX. The check can therefore never
fail for FIT, where it only adds confusion and code.
Move the test to the legacy branch of bootm_find_os(), rejecting an
out-of-range OS where the untrusted byte enters. This keeps the FIT path
clear and lets the check be compiled out when CONFIG_LEGACY_IMAGE_FORMAT
is disabled. A valid OS id that has no handler is still reported by the
existing NULL return path in bootm_run_states().
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When I merged the changes in commit 0d8e33717d ("Merge patch series
"arm: aspeed: add initial AST2700 SoC support"") I didn't fully remove
the before/after changes. Finish this merge now.
Reported-by: Yao Zi <me@ziyao.cc>
Signed-off-by: Tom Rini <trini@konsulko.com>
Convert the Layerscape PCIe endpoint driver to use device and ofnode-based
APIs instead of legacy FDT interfaces.
Replace devfdt_get_addr_index_ptr(), fdt_get_named_resource(),
fdtdec_get_bool(), and fdtdec_get_int() with their modern counterparts such
as dev_read_addr_index_ptr(), dev_read_resource_byname(),
dev_read_bool(), and dev_read_s32_default().
Also remove the dependency on gd->fdt_blob and global data access.
No functional changes.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260526-devfdt-pci-v1-5-ed7f31d73938@nxp.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
The commit 55a3421769 ("common: Add an option to relocate on ram top")
changed so that dram_init_banksize() is called before gd->ram_top has
been initialized. This change broke Rockchip DRAM banks configuration
due to gd->ram_top now being 0 when dram_init_banksize() is called.
This makes first DRAM bank size calculation overflow and end up with
DRAM bank = 0x0000000000000000
-> start = 0x0000000000200000
-> size = 0xffffffffffe00000
instead of the expected (for 2 GiB)
DRAM bank = 0x0000000000000000
-> start = 0x0000000000200000
-> size = 0x000000007fe00000
or (for 4 GiB)
DRAM bank = 0x0000000000000000
-> start = 0x0000000000200000
-> size = 0x00000000f7e00000
on e.g. RK3399 boards.
Change to not depend on gd->ram_top having to be pre-calculated before
dram_init_banksize() is called, also move the related method
board_get_usable_ram_top() closer to more easily get an overview of
their interdependence, to restore working DRAM bank initialization.
Fixes: 55a3421769 ("common: Add an option to relocate on ram top")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reported-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> # on Radxa ROCK
Commit 6d04828b45 ("dm: Remove pre-schema tag support") removed the
definitions of these migrate_xxx variables, but left behind their use
in the fdtgrep rule, which now makes that somewhat hard to understand.
Signed-off-by: Rasmus Villemoes <rv@rasmusvillemoes.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use N: to match on all cortina files, drop the large list of
entries which represent the same set of relevant files and miss a
few in the process.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Ryan Chen <ryan_chen@aspeedtech.com> says:
AST2700 is the 8th generation of Integrated Remote Management
Processor introduced by ASPEED Technology Inc. It is a Board
Management Controller (BMC) SoC family with a dual-die architecture:
SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and
SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs,
clock dividers and reset domains.
Link: https://lore.kernel.org/r/20260612-ast2700_clk-v4-0-9bea29cfdc39@aspeedtech.com
Set the acpi_ops structure as static const where applicable. The
The structure is not accessible from outside of drivers and is not
going to be modified at runtime. The structure may be unused in a
couple of drivers depending on their configuration, mark those
sites with __maybe_unused .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert dm_cros_ec_get_ops into an inline function to improve compiler
code coverage, and constify struct dm_cros_ec_ops in a few places.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The current environment loading code prints a partial string
"Loading Environment from %s..." and then triggers env driver
loading function. That env driver loading function may trigger
further prints, either from the env driver itself or from any
other driver that gets probed at that time. The result is a
print which mixed environment loading code prints and driver
code prints, as follows:
"
Environment code print _________________________
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vv
Loading Environment from SPIFlash... SF: Detected w25q128jw... OK
^^^^^^^^^^^^^^^^^^^^^^
Driver code print
"
Adjust the environment loading code print such, that it places
CR at the end of the line. This way, when the driver code prints
something, it overwrites the previous "Loading Environment from %s"
output and the result is not mixed. Furthermore, in case the env
was loaded correctly, print the "Loading Environment from %s ... OK"
in full again. This either overwrites the "Loading Environment from"
message and appends the print with "OK", or, it prints the line in
full after all the driver code prints.
This is not ideal, but it is the best we can do with only CR and
without ANSI control sequences. The result looks as follows:
"
SF: Detected w25q128jw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
Loading Environment from SPIFlash... OK
"
Signed-off-by: Alexander Koch <akoch@initse.com>
Signed-off-by: Marek Vasut <marex@nabladev.com>
The leap year check in rtc_set() passes the loop variable 'i' (month
index, always 1 when the condition is true) to isleap() instead of the
actual year. Since isleap(1) is always false, February 29th is never
accounted for when computing the day count, resulting in the RTC being
set one day behind for any date after February in a leap year.
Pass tmp->tm_year to isleap() so the leap day is correctly included.
Fixes: 8e585f02f8 ("Added M5329AFEE and M5329BFEE Platforms")
Signed-off-by: Naveen Kumar Chaudhary <naveen.osdev@gmail.com>
Add a SDRAM controller driver for the AST2700, derived from the
existing AST2700 controller code used by the Ibex SPL but adapted
to run from ARM U-Boot proper on the Cortex-A35 cores.
The DDR4/DDR5 controller and its DesignWare PHY are programmed by
the Ibex SPL before ARM U-Boot proper takes over. This driver
reads back the configuration left by the SPL, probes the
controller, and exposes ram_info (base and size, with the VGA
carve-out subtracted) via UCLASS_RAM so that dram_init() can
populate gd->ram_size.
The PHY firmware-load entry points (dwc_ddrphy_phyinit_userCustom_*)
are kept compiled but call a __weak fmc_hdr_get_prebuilt() stub
when ARM U-Boot proper is the caller; the real implementation is
provided by the Ibex SPL via the same fmc_hdr.h descriptor format
(here added for the ARM build).
Adds the supporting register-layout headers under
arch/arm/include/asm/arch-aspeed/:
- sdram.h: SDRAM controller and DWC PHY register definitions
- scu.h: SCU bits referenced by the SDRAM driver
- fmc_hdr.h: prebuilt-blob descriptor (binary-compatible with
arch/riscv/include/asm/arch-ast2700/fmc_hdr.h used
by the Ibex SPL)
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Add reset controller driver for the dual-die AST2700 SoC. The
controller manages module-level reset signals via the modrst
register block at offset 0x200 within each SCU.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Add clock controller driver for the dual-die AST2700 SoC. The chip
has two SCUs (SoC0/CPU at 0x12c02000, SoC1/IO at 0x14c02000), each
with its own PLLs (HPLL/APLL/DPLL/MPLL), clock dividers and clock
gate controls. This commit registers two UCLASS_CLK drivers
matching "aspeed,ast2700-scu0" and "aspeed,ast2700-scu1".
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Add initial device tree support for the ASPEED AST27xx family, the
8th-generation Baseboard Management Controller (BMC) SoCs.
AST27xx SOC Family
- https://www.aspeedtech.com/server_ast2700/
- https://www.aspeedtech.com/server_ast2720/
- https://www.aspeedtech.com/server_ast2750/
The AST27xx features a dual-SoC architecture consisting of two ties,
referred to as SoC0 and SoC1 - interconnected through an internal
property bus. Both SoCs share the same address decoding scheme,
while each maintains independent clock and reset domains.
- SoC0 (CPU die): contains a dual-core Cortex-A35 cluster and two
Cortex-M4 cores, along with high-speed peripherals.
- SoC1 (I/O die): includes the BootMCU (responsible for system
boot) and its own clock/reset domains low-speed peripherals.
The device tree describes the SoC0 and SoC1 domains and their peripheral
layouts.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Add initial support for the ASPEED AST2700, an arm64 (Cortex-A35)
Baseboard Management Controller (BMC) SoC. AST2700 is Aspeed's 8th
generation BMC and uses a dual-die architecture: SoC0 (the "CPU"
die) hosts the four Cortex-A35 cores and its own SCU at 0x12c02000,
while SoC1 (the "IO" die) hosts the peripherals and its own SCU at
0x14c02000.
This commit adds:
- ASPEED_AST2700 Kconfig option and the ast2700 mach subdir
(mach Makefile, ast2700/Kconfig, board/aspeed/evb_ast2700/*)
- arm64 MMU map covering the SoC device window and the DRAM
region at 0x4_0000_0000 (up to 8 GiB)
- lowlevel_init.S for early CPU bring-up
- cpu-info: print SoC ID (AST2700/2720/2750 A0/A1/A2 variants)
and reset cause (cold reset, EXT reset, WDT reset)
- board_common: dram_init via UCLASS_RAM, AHBC timeout init
- platform: env_get_location() that selects SPI/eMMC based on
the IO-die HW strap; arch_misc_init() that exposes
${boot_device} and ${verify} to the boot script
- SCU0/SCU1 register layout header (scu_ast2700.h)
- configs/evb-ast2700_defconfig and include/configs/evb_ast2700.h
for the AST2700 EVB board
The defconfig depends on ast2700-evb.dts, which is introduced in
a subsequent patch; this commit must be applied with the
remaining series for evb-ast2700_defconfig to build.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
AST2700 is a 64-bit SoC whose flash AHB windows are decoded above
the 32-bit address space, so rework AHB addresses to uintptr_t and
decoded window sizes to size_t.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
CI:https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/30547
- Move environment variables to .env file on imx7ul-evk/imx6ull-evk/mx6-sabre
- imx ipuv3 improvements.
- Initial support for aquila imx95
- Add support for OPTEE on i.MX93
- Allow users to inhibit i.MX trip point setup
- Add support for imx93_frdm 2CS 2GB DRAM support
- Add optee binary to i.MX9 platform types
- Enable booting Image.gz on imx8m-evk/imx9-evk
Add support for booting compressed kernel Image.gz by defining
kernel_comp_addr_r and kernel_comp_size in the default environment.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add support for booting compressed kernel Image.gz by defining
kernel_comp_addr_r and kernel_comp_size in the default environment.
While at here, set ip_dyn to yes to allow dhcp work properly.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add support for booting compressed kernel Image.gz by defining
kernel_comp_addr_r and kernel_comp_size in the default environment.
Set kernel_comp_addr_r to a high memory region to provide a dedicated
decompression buffer, avoiding overlap between compressed
input and decompressed output.
Also adjust CONFIG_SYS_LOAD_ADDR from 0x40480000 to 0x40400000.
With TEXT_OFFSET=0, the kernel is relocated directly to loadaddr, so
separating decompression and execution regions is required to guarantee
safe decompression without additional copying.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add support for booting compressed kernel Image.gz by defining
kernel_comp_addr_r and kernel_comp_size in the default environment.
Set kernel_comp_addr_r to a high memory region to provide a dedicated
decompression buffer, avoiding overlap between compressed
input and decompressed output.
Also adjust CONFIG_SYS_LOAD_ADDR from 0x40480000 to 0x40400000.
With TEXT_OFFSET=0, the kernel is relocated directly to loadaddr, so
separating decompression and execution regions is required to guarantee
safe decompression without additional copying.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add support for booting compressed kernel Image.gz by defining
kernel_comp_addr_r and kernel_comp_size in the default environment.
Set kernel_comp_addr_r to a high memory region (0x80000000) to provide
a dedicated decompression buffer, avoiding overlap between compressed
input and decompressed output.
Also adjust CONFIG_SYS_LOAD_ADDR from 0x40480000 to 0x40600000.
With TEXT_OFFSET=0, the kernel is relocated directly to loadaddr, so
separating decompression and execution regions is required to guarantee
safe decompression without additional copying.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We want the watchdog to be enabled at boot by default so it can
handle emergency situations in any case.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Now that non-linear clk divider tables are supported, replace the fixed
factor implementation with the proper divider, which allows more fine
control over clock rates.
Signed-off-by: Brian Ruley <brian.ruley@gehealthcare.com>
The existing clk_register_divider() only supports linear or
power-of-two divider mappings. Some hardware (e.g. i.MX6 PLL5
post_div and video_div) uses non-linear register-value-to-divisor
mappings that require a lookup table.
Add clk_register_divider_table() which accepts a clk_div_table,
and reimplement clk_register_divider() as a wrapper passing
table=NULL.
Signed-off-by: Brian Ruley <brian.ruley@gehealthcare.com>
Obviously, the clock has to be enabled if writing to it's registers.
This was missed because the board I tested on had enabled the clocks in
early init.
Also, remove the completely useless "ipu_clk_enabled" struct member and
use the accurate usecount / enabled_count instead.
Signed-off-by: Brian Ruley <brian.ruley@gehealthcare.com>
A hardware bug prevents LDB clock selectors from being configured later
on non-plus i.MX6QD variants, so let's set the desired configuration in
the probe before we register them. We also have to make the necessary
clock functions available in XPL builds.
Signed-off-by: Brian Ruley <brian.ruley@gehealthcare.com>
The LDB clock sources don't have to be the same, so allow DI1 clock to
be configured separately.
Unlikely to be significant, but the reason will become apparent in the
following commit.
Signed-off-by: Brian Ruley <brian.ruley@gehealthcare.com>
After reset, all PLLs are bypassed by default so unbypass them so that
dependent clocks can function correctly.
Signed-off-by: Brian Ruley <brian.ruley@gehealthcare.com>
Denis MukhinandTom Rini
Nora SchifferandTom Rini
Vishal MahaveerandTom Rini
Vincent JardinandTom Rini
Aristo ChenandTom Rini
Peng FanandNeil Armstrong
Jonas KarlmanandTom Rini
Rasmus VillemoesandTom Rini
Marek VasutandTom Rini
Alexander KochandTom Rini
Naveen Kumar ChaudharyandTom Rini
Ryan ChenandTom Rini
Ye LiandFabio Estevam
Frieder SchrempfandFabio Estevam
Brian RuleyandFabio Estevam