Merge tag 'u-boot-imx-next-20260627' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI:https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/30547 - Move environment variables to .env file on imx7ul-evk/imx6ull-evk/mx6-sabre - imx ipuv3 improvements. - Initial support for aquila imx95 - Add support for OPTEE on i.MX93 - Allow users to inhibit i.MX trip point setup - Add support for imx93_frdm 2CS 2GB DRAM support - Add optee binary to i.MX9 platform types - Enable booting Image.gz on imx8m-evk/imx9-evk
This commit is contained in:
Tom Rini
@@ -82,25 +82,25 @@
|
||||
};
|
||||
|
||||
ddr-1d-imem-fw {
|
||||
filename = "lpddr4_pmu_train_1d_imem.bin";
|
||||
filename = "lpddr4_pmu_train_1d_imem_202006.bin";
|
||||
align-end = <4>;
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
ddr-1d-dmem-fw {
|
||||
filename = "lpddr4_pmu_train_1d_dmem.bin";
|
||||
filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
|
||||
align-end = <4>;
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
ddr-2d-imem-fw {
|
||||
filename = "lpddr4_pmu_train_2d_imem.bin";
|
||||
filename = "lpddr4_pmu_train_2d_imem_202006.bin";
|
||||
align-end = <4>;
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
ddr-2d-dmem-fw {
|
||||
filename = "lpddr4_pmu_train_2d_dmem.bin";
|
||||
filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
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||||
align-end = <4>;
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
@@ -137,7 +137,7 @@
|
||||
|
||||
ddr-1d-imem-fw {
|
||||
#ifdef CONFIG_IMX8M_LPDDR4
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||||
filename = "lpddr4_pmu_train_1d_imem.bin";
|
||||
filename = "lpddr4_pmu_train_1d_imem_202006.bin";
|
||||
#elif CONFIG_IMX8M_DDR4
|
||||
filename = "ddr4_imem_1d_201810.bin";
|
||||
#else
|
||||
@@ -149,7 +149,7 @@
|
||||
|
||||
ddr-1d-dmem-fw {
|
||||
#ifdef CONFIG_IMX8M_LPDDR4
|
||||
filename = "lpddr4_pmu_train_1d_dmem.bin";
|
||||
filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
|
||||
#elif CONFIG_IMX8M_DDR4
|
||||
filename = "ddr4_dmem_1d_201810.bin";
|
||||
#else
|
||||
@@ -162,7 +162,7 @@
|
||||
#if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4)
|
||||
ddr-2d-imem-fw {
|
||||
#ifdef CONFIG_IMX8M_LPDDR4
|
||||
filename = "lpddr4_pmu_train_2d_imem.bin";
|
||||
filename = "lpddr4_pmu_train_2d_imem_202006.bin";
|
||||
#else
|
||||
filename = "ddr4_imem_2d_201810.bin";
|
||||
#endif
|
||||
@@ -172,7 +172,7 @@
|
||||
|
||||
ddr-2d-dmem-fw {
|
||||
#ifdef CONFIG_IMX8M_LPDDR4
|
||||
filename = "lpddr4_pmu_train_2d_dmem.bin";
|
||||
filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
|
||||
#else
|
||||
filename = "ddr4_dmem_2d_201810.bin";
|
||||
#endif
|
||||
|
||||
@@ -96,25 +96,25 @@
|
||||
};
|
||||
|
||||
ddr-1d-imem-fw {
|
||||
filename = "lpddr4_pmu_train_1d_imem.bin";
|
||||
filename = "lpddr4_pmu_train_1d_imem_202006.bin";
|
||||
align-end = <4>;
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
ddr-1d-dmem-fw {
|
||||
filename = "lpddr4_pmu_train_1d_dmem.bin";
|
||||
filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
|
||||
align-end = <4>;
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
ddr-2d-imem-fw {
|
||||
filename = "lpddr4_pmu_train_2d_imem.bin";
|
||||
filename = "lpddr4_pmu_train_2d_imem_202006.bin";
|
||||
align-end = <4>;
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
ddr-2d-dmem-fw {
|
||||
filename = "lpddr4_pmu_train_2d_dmem.bin";
|
||||
filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
|
||||
align-end = <4>;
|
||||
type = "blob-ext";
|
||||
};
|
||||
|
||||
@@ -69,6 +69,9 @@
|
||||
container;
|
||||
image0 = "a55", "bl31.bin", "0x204E0000";
|
||||
image1 = "a55", "u-boot.bin", "0x80200000";
|
||||
#if defined(CONFIG_OPTEE)
|
||||
image2 = "a55", "tee.bin", "0x96000000";
|
||||
#endif
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,40 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/* Copyright (c) Toradex */
|
||||
|
||||
#include "imx95-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
sysinfo {
|
||||
compatible = "toradex,sysinfo";
|
||||
};
|
||||
};
|
||||
|
||||
&lpuart1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_uart1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1_200mhz {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&usb3_dwc3 {
|
||||
bootph-pre-ram;
|
||||
compatible = "fsl,imx95a-dwc3", "fsl,imx8mq-dwc3", "snps,dwc3";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,389 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright (c) Toradex
|
||||
*
|
||||
* https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
|
||||
* https://www.toradex.com/products/carrier-board/aquila-development-board-kit
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
#include "imx95-aquila.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Aquila iMX95 on Aquila Development Board";
|
||||
compatible = "toradex,aquila-imx95-dev",
|
||||
"toradex,aquila-imx95",
|
||||
"fsl,imx95";
|
||||
|
||||
aliases {
|
||||
eeprom1 = &carrier_eeprom;
|
||||
};
|
||||
|
||||
dp_1_connector: dp0-connector {
|
||||
compatible = "dp-connector";
|
||||
dp-pwr-supply = <®_dp_3p3v>;
|
||||
type = "full-size";
|
||||
|
||||
port {
|
||||
dp_1_connector_in: endpoint {
|
||||
remote-endpoint = <&dsi2dp_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
reg_carrier_1p8v: regulator-carrier-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-name = "On-carrier 1V8";
|
||||
};
|
||||
|
||||
reg_dp_3p3v: regulator-dp-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_21_dp>;
|
||||
/* Aquila GPIO_21_DP */
|
||||
gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-name = "DP_3V3";
|
||||
startup-delay-us = <10000>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,bitclock-master = <&codec_dai>;
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,frame-master = <&codec_dai>;
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,name = "aquila-wm8904";
|
||||
simple-audio-card,routing =
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"IN2L", "Line In Jack",
|
||||
"IN2R", "Line In Jack",
|
||||
"Microphone Jack", "MICBIAS",
|
||||
"IN1L", "Microphone Jack",
|
||||
"IN1R", "Digital Mic";
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Microphone Jack",
|
||||
"Microphone", "Digital Mic",
|
||||
"Headphone", "Headphone Jack",
|
||||
"Line", "Line In Jack";
|
||||
|
||||
codec_dai: simple-audio-card,codec {
|
||||
sound-dai = <&wm8904_1a>;
|
||||
};
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&sai2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Aquila ADC_[1-4] */
|
||||
&adc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila CTRL_WAKE1_MICO# */
|
||||
&aquila_key_wake {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi2dp_out {
|
||||
remote-endpoint = <&dp_1_connector_in>;
|
||||
};
|
||||
|
||||
/* Aquila ETH_1 */
|
||||
&enetc_port0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila CAN_1 */
|
||||
&flexcan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila CAN_2 */
|
||||
&flexcan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila CAN_3 */
|
||||
&flexcan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila CAN_4 */
|
||||
&flexcan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila QSPI_1 */
|
||||
&flexspi1 {
|
||||
pinctrl-0 = <&pinctrl_flexspi1_4bit>,
|
||||
<&pinctrl_qspi_cs1>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-max-frequency = <66000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_8>;
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_1>,
|
||||
<&pinctrl_gpio_2>,
|
||||
<&pinctrl_gpio_3>,
|
||||
<&pinctrl_gpio_4>,
|
||||
<&pinctrl_gpio_5>,
|
||||
<&pinctrl_gpio_6>,
|
||||
<&pinctrl_gpio_7>;
|
||||
};
|
||||
|
||||
/* Aquila I2C_1 */
|
||||
&lpi2c2 {
|
||||
status = "okay";
|
||||
|
||||
fan_controller: fan@18 {
|
||||
compatible = "ti,amc6821";
|
||||
reg = <0x18>;
|
||||
#pwm-cells = <2>;
|
||||
|
||||
fan {
|
||||
cooling-levels = <255>;
|
||||
pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
|
||||
};
|
||||
};
|
||||
|
||||
wm8904_1a: audio-codec@1a {
|
||||
compatible = "wlf,wm8904";
|
||||
reg = <0x1a>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai2_mclk>;
|
||||
clocks = <&scmi_clk IMX95_CLK_SAI2>;
|
||||
clock-names = "mclk";
|
||||
#sound-dai-cells = <0>;
|
||||
AVDD-supply = <®_carrier_1p8v>;
|
||||
CPVDD-supply = <®_carrier_1p8v>;
|
||||
DBVDD-supply = <®_carrier_1p8v>;
|
||||
DCVDD-supply = <®_carrier_1p8v>;
|
||||
MICVDD-supply = <®_carrier_1p8v>;
|
||||
wlf,drc-cfg-names = "default", "peaklimiter";
|
||||
/*
|
||||
* Config registers per name, respectively:
|
||||
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
|
||||
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
|
||||
*/
|
||||
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
|
||||
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>;
|
||||
/* GPIO1 = DMIC_CLK, don't touch others */
|
||||
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
|
||||
wlf,in1r-as-dmicdat2;
|
||||
};
|
||||
|
||||
/* Current measurement into module VCC */
|
||||
hwmon@41 {
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
||||
temperature-sensor@4f {
|
||||
compatible = "ti,tmp1075";
|
||||
reg = <0x4f>;
|
||||
};
|
||||
|
||||
/* USB-C OTG (TCPC USB PD PHY) */
|
||||
tcpc@52 {
|
||||
compatible = "nxp,ptn5110", "tcpci";
|
||||
reg = <0x52>;
|
||||
interrupt-parent = <&som_gpio_expander_1>;
|
||||
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
data-role = "dual";
|
||||
op-sink-microwatt = <0>;
|
||||
power-role = "dual";
|
||||
self-powered;
|
||||
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
|
||||
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
|
||||
try-power-role = "sink";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
typec_con_hs: endpoint {
|
||||
remote-endpoint = <&usb1_con_hs>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
typec_con_ss: endpoint {
|
||||
remote-endpoint = <&usb1_con_ss>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
carrier_eeprom: eeprom@57 {
|
||||
compatible = "st,24c02", "atmel,24c02";
|
||||
reg = <0x57>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Aquila I2C_2 */
|
||||
&i3c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila I2C_4_CSI1 */
|
||||
&lpi2c4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila I2C_6 */
|
||||
&lpi2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila I2C_3_DSI1/I2C_5_CSI2 */
|
||||
&lpi2c8 {
|
||||
status = "okay";
|
||||
|
||||
i2c-mux@70 {
|
||||
compatible = "nxp,pca9543";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* I2C on DSI Connector Pin #4 and #6 */
|
||||
i2c_dsi_0: i2c@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
/* I2C on DSI Connector Pin #52 and #54 */
|
||||
i2c_dsi_1: i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Aquila SPI_1 */
|
||||
&lpspi6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila UART_3, used as the Linux Console */
|
||||
&lpuart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila UART_4 */
|
||||
&lpuart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila UART_1 */
|
||||
&lpuart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila UART_2 as RS485 */
|
||||
&lpuart7 {
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
rs485-rts-active-low;
|
||||
rs485-rx-during-tx;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila PCIE_1 */
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila I2S_1 */
|
||||
&sai2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila PWM_1 */
|
||||
&tpm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila PWM_2 */
|
||||
&tpm6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila PWM_3_DSI and PWM_4_DP */
|
||||
&tpm5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila USB_2, optional Bluetooth USB */
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Aquila USB_1 */
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_dwc3 {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
usb1_con_hs: endpoint {
|
||||
remote-endpoint = <&typec_con_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_phy {
|
||||
orientation-switch;
|
||||
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
usb1_con_ss: endpoint {
|
||||
remote-endpoint = <&typec_con_ss>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Aquila SD_1 */
|
||||
&usdhc2 {
|
||||
status = "okay";
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -181,12 +181,7 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
reg = <0 0x43810000 0 0x1000>, <0 0x43810040 0 0x40>;
|
||||
bootph-pre-ram;
|
||||
/*
|
||||
* Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2
|
||||
@@ -196,17 +191,14 @@
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
reg = <0 0x43820000 0 0x1000>, <0 0x43820040 0 0x40>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
reg = <0 0x43840000 0 0x1000>, <0 0x43840040 0 0x40>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
reg = <0 0x43850000 0 0x1000>, <0 0x43850040 0 0x40>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
|
||||
@@ -82,7 +82,7 @@ int enable_lcdif_clock(u32 base_addr, bool enable);
|
||||
void enable_qspi_clk(int qspi_num);
|
||||
void enable_thermal_clk(void);
|
||||
void mxs_set_lcdclk(u32 base_addr, u32 freq);
|
||||
void select_ldb_di_clock_source(enum ldb_di_clock clk);
|
||||
void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1);
|
||||
void enable_eim_clk(unsigned char enable);
|
||||
int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[]);
|
||||
|
||||
@@ -30,6 +30,7 @@
|
||||
#define ELE_START_RNG (0xA3)
|
||||
#define ELE_CMD_DERIVE_KEY (0xA9)
|
||||
#define ELE_GENERATE_DEK_BLOB (0xAF)
|
||||
#define ELE_V2X_GET_STATE_REQ (0xB2)
|
||||
#define ELE_ENABLE_PATCH_REQ (0xC3)
|
||||
#define ELE_RELEASE_RDC_REQ (0xC4)
|
||||
#define ELE_GET_FW_STATUS_REQ (0xC5)
|
||||
@@ -141,6 +142,12 @@ struct ele_get_info_data {
|
||||
u32 reserved[8];
|
||||
};
|
||||
|
||||
struct v2x_get_state {
|
||||
u8 v2x_state;
|
||||
u8 v2x_power_state;
|
||||
u32 v2x_err_code;
|
||||
};
|
||||
|
||||
int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response);
|
||||
int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
|
||||
int ele_release_container(u32 *response);
|
||||
@@ -166,4 +173,5 @@ int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response);
|
||||
int ele_set_gmid(u32 *response);
|
||||
int ele_volt_change_start_req(void);
|
||||
int ele_volt_change_finish_req(void);
|
||||
int ele_v2x_get_state(struct v2x_get_state *state, u32 *response);
|
||||
#endif
|
||||
|
||||
+1
-59
@@ -47,7 +47,7 @@ u32 get_imx_reset_cause(void)
|
||||
return reset_cause;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD)
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) && !CONFIG_IS_ENABLED(CPU)
|
||||
static char *get_reset_cause(void)
|
||||
{
|
||||
switch (get_imx_reset_cause()) {
|
||||
@@ -75,11 +75,6 @@ static char *get_reset_cause(void)
|
||||
return "WDOG4";
|
||||
case 0x00200:
|
||||
return "TEMPSENSE";
|
||||
#elif defined(CONFIG_IMX8M)
|
||||
case 0x00100:
|
||||
return "WDOG2";
|
||||
case 0x00200:
|
||||
return "TEMPSENSE";
|
||||
#else
|
||||
case 0x00100:
|
||||
return "TEMPSENSE";
|
||||
@@ -90,63 +85,10 @@ static char *get_reset_cause(void)
|
||||
return "unknown reset";
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD)
|
||||
|
||||
const char *get_imx_type(u32 imxtype)
|
||||
{
|
||||
switch (imxtype) {
|
||||
case MXC_CPU_IMX8MP:
|
||||
return "8MP[8]"; /* Quad-core version of the imx8mp */
|
||||
case MXC_CPU_IMX8MPD2:
|
||||
return "8MP Dual[2]"; /* Dual-core version of the imx8mp, low cost industrial & HMI */
|
||||
case MXC_CPU_IMX8MPD:
|
||||
return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
|
||||
case MXC_CPU_IMX8MPL:
|
||||
return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
|
||||
case MXC_CPU_IMX8MP5:
|
||||
return "8MP[5]"; /* Quad-core version of the imx8mp, low cost industrial & HMI */
|
||||
case MXC_CPU_IMX8MP6:
|
||||
return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
|
||||
case MXC_CPU_IMX8MPUL:
|
||||
return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */
|
||||
case MXC_CPU_IMX8MN:
|
||||
return "8MNano Quad"; /* Quad-core version */
|
||||
case MXC_CPU_IMX8MND:
|
||||
return "8MNano Dual"; /* Dual-core version */
|
||||
case MXC_CPU_IMX8MNS:
|
||||
return "8MNano Solo"; /* Single-core version */
|
||||
case MXC_CPU_IMX8MNL:
|
||||
return "8MNano QuadLite"; /* Quad-core Lite version */
|
||||
case MXC_CPU_IMX8MNDL:
|
||||
return "8MNano DualLite"; /* Dual-core Lite version */
|
||||
case MXC_CPU_IMX8MNSL:
|
||||
return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
|
||||
case MXC_CPU_IMX8MNUQ:
|
||||
return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
|
||||
case MXC_CPU_IMX8MNUD:
|
||||
return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
|
||||
case MXC_CPU_IMX8MNUS:
|
||||
return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
|
||||
case MXC_CPU_IMX8MM:
|
||||
return "8MMQ"; /* Quad-core version of the imx8mm */
|
||||
case MXC_CPU_IMX8MML:
|
||||
return "8MMQL"; /* Quad-core Lite version of the imx8mm */
|
||||
case MXC_CPU_IMX8MMD:
|
||||
return "8MMD"; /* Dual-core version of the imx8mm */
|
||||
case MXC_CPU_IMX8MMDL:
|
||||
return "8MMDL"; /* Dual-core Lite version of the imx8mm */
|
||||
case MXC_CPU_IMX8MMS:
|
||||
return "8MMS"; /* Single-core version of the imx8mm */
|
||||
case MXC_CPU_IMX8MMSL:
|
||||
return "8MMSL"; /* Single-core Lite version of the imx8mm */
|
||||
case MXC_CPU_IMX8MQ:
|
||||
return "8MQ"; /* Quad-core version of the imx8mq */
|
||||
case MXC_CPU_IMX8MQL:
|
||||
return "8MQLite"; /* Quad-core Lite version of the imx8mq */
|
||||
case MXC_CPU_IMX8MD:
|
||||
return "8MD"; /* Dual-core version of the imx8mq */
|
||||
case MXC_CPU_MX7S:
|
||||
return "7S"; /* Single-core version of the mx7 */
|
||||
case MXC_CPU_MX7D:
|
||||
|
||||
@@ -3,6 +3,7 @@
|
||||
* Copyright 2024 NXP
|
||||
*/
|
||||
|
||||
#include <env.h>
|
||||
#include <errno.h>
|
||||
#include <fdtdec.h>
|
||||
#include <malloc.h>
|
||||
@@ -91,6 +92,15 @@ int fixup_thermal_trips(void *blob, const char *name)
|
||||
int minc, maxc;
|
||||
int node, trip;
|
||||
|
||||
/*
|
||||
* During development or various dangerous experiments, it may
|
||||
* be necessary to override the trip points. Allow users to do
|
||||
* that. However, do keep in mind that this may damage the SoC.
|
||||
*/
|
||||
if (CONFIG_IS_ENABLED(ENV_SUPPORT))
|
||||
if (env_get("imx_skip_fixup_thermal_trips"))
|
||||
return 0;
|
||||
|
||||
node = fdt_path_offset(blob, "/thermal-zones");
|
||||
if (node < 0)
|
||||
return node;
|
||||
|
||||
@@ -10,6 +10,7 @@ config IMX8M
|
||||
select ARMV8_CRYPTO
|
||||
imply CPU
|
||||
imply CPU_IMX
|
||||
imply DM_THERMAL
|
||||
imply IMX_TMU
|
||||
|
||||
config IMX8MQ
|
||||
|
||||
@@ -1480,6 +1480,33 @@ void reset_cpu(void)
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_ARCH_MISC_INIT)
|
||||
static char *get_reset_cause(void)
|
||||
{
|
||||
switch (get_imx_reset_cause()) {
|
||||
case 0x00001:
|
||||
case 0x00011:
|
||||
return "POR";
|
||||
case 0x00004:
|
||||
return "CSU";
|
||||
case 0x00008:
|
||||
return "IPP USER";
|
||||
case 0x00010:
|
||||
return "WDOG";
|
||||
case 0x00020:
|
||||
return "JTAG HIGH-Z";
|
||||
case 0x00040:
|
||||
return "JTAG SW";
|
||||
case 0x00080:
|
||||
return "WDOG3";
|
||||
case 0x00100:
|
||||
return "WDOG2";
|
||||
case 0x00200:
|
||||
return "TEMPSENSE";
|
||||
default:
|
||||
return "unknown reset";
|
||||
}
|
||||
}
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
|
||||
@@ -1491,6 +1518,9 @@ int arch_misc_init(void)
|
||||
printf("Failed to initialize caam_jr: %d\n", ret);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_XPL_BUILD))
|
||||
printf("Reset cause: %s\n", get_reset_cause());
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -254,11 +254,6 @@ static char *get_reset_cause(char *ret)
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||
const char *get_imx_type(u32 imxtype)
|
||||
{
|
||||
return "8ULP";
|
||||
}
|
||||
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
u32 cpurev;
|
||||
@@ -266,8 +261,7 @@ int print_cpuinfo(void)
|
||||
|
||||
cpurev = get_cpu_rev();
|
||||
|
||||
printf("CPU: i.MX%s rev%d.%d at %d MHz\n",
|
||||
get_imx_type((cpurev & 0xFF000) >> 12),
|
||||
printf("CPU: i.MX8ULP rev%d.%d at %d MHz\n",
|
||||
(cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
|
||||
mxc_get_clock(MXC_ARM_CLK) / 1000000);
|
||||
|
||||
|
||||
@@ -14,6 +14,7 @@ config IMX9
|
||||
select HAS_CAAM
|
||||
select ROM_UNIFIED_SECTIONS
|
||||
imply IMX_TMU
|
||||
imply OF_LIVE
|
||||
|
||||
config IMX93
|
||||
bool
|
||||
@@ -172,6 +173,10 @@ config TARGET_IMX943_EVK
|
||||
imply BOOTSTD_FULL
|
||||
imply OF_UPSTREAM
|
||||
|
||||
config TARGET_AQUILA_IMX95
|
||||
bool "Support Toradex Aquila iMX95"
|
||||
select IMX95
|
||||
|
||||
config TARGET_TORADEX_SMARC_IMX95
|
||||
bool "Support Toradex SMARC iMX95"
|
||||
select IMX95
|
||||
@@ -205,6 +210,7 @@ source "board/phytec/phycore_imx91_93/Kconfig"
|
||||
source "board/variscite/imx93_var_som/Kconfig"
|
||||
source "board/nxp/imx94_evk/Kconfig"
|
||||
source "board/nxp/imx95_evk/Kconfig"
|
||||
source "board/toradex/aquila-imx95/Kconfig"
|
||||
source "board/toradex/smarc-imx95/Kconfig"
|
||||
source "board/toradex/verdin-imx95/Kconfig"
|
||||
source "board/nxp/imx952_evk/Kconfig"
|
||||
|
||||
@@ -11,7 +11,7 @@ obj-y += soc.o clock.o clock_root.o trdc.o
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
obj-y += imx_bootaux.o
|
||||
obj-y += imx_bootaux.o misc.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_$(PHASE_)IMX_QB) += qb.o
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2023-2026 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
#include <command.h>
|
||||
#include <cpu_func.h>
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <asm/arch-imx/cpu.h>
|
||||
#include <asm/mach-imx/ele_api.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <display_options.h>
|
||||
|
||||
static int do_v2x_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
{
|
||||
int ret;
|
||||
u32 resp = 0;
|
||||
struct v2x_get_state state;
|
||||
|
||||
if (is_imx91() || is_imx93()) {
|
||||
printf("No V2X supported\n");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
ret = ele_v2x_get_state(&state, &resp);
|
||||
if (ret) {
|
||||
printf("get v2x state failed, resp 0x%x, ret %d\n", resp, ret);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
printf("V2X state: 0x%x\n", state.v2x_state);
|
||||
printf("V2X power state: 0x%x\n", state.v2x_power_state);
|
||||
printf("V2X err code: 0x%x\n", state.v2x_err_code);
|
||||
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static int do_ele_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
{
|
||||
int ret;
|
||||
u32 res = 0, length;
|
||||
struct ele_get_info_data *info;
|
||||
|
||||
/* ELE can't access full DDR */
|
||||
info = (struct ele_get_info_data *)(CONFIG_TEXT_BASE + SZ_2M -
|
||||
sizeof(struct ele_get_info_data));
|
||||
flush_dcache_range((ulong)info, (ulong)info + sizeof(struct ele_get_info_data));
|
||||
|
||||
ret = ele_get_info(info, &res);
|
||||
if (ret) {
|
||||
printf("Get ELE info failed, resp 0x%x, ret %d\n", res, ret);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
invalidate_dcache_range((ulong)info, (ulong)info + sizeof(struct ele_get_info_data));
|
||||
|
||||
printf("SOC: 0x%x\n", info->soc);
|
||||
printf("LC: 0x%x\n", info->lc);
|
||||
|
||||
printf("\nUID:\n");
|
||||
print_buffer(0, &info->uid, 4, 4, 0);
|
||||
|
||||
printf("\nSHA256 ROM PATCH:\n");
|
||||
print_buffer(0, &info->sha256_rom_patch, 4, 8, 0);
|
||||
|
||||
printf("\nSHA FW:\n");
|
||||
print_buffer(0, &info->sha_fw, 4, 8, 0);
|
||||
|
||||
printf("\nOEM SRKH:\n");
|
||||
print_buffer(0, &info->oem_srkh, 4, 16, 0);
|
||||
|
||||
printf("\nSTATE: 0x%x\n", info->state);
|
||||
|
||||
length = (info->hdr >> 16) & 0xffff;
|
||||
if (length == sizeof(struct ele_get_info_data)) {
|
||||
printf("\nOEM PQC SRKH:\n");
|
||||
print_buffer(0, &info->oem_pqc_srkh, 4, 16, 0);
|
||||
}
|
||||
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(v2x_status, CONFIG_SYS_MAXARGS, 1, do_v2x_status,
|
||||
"display v2x status",
|
||||
""
|
||||
);
|
||||
|
||||
U_BOOT_CMD(ele_info, CONFIG_SYS_MAXARGS, 1, do_ele_info,
|
||||
"display ELE information",
|
||||
""
|
||||
);
|
||||
@@ -21,6 +21,7 @@
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <dm/ofnode.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <env.h>
|
||||
#include <env_internal.h>
|
||||
@@ -738,13 +739,16 @@ int arch_cpu_init(void)
|
||||
int imx9_probe_mu(void)
|
||||
{
|
||||
struct udevice *devp;
|
||||
int node, ret;
|
||||
ofnode node;
|
||||
int ret;
|
||||
u32 res;
|
||||
struct ele_get_info_data info;
|
||||
|
||||
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");
|
||||
node = ofnode_by_compatible(ofnode_null(), "fsl,imx93-mu-s4");
|
||||
if (!ofnode_valid(node))
|
||||
return -ENODEV;
|
||||
|
||||
ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
|
||||
ret = uclass_get_device_by_ofnode(UCLASS_MISC, node, &devp);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
@@ -1452,7 +1452,7 @@ static void enable_ldb_di_clock_sources(void)
|
||||
* Try call this function as early in the boot process as possible since the
|
||||
* function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
|
||||
*/
|
||||
void select_ldb_di_clock_source(enum ldb_di_clock clk)
|
||||
void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
int reg;
|
||||
@@ -1525,8 +1525,8 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
|
||||
reg = readl(&mxc_ccm->cs2cdr);
|
||||
reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
|
||||
| MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
|
||||
reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
|
||||
| (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
|
||||
reg |= ((clk0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
|
||||
| (clk1 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
|
||||
writel(reg, &mxc_ccm->cs2cdr);
|
||||
|
||||
/* Unbypass pll3_sw_clk */
|
||||
|
||||
@@ -259,11 +259,6 @@ void reset_cpu(void)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||
const char *get_imx_type(u32 imxtype)
|
||||
{
|
||||
return "7ULP";
|
||||
}
|
||||
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
u32 cpurev;
|
||||
@@ -271,8 +266,7 @@ int print_cpuinfo(void)
|
||||
|
||||
cpurev = get_cpu_rev();
|
||||
|
||||
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
|
||||
get_imx_type((cpurev & 0xFF000) >> 12),
|
||||
printf("CPU: Freescale i.MX7ULP rev%d.%d at %d MHz\n",
|
||||
(cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
|
||||
mxc_get_clock(MXC_ARM_CLK) / 1000000);
|
||||
|
||||
|
||||
@@ -218,7 +218,7 @@ static void set_gpr_register(void)
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
select_ldb_di_clock_source(MXC_PLL5_CLK);
|
||||
select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
|
||||
set_gpr_register();
|
||||
|
||||
/*
|
||||
|
||||
@@ -320,7 +320,7 @@ int overwrite_console(void)
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
select_ldb_di_clock_source(MXC_PLL5_CLK);
|
||||
select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -383,7 +383,7 @@ int board_early_init_f(void)
|
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3)
|
||||
/* Set LDB clock to Video PLL */
|
||||
select_ldb_di_clock_source(MXC_PLL5_CLK);
|
||||
select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -12,6 +12,8 @@ initrd_addr=0x48080000
|
||||
image=Image
|
||||
ip_dyn=yes
|
||||
kernel_addr_r=0x42000000
|
||||
kernel_comp_addr_r=0x60000000
|
||||
kernel_comp_size=0x2000000
|
||||
loadaddr=CONFIG_SYS_LOAD_ADDR
|
||||
mmcautodetect=yes
|
||||
mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
|
||||
|
||||
@@ -12,6 +12,8 @@ initrd_addr=0x48080000
|
||||
image=Image
|
||||
ip_dyn=yes
|
||||
kernel_addr_r=0x42000000
|
||||
kernel_comp_addr_r=0x60000000
|
||||
kernel_comp_size=0x2000000
|
||||
loadaddr=CONFIG_SYS_LOAD_ADDR
|
||||
mmcautodetect=yes
|
||||
mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
|
||||
|
||||
@@ -10,6 +10,8 @@ fdt_addr=0x43000000
|
||||
fdtfile=DEFAULT_FDT_FILE
|
||||
image=Image
|
||||
ip_dyn=yes
|
||||
kernel_comp_addr_r=0x80000000
|
||||
kernel_comp_size=0x2000000
|
||||
mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
|
||||
mmcpart=1
|
||||
mmcroot=/dev/mmcblk1p2 rootwait rw
|
||||
|
||||
@@ -10,6 +10,8 @@ initrd_addr=0x43800000
|
||||
image=Image
|
||||
ip_dyn=yes
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
kernel_comp_addr_r=0x80000000
|
||||
kernel_comp_size=0x2000000
|
||||
loadaddr=CONFIG_SYS_LOAD_ADDR
|
||||
mmcautodetect=yes
|
||||
mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
|
||||
|
||||
@@ -10,13 +10,16 @@ fdt_addr_r=0x83000000
|
||||
fdt_addr=0x83000000
|
||||
fdtfile=DEFAULT_FDT_FILE
|
||||
image=Image
|
||||
ip_dyn=yes
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
kernel_comp_addr_r=0xC0000000
|
||||
kernel_comp_size=0x2000000
|
||||
mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
|
||||
mmcpart=1
|
||||
mmcroot=/dev/mmcblk1p2 rootwait rw
|
||||
mmcautodetect=yes
|
||||
mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}
|
||||
prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
|
||||
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
|
||||
loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
|
||||
|
||||
@@ -7,5 +7,5 @@
|
||||
obj-y += imx93_frdm.o
|
||||
|
||||
ifdef CONFIG_XPL_BUILD
|
||||
obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o
|
||||
obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_1cs_2gb_timing.o lpddr4x_2cs_2gb_timing.o
|
||||
endif
|
||||
|
||||
@@ -10,12 +10,15 @@ fdt_addr_r=0x83000000
|
||||
fdt_addr=0x83000000
|
||||
fdtfile=DEFAULT_FDT_FILE
|
||||
image=Image
|
||||
ip_dyn=yes
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
kernel_comp_addr_r=0xC0000000
|
||||
kernel_comp_size=0x2000000
|
||||
mmcdev=1
|
||||
mmcpart=1
|
||||
mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw
|
||||
mmcautodetect=yes
|
||||
mmcargs=setenv bootargs console=${console} root=${mmcroot}
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
|
||||
loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
|
||||
boot_os=booti ${loadaddr} - ${fdt_addr_r}
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#define __LPDDR4_TIMING_H__
|
||||
|
||||
extern struct dram_timing_info dram_timing_1GB;
|
||||
extern struct dram_timing_info dram_timing_2GB;
|
||||
extern struct dram_timing_info dram_timing_1CS_2GB;
|
||||
extern struct dram_timing_info dram_timing_2CS_2GB;
|
||||
|
||||
#endif /* __LPDDR4_TIMING_H__ */
|
||||
|
||||
+1
-1
@@ -1978,7 +1978,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
|
||||
};
|
||||
|
||||
/* ddr timing config params */
|
||||
struct dram_timing_info dram_timing_2GB = {
|
||||
struct dram_timing_info dram_timing_1CS_2GB = {
|
||||
.ddrc_cfg = ddr_ddrc_cfg,
|
||||
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
|
||||
.ddrphy_cfg = ddr_ddrphy_cfg,
|
||||
File diff suppressed because it is too large
Load Diff
@@ -33,9 +33,10 @@ static struct _drams {
|
||||
u8 mr8;
|
||||
struct dram_timing_info *pdram_timing;
|
||||
char *name;
|
||||
} frdm_drams[2] = {
|
||||
} frdm_drams[3] = {
|
||||
{0x10, &dram_timing_1GB, "1GB DRAM" },
|
||||
{0x18, &dram_timing_2GB, "2GB DRAM" },
|
||||
{0x12, &dram_timing_2CS_2GB, "2CS_2GB DRAM" },
|
||||
{0x18, &dram_timing_1CS_2GB, "1CS_2GB DRAM" },
|
||||
};
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
|
||||
@@ -10,6 +10,10 @@ fdt_addr_r=0x83000000
|
||||
fdt_addr=0x83000000
|
||||
fdtfile=DEFAULT_FDT_FILE
|
||||
image=Image
|
||||
ip_dyn=yes
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
kernel_comp_addr_r=0xC0000000
|
||||
kernel_comp_size=0x2000000
|
||||
mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
|
||||
mmcpart=1
|
||||
mmcroot=/dev/mmcblk1p2 rootwait rw
|
||||
|
||||
@@ -19,7 +19,10 @@ initrd_addr=0x93800000
|
||||
emmc_dev=0
|
||||
sd_dev=1
|
||||
scriptaddr=0x93500000
|
||||
ip_dyn=yes
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
kernel_comp_addr_r=0xC0000000
|
||||
kernel_comp_size=0x2000000
|
||||
image=Image
|
||||
splashimage=0xA0000000
|
||||
console=ttyLP0,115200 earlycon
|
||||
|
||||
@@ -52,7 +52,10 @@ initrd_addr=0x93800000
|
||||
emmc_dev=0
|
||||
sd_dev=1
|
||||
scriptaddr=0x93500000
|
||||
ip_dyn=yes
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
kernel_comp_addr_r=0xC0000000
|
||||
kernel_comp_size=0x2000000
|
||||
image=Image
|
||||
splashimage=0xA0000000
|
||||
console=ttyLP0,115200 earlycon
|
||||
|
||||
@@ -3,8 +3,11 @@ initrd_addr=0x93800000
|
||||
emmc_dev=0
|
||||
sd_dev=1
|
||||
scriptaddr=0x93500000
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
image=Image
|
||||
ip_dyn=yes
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
kernel_comp_addr_r=0xC0000000
|
||||
kernel_comp_size=0x2000000
|
||||
splashimage=0xA0000000
|
||||
console=ttyLP0,115200 earlycon
|
||||
fdt_addr_r=0x93000000
|
||||
|
||||
@@ -0,0 +1,5 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
|
||||
console=ttymxc3
|
||||
|
||||
#include <env/nxp/mx6sabre_common.env>
|
||||
@@ -0,0 +1,5 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
|
||||
console=ttymxc0
|
||||
|
||||
#include <env/nxp/mx6sabre_common.env>
|
||||
@@ -0,0 +1,69 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
|
||||
script=boot.scr
|
||||
image=zImage
|
||||
console=ttymxc0
|
||||
initrd_high=0xffffffff
|
||||
fdt_file=undefined
|
||||
fdt_addr=0x83000000
|
||||
boot_fdt=try
|
||||
ip_dyn=yes
|
||||
videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0
|
||||
mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
|
||||
mmcpart=1
|
||||
mmcroot=/dev/mmcblk1p2 rootwait rw
|
||||
mmcautodetect=yes
|
||||
mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}
|
||||
loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
|
||||
bootscript=echo Running bootscript from mmc ...; source
|
||||
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
|
||||
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
|
||||
mmcboot=echo Booting from mmc ...;
|
||||
run mmcargs;
|
||||
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
|
||||
if run loadfdt; then
|
||||
bootz ${loadaddr} - ${fdt_addr};
|
||||
else
|
||||
if test ${boot_fdt} = try; then
|
||||
bootz;
|
||||
else
|
||||
echo WARN: Cannot load the DT;
|
||||
fi;
|
||||
fi;
|
||||
else
|
||||
bootz;
|
||||
fi;
|
||||
findfdt=if test $fdt_file = undefined; then
|
||||
if test $board_name = ULZ-EVK && test $board_rev = 14X14; then
|
||||
setenv fdt_file imx6ulz-14x14-evk.dtb;
|
||||
fi;
|
||||
if test $board_name = EVK && test $board_rev = 14X14; then
|
||||
setenv fdt_file imx6ull-14x14-evk.dtb;
|
||||
fi;
|
||||
if test $fdt_file = undefined; then
|
||||
echo WARNING: Could not determine dtb to use;
|
||||
fi;
|
||||
fi;
|
||||
netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs
|
||||
ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
|
||||
netboot=echo Booting from net ...;
|
||||
run netargs;
|
||||
if test ${ip_dyn} = yes; then
|
||||
setenv get_cmd dhcp;
|
||||
else
|
||||
setenv get_cmd tftp;
|
||||
fi;
|
||||
${get_cmd} ${image};
|
||||
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
|
||||
if ${get_cmd} ${fdt_addr} ${fdt_file}; then
|
||||
bootz ${loadaddr} - ${fdt_addr};
|
||||
else
|
||||
if test ${boot_fdt} = try; then
|
||||
bootz;
|
||||
else
|
||||
echo WARN: Cannot load the DT;
|
||||
fi;
|
||||
fi;
|
||||
else
|
||||
bootz;
|
||||
fi;
|
||||
@@ -0,0 +1,59 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
|
||||
script=boot.scr
|
||||
image=zImage
|
||||
console=ttyLP0
|
||||
initrd_high=0xffffffff
|
||||
fdt_file=imx7ulp-evk.dtb
|
||||
fdt_addr=0x63000000
|
||||
boot_fdt=try
|
||||
earlycon=lpuart32,0x402D0010
|
||||
ip_dyn=yes
|
||||
mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
|
||||
mmcpart=1
|
||||
mmcroot=/dev/mmcblk0p2 rootwait rw
|
||||
mmcautodetect=yes
|
||||
mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}
|
||||
loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
|
||||
bootscript=echo Running bootscript from mmc ...; source
|
||||
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
|
||||
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
|
||||
mmcboot=echo Booting from mmc ...;
|
||||
run mmcargs;
|
||||
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
|
||||
if run loadfdt; then
|
||||
bootz ${loadaddr} - ${fdt_addr};
|
||||
else
|
||||
if test ${boot_fdt} = try; then
|
||||
bootz;
|
||||
else
|
||||
echo WARN: Cannot load the DT;
|
||||
fi;
|
||||
fi;
|
||||
else
|
||||
bootz;
|
||||
fi;
|
||||
netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs
|
||||
ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
|
||||
netboot=echo Booting from net ...;
|
||||
run netargs;
|
||||
if test ${ip_dyn} = yes; then
|
||||
setenv get_cmd dhcp;
|
||||
else
|
||||
setenv get_cmd tftp;
|
||||
fi;
|
||||
usb start;
|
||||
${get_cmd} ${image};
|
||||
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
|
||||
if ${get_cmd} ${fdt_addr} ${fdt_file}; then
|
||||
bootz ${loadaddr} - ${fdt_addr};
|
||||
else
|
||||
if test ${boot_fdt} = try; then
|
||||
bootz;
|
||||
else
|
||||
echo WARN: Cannot load the DT;
|
||||
fi;
|
||||
fi;
|
||||
else
|
||||
bootz;
|
||||
fi;
|
||||
@@ -0,0 +1,36 @@
|
||||
if TARGET_AQUILA_IMX95
|
||||
|
||||
config SYS_BOARD
|
||||
default "aquila-imx95"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "toradex"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "aquila-imx95"
|
||||
|
||||
config TDX_CFG_BLOCK
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_2ND_ETHADDR
|
||||
default y
|
||||
|
||||
config TDX_CFG_BLOCK_DEV
|
||||
default "0"
|
||||
|
||||
# Toradex config block in eMMC, at the end of 1st "boot sector"
|
||||
config TDX_CFG_BLOCK_OFFSET
|
||||
default "-512"
|
||||
|
||||
config TDX_CFG_BLOCK_PART
|
||||
default "1"
|
||||
|
||||
config TDX_HAVE_EEPROM_EXTRA
|
||||
default y
|
||||
|
||||
config TDX_HAVE_MMC
|
||||
default y
|
||||
|
||||
source "board/toradex/common/Kconfig"
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,11 @@
|
||||
Aquila iMX95
|
||||
F: arch/arm/dts/imx95-aquila.dtsi
|
||||
F: arch/arm/dts/imx95-aquila-dev.dts
|
||||
F: arch/arm/dts/imx95-aquila-dev-u-boot.dtsi
|
||||
F: board/toradex/aquila-imx95/
|
||||
F: configs/aquila-imx95_defconfig
|
||||
F: doc/board/toradex/aquila-imx95.rst
|
||||
F: include/configs/aquila-imx95.h
|
||||
M: Francesco Dolcini <francesco.dolcini@toradex.com>
|
||||
S: Maintained
|
||||
W: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
|
||||
@@ -0,0 +1,8 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# Copyright (c) Toradex
|
||||
|
||||
obj-y += aquila-imx95.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
endif
|
||||
@@ -0,0 +1,23 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/* Copyright (c) Toradex */
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <fdt_support.h>
|
||||
#include <init.h>
|
||||
|
||||
#include "../common/tdx-cfg-block.h"
|
||||
|
||||
int board_phys_sdram_size(phys_size_t *size)
|
||||
{
|
||||
*size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
return ft_common_board_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,20 @@
|
||||
boot_scripts=boot.scr
|
||||
boot_script_dhcp=boot.scr
|
||||
boot_targets=mmc1 mmc0 dhcp
|
||||
console=ttyLP2
|
||||
fdt_board=dev
|
||||
fdt_addr=0x9c400000
|
||||
fdt_addr_r=0x9c400000
|
||||
kernel_addr_r=CONFIG_SYS_LOAD_ADDR
|
||||
kernel_comp_addr_r=0x94400000
|
||||
kernel_comp_size=0x8000000
|
||||
ramdisk_addr_r=0x9c800000
|
||||
scriptaddr=0x9c600000
|
||||
|
||||
update_uboot=
|
||||
askenv confirm Did you load flash.bin (y/N)?;
|
||||
if test "$confirm" = y; then
|
||||
setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt
|
||||
${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0
|
||||
${blkcnt};
|
||||
fi
|
||||
@@ -0,0 +1,75 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/* Copyright (c) Toradex */
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/mu.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/ele_api.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <clk.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <hang.h>
|
||||
#include <i2c.h>
|
||||
#include <init.h>
|
||||
#include <spl.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
{
|
||||
switch (boot_dev_spl) {
|
||||
case SD1_BOOT:
|
||||
case MMC1_BOOT:
|
||||
return BOOT_DEVICE_MMC1;
|
||||
case SD2_BOOT:
|
||||
case MMC2_BOOT:
|
||||
return BOOT_DEVICE_MMC2;
|
||||
case USB_BOOT:
|
||||
return BOOT_DEVICE_BOARD;
|
||||
default:
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ele_start_rng();
|
||||
if (ret)
|
||||
printf("Fail to start RNG: %d\n", ret);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION))
|
||||
spl_save_restore_data();
|
||||
|
||||
timer_init();
|
||||
|
||||
/* Need dm_init() to run before any SCMI calls */
|
||||
spl_early_init();
|
||||
|
||||
/* Need to enable SCMI drivers and ELE driver before console */
|
||||
ret = imx9_probe_mu();
|
||||
if (ret)
|
||||
hang(); /* MU not probed, nothing can be outputed, hang */
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
debug("SOC: 0x%x\n", gd->arch.soc_rev);
|
||||
debug("LC: 0x%x\n", gd->arch.lifecycle);
|
||||
|
||||
get_reset_reason(true, false);
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
@@ -0,0 +1,186 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX9=y
|
||||
CONFIG_TEXT_BASE=0x90200000
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xFFFFDE00
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx95-aquila-dev"
|
||||
CONFIG_TARGET_AQUILA_IMX95=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SYS_MONITOR_LEN=524288
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL_STACK=0x204d6000
|
||||
CONFIG_SPL_TEXT_BASE=0x20480000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x204d6000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
CONFIG_SYS_LOAD_ADDR=0x90400000
|
||||
CONFIG_WATCHDOG_TIMEOUT_MSECS=30000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_RECOVER_DATA_SECTION=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SYS_MEMTEST_START=0x90000000
|
||||
CONFIG_SYS_MEMTEST_END=0xA0000000
|
||||
CONFIG_REMAKE_ELF=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_BOOTSTD_FULL=y
|
||||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="bootflow scan -b"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_PREBOOT="test -n \"${fdtfile}\" || setenv fdtfile imx95-aquila-${fdt_board}.dtb"
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_PBSIZE=2074
|
||||
CONFIG_LOG=y
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
# CONFIG_BOARD_INIT is not set
|
||||
CONFIG_PCI_INIT_R=y
|
||||
CONFIG_SPL_MAX_SIZE=0x30000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_LOAD_IMX_CONTAINER=y
|
||||
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/scmi/container.cfg"
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_HAVE_INIT_STACK=y
|
||||
CONFIG_SPL_SYS_MALLOC=y
|
||||
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
|
||||
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000
|
||||
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
|
||||
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_THERMAL=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SYS_PROMPT="Aquila iMX95 # "
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_NVEDIT_EFI=y
|
||||
CONFIG_CRC32_VERIFY=y
|
||||
CONFIG_CMD_MD5SUM=y
|
||||
CONFIG_MD5SUM_VERIFY=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_REMOTEPROC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_SDP=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_BOOTCOUNT=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_SYSBOOT=y
|
||||
CONFIG_CMD_UUID=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_HASH=y
|
||||
CONFIG_CMD_SCMI=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_MMC_EMMC_HW_PARTITION=1
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_USE_ETHPRIME=y
|
||||
CONFIG_ETHPRIME="eth0"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_PROT_UDP=y
|
||||
CONFIG_IP_DEFRAG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_TFTP_BLOCKSIZE=4096
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_BOOTCOUNT_ENV=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_SPL_CLK_CCF=y
|
||||
CONFIG_CLK_CCF=y
|
||||
CONFIG_CLK_SCMI=y
|
||||
CONFIG_SPL_CLK_SCMI=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x90400000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_UUU_SUPPORT=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_SPL_FIRMWARE=y
|
||||
# CONFIG_SCMI_AGENT_SMCCC is not set
|
||||
CONFIG_IMX_SM_CPU=y
|
||||
CONFIG_IMX_SM_LMM=y
|
||||
CONFIG_IMX_RGPIO2P=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_SPL_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||
CONFIG_IMX_MU_MBOX=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_FSL_ENETC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_TI_DP83867=y
|
||||
CONFIG_PCIE_ECAM_GENERIC=y
|
||||
CONFIG_PHY_IMX8MQ_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX_SCMI=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_SCMI_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_REMOTEPROC_IMX=y
|
||||
CONFIG_DM_RNG=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_SPL_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_SPL_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
|
||||
CONFIG_USB_GADGET_OS_DESCRIPTORS=y
|
||||
CONFIG_SDP_LOADADDR=0x90400000
|
||||
CONFIG_SPL_USB_SDP_SUPPORT=y
|
||||
CONFIG_ULP_WATCHDOG=y
|
||||
CONFIG_WDT=y
|
||||
# CONFIG_SPL_SHA1 is not set
|
||||
CONFIG_LZO=y
|
||||
@@ -136,7 +136,6 @@ CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_TPM2_TIS_SPI=y
|
||||
CONFIG_TPM2_FTPM_TEE=y
|
||||
CONFIG_USB=y
|
||||
|
||||
@@ -139,7 +139,6 @@ CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_TPM2_TIS_SPI=y
|
||||
CONFIG_TPM2_FTPM_TEE=y
|
||||
CONFIG_USB=y
|
||||
|
||||
@@ -88,4 +88,3 @@ CONFIG_MXC_UART=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
|
||||
@@ -88,4 +88,3 @@ CONFIG_MXC_UART=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
|
||||
@@ -149,7 +149,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_SPL_USB_HOST=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -105,5 +105,4 @@ CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
|
||||
@@ -135,7 +135,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_SPL_USB_HOST=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -133,7 +133,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_SPL_USB_HOST=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -18,7 +18,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x910000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40400000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_EFI_MM_COMM_TEE=y
|
||||
CONFIG_EFI_VAR_BUF_SIZE=139264
|
||||
@@ -71,6 +71,7 @@ CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
|
||||
@@ -120,7 +121,6 @@ CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_SPL_USB_HOST=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -21,7 +21,7 @@ CONFIG_SPL_TEXT_BASE=0x7E2000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x910000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40400000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
@@ -59,6 +59,7 @@ CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
|
||||
@@ -107,7 +108,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
CONFIG_FSPI_CONF_HEADER=y
|
||||
CONFIG_FSPI_CONF_FILE="fspi_header.bin"
|
||||
|
||||
@@ -103,7 +103,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_SPL_USB_HOST=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -157,7 +157,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
# CONFIG_TPM_V1 is not set
|
||||
CONFIG_TPM2_TIS_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
||||
@@ -131,7 +131,6 @@ CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -138,7 +138,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -137,7 +137,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -62,6 +62,7 @@ CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_REDUNDANT=y
|
||||
@@ -97,7 +98,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -80,6 +80,7 @@ CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_REDUNDANT=y
|
||||
@@ -126,6 +127,5 @@ CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
CONFIG_SHA384=y
|
||||
|
||||
@@ -152,7 +152,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
# CONFIG_TPM_V1 is not set
|
||||
CONFIG_TPM2_TIS_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
||||
@@ -152,7 +152,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_TPM2_TIS_SPI=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
|
||||
@@ -19,7 +19,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x98fc00
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x400
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40600000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x20400
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
|
||||
@@ -75,6 +75,7 @@ CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_REDUNDANT=y
|
||||
|
||||
@@ -159,7 +159,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_SYS_WHITE_ON_BLACK=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
|
||||
@@ -160,7 +160,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_SYS_WHITE_ON_BLACK=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
|
||||
@@ -157,7 +157,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
# CONFIG_TPM_V1 is not set
|
||||
CONFIG_TPM2_TIS_SPI=y
|
||||
CONFIG_USB=y
|
||||
|
||||
@@ -94,6 +94,5 @@ CONFIG_MXC_UART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
CONFIG_WDT=y
|
||||
|
||||
@@ -19,7 +19,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x180000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40400000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x204000
|
||||
CONFIG_IMX_BOOTAUX=y
|
||||
@@ -70,6 +70,7 @@ CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_REDUNDANT=y
|
||||
@@ -107,7 +108,6 @@ CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
|
||||
@@ -93,4 +93,3 @@ CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
|
||||
@@ -93,7 +93,6 @@ CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
|
||||
@@ -35,7 +35,7 @@ CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd"
|
||||
CONFIG_DEFAULT_FDT_FILE="freescale/imx952-evk.dtb"
|
||||
CONFIG_DEFAULT_FDT_FILE="imx952-evk.dtb"
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_PBSIZE=2074
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
|
||||
@@ -192,7 +192,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_SPL_USB_HOST=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
@@ -210,5 +209,4 @@ CONFIG_SDP_LOADADDR=0x40400000
|
||||
CONFIG_USB_ETHER=y
|
||||
CONFIG_USB_ETH_CDC=y
|
||||
CONFIG_SPL_USB_SDP_SUPPORT=y
|
||||
# CONFIG_WATCHDOG_AUTOSTART is not set
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
|
||||
@@ -106,7 +106,6 @@ CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_RV8803=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
|
||||
@@ -130,7 +130,6 @@ CONFIG_MXC_UART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MXC_SPI=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
||||
@@ -131,5 +131,4 @@ CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
|
||||
@@ -162,7 +162,6 @@ CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
||||
@@ -91,4 +91,3 @@ CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
|
||||
@@ -160,7 +160,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
|
||||
@@ -145,7 +145,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_SPL_USB_HOST=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
||||
@@ -162,7 +162,6 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
|
||||
@@ -0,0 +1,175 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
Toradex Aquila iMX95 Module
|
||||
===========================
|
||||
|
||||
- SoM: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
|
||||
- Carrier board: https://www.toradex.com/products/carrier-board/aquila-development-board-kit
|
||||
|
||||
Quick Start
|
||||
-----------
|
||||
|
||||
- Setup environment
|
||||
- Get ahab-container.img
|
||||
- Get DDR PHY Firmware Images
|
||||
- Get and Build OEI Images
|
||||
- Get and Build System Manager Image
|
||||
- Get and Build the ARM Trusted Firmware
|
||||
- Build the Bootloader Image
|
||||
- Boot
|
||||
|
||||
Setup environment
|
||||
-----------------
|
||||
|
||||
Suggested current toolchains are ARM 14.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads):
|
||||
|
||||
- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz
|
||||
- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
$ export TOOLS=<path/to/directory/with/toolchains>
|
||||
$ export CROSS_COMPILE_32=<path/to/arm/toolchain/bin/>arm-none-linux-gnueabihf-
|
||||
$ export CROSS_COMPILE_64=<path/to/arm64/toolchain/bin/>aarch64-none-linux-gnu-
|
||||
|
||||
Get ahab-container.img
|
||||
----------------------
|
||||
|
||||
Note: `$srctree` is the U-Boot source directory
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin
|
||||
$ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept
|
||||
$ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree)
|
||||
|
||||
Get DDR PHY Firmware Images
|
||||
---------------------------
|
||||
|
||||
Note: `$srctree` is the U-Boot source directory
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin
|
||||
$ sh firmware-imx-8.28-994fa14.bin --auto-accept
|
||||
$ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree)
|
||||
|
||||
Get and Build OEI Images
|
||||
------------------------
|
||||
|
||||
Note: `$srctree` is the U-Boot source directory
|
||||
Get OEI from: https://git.toradex.com/cgit/imx-oei-toradex.git/
|
||||
branch: main
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
$ git clone -b main https://git.toradex.com/cgit/imx-oei-toradex.git/
|
||||
$ cd imx-oei-toradex
|
||||
|
||||
$ make board=toradex-aquila-imx95 oei=ddr DEBUG=1 r=B0 all
|
||||
$ cp build/toradex-aquila-imx95/ddr/oei-m33-ddr.bin $(srctree)
|
||||
|
||||
$ make board=toradex-aquila-imx95 oei=tcm DEBUG=1 r=B0 all
|
||||
$ cp build/toradex-aquila-imx95/tcm/oei-m33-tcm.bin $(srctree)
|
||||
|
||||
The Makefile will set `DDR_CONFIG` automatically based on the selected silicon
|
||||
revision.
|
||||
|
||||
Get and Build the System Manager Image
|
||||
--------------------------------------
|
||||
|
||||
Note: `$srctree` is the U-Boot source directory
|
||||
Get System Manager from: https://git.toradex.com/cgit/imx-sm-toradex.git/
|
||||
branch: main
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
$ git clone -b main https://git.toradex.com/cgit/imx-sm-toradex.git/
|
||||
$ cd imx-sm-toradex
|
||||
$ make config=aquila-imx95 all
|
||||
$ cp build/aquila-imx95/m33_image.bin $(srctree)
|
||||
|
||||
Get and Build the ARM Trusted Firmware
|
||||
--------------------------------------
|
||||
|
||||
Note: `$srctree` is the U-Boot source directory
|
||||
Get ATF from: https://github.com/nxp-imx/imx-atf/
|
||||
branch: lf_v2.12
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
$ export CROSS_COMPILE=$CROSS_COMPILE_64
|
||||
$ unset LDFLAGS
|
||||
$ unset AS
|
||||
$ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git
|
||||
$ cd imx-atf
|
||||
$ make PLAT=imx95 bl31
|
||||
$ cp build/imx95/release/bl31.bin $(srctree)
|
||||
|
||||
Build the Bootloader Image
|
||||
--------------------------
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
$ export CROSS_COMPILE=$CROSS_COMPILE_64
|
||||
$ make aquila-imx95_defconfig
|
||||
$ make
|
||||
|
||||
Flash to eMMC
|
||||
-------------
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
> tftpboot ${loadaddr} flash.bin
|
||||
> setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
|
||||
> mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt}
|
||||
|
||||
As a convenience, instead of the last two commands, one may also use the update
|
||||
U-Boot wrapper:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
> run update_uboot
|
||||
|
||||
Boot
|
||||
----
|
||||
|
||||
Boot sequence is:
|
||||
|
||||
* SPL ---> ATF (TF-A) ---> U-Boot proper
|
||||
|
||||
Output:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
U-Boot SPL 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200)
|
||||
SYS Boot reason: por, origin: -1, errid: -1
|
||||
WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout)
|
||||
Trying to boot from MMC1
|
||||
Load image from MMC/SD 0xd2800
|
||||
NOTICE: BL31: v2.10.0 (release):lf-6.6.52-2.2.1-dirty
|
||||
NOTICE: BL31: Built : 06:40:36, Jul 7 2025
|
||||
|
||||
|
||||
U-Boot 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200)
|
||||
|
||||
CPU: NXP i.MX95 Rev2.0 A55 at 1800 MHz - invalid sensor data
|
||||
DRAM: 7.8 GiB
|
||||
Core: 321 devices, 30 uclasses, devicetree: separate
|
||||
WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout)
|
||||
MMC: FSL_SDHC: 0, FSL_SDHC: 1
|
||||
Loading Environment from MMC... Reading from MMC(0)... OK
|
||||
In: serial@44380000
|
||||
Out: serial@44380000
|
||||
Err: serial@44380000
|
||||
Model: Toradex 0098 Aquila iMX95 Hexa 8GB WB IT V1.0A
|
||||
Serial#: 12594391
|
||||
|
||||
BuildInfo:
|
||||
- ELE firmware version 2.0.2-c110ba4b
|
||||
|
||||
Net: WARNING: no MAC address assigned for MAC0
|
||||
imx_get_mac_from_fuse: fuse read err: 0
|
||||
eth0: enetc-0 [PRIME]
|
||||
Hit any key to stop autoboot: 0
|
||||
Aquila iMX95 #
|
||||
@@ -8,6 +8,7 @@ Toradex
|
||||
|
||||
apalis-imx8
|
||||
aquila-am69
|
||||
aquila-imx95
|
||||
colibri_imx7
|
||||
colibri-imx8x
|
||||
smarc-imx8mp
|
||||
|
||||
@@ -228,18 +228,28 @@ static struct clk *_register_divider(struct udevice *dev, const char *name,
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *clk_register_divider_table(struct udevice *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_divider_flags, const struct clk_div_table *table)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
clk = _register_divider(dev, name, parent_name, flags, reg, shift,
|
||||
width, clk_divider_flags, table);
|
||||
if (IS_ERR(clk))
|
||||
return ERR_CAST(clk);
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *clk_register_divider(struct udevice *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_divider_flags)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
clk = _register_divider(dev, name, parent_name, flags, reg, shift,
|
||||
width, clk_divider_flags, NULL);
|
||||
if (IS_ERR(clk))
|
||||
return ERR_CAST(clk);
|
||||
return clk;
|
||||
return clk_register_divider_table(dev, name, parent_name, flags, reg,
|
||||
shift, width, clk_divider_flags,
|
||||
NULL);
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(ccf_clk_divider) = {
|
||||
|
||||
+236
-19
@@ -9,6 +9,7 @@
|
||||
#include <log.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <dm/of_access.h>
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
#include "clk.h"
|
||||
@@ -46,6 +47,33 @@ static struct clk_ops imx6q_clk_ops = {
|
||||
.disable = ccf_clk_disable,
|
||||
};
|
||||
|
||||
static const char *const pll_bypass_src_sels[] = {
|
||||
"osc",
|
||||
"lvds1_in",
|
||||
"lvds2_in",
|
||||
"dummy",
|
||||
};
|
||||
|
||||
static const char *const pll2_bypass_sels[] = {
|
||||
"pll2",
|
||||
"pll2_bypass_src",
|
||||
};
|
||||
|
||||
static const char *const pll3_bypass_sels[] = {
|
||||
"pll3",
|
||||
"pll3_bypass_src",
|
||||
};
|
||||
|
||||
static const char *const pll5_bypass_sels[] = {
|
||||
"pll5",
|
||||
"pll5_bypass_src",
|
||||
};
|
||||
|
||||
static const char *const pll6_bypass_sels[] = {
|
||||
"pll6",
|
||||
"pll6_bypass_src",
|
||||
};
|
||||
|
||||
static const char *const usdhc_sels[] = {
|
||||
"pll2_pfd2_396m",
|
||||
"pll2_pfd0_352m",
|
||||
@@ -72,6 +100,23 @@ static const char *const ecspi_sels[] = {
|
||||
"pll3_60m",
|
||||
"osc",
|
||||
};
|
||||
|
||||
static const struct clk_div_table post_div_table[] = {
|
||||
{ .val = 2, .div = 1, },
|
||||
{ .val = 1, .div = 2, },
|
||||
{ .val = 0, .div = 4, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct clk_div_table video_div_table[] = {
|
||||
{ .val = 0, .div = 1, },
|
||||
{ .val = 1, .div = 2, },
|
||||
{ .val = 2, .div = 1, },
|
||||
{ .val = 3, .div = 4, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(VIDEO)
|
||||
static const char *const ipu_sels[] = {
|
||||
"mmdc_ch0_axi",
|
||||
"pll2_pfd2_396m",
|
||||
@@ -113,6 +158,122 @@ static const char *ipu2_di1_sels_2[] = {
|
||||
|
||||
static unsigned int share_count_mipi_core_cfg;
|
||||
|
||||
static void of_assigned_ldb_sels(struct udevice *dev, int *ldb_di0_sel,
|
||||
int *ldb_di1_sel)
|
||||
{
|
||||
struct ofnode_phandle_args clk_args, parent_args;
|
||||
ofnode node = dev_ofnode(dev);
|
||||
int count, err;
|
||||
|
||||
count = dev_count_phandle_with_args(dev, "assigned-clocks",
|
||||
"#clock-cells", 0);
|
||||
if (count <= 0) {
|
||||
if (count == 0)
|
||||
debug("%s: no assigned_clocks found\n", dev->name);
|
||||
else
|
||||
pr_err("%s: failed to get phandle count (%d)\n",
|
||||
dev->name, count);
|
||||
return;
|
||||
}
|
||||
|
||||
for (int i = 0; i < count; i++) {
|
||||
err = dev_read_phandle_with_args(dev, "assigned-clocks",
|
||||
"#clock-cells", 0, i,
|
||||
&clk_args);
|
||||
if (err == -ENOENT)
|
||||
/* Skip empty handles */
|
||||
continue;
|
||||
else if (err < 0)
|
||||
return;
|
||||
|
||||
if (!ofnode_equal(clk_args.node, node) ||
|
||||
clk_args.args[0] >= IMX6QDL_CLK_END) {
|
||||
pr_err("%s: clock %d not in ccm\n", dev->name, i);
|
||||
return;
|
||||
}
|
||||
|
||||
err = dev_read_phandle_with_args(dev, "assigned-clock-parents",
|
||||
"#clock-cells", 0, i,
|
||||
&parent_args);
|
||||
if (err < 0)
|
||||
return;
|
||||
|
||||
if (!ofnode_equal(parent_args.node, node) ||
|
||||
parent_args.args[0] >= IMX6QDL_CLK_END) {
|
||||
pr_err("%s: parent clock %d not in ccm\n", dev->name,
|
||||
i);
|
||||
return;
|
||||
}
|
||||
|
||||
if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI0_SEL)
|
||||
*ldb_di0_sel = parent_args.args[0];
|
||||
else if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI1_SEL)
|
||||
*ldb_di1_sel = parent_args.args[0];
|
||||
}
|
||||
}
|
||||
|
||||
static void imx6q_init_ldb_clks(struct udevice *dev)
|
||||
{
|
||||
int ldb_di_sel[] = { IMX6QDL_CLK_END, IMX6QDL_CLK_END };
|
||||
enum ldb_di_clock ldb_di_clk[] = { MXC_MMDC_CH1_CLK, MXC_MMDC_CH1_CLK };
|
||||
|
||||
of_assigned_ldb_sels(dev, &ldb_di_sel[0], &ldb_di_sel[1]);
|
||||
for (int i = 0; i < 2; i++) {
|
||||
switch (ldb_di_sel[i]) {
|
||||
case IMX6QDL_CLK_PLL5_VIDEO_DIV:
|
||||
ldb_di_clk[i] = MXC_PLL5_CLK;
|
||||
break;
|
||||
case IMX6QDL_CLK_PLL2_PFD0_352M:
|
||||
ldb_di_clk[i] = MXC_PLL2_PFD0_CLK;
|
||||
break;
|
||||
case IMX6QDL_CLK_PLL2_PFD2_396M: {
|
||||
struct clk *clk, *parent;
|
||||
|
||||
int err = clk_get_by_id(IMX6QDL_CLK_PERIPH_PRE, &clk);
|
||||
|
||||
if (err) {
|
||||
pr_err("%s: failed to get periph_pre clock "
|
||||
"(%d)\n",
|
||||
dev->name, err);
|
||||
return;
|
||||
}
|
||||
|
||||
err = clk_get_by_id(IMX6QDL_CLK_PLL2_PFD2_396M,
|
||||
&parent);
|
||||
if (err) {
|
||||
pr_err("%s: failed to get pll2_pfd2_396m clock"
|
||||
" (%d)\n",
|
||||
dev->name, err);
|
||||
return;
|
||||
}
|
||||
|
||||
if (parent == clk) {
|
||||
pr_err("%s: ldb_di%d_sel: couldn't disable "
|
||||
"pll2_pfd2_396m clock\n",
|
||||
dev->name, i);
|
||||
return;
|
||||
}
|
||||
|
||||
ldb_di_clk[i] = MXC_PLL2_PFD2_CLK;
|
||||
break;
|
||||
}
|
||||
case IMX6QDL_CLK_MMDC_CH1_AXI:
|
||||
case IMX6QDL_CLK_END:
|
||||
/* use the default clock */
|
||||
break;
|
||||
case IMX6QDL_CLK_PLL3_USB_OTG:
|
||||
ldb_di_clk[i] = MXC_PLL3_SW_CLK;
|
||||
break;
|
||||
default:
|
||||
pr_err("%s: invalid LDB clock parent\n", dev->name);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
select_ldb_di_clock_source(ldb_di_clk[0], ldb_di_clk[1]);
|
||||
}
|
||||
#endif /* CONFIG_IS_ENABLED(VIDEO) */
|
||||
|
||||
static int imx6q_clk_probe(struct udevice *dev)
|
||||
{
|
||||
void *base;
|
||||
@@ -120,26 +281,70 @@ static int imx6q_clk_probe(struct udevice *dev)
|
||||
/* Anatop clocks */
|
||||
base = (void *)ANATOP_BASE_ADDR;
|
||||
|
||||
clk_dm(IMX6QDL_CLK_PLL2,
|
||||
imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc",
|
||||
base + 0x30, 0x1));
|
||||
clk_dm(IMX6QDL_PLL2_BYPASS_SRC,
|
||||
imx_clk_mux(dev, "pll2_bypass_src", base + 0x30, 14, 2,
|
||||
pll_bypass_src_sels,
|
||||
ARRAY_SIZE(pll_bypass_src_sels)));
|
||||
clk_dm(IMX6QDL_PLL3_BYPASS_SRC,
|
||||
imx_clk_mux(dev, "pll3_bypass_src", base + 0x10, 14, 2,
|
||||
pll_bypass_src_sels,
|
||||
ARRAY_SIZE(pll_bypass_src_sels)));
|
||||
clk_dm(IMX6QDL_PLL5_BYPASS_SRC,
|
||||
imx_clk_mux(dev, "pll5_bypass_src", base + 0xa0, 14, 2,
|
||||
pll_bypass_src_sels,
|
||||
ARRAY_SIZE(pll_bypass_src_sels)));
|
||||
clk_dm(IMX6QDL_PLL6_BYPASS_SRC,
|
||||
imx_clk_mux(dev, "pll6_bypass_src", base + 0xe0, 14, 2,
|
||||
pll_bypass_src_sels,
|
||||
ARRAY_SIZE(pll_bypass_src_sels)));
|
||||
|
||||
clk_dm(IMX6QDL_CLK_PLL2, imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2",
|
||||
"osc", base + 0x30, 0x1));
|
||||
clk_dm(IMX6QDL_CLK_PLL3, imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3",
|
||||
"osc", base + 0x10, 0x3));
|
||||
clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc",
|
||||
base + 0xa0, 0x7f));
|
||||
clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6",
|
||||
"osc", base + 0xe0, 0x3));
|
||||
|
||||
clk_dm(IMX6QDL_PLL2_BYPASS,
|
||||
imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1,
|
||||
pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels),
|
||||
CLK_SET_RATE_PARENT));
|
||||
clk_dm(IMX6QDL_PLL3_BYPASS,
|
||||
imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1,
|
||||
pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels),
|
||||
CLK_SET_RATE_PARENT));
|
||||
clk_dm(IMX6QDL_PLL5_BYPASS,
|
||||
imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1,
|
||||
pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels),
|
||||
CLK_SET_RATE_PARENT));
|
||||
clk_dm(IMX6QDL_PLL6_BYPASS,
|
||||
imx_clk_mux_flags(dev, "pll6_bypass", base + 0xe0, 16, 1,
|
||||
pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels),
|
||||
CLK_SET_RATE_PARENT));
|
||||
|
||||
SET_CLK_PARENT(IMX6QDL_PLL2_BYPASS, IMX6QDL_CLK_PLL2);
|
||||
SET_CLK_PARENT(IMX6QDL_PLL3_BYPASS, IMX6QDL_CLK_PLL3);
|
||||
SET_CLK_PARENT(IMX6QDL_PLL5_BYPASS, IMX6QDL_CLK_PLL5);
|
||||
SET_CLK_PARENT(IMX6QDL_PLL6_BYPASS, IMX6QDL_CLK_PLL6);
|
||||
|
||||
clk_dm(IMX6QDL_CLK_PLL2_BUS,
|
||||
imx_clk_gate(dev, "pll2_bus", "pll2_bypass", base + 0x30, 13));
|
||||
clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
|
||||
imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc",
|
||||
base + 0x10, 0x3));
|
||||
imx_clk_gate(dev, "pll3_usb_otg", "pll3_bypass", base + 0x10,
|
||||
13));
|
||||
clk_dm(IMX6QDL_CLK_PLL5_VIDEO,
|
||||
imx_clk_gate(dev, "pll5_video", "pll5_bypass", base + 0xa0, 13));
|
||||
clk_dm(IMX6QDL_CLK_PLL6_ENET,
|
||||
imx_clk_gate(dev, "pll6_enet", "pll6_bypass", base + 0xe0, 13));
|
||||
|
||||
clk_dm(IMX6QDL_CLK_PLL3_60M,
|
||||
imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8));
|
||||
clk_dm(IMX6QDL_CLK_PLL3_80M,
|
||||
imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6));
|
||||
clk_dm(IMX6QDL_CLK_PLL3_120M,
|
||||
imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4));
|
||||
clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc",
|
||||
base + 0xa0, 0x7f));
|
||||
clk_dm(IMX6QDL_CLK_PLL5_VIDEO,
|
||||
imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13));
|
||||
clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6",
|
||||
"osc", base + 0xe0, 0x3));
|
||||
clk_dm(IMX6QDL_CLK_PLL6_ENET,
|
||||
imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13));
|
||||
|
||||
clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
|
||||
imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
|
||||
@@ -151,10 +356,14 @@ static int imx6q_clk_probe(struct udevice *dev)
|
||||
clk_dm(IMX6QDL_CLK_PLL2_198M,
|
||||
imx_clk_fixed_factor(dev, "pll2_198m", "pll2_pfd2_396m", 1, 2));
|
||||
clk_dm(IMX6QDL_CLK_PLL5_POST_DIV,
|
||||
imx_clk_fixed_factor(dev, "pll5_post_div", "pll5_video", 1, 1));
|
||||
clk_register_divider_table(dev, "pll5_post_div", "pll5_video",
|
||||
CLK_SET_RATE_PARENT, base + 0xa0, 19,
|
||||
2, 0, post_div_table));
|
||||
clk_dm(IMX6QDL_CLK_PLL5_VIDEO_DIV,
|
||||
imx_clk_fixed_factor(dev, "pll5_video_div", "pll5_post_div", 1,
|
||||
1));
|
||||
clk_register_divider_table(dev, "pll5_video_div",
|
||||
"pll5_post_div", CLK_SET_RATE_PARENT,
|
||||
base + 0x170, 30, 2, 0,
|
||||
video_div_table));
|
||||
clk_dm(IMX6QDL_CLK_VIDEO_27M,
|
||||
imx_clk_fixed_factor(dev, "video_27m", "pll3_pfd1_540m", 1,
|
||||
20));
|
||||
@@ -263,6 +472,7 @@ static int imx6q_clk_probe(struct udevice *dev)
|
||||
imx_clk_gate2(dev, "mmdc_ch1_axi", "mmdc_ch1_axi_podf",
|
||||
base + 0x74, 22));
|
||||
|
||||
#if CONFIG_IS_ENABLED(VIDEO)
|
||||
clk_dm(IMX6QDL_CLK_IPU1_SEL,
|
||||
imx_clk_mux(dev, "ipu1_sel", base + 0x3c, 9, 2, ipu_sels,
|
||||
ARRAY_SIZE(ipu_sels)));
|
||||
@@ -279,9 +489,12 @@ static int imx6q_clk_probe(struct udevice *dev)
|
||||
ldb_di_sels, ARRAY_SIZE(ldb_di_sels)));
|
||||
} else {
|
||||
/*
|
||||
* Need to set these as read-only due to a hardware bug.
|
||||
* Keeping default mux values. Fixed on the i.MX6 QuadPlus
|
||||
*/
|
||||
* Need to set these as read-only due to a hardware bug.
|
||||
* Keeping default mux values. Fixed on the i.MX6 QuadPlus
|
||||
* Need to set the clocks now and make them read-only due to a
|
||||
* hardware bug. Fixed on the i.MX6 QuadPlus
|
||||
*/
|
||||
imx6q_init_ldb_clks(dev);
|
||||
clk_dm(IMX6QDL_CLK_LDB_DI0_SEL,
|
||||
imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3,
|
||||
ldb_di_sels, ARRAY_SIZE(ldb_di_sels),
|
||||
@@ -413,6 +626,7 @@ static int imx6q_clk_probe(struct udevice *dev)
|
||||
ARRAY_SIZE(ipu2_di1_sels),
|
||||
CLK_SET_RATE_PARENT));
|
||||
}
|
||||
#endif /* CONFIG_IS_ENABLED(VIDEO) */
|
||||
|
||||
clk_dm(IMX6QDL_CLK_ECSPI1,
|
||||
imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0));
|
||||
@@ -453,6 +667,8 @@ static int imx6q_clk_probe(struct udevice *dev)
|
||||
imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10));
|
||||
clk_dm(IMX6QDL_CLK_ENET_REF,
|
||||
imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1));
|
||||
|
||||
#if CONFIG_IS_ENABLED(VIDEO)
|
||||
clk_dm(IMX6QDL_CLK_MIPI_CORE_CFG,
|
||||
imx_clk_gate2_shared(dev, "mipi_core_cfg", "video_27m",
|
||||
base + 0x74, 16,
|
||||
@@ -480,6 +696,7 @@ static int imx6q_clk_probe(struct udevice *dev)
|
||||
SET_CLK_PARENT(IMX6QDL_CLK_IPU1_SEL,
|
||||
IMX6QDL_CLK_PLL3_PFD1_540M);
|
||||
}
|
||||
#endif /* CONFIG_IS_ENABLED(VIDEO) */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -194,11 +194,11 @@ static int imx_rgpio2p_bind(struct udevice *dev)
|
||||
dual_base = true;
|
||||
|
||||
if (dual_base) {
|
||||
addr = devfdt_get_addr_index(dev, 1);
|
||||
addr = dev_read_addr_index(dev, 1);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
} else {
|
||||
addr = devfdt_get_addr_index(dev, 0);
|
||||
addr = dev_read_addr_index(dev, 0);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
|
||||
@@ -795,6 +795,38 @@ int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_outp
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ele_v2x_get_state(struct v2x_get_state *state, u32 *response)
|
||||
{
|
||||
struct udevice *dev = gd->arch.ele_dev;
|
||||
int size = sizeof(struct ele_msg);
|
||||
struct ele_msg msg = {};
|
||||
int ret;
|
||||
|
||||
if (!dev) {
|
||||
printf("ele dev is not initialized\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
msg.version = ELE_VERSION;
|
||||
msg.tag = ELE_CMD_TAG;
|
||||
msg.size = 1;
|
||||
msg.command = ELE_V2X_GET_STATE_REQ;
|
||||
|
||||
ret = misc_call(dev, false, &msg, size, &msg, size);
|
||||
if (ret)
|
||||
printf("Error: %s: ret %d, response 0x%x\n",
|
||||
__func__, ret, msg.data[0]);
|
||||
|
||||
if (response)
|
||||
*response = msg.data[0];
|
||||
|
||||
state->v2x_state = msg.data[1] & 0xFF;
|
||||
state->v2x_power_state = (msg.data[1] & 0xFF00) >> 8;
|
||||
state->v2x_err_code = msg.data[2];
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ele_volt_change_start_req(void)
|
||||
{
|
||||
struct udevice *dev = gd->arch.ele_dev;
|
||||
|
||||
@@ -209,7 +209,7 @@ static int imx8ulp_mu_probe(struct udevice *dev)
|
||||
|
||||
debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
|
||||
|
||||
addr = devfdt_get_addr(dev);
|
||||
addr = dev_read_addr(dev);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
|
||||
@@ -519,8 +519,7 @@ static int lpuart_serial_probe(struct udevice *dev)
|
||||
static int lpuart_serial_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct lpuart_serial_plat *plat = dev_get_plat(dev);
|
||||
const void *blob = gd->fdt_blob;
|
||||
int node = dev_of_offset(dev);
|
||||
ofnode node = dev_ofnode(dev);
|
||||
fdt_addr_t addr;
|
||||
|
||||
addr = dev_read_addr(dev);
|
||||
@@ -530,18 +529,18 @@ static int lpuart_serial_of_to_plat(struct udevice *dev)
|
||||
plat->reg = (void *)addr;
|
||||
plat->flags = dev_get_driver_data(dev);
|
||||
|
||||
if (fdtdec_get_bool(blob, node, "little-endian"))
|
||||
if (ofnode_read_bool(node, "little-endian"))
|
||||
plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
|
||||
|
||||
if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
|
||||
if (ofnode_device_is_compatible(node, "fsl,ls1021a-lpuart"))
|
||||
plat->devtype = DEV_LS1021A;
|
||||
else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
|
||||
else if (ofnode_device_is_compatible(node, "fsl,imx7ulp-lpuart"))
|
||||
plat->devtype = DEV_MX7ULP;
|
||||
else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
|
||||
else if (ofnode_device_is_compatible(node, "fsl,vf610-lpuart"))
|
||||
plat->devtype = DEV_VF610;
|
||||
else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
|
||||
else if (ofnode_device_is_compatible(node, "fsl,imx8qm-lpuart"))
|
||||
plat->devtype = DEV_IMX8;
|
||||
else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
|
||||
else if (ofnode_device_is_compatible(node, "fsl,imxrt-lpuart"))
|
||||
plat->devtype = DEV_IMXRT;
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -136,7 +136,6 @@ struct ipu_ctx {
|
||||
|
||||
struct clk *ipu_clk;
|
||||
struct clk *ldb_clk;
|
||||
unsigned char ipu_clk_enabled;
|
||||
struct clk *di_clk[2];
|
||||
struct clk *pixel_clk[2];
|
||||
|
||||
|
||||
@@ -299,9 +299,9 @@ struct ipu_ctx *ipu_probe(struct udevice *dev)
|
||||
#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY)
|
||||
clk_set_parent(ctx->pixel_clk[0], ctx->ipu_clk);
|
||||
clk_set_parent(ctx->pixel_clk[1], ctx->ipu_clk);
|
||||
#endif
|
||||
|
||||
clk_enable(ctx->ipu_clk);
|
||||
#endif
|
||||
|
||||
for (int i = 0; i <= 1; i++) {
|
||||
ret = ipu_di_clk_init(ctx, i);
|
||||
@@ -384,10 +384,8 @@ int32_t ipu_init_channel(struct ipu_ctx *ctx, ipu_channel_t channel,
|
||||
|
||||
debug("init channel = %d\n", IPU_CHAN_ID(channel));
|
||||
|
||||
if (ctx->ipu_clk_enabled == 0) {
|
||||
ctx->ipu_clk_enabled = 1;
|
||||
if (!ipu_clk_enabled(ctx))
|
||||
clk_enable(ipu_clk);
|
||||
}
|
||||
|
||||
if (*channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
|
||||
printf("Warning: channel already initialized %d\n",
|
||||
@@ -543,7 +541,6 @@ void ipu_uninit_channel(struct ipu_ctx *ctx, ipu_channel_t channel)
|
||||
|
||||
if (ipu_conf == 0) {
|
||||
clk_disable(ctx->ipu_clk);
|
||||
ctx->ipu_clk_enabled = 0;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1045,5 +1042,9 @@ ipu_color_space_t format_to_colorspace(u32 fmt)
|
||||
|
||||
bool ipu_clk_enabled(struct ipu_ctx *ctx)
|
||||
{
|
||||
return ctx->ipu_clk_enabled;
|
||||
#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY)
|
||||
return clk_get_usecount(ctx->ipu_clk);
|
||||
#else
|
||||
return ctx->ipu_clk->enable_count;
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* Copyright (c) Toradex */
|
||||
|
||||
#ifndef __AQUILA_IMX95_H
|
||||
#define __AQUILA_IMX95_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CFG_SYS_UBOOT_BASE \
|
||||
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above */
|
||||
#define SZ_6G _AC(0x180000000, ULL)
|
||||
|
||||
/* first 256MB reserved for firmware */
|
||||
#define CFG_SYS_INIT_RAM_ADDR 0x90000000
|
||||
#define CFG_SYS_INIT_RAM_SIZE SZ_2M
|
||||
|
||||
#define CFG_SYS_SDRAM_BASE 0x90000000
|
||||
#define PHYS_SDRAM 0x90000000
|
||||
#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M)
|
||||
#define PHYS_SDRAM_2_SIZE SZ_6G
|
||||
|
||||
#define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */
|
||||
#define CFG_SYS_SECURE_SDRAM_SIZE 0x06000000
|
||||
|
||||
#endif
|
||||
@@ -8,133 +8,11 @@
|
||||
#ifndef __MX6QSABRE_COMMON_CONFIG_H
|
||||
#define __MX6QSABRE_COMMON_CONFIG_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#include "mx6_common.h"
|
||||
|
||||
/* MMC Configs */
|
||||
#define CFG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#ifdef CONFIG_SUPPORT_EMMC_BOOT
|
||||
#define EMMC_ENV \
|
||||
"emmcdev=2\0" \
|
||||
"update_emmc_firmware=" \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
|
||||
"if mmc dev ${emmcdev} 1; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
||||
"fi; " \
|
||||
"fi\0"
|
||||
#else
|
||||
#define EMMC_ENV ""
|
||||
#endif
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"fdtfile=undefined\0" \
|
||||
"fdt_addr=0x18000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"console=" CONSOLE_DEV "\0" \
|
||||
"dfuspi=dfu 0 sf 0:0:10000000:0\0" \
|
||||
"dfu_alt_info_spl=spl raw 0x400\0" \
|
||||
"dfu_alt_info_img=u-boot raw 0x10000\0" \
|
||||
"dfu_alt_info=spl raw 0x400\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \
|
||||
"mmcpart=1\0" \
|
||||
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
|
||||
"update_sd_firmware=" \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"if mmc dev ${mmcdev}; then " \
|
||||
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
EMMC_ENV \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=PARTUUID=${uuid} rootwait rw\0" \
|
||||
"loadbootscript=" \
|
||||
"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \
|
||||
"load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \
|
||||
"load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
|
||||
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \
|
||||
"load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run finduuid; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"findfdt="\
|
||||
"if test $fdtfile = undefined; then " \
|
||||
"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
|
||||
"setenv fdtfile imx6qp-sabreauto.dtb; fi; " \
|
||||
"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
|
||||
"setenv fdtfile imx6q-sabreauto.dtb; fi; " \
|
||||
"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
|
||||
"setenv fdtfile imx6dl-sabreauto.dtb; fi; " \
|
||||
"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
|
||||
"setenv fdtfile imx6qp-sabresd.dtb; fi; " \
|
||||
"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
|
||||
"setenv fdtfile imx6q-sabresd.dtb; fi; " \
|
||||
"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
|
||||
"setenv fdtfile imx6dl-sabresd.dtb; fi; " \
|
||||
"if test $fdtfile = undefined; then " \
|
||||
"echo WARNING: Could not determine dtb to use; fi; " \
|
||||
"fi;\0" \
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user