Commit Graph
105605 Commits
Author SHA1 Message Date
Ryan ChenandTom Rini 3fa1b49c94 spi: aspeed: add AST2700 support
AST2700 is a 64-bit SoC whose flash AHB windows are decoded above
the 32-bit address space, so rework AHB addresses to uintptr_t and
decoded window sizes to size_t.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
2026-06-29 13:43:20 -06:00
Tom Rini 3cdce049f9 Merge tag 'u-boot-rockchip-20260610' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/30398

Please pull the updates for rockchip platform:
- New Board support: rk3588 FriendlyElec NanoPi R76S
- UFS boot from SPL for rk3576 (NanoPi M5, ROCK 4D)
- Clock support for RK3576 GMAC 25MHz output and RK3528/RK3576 USB3 OTG
- Switch rk3128/rk3229 boards to upstream devicetree
- MAINTAINERS update for upstream devicetree references
- rk3588-rock-5b: Remove USB-C controller from u-boot.dtsi
2026-06-10 13:12:35 -06:00
Tom Rini a30fd0895d Merge branch 'qcom-main' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/30394

- Define memory map for lemans-evk (pending SMEM)
- Fix CONFIG_SYS_INIT_SP_BSS_OFFSET in db410c chainloaded fragment
- Fix the "dump bootargs" command in the qcom-phone boot menu
- Fix a bug in the rpmh-regulator driver where the regulator mode may
  not be set during enable.
- Enable watchdog autostart for Dragonwing boards
- Fix serial console init on ipq5424-rdp466
2026-06-10 13:11:35 -06:00
Gurumoorthy SanthakumarandCasey Connolly 757a95c7fa arm: dts: ipq5424-rdp466: add chosen node for serial console
Add a /chosen node with stdout-path pointing to serial0 (uart1) to
enable the DT-driven console discovery path in
serial_find_console_or_panic().

Without this node, the live DT path in serial_find_console_or_panic()
is skipped and the fallback path is used. Adding the /chosen node makes
the console selection explicit and deterministic, ensuring the correct
serial device is always selected as the console.

Signed-off-by: Gurumoorthy Santhakumar <gurumoorthy.santhakumar@oss.qualcomm.com>
Link: https://patch.msgid.link/20260603113853.3396271-1-gurumoorthy.santhakumar@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-06-10 13:36:18 +02:00
Aswin MuruganandCasey Connolly c2019e01d0 dts: lemans-evk-u-boot: add override dtsi
Add initial support for the lemans EVK platform based on lemans SoC.
Define memory layout statically.

Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260424104237.968195-1-sumit.garg@kernel.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-06-10 13:36:18 +02:00
Balaji SelvanathanandCasey Connolly a50e32bae6 configs: qcs615/qcs9100: Enable watchdog autostart
Enable watchdog autostart for QCS615 and QCS9100 platforms to ensure
the watchdog timer is automatically started during U-Boot
initialization.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260526-wdt-v1-1-8236040fe56a@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-06-10 13:36:18 +02:00
Sam DayandCasey Connolly 146963054b board: dragonboard410c: fix chainloaded.config
Since c8a74db0c, SYS_INIT_SP_BSS_OFFSET only supports hex encoding.

Signed-off-by: Sam Day <me@samcday.com>
Link: https://patch.msgid.link/20260531-db410c-chainloaded-fix-v1-1-94176aa147d1@samcday.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-06-10 13:36:18 +02:00
Sam DayandCasey Connolly 688890d15c board: qualcomm: phone: fix 'Dump bootargs'
This menu option wasn't dumping /chosen, because no FDT addr had been
set yet.

Signed-off-by: Sam Day <me@samcday.com>
Link: https://patch.msgid.link/20260531-qcom-phoneconfig-fix-v1-1-110a1c542dc3@samcday.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-06-10 13:36:18 +02:00
Petr HodinaandCasey Connolly 8a4c199aa4 gpio: qcom_spmi_gpio: move PM8998 GPIO from legacy pmic driver
Move the "qcom,pm8998-gpio" compatible from the legacy driver
qcom_pmic_gpio.c to qcom_spmi_gpio.c. Enables on PM8998-based boards
(sdm845: SHIFT 6mq, Pixel 3, OnePlus 6, Poco F1, Sony Xperia Akatsuki)
the Volume UP gpio-key.

Signed-off-by: Petr Hodina <petr.hodina@protonmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260605-qcom-gpio-v2-1-c34093041c66@protonmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-06-10 13:36:18 +02:00
Tom Rini 1ab49f6a91 CI: Sage: Pin to labgrid 25.0.1
With the recent release of labgrid 26.0, we need to pin to 25.0.1 for
the Sage lab until everything can be upgraded.

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-06-09 13:16:20 -06:00
Tom Rini 3f79f77761 Merge tag 'efi-2026-07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2026-07-rc5

CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/30365

Documentation:

* Update urllib3 version for building
* usb: typos 'requird', 'current'

UEFI

* Improve PE-COFF relocation data validation

Devicetree-to-C generator:

* dtoc: test: add missing escape in help text
2026-06-09 10:27:02 -06:00
Tom Rini cf81e36fa0 Merge patch series "ti: j7: Update to v0.12.0 of DDR config tool"
Neha Malcom Francis <n-francis@ti.com> says:

Update all DDR configuration DTSIs to the latest auto-generated output of
the Sysconfig Tool (DDR Configuration for TDA4x, DRA8x, AM67x, AM68x,
AM69x (0.12.00.0000)) [0]

The auto-generated files must not be modified, but effort will be taken to
change the tool output to adhere to the latest checkpatch.pl rules. J722S
and J721E will also be updated in a subsequent series.

All the changes have been kernel boot tested and memtester has passed (same
as v1, as no functional changes made).

[0] https://dev.ti.com/sysconfig/#/start

Link: https://lore.kernel.org/r/20251103071035.674604-1-n-francis@ti.com
2026-06-09 10:26:36 -06:00
Neha Malcom FrancisandTom Rini 11dc7c0608 doc: ti: k3: Add section for DDR configuration
Add a concise section for DDR configuration pointing to the public tool
that can be used to generate the configuration DTSI.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Romain Naour <romain.naour@smile.fr>
2026-06-09 10:26:21 -06:00
Neha Malcom FrancisandTom Rini 54fb646ca4 arm: dts: k3-j742s2: ddr: Update to v0.12.0 of DDR config tool
Update the DDR configuration for J742S2 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].

[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html

Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2026-06-09 10:26:21 -06:00
Neha Malcom FrancisandTom Rini fe22382b64 arm: dts: k3-am69: ddr: Update to v0.12.0 of DDR config tool
Update the DDR configuration for AM69 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].

[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html

Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2026-06-09 10:26:21 -06:00
Neha Malcom FrancisandTom Rini c70fd4e5a2 arm: dts: k3-j784s4: ddr: Update to v0.12.0 of DDR config tool
Update the DDR configuration for J784S4 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].

[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html

Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2026-06-09 10:26:21 -06:00
Neha Malcom FrancisandTom Rini 1686817959 arm: dts: k3-am68: ddr: Update to v0.12.0 of DDR config tool
Update the DDR configuration for AM68 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].

[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html

Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2026-06-09 10:26:21 -06:00
Neha Malcom FrancisandTom Rini 9627d70840 arm: dts: k3-j721s2: ddr: Update to v0.12.0 of DDR config tool
Update the DDR configuration for J721S2 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].

[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html

Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2026-06-09 10:26:20 -06:00
Neha Malcom FrancisandTom Rini e126a99992 arm: dts: k3-j7200: ddr: Update to v0.12.0 of DDR config tool
Update the DDR configuration for J7200 according to the SysConfig
DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
is [0].

[0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html

Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2026-06-09 10:26:20 -06:00
Johan JonkerandKever 22fa81fd8c rockchip: MAINTAINERS: upstream devicetree update
Most Rockchip boards are now using the upstream device tree.
Some MAINTAINERS files still contain a reference to
no longer available files. Update and where possible
streamline with '*' ending.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-06-10 00:19:05 +08:00
Alexey CharkovandKever 957941943b rockchip: clk: clk_rk3576: Add support for RK3576 GMAC 25MHz clock output
Rockchip RK3576 SoC has two built-in GMACs which connect to external PHYs
via RGMII interface. The RGMII link can be clocked by either the PHY or
the SoC. When the SoC is the master, as is the case on the RK3576 EVB1,
the output clock needs to be configured in the CRU.

Add the respective logic for getting and setting the RGMII reference clock
output for both GMAC0 and GMAC1.

Signed-off-by: Alexey Charkov <alchark@flipper.net>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-06-10 00:19:05 +08:00
Federico Amedeo IzzoandCasey Connolly 5e6f370c1e regulator: qcom-rpmh-regulator: fix regulator mode mismatch
Initial regulator mode was read from dts but never applied.
This caused a mismatch between saved mode and actual regulator mode.

Apply the current mode from priv->mode during enable() and move
rpmh_regulator_vrm_set_mode function before rpmh_regulator_set_enable_state().

Signed-off-by: Federico Amedeo Izzo <federico@izzo.pro>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260523-qcom-ufs-regulator-support-v4-1-45639533b06d@izzo.pro
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2026-06-09 14:37:20 +02:00
Tom Rini 1a8b7ad50a Merge patch series "mailbox: mpfs-mbox: fixes and syscon support"
Jamie Gibbons <jamie.gibbons@microchip.com> says:

This series updates the Microchip PolarFire SoC (MPFS) mailbox driver in
U-Boot.

The first three patches contain a set of bug fixes and cleanups to the
existing driver, fixing MMIO size calculations, and removing invalid
mailbox channel and private-data handling. These changes are independent
of any devicetree updates and fix issues present in the legacy driver.

The final patch adds support for the corrected, syscon-based devicetree
bindings for the MPFS mailbox. Linux has moved to this binding to more
accurately model the hardware, and U-Boot already supports the same
approach for the MPFS clock controller. This patch updates the mailbox
driver accordingly, while retaining support for the legacy binding for
backwards compatibility.

The final patch is required ASAP as boot is currently broken on master
for MPFS generic boards.

Tested on a PolarFire SoC Icicle Kit ES.

Link: https://lore.kernel.org/r/20260518141712.3597880-1-jamie.gibbons@microchip.com
2026-06-08 15:38:25 -06:00
Jamie GibbonsandTom Rini 6c12873824 mailbox: mpfs-mbox: support new syscon based devicetree configuration
The original PolarFire SoC mailbox devicetree bindings described the
control/status and interrupt registers as standalone reg regions of the
mailbox device. This was incorrect, as these registers are shared system
control blocks and should instead be modeled as syscon devices.

Linux has since corrected this by introducing syscon-based bindings for
the MPFS mailbox and updating the mailbox driver to access the control
and interrupt registers via syscon/regmap. U-Boot, however, continued to
expect the legacy binding, causing mailbox access to fail when using
Linux-aligned devicetrees.

Update the U-Boot MPFS mailbox driver to support the new syscon-based
bindings by resolving the control and sysreg syscon nodes and accessing
the registers through regmap. Support for the legacy mailbox binding is
retained for backwards compatibility with existing firmware-provided
devicetrees.

This brings the U-Boot mailbox driver in line with the corrected hardware
description and matches the behavior of the Linux mailbox driver.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2026-06-08 15:38:25 -06:00
Jamie GibbonsandTom Rini 763435d0e3 mailbox: mpfs-mbox: fix driver bug and cleanup
Remove an unused and invalid struct mbox_chan pointer from the private
data and fix incorrect memory handling in the probe path, where the
private data structure was allocated.

This change corrects a functional bugs and cleans up the driver without
altering its behavior.

Fixes: 111e9bf6a5 ("mailbox: add PolarFire SoC mailbox driver")
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2026-06-08 15:38:25 -06:00
Jamie GibbonsandTom Rini 1173e02c98 mailbox: mpfs-mbox: fix Driver Model private data handling
The MPFS mailbox driver declares priv_auto but also allocates a second
private data structure in the legacy probe path and overwrites the
device’s private pointer using dev_set_priv().

This results in leaking the auto-allocated private data and replacing
the driver’s private state mid-probe, which is incorrect usage of the
U-Boot Driver Model and can lead to undefined behavior.

Remove the redundant allocation and dev_set_priv() call so that the
driver consistently uses the auto-allocated private data provided by
U-Boot.

Fixes: 111e9bf6a5 ("mailbox: add PolarFire SoC mailbox driver")
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2026-06-08 15:38:25 -06:00
Jamie GibbonsandTom Rini a05adbb9b3 mailbox: mpfs-mbox: fix MMIO mapping calculation
Correct the MMIO mapping size calculation, which
previously relied on an invalid start/end subtraction.

This change corrects a functional bug and cleans up the driver without
altering its behavior.

Fixes: 111e9bf6a5 ("mailbox: add PolarFire SoC mailbox driver")
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2026-06-08 15:38:25 -06:00
Tom Rini 1296a428c6 Prepare v2026.07-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-06-08 13:43:04 -06:00
Frank BöwinglohandTom Rini 6d7171bcfe smbios: Fix wrong sysinfo ID for Type 3 enclosure asset tag
smbios_write_type3() uses SYSID_SM_BASEBOARD_ASSET_TAG (Type 2) instead
of SYSID_SM_ENCLOSURE_ASSET_TAG (Type 3) for the enclosure asset tag.
This causes the enclosure's asset tag to be read from the baseboard
sysinfo field rather than the enclosure-specific one.

Fixes: bcf456dd ("smbios: add detailed smbios information")

Signed-off-by: Frank Böwingloh <f.boewingloh@beckhoff.com>
Cc: Raymond Mao <raymondmaoca@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Raymond Mao <raymondmaoca@gmail.com>
2026-06-08 13:29:03 -06:00
Marek VasutandTom Rini 3dd149ba17 lmb: Rename LMB_LIMIT_DMA_BELOW_4G to LMB_LIMIT_DMA_BELOW_RAM_TOP
Rename LMB_LIMIT_DMA_BELOW_4G to LMB_LIMIT_DMA_BELOW_RAM_TOP
to make the Kconfig option more descriptive. No functional
change.

Suggested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2026-06-08 13:28:49 -06:00
Johan JonkerandKever Yang 924f87b995 rockchip: Switch rk3229 boards to upstream devicetree
Switch rk3229 boards to upstream devicetree.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-06-08 21:34:59 +08:00
Johan JonkerandKever Yang 3336e85b6a rockchip: Switch rk3128 boards to upstream devicetree
Switch rk3128 boards to upstream devicetree.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-06-08 21:34:59 +08:00
Alexey CharkovandKever Yang f7deed714c rockchip: rk3576-nanopi-m5: Enable UFS support
NanoPi M5 supports UFS modules to be inserted into its eMMC/UFS slot,
using the on-chip UFS controller inside the RK3576 SoC.

Enable respective drivers in its default config to be able to load
kernels from UFS.

Signed-off-by: Alexey Charkov <alchark@flipper.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-06-08 21:32:40 +08:00
Jonas KarlmanandKever Yang b00307e3c0 rockchip: rk3576-rock-4d: Enable UFS support
The Radxa ROCK 4D has a eMMC 5.1 / UFS 2.0 module connector.

Enable UFS related Kconfig options to support booting from UFS storage
on ROCK 4D.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-06-08 21:32:40 +08:00
Alexey CharkovandKever Yang 9941ec2c5c rockchip: spl: Add support for booting from UFS
Add the required architecture-specific lookups to enable U-boot SPL to
load images from UFS storage devices on Rockchip RK3576, which has a
boot ROM capable of loading the SPL image from UFS.

Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
2026-06-08 21:32:40 +08:00
Alexey CharkovandKever Yang 1165c206c2 reset: rockchip: make device resets available in SPL
Enable the Rockchip reset controller driver in SPL to allow resetting
attached devices like UFS during early boot.

Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Alexey Charkov <alchark@flipper.net>
2026-06-08 21:32:40 +08:00
Jonas KarlmanandKever Yang 82a5b5f7ca board: rockchip: Add FriendlyElec NanoPi R76S
The NanoPi R76S (as "R76S") is an open-sourced mini IoT gateway
device with two 2.5G, designed and developed by FriendlyElec.

Features tested on a NanoPi R76S 2411:
- SD-card boot
- eMMC boot
- LEDs and button
- PCIe/Ethernet
- USB host

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-06-08 21:22:19 +08:00
Jonas KarlmanandKever Yang 3d294c0185 rockchip: rk3588-rock-5b: Remove USB-C controller from u-boot.dtsi
The commit 12049db764 ("rockchip: rk3588-rock-5b: Add USB-C controller
to u-boot.dtsi") added the USB-C controller node to the ROCK 5B board
u-boot.dtsi, this and related usb nodes are now part of upstream DT.

Remove the upstream USB-C controller related DT nodes from u-boot.dtsi,
including the temporary used dr_mode and maximum-speed props of the
usb_host0_xhci node. Only usbc0 status = "okay" is kept ensuring USB-C
power delivery continues to work as intended.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-06-08 21:21:52 +08:00
Jonas KarlmanandKever Yang c97c7d5caa clk: rockchip: rk3576: Add CLK_REF_USB3OTGx support
The CLK_REF_USB3OTGx clocks are used as reference clocks for the two
DWC3 blocks.

Add simple support to get rate of CLK_REF_USB3OTGx clocks to fix
reference clock period configuration.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-06-08 21:21:52 +08:00
Jonas KarlmanandKever Yang a9c1f2af71 clk: rockchip: rk3528: Add CLK_REF_USB3OTG support
The CLK_REF_USB3OTG clock is used as reference clock for the DWC3 block.

Add simple support to get rate of CLK_REF_USB3OTG clock to fix reference
clock period configuration.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2026-06-08 21:21:52 +08:00
Heinrich Schuchardt 5a1818d54c usb: typos 'requird', 'current'
%s/requird/required/
%s/current XHCI/currently XHCI/

Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-06-07 16:44:04 +02:00
Heinrich Schuchardt bc82aa5b41 efi_loader: validate PE-COFF relocation data
When applying base relocations from a PE-COFF binary all data must
be treated as untrusted. Add the following checks to
efi_loader_relocate():

* Reject relocation blocks that don't start on a 32-bit aligned
  address.
* Reject relocation blocks whose SizeOfBlock is smaller than the
  block header, which would cause an unsigned underflow when computing
  the entry count.
* A block with SizeOfBlock == 0 is invalid and does not mark the end of
  the relocation table.
* Reject relocation blocks that extend beyond the end of the
  relocation section.
* Reject individual relocation entries whose target offset, together
  with the access width, exceeds the mapped image size, preventing
  out-of-bounds writes.

Pass virt_size to efi_loader_relocate() from efi_load_pe() to enable
the per-entry bounds check.

Reported-by: Anas Cherni <anas@calif.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2026-06-07 16:43:06 +02:00
Francesco VallaandHeinrich Schuchardt badf750282 dtoc: test: add missing escape in help text
A single percent sign might be interpreted as a string format directive
and shall thus be escaped - doubling it - to actually indicate a
percentage.

Without the escape, pytest fails to run test_fdt.py with the following
error:

  ValueError: Test coverage failure
  fdt code coverage: Traceback (most recent call last):
    File "/usr/lib64/python3.14/argparse.py", line 1748, in _check_help
      formatter._expand_help(action)
      ~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^
    File "/usr/lib64/python3.14/argparse.py", line 676, in _expand_help
      return help_string % params
             ~~~~~~~~~~~~^~~~~~~~
  TypeError: %c requires an int or a unicode character, not dict

  The above exception was the direct cause of the following exception:

  Traceback (most recent call last):
    File "/home/user/u-boot/./tools/dtoc/test_fdt", line 1002, in <module>
      sys.exit(main())
               ~~~~^^
    File "/home/user/u-boot/./tools/dtoc/test_fdt", line 987, in main
      parser.add_argument('-T', '--test-coverage', action='store_true',
      ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                          default=False,
                          ^^^^^^^^^^^^^^
                          help='run tests and check for 100% coverage')
                          ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
    File "/usr/lib64/python3.14/argparse.py", line 1562, in add_argument
      self._check_help(action)
      ~~~~~~~~~~~~~~~~^^^^^^^^
    File "/usr/lib64/python3.14/argparse.py", line 1750, in _check_help
      raise ValueError('badly formed help string') from exc
  ValueError: badly formed help string

Fixes: 7640b16660 ("test_fdt: Convert to use argparse")
Signed-off-by: Francesco Valla <francesco@valla.it>
2026-06-07 16:42:50 +02:00
Tom RiniandHeinrich Schuchardt 969a1dde3a doc: Update urllib3 version for building
The GitHub dependabot tool has reported two "high" priority bug,
CVE-2026-44431 and CVE-2026-44432, with this package. Update to the
patched version.

Reported-by: GitHub dependabot
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-06-07 16:41:27 +02:00
Tom Rini 75daa27794 Merge tag 'u-boot-imx-master-20260604' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/30353

- Fix RAM size calculation on verdin-imx95.
- Fix boot from SPI on i.MX8MM.
- Fix boot abort on kontron-sl-mx6ul.
- Fix the imx8 CPU market segment report.
2026-06-04 18:56:57 -06:00
Marek VasutandFabio Estevam 0fba623e4f tools: imx8image: Fix FSPI alignment to 4 kiB
The SPI NOR minimum subsector size is 4 kiB, update the alignment.
THis is particularly important in case of embedded DUMMY_DDR, which
must be at at least 4 kiB aligned offset.

Fixes: a2b96ece5b ("tools: add i.MX8/8X image support")
Signed-off-by: Marek Vasut <marex@nabladev.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2026-06-04 17:27:17 -03:00
Marek VasutandFabio Estevam b9fc16e72d arm64: dts: imx8mn: Generate FSPI header using binman imx8mimage
The binman imx8mimage now correctly handles generated fspi_header.bin
in its imx8mimage etype. Make use of this, remove fspi_conf_block in
favor of generated fspi_header.bin, and configure imx8mimage accordingly.

Signed-off-by: Marek Vasut <marex@nabladev.com>
2026-06-04 17:26:40 -03:00
Marek VasutandFabio Estevam c3680dcf9a arm64: dts: imx8mm: Generate FSPI header using binman imx8mimage
The binman imx8mimage now correctly handles generated fspi_header.bin
in its imx8mimage etype. Make use of this, remove fspi_conf_block in
favor of generated fspi_header.bin, and configure imx8mimage accordingly.

Signed-off-by: Marek Vasut <marex@nabladev.com>
2026-06-04 17:26:40 -03:00
Marek VasutandFabio Estevam 822a98588d binman: imx8mimage: Handle nxp,boot-from = "fspi"
Boot from FSPI requires additional 448 Byte long header, with U-Boot SPL
starting at offset 0x1000. Currently, both i.MX8MM and i.MX8MN attempt
to generate this header using fspi_conf_block with filename pointing at
CONFIG_FSPI_CONF_FILE file. This does not work, for two reasons.

First, the CONFIG_FSPI_CONF_FILE is generated by mkimage -T imx8mimage
and may not be available yet when the fspi_conf_block is evaluated. That
leads to a race condition where highly parallel builds fail to find the
CONFIG_FSPI_CONF_FILE, which is usually called fspi_header.bin, on first
build attempt.

Second, binman gets confused and patches incorrect offset of DDR PHY
firmware blobs into U-Boot SPL, the offset is incremented by exactly
0x1000 which is the size of fspi_conf_block.

Fix both problems at once, make imx8mimage handle the generated FSPI
header and prepend it in front of the imx8mimage processed data. This
way, the race condition is solved, because the data generated by the
imx8mimage are surely combined only after mkimage -T imx8mimage ran.
The binman offset calculation is also solved, because there is no
fspi_conf_block node in the DT anymore.

Signed-off-by: Marek Vasut <marex@nabladev.com>
2026-06-04 17:26:40 -03:00
Ye LiandFabio Estevam cdb9e79056 cpu: imx8_cpu: Fix CPU segment information print
Should not use CONFIG_IMX_TMU to determine the print of CPU market
segment information. Only iMX8 platforms don't have segment fuse.
And there is no extended commercial part on iMX9 (91/93/94/95),
fix it to extended industrial.

Signed-off-by: Ye Li <ye.li@nxp.com>
2026-06-04 17:25:22 -03:00