rockchip: Switch rk3229 boards to upstream devicetree
Switch rk3229 boards to upstream devicetree. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Johan Jonker
Kever Yang
@@ -45,9 +45,6 @@ dtb-$(CONFIG_MACH_S900) += \
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dtb-$(CONFIG_MACH_S700) += \
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s700-cubieboard7.dtb
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dtb-$(CONFIG_ROCKCHIP_RK322X) += \
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rk3229-evb.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3368) += \
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rk3368-sheep.dtb \
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rk3368-geekbox.dtb \
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@@ -1,256 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "rk3229.dtsi"
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/ {
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model = "Rockchip RK3229 Evaluation board";
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compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
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aliases {
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mmc0 = &emmc;
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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dc_12v: dc-12v-regulator {
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compatible = "regulator-fixed";
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regulator-name = "dc_12v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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ext_gmac: ext_gmac {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "ext_gmac";
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#clock-cells = <0>;
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};
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vcc_host: vcc-host-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&host_vbus_drv>;
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regulator-name = "vcc_host";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc_sys>;
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};
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vcc_phy: vcc-phy-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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regulator-name = "vcc_phy";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vccio_1v8>;
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};
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vcc_sys: vcc-sys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_12v>;
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};
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vccio_1v8: vccio-1v8-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vccio_1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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vin-supply = <&vcc_sys>;
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};
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vccio_3v3: vccio-3v3-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vccio_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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vin-supply = <&vcc_sys>;
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};
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vdd_arm: vdd-arm-regulator {
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compatible = "pwm-regulator";
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pwms = <&pwm1 0 25000 1>;
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pwm-supply = <&vcc_sys>;
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regulator-name = "vdd_arm";
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <1400000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vdd_log: vdd-log-regulator {
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compatible = "pwm-regulator";
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pwms = <&pwm2 0 25000 1>;
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pwm-supply = <&vcc_sys>;
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regulator-name = "vdd_log";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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gpio_keys {
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compatible = "gpio-keys";
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autorepeat;
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pinctrl-names = "default";
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pinctrl-0 = <&pwr_key>;
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power_key: power-key {
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label = "GPIO Key Power";
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gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_POWER>;
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debounce-interval = <100>;
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wakeup-source;
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};
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};
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};
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&cpu0 {
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cpu-supply = <&vdd_arm>;
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};
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&cpu1 {
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cpu-supply = <&vdd_arm>;
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};
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&cpu2 {
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cpu-supply = <&vdd_arm>;
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};
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&cpu3 {
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cpu-supply = <&vdd_arm>;
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};
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&emmc {
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cap-mmc-highspeed;
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non-removable;
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status = "okay";
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};
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&gmac {
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assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
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assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
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clock_in_out = "input";
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phy-supply = <&vcc_phy>;
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 1000000>;
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tx_delay = <0x30>;
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rx_delay = <0x10>;
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status = "okay";
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};
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&io_domains {
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status = "okay";
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vccio1-supply = <&vccio_3v3>;
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vccio2-supply = <&vccio_1v8>;
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vccio4-supply = <&vccio_3v3>;
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};
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&pinctrl {
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keys {
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pwr_key: pwr-key {
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rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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usb {
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host_vbus_drv: host-vbus-drv {
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rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&pwm1 {
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status = "okay";
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};
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&pwm2 {
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status = "okay";
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};
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&tsadc {
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rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&u2phy0 {
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status = "okay";
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u2phy0_otg: otg-port {
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status = "okay";
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};
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u2phy0_host: host-port {
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phy-supply = <&vcc_host>;
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status = "okay";
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};
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};
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&u2phy1 {
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status = "okay";
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u2phy1_otg: otg-port {
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phy-supply = <&vcc_host>;
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status = "okay";
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};
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u2phy1_host: host-port {
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phy-supply = <&vcc_host>;
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status = "okay";
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};
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};
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&usb_host0_ehci {
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status = "okay";
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};
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&usb_host0_ohci {
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status = "okay";
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};
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&usb_host1_ehci {
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status = "okay";
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};
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&usb_host1_ohci {
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status = "okay";
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};
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&usb_host2_ehci {
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status = "okay";
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};
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&usb_host2_ohci {
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status = "okay";
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};
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&usb_otg {
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status = "okay";
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};
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@@ -1,52 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include "rk322x.dtsi"
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/ {
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compatible = "rockchip,rk3229";
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/delete-node/ opp-table0;
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cpu0_opp_table: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <950000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <975000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1000000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1175000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1275000>;
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};
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opp-1296000000 {
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opp-hz = /bits/ 64 <1296000000>;
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opp-microvolt = <1325000>;
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};
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opp-1392000000 {
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opp-hz = /bits/ 64 <1392000000>;
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opp-microvolt = <1375000>;
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};
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opp-1464000000 {
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opp-hz = /bits/ 64 <1464000000>;
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opp-microvolt = <1400000>;
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};
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};
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};
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File diff suppressed because it is too large
Load Diff
@@ -109,6 +109,7 @@ config ROCKCHIP_RK322X
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select TPL_OF_LIBFDT
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select TPL_HAVE_INIT_STACK if TPL
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select SPL_DRIVERS_MISC
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imply OF_UPSTREAM
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imply ROCKCHIP_COMMON_BOARD
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imply SPL_SERIAL
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imply SPL_ROCKCHIP_COMMON_BOARD
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@@ -1,7 +1,6 @@
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EVB-RK3229
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M: Kever Yang <kever.yang@rock-chips.com>
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S: Maintained
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F: arch/arm/dts/rk3229-evb.dts
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F: arch/arm/dts/rk3229-evb-u-boot.dtsi
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F: board/rockchip/evb_rk3229
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F: include/configs/evb_rk3229.h
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@@ -9,7 +9,7 @@ CONFIG_NR_DRAM_BANKS=2
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x61100000
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CONFIG_ENV_OFFSET=0x3F8000
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CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
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CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3229-evb"
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CONFIG_ROCKCHIP_RK322X=y
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CONFIG_TARGET_EVB_RK3229=y
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CONFIG_SPL_STACK_R_ADDR=0x60600000
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@@ -24,7 +24,7 @@ CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_USE_PREBOOT=y
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CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3229-evb.dtb"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_SPL_MAX_SIZE=0x100000
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@@ -1,287 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
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* Author: Jeffy Chen <jeffy.chen@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_GPLL 4
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#define ARMCLK 5
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/* sclk gates (special clocks) */
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#define SCLK_SPI0 65
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#define SCLK_NANDC 67
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#define SCLK_SDMMC 68
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#define SCLK_SDIO 69
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#define SCLK_EMMC 71
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#define SCLK_TSADC 72
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#define SCLK_UART0 77
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#define SCLK_UART1 78
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#define SCLK_UART2 79
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#define SCLK_I2S0 80
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#define SCLK_I2S1 81
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#define SCLK_I2S2 82
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#define SCLK_SPDIF 83
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#define SCLK_TIMER0 85
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#define SCLK_TIMER1 86
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#define SCLK_TIMER2 87
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#define SCLK_TIMER3 88
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#define SCLK_TIMER4 89
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#define SCLK_TIMER5 90
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#define SCLK_I2S_OUT 113
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#define SCLK_SDMMC_DRV 114
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#define SCLK_SDIO_DRV 115
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#define SCLK_EMMC_DRV 117
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#define SCLK_SDMMC_SAMPLE 118
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#define SCLK_SDIO_SAMPLE 119
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#define SCLK_SDIO_SRC 120
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_VOP 122
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#define SCLK_HDMI_HDCP 123
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#define SCLK_MAC_SRC 124
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#define SCLK_MAC_EXTCLK 125
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#define SCLK_MAC 126
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#define SCLK_MAC_REFOUT 127
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#define SCLK_MAC_REF 128
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#define SCLK_MAC_RX 129
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#define SCLK_MAC_TX 130
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#define SCLK_MAC_PHY 131
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#define SCLK_MAC_OUT 132
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#define SCLK_VDEC_CABAC 133
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#define SCLK_VDEC_CORE 134
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#define SCLK_RGA 135
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#define SCLK_HDCP 136
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#define SCLK_HDMI_CEC 137
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#define SCLK_CRYPTO 138
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#define SCLK_TSP 139
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#define SCLK_HSADC 140
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#define SCLK_WIFI 141
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#define SCLK_OTGPHY0 142
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#define SCLK_OTGPHY1 143
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#define SCLK_HDMI_PHY 144
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/* dclk gates */
|
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#define DCLK_VOP 190
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#define DCLK_HDMI_PHY 191
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/* aclk gates */
|
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#define ACLK_DMAC 194
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#define ACLK_CPU 195
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#define ACLK_VPU_PRE 196
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#define ACLK_RKVDEC_PRE 197
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#define ACLK_RGA_PRE 198
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||||
#define ACLK_IEP_PRE 199
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#define ACLK_HDCP_PRE 200
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#define ACLK_VOP_PRE 201
|
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#define ACLK_VPU 202
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#define ACLK_RKVDEC 203
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#define ACLK_IEP 204
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#define ACLK_RGA 205
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#define ACLK_HDCP 206
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#define ACLK_PERI 210
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#define ACLK_VOP 211
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#define ACLK_GMAC 212
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#define ACLK_GPU 213
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|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GPIO3 323
|
||||
#define PCLK_VIO_H2P 324
|
||||
#define PCLK_HDCP 325
|
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#define PCLK_EFUSE_1024 326
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#define PCLK_EFUSE_256 327
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#define PCLK_GRF 329
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#define PCLK_I2C0 332
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#define PCLK_I2C1 333
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#define PCLK_I2C2 334
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#define PCLK_I2C3 335
|
||||
#define PCLK_SPI0 338
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#define PCLK_UART0 341
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||||
#define PCLK_UART1 342
|
||||
#define PCLK_UART2 343
|
||||
#define PCLK_TSADC 344
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_CPU 354
|
||||
#define PCLK_PERI 363
|
||||
#define PCLK_HDMI_CTRL 364
|
||||
#define PCLK_HDMI_PHY 365
|
||||
#define PCLK_GMAC 367
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_I2S0_8CH 442
|
||||
#define HCLK_I2S1_8CH 443
|
||||
#define HCLK_I2S2_2CH 444
|
||||
#define HCLK_SPDIF_8CH 445
|
||||
#define HCLK_VOP 452
|
||||
#define HCLK_NANDC 453
|
||||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_CPU 460
|
||||
#define HCLK_VPU_PRE 461
|
||||
#define HCLK_RKVDEC_PRE 462
|
||||
#define HCLK_VIO_PRE 463
|
||||
#define HCLK_VPU 464
|
||||
#define HCLK_RKVDEC 465
|
||||
#define HCLK_VIO 466
|
||||
#define HCLK_RGA 467
|
||||
#define HCLK_IEP 468
|
||||
#define HCLK_VIO_H2P 469
|
||||
#define HCLK_HDCP_MMU 470
|
||||
#define HCLK_HOST0 471
|
||||
#define HCLK_HOST1 472
|
||||
#define HCLK_HOST2 473
|
||||
#define HCLK_OTG 474
|
||||
#define HCLK_TSP 475
|
||||
#define HCLK_M_CRYPTO 476
|
||||
#define HCLK_S_CRYPTO 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
#define SRST_CORE2_PO 2
|
||||
#define SRST_CORE3_PO 3
|
||||
#define SRST_CORE0 4
|
||||
#define SRST_CORE1 5
|
||||
#define SRST_CORE2 6
|
||||
#define SRST_CORE3 7
|
||||
#define SRST_CORE0_DBG 8
|
||||
#define SRST_CORE1_DBG 9
|
||||
#define SRST_CORE2_DBG 10
|
||||
#define SRST_CORE3_DBG 11
|
||||
#define SRST_TOPDBG 12
|
||||
#define SRST_ACLK_CORE 13
|
||||
#define SRST_NOC 14
|
||||
#define SRST_L2C 15
|
||||
|
||||
#define SRST_CPUSYS_H 18
|
||||
#define SRST_BUSSYS_H 19
|
||||
#define SRST_SPDIF 20
|
||||
#define SRST_INTMEM 21
|
||||
#define SRST_ROM 22
|
||||
#define SRST_OTG_ADP 23
|
||||
#define SRST_I2S0 24
|
||||
#define SRST_I2S1 25
|
||||
#define SRST_I2S2 26
|
||||
#define SRST_ACODEC_P 27
|
||||
#define SRST_DFIMON 28
|
||||
#define SRST_MSCH 29
|
||||
#define SRST_EFUSE1024 30
|
||||
#define SRST_EFUSE256 31
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_GPIO3 35
|
||||
#define SRST_PERIPH_NOC_A 36
|
||||
#define SRST_PERIPH_NOC_BUS_H 37
|
||||
#define SRST_PERIPH_NOC_P 38
|
||||
#define SRST_UART0 39
|
||||
#define SRST_UART1 40
|
||||
#define SRST_UART2 41
|
||||
#define SRST_PHYNOC 42
|
||||
#define SRST_I2C0 43
|
||||
#define SRST_I2C1 44
|
||||
#define SRST_I2C2 45
|
||||
#define SRST_I2C3 46
|
||||
|
||||
#define SRST_PWM 48
|
||||
#define SRST_A53_GIC 49
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_NOC 52
|
||||
#define SRST_CRYPTO 53
|
||||
#define SRST_SGRF 54
|
||||
#define SRST_GRF 55
|
||||
#define SRST_GMAC 56
|
||||
#define SRST_PERIPH_NOC_H 58
|
||||
#define SRST_MACPHY 63
|
||||
|
||||
#define SRST_DMA 64
|
||||
#define SRST_NANDC 68
|
||||
#define SRST_USBOTG 69
|
||||
#define SRST_OTGC 70
|
||||
#define SRST_USBHOST0 71
|
||||
#define SRST_HOST_CTRL0 72
|
||||
#define SRST_USBHOST1 73
|
||||
#define SRST_HOST_CTRL1 74
|
||||
#define SRST_USBHOST2 75
|
||||
#define SRST_HOST_CTRL2 76
|
||||
#define SRST_USBPOR0 77
|
||||
#define SRST_USBPOR1 78
|
||||
#define SRST_DDRMSCH 79
|
||||
|
||||
#define SRST_SMART_CARD 80
|
||||
#define SRST_SDMMC 81
|
||||
#define SRST_SDIO 82
|
||||
#define SRST_EMMC 83
|
||||
#define SRST_SPI 84
|
||||
#define SRST_TSP_H 85
|
||||
#define SRST_TSP 86
|
||||
#define SRST_TSADC 87
|
||||
#define SRST_DDRPHY 88
|
||||
#define SRST_DDRPHY_P 89
|
||||
#define SRST_DDRCTRL 90
|
||||
#define SRST_DDRCTRL_P 91
|
||||
#define SRST_HOST0_ECHI 92
|
||||
#define SRST_HOST1_ECHI 93
|
||||
#define SRST_HOST2_ECHI 94
|
||||
#define SRST_VOP_NOC_A 95
|
||||
|
||||
#define SRST_HDMI_P 96
|
||||
#define SRST_VIO_ARBI_H 97
|
||||
#define SRST_IEP_NOC_A 98
|
||||
#define SRST_VIO_NOC_H 99
|
||||
#define SRST_VOP_A 100
|
||||
#define SRST_VOP_H 101
|
||||
#define SRST_VOP_D 102
|
||||
#define SRST_UTMI0 103
|
||||
#define SRST_UTMI1 104
|
||||
#define SRST_UTMI2 105
|
||||
#define SRST_UTMI3 106
|
||||
#define SRST_RGA 107
|
||||
#define SRST_RGA_NOC_A 108
|
||||
#define SRST_RGA_A 109
|
||||
#define SRST_RGA_H 110
|
||||
#define SRST_HDCP_A 111
|
||||
|
||||
#define SRST_VPU_A 112
|
||||
#define SRST_VPU_H 113
|
||||
#define SRST_VPU_NOC_A 116
|
||||
#define SRST_VPU_NOC_H 117
|
||||
#define SRST_RKVDEC_A 118
|
||||
#define SRST_RKVDEC_NOC_A 119
|
||||
#define SRST_RKVDEC_H 120
|
||||
#define SRST_RKVDEC_NOC_H 121
|
||||
#define SRST_RKVDEC_CORE 122
|
||||
#define SRST_RKVDEC_CABAC 123
|
||||
#define SRST_IEP_A 124
|
||||
#define SRST_IEP_H 125
|
||||
#define SRST_GPU_A 126
|
||||
#define SRST_GPU_NOC_A 127
|
||||
|
||||
#define SRST_CORE_DBG 128
|
||||
#define SRST_DBG_P 129
|
||||
#define SRST_TIMER0 130
|
||||
#define SRST_TIMER1 131
|
||||
#define SRST_TIMER2 132
|
||||
#define SRST_TIMER3 133
|
||||
#define SRST_TIMER4 134
|
||||
#define SRST_TIMER5 135
|
||||
#define SRST_VIO_H2P 136
|
||||
#define SRST_HDMIPHY 139
|
||||
#define SRST_VDAC 140
|
||||
#define SRST_TIMER_6CH_P 141
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user