Since commit ecb1c37a7b ("clk: imx8mp: Add EQoS MAC clock"),
the clocks for the DWMAC driver can be configured, and removing
them breaks operation.
Fixes: ecb1c37a7b ("clk: imx8mp: Add EQoS MAC clock")
Suggested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Booting an initramfs with the current initrd_addr address may lead to
initramfs corruption and boot failure.
Fix the initramfs problem by applying the following layout
suggested by Tom Rini:
loadaddr=0x40480000 --> Gets moved to 0x40600000 in run-time:
Uncompressing Kernel Image
Moving Image from 0x40480000 to 0x40600000, end=41e80000
fdt_addr_r= moved loadaddr + 128 MiB = 0x48600000
initrd_addr=fdt_addr_r + 512 KiB = 0x48680000
Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
The mux flags (u8), div flags (u8), and gate flags (u8) are not the clk
flags (unsigned long). They have different meanings
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
The mux flags (u8), div flags (u8), and gate flags (u8) are not the clk
flags (unsigned long). They have different meanings
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
The production DH i.MX8MP DHCOM SoM rev.200 uses updated PHY MDIO addresses
for the Fast ethernet PHYs. Update the base SoM DT and SoM rev.100 backward
compatibility DTO to cater for this change.
Since the MDIO address adjustment is now also in the rev.100 SoM DTO, not
only in the rev.100 PDK3 DTO, update Makefile accordingly as well, else the
DTC would complain about the DTO overriding the 'reg' property without also
updating the node unit-address, which is not doable without duplicating the
entire PHY node in the DTO, which leads to large amount of duplication with
no gain.
Fixes: 9de599ec3d ("arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200")
Signed-off-by: Marek Vasut <marex@denx.de>
Enable PCA953x GPIO expander driver in DH i.MX8MP DHCOM PDK2 configuration.
The PCA9539 GPIO expander is used on production DH i.MX8MP DHCOM SoM rev.200.
This is already enabled in DH i.MX8MP DHCOM PDK3 configuration so align the
two configurations.
Fixes: 9de599ec3d ("arm64: dts: imx8mp: Update i.MX8MP DHCOM SoM DT to production rev.200")
Signed-off-by: Marek Vasut <marex@denx.de>
Enable 'cat' command to print file from filesystem to stdout.
Enable 'xxd' command to hexdump file from filesystem to stdout.
Signed-off-by: Marek Vasut <marex@denx.de>
The older i.MX8M Mini Verdin SoMs may came with 20 MHz SPI CAN controller
oscillator, the newer SoMs always use 40 MHz oscillator. Handle both by
overriding the oscillator frequency just before booting the kernel.
These are the known variants with 20 MHz oscillator:
- 0055, V1.1A, V1.1B, V1.1C and V1.1D, use a 20MHz oscillator
- 0059, V1.1A and V1.1B, use a 20MHz oscillator
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
- Re-instate the zlib update, so we can fix it for this release,
assorted whitespace cleanups, allow mkimage to 'auto-conf' signing of
scripts, enhance ELF image support, add more HW rev support to e1000
driver, update am64x_evm config, correct mpc8xxx watchdog, update
phycore-am6 docs.
Timer value is a 16 bits calculated from the wanted timeout and the
system clock. On powerpc/8xx, a timeout of 2s gives a value which
is over U16_MAX so U16_MAX shall be used. But the calculation is
casted to u16 so at the end the result is 63770 instead of 128906.
So the timer gets loaded with 63770 instead of 65535. It is not
a big difference in that case, but lets make the code correct and
cast to u32 instead of u16.
Fixes: 26e8ebcd7c ("watchdog: mpc8xxx: Make it generic")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
This patch fixes the I225 hardware default value
at 0x15FD meaning empty flash image
or the NVM configuration loading failed
Signed-off-by: Marjolaine Amate <marjolaine.amate@odyssee-systemes.fr>
This patch adds support for Intel Foxville I226
devices LM,V,I,K in e1000 driver.
Signed-off-by: Marjolaine Amate <marjolaine.amate@odyssee-systemes.fr>
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^ /\t/' -i */Kconfig
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
The board has the TCA9554 I2C GPIO expander chip for expansion
board presence detection logic.
Enable the relevant I2C GPIO drivers.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Some operating systems (e.g. seL4) and embedded applications are ELF
images. It is convenient to use FIT-images to implement trusted boot.
Added "elf" image type for booting using bootm command.
Signed-off-by: Maxim Moskalets <maximmosk4@gmail.com>
U-Boot configured for verified boot with the "required" option set to
"conf" also checks scripts put in FIT images for a valid signature, and
refuses to source and run such a script if the signature for the
configuration is bad or missing. Such a script could not be packaged
before, because mkimage failed like this:
% tools/mkimage -T script -C none -d tmp/my.scr -f auto-conf -k tmp -g dev -o sha256,rsa4096 my.uimg
Failed to find any images for configuration 'conf-1/signature'
tools/mkimage Can't add hashes to FIT blob: -1
Error: Bad parameters for FIT image type
This is especially unfortunate if LEGACY_IMAGE_FORMAT is disabled as
recommended.
Listing the script configuration in a "sign-images" subnode instead,
would have added even more complexity to the already complex auto fit
generation code.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Various minor fixes and improvements:
* Fix Qualcomm SPMI v5 support
* Move default environment to a file
* Add support for special pins (e.g ufs/mmc reset/data pins)
* IPQ moves to OF_UPSTREAM and receives some cleanup and MAINTAINERS
changes
* Add a reset driver for devices without PSCI
* msm8916 USB clock improvements for mobile devices
Branch contains minor improvemets for existing tegra devices along
with bring up of 4 new devices (ASUS Transformers T20, Microsoft
Surface RT, Lenovo Ideapad Yoga 11 and WEXLER Tab 7t).
Commit ee1d8aa5ec ("spmi: msm: support controller version 7") broke
support for channels > 128 on v5 controllers, resulting in some
peripherals (like the power button / pon) working but others (like
gpios) reading bogus data.
Correct max_channels for v5 controllers.
Fixes: ee1d8aa5ec ("spmi: msm: support controller version 7")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Make use of CONFIG_DEFAULT_ENV_FILE and move the default qcom
environment to a file under board/qualcomm.
This is much cleaner and means we don't need to recompile on changing
the environment.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Most devices have buttons exposed via the PMIC, the button polling
therefore triggers a log spam if debug logging is enabled.
Demote these to debug() so that they aren't printed unless LOG_DEBUG is
defined explicitly for this file.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Add the special pins configuration data to allow setup the bias
of the UFS and SDCard pins on the SM8650 SoC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Add the special pins configuration data to allow setup the bias
of the UFS and SDCard pins on the SM8550 SoC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Use the previously introduced msm_special_pin_data to setup the special
pins configuration if the SoC driver have them specified.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
In order to help setup pin configuration for special pins (UFS, SDCard),
introduce the msm_special_pin_data struct largely inspired from the
Linux conterpart but with only U-Boot required fields.
This struct is added to the pins_data to allow specifying the special
pins data for each SoC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
I2C clocks are not initialized by the SBL, so lets add support for clocks
required by both of the QUP I2C controllers.
BLSP1 AHB clock is already initialized by SBL, but QUP I2C driver is
requesting it so we have to add it to the enable list.
Based off QCS404 clock driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Pinctrl drivers were moved to a dedicated directory but the entry was never
updated, so add the pinctrl-ipq4019 driver entry.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The reset handling was added to the clock drivers but the entry was never
updated, so add the clock-ipq4019 driver instead.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The separate clock and reset dt-bindings for IPQ40XX were merged into one
recently, but the entry was not updated so do it now.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Now that drivers are compatible enough with the upstream DTS, there is no
reason to not use the upstream DTS, so imply OF_UPSTREAM by default.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Number of Qualcomm ARMv7 SoC-s did not use PSCI but rather used PSHOLD
(Qualcomm Power Supply Hold Reset) bit to trigger reset or poweroff.
Qualcomm IPQ40XX is one of them, so provide a simple sysreset driver based
on the upstream Linux one, it is DT compatible as well.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This seems to be necessary on my samsung-a5. Without this patch, the
first access of EHCI registers causes a bus stall and subsequent reset.
I am unsure why this wasn't already necessary for db410c, perhaps those
clocks are already enabled on boot.
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sam Day <me@samcday.com>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
The newer "register map for simple gate clocks" support added for qcom
clocks is used. As a result gcc_apq8016 now has a mixture of the old and
new styles. I didn't (and still don't!) feel comfortable enough in this
area to update the existing code.
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Enable the clock/pinctrl drivers for these two SoCs. Previously left out
due to only being used on the db410c and db820c respectively which both
have their own board code. We can still boot these with most features
working without that board code.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sam Day <me@samcday.com>
The Lenovo IdeaPad Yoga 11 is a hybrid laptop/tablet Windows RT-based
computer released in late 2012. The device uses a 1.3 GHz quad-core
Nvidia Tegra 3 chipset with 2 GB of RAM, features a 11.6 inch 1366x768
screen and 32/64 GB of internal memory that can be supplemented with
a microSDXC card slot, full size SD card slot and 2 full size USB 2.0
ports.
Tested-by: Jethro Bull <jethrob@hotmail.com>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Surface RT is a hybrid tablet computer developed and manufactured
by Microsoft and shipped with Windows RT. The tablet uses a 1.3 GHz
quad-core Nvidia Tegra 3 chipset with 2 GB of RAM, features 10.8
inch 1366x768 screen and 32/64 GB of internal memory that can be
supplemented with a microSDXC card giving up to 200 GB of
additional storage.
Tested-by: Jethro Bull <jethrob@hotmail.com>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
WEXLER Tab 7t is a mini tablet computer developed by WEXLER that
runs the Android operating system. The device features a 7.0-inch
(180 mm) HD display, an Nvidia Tegra 3 quad-core chip, 1 GB of RAM,
8, 16 or 32 GB of storage that can be supplemented with a microSDXC
card giving up to 64 GB of additional storage and a full size USB
port.
Tested-by: Maksim Kurnosenko <asusx2@mail.ru>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
The Asus Eee Pad Transformer family are 2-in-1 detachable/slider
tablets developed by Asus that run the Android operating system.
The Eee Pad Transformers feature a 10.1-inch (260 mm) display,
an Nvidia Tegra 2 dual-core chip, 1 GB of RAM, and 16/32 GB of storage.
Transformers board derives from Nvidia Ventana development board.
This patch brings support for all 3 known T20 Transformers:
- Asus Eee Pad Transformer TF101
- Asus Eee Pad Transformer TF101G
- Asus Eee Pad Slider SL101
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101
Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # ASUS TF101
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This ensures that the device can boot from a USB device prior to MMC. Useful
cases are when installing a new OS from USB while MMC still has a working OS
configuration or if the OS configuration is broken in late boot stages
(kernel boots but the system does not start).
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
