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pinctrl: qcom: add support setting pin configuration for special pins

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Use the previously introduced msm_special_pin_data to setup the special
pins configuration if the SoC driver have them specified.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Neil Armstrong
2024-07-05 12:04:48 +02:00
committed by Caleb Connolly
parent 8daee349e5
commit 0e044c8098
1 changed files with 35 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/pinctrl/qcom/pinctrl-qcom.c
+35 -2
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@@ -103,14 +103,47 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
return 0;
}
static int msm_pinconf_set_special(struct msm_pinctrl_priv *priv, unsigned int pin_selector,
unsigned int param, unsigned int argument)
{
unsigned int offset = pin_selector - priv->data->pin_data.special_pins_start;
const struct msm_special_pin_data *data;
if (!priv->data->pin_data.special_pins_data)
return 0;
data = &priv->data->pin_data.special_pins_data[offset];
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
argument = (argument / 2) - 1;
clrsetbits_le32(priv->base + data->ctl_reg,
GENMASK(2, 0) << data->drv_bit,
argument << data->drv_bit);
break;
case PIN_CONFIG_BIAS_DISABLE:
clrbits_le32(priv->base + data->ctl_reg,
TLMM_GPIO_PULL_MASK << data->pull_bit);
break;
case PIN_CONFIG_BIAS_PULL_UP:
clrsetbits_le32(priv->base + data->ctl_reg,
TLMM_GPIO_PULL_MASK << data->pull_bit,
argument << data->pull_bit);
break;
default:
return 0;
}
return 0;
}
static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
unsigned int param, unsigned int argument)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
/* Always NOP for special pins */
if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
return 0;
return msm_pinconf_set_special(priv, pin_selector, param, argument);
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH: