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arm: mach-omap2: am33xx: ddr: ensure proper reset->cke delay

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With the Beaglebone Black the delay on DDR_RESET to DDR_CKE is currently
~135us and not the >500us required by JEDEC spec.

The issue here is the REF_CTRL register performs two purposes. It is the
counter for CKE to RESET delay before the DDR controller is initialized
and used to configure the refresh rate after initialization of the
controller.

So to avoid inadvertently configuring the CKE to DDR delay, ensure we
initialize the controller before we configure the refresh rate.

Fixes: 69b918b65d ("am33xx,ddr3: fix ddr3 sdram configuration")
Signed-off-by: Bryan Brattlof <bb@ti.com>
This commit is contained in:
Bryan Brattlof
2026-07-15 13:54:02 -06:00
committed by Tom Rini
parent fcda974e36
commit b158ef7c44
1 changed files with 1 additions and 1 deletions
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arch/arm/mach-omap2/am33xx/ddr.c
+1 -1
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@@ -185,10 +185,10 @@ void config_sdram(const struct emif_regs *regs, int nr)
if (regs->zq_config) {
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
/* Trigger initialization */
writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
/* Wait 1ms because of L3 timeout error */
udelay(1000);