From b158ef7c445a1ab66134c410c901766d0a73e486 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Wed, 24 Jun 2026 10:35:07 -0500 Subject: [PATCH] arm: mach-omap2: am33xx: ddr: ensure proper reset->cke delay With the Beaglebone Black the delay on DDR_RESET to DDR_CKE is currently ~135us and not the >500us required by JEDEC spec. The issue here is the REF_CTRL register performs two purposes. It is the counter for CKE to RESET delay before the DDR controller is initialized and used to configure the refresh rate after initialization of the controller. So to avoid inadvertently configuring the CKE to DDR delay, ensure we initialize the controller before we configure the refresh rate. Fixes: 69b918b65d11 ("am33xx,ddr3: fix ddr3 sdram configuration") Signed-off-by: Bryan Brattlof --- arch/arm/mach-omap2/am33xx/ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 41eec005cb1..a40813a99d8 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -185,10 +185,10 @@ void config_sdram(const struct emif_regs *regs, int nr) if (regs->zq_config) { writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); /* Trigger initialization */ writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); /* Wait 1ms because of L3 timeout error */ udelay(1000);