Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
This is a DRAM controller driver for the R-Car X5H and its enablement. This makes the U-Boot on RSIP usable beyond U-Boot shell running on Cortex-M33, as the U-Boot on RSIP can now load not only SCP firmware into the SCP core STCM, but also TFA BL31, OPTEE-OS and U-Boot into DRAM and start them on the Cortex-A720AE core. This is self-contained and affects only the R-Car X5H and a bit of R-Car V4H, besides it went through rounds of testing until now, therefore it is safe to include it this late in the release cycle. I know this will make rc5 massive, sorry about that.
This commit is contained in:
Tom Rini
@@ -65,10 +65,20 @@
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syscon = <&ctl>;
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};
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ram@b8940000 { /* RT-VRAM */
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compatible = "renesas,r8a78000-rtvram";
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reg = <0 0xb8940000 0 0xf000>;
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};
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scp@c1340000 {
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compatible = "renesas,r8a78000-rproc";
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reg = <0 0xc1340000 0 0x80000>;
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};
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ram@e9800000 { /* DBSC5 */
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compatible = "renesas,r8a78000-dbsc";
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reg = <0 0xe9800000 0 0x1000000>;
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};
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};
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&cpg {
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@@ -2,6 +2,7 @@ if RCAR_GEN5
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config RCAR_64_RSIP
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bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)"
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select LMB_ARCH_MEM_MAP
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select SKIP_RELOCATE_CODE
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select TMU_TIMER
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help
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@@ -904,6 +904,24 @@ static void mfis_unprotect(void)
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writel(MFIS_CODEVALUE, MFIS_WPCNTR);
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}
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/**
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* rsip_write_reg() - Write RSIP control register
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* @reg: Register to write
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* @val: Value to set in the register
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*/
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static void rsip_write_reg(const u32 reg, const int val)
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{
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for (;;) {
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writel(RSIP_CTL_PROT0PCMD_WREN, RSIP_CTL_PROT0PCMD);
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writel(val, reg);
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writel(~val, reg);
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writel(val, reg);
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if (readl(RSIP_CTL_PROT0PS) != RSIP_CTL_PROT0PS_ERR)
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break;
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}
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}
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/**
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* rsip_irq_setup() - Configure RSIP interrupts
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*/
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@@ -1353,6 +1371,26 @@ int mach_cpu_init(void)
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return 0;
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}
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int board_early_init_r(void)
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{
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u32 remaptmp = readl(RSIP_CTL_ESICREMAP0);
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struct udevice *dev;
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int ret;
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/* Remap DDR PHY during DRAM init. */
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rsip_write_reg(RSIP_CTL_ESICREMAP0, 0xe0000000);
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/* Start DBSC5 */
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ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e9800000", &dev);
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if (ret)
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printf("DBSC5 init failed: %d\n", ret);
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/* Restore remapping. */
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rsip_write_reg(RSIP_CTL_ESICREMAP0, remaptmp);
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return 0;
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}
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/**
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* board_debug_uart_init() - Initialize all HSCIF
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*/
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@@ -1407,3 +1445,14 @@ void __weak reset_cpu(void)
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writel(RST_KCPROT_DIS, RST_RESKCPROT0);
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writel(0x1, RST_SWSRES1A);
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}
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/**
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* lmb_arch_add_memory() - Add memory to LMB
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*
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* Add the window to a subset of 32bit DRAM are into LMB,
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* to make it possible to TFTP into it.
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*/
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void lmb_arch_add_memory(void)
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{
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lmb_add(0x60000000, 0x40000000);
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}
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@@ -5,7 +5,7 @@
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#include <asm/io.h>
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#include <compiler.h>
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#include <dbsc5.h>
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#include <r8a779g0-dbsc5.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <spl.h>
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@@ -17,9 +17,14 @@ CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET=0xa0000000
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_BAUDRATE=1843200
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CONFIG_BOOTCOMMAND=""
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_BOOTCOMMAND="run rsip_ipl_boot_ca0"
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CONFIG_BOUNCE_BUFFER=y
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CONFIG_CMD_IMI=y
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CONFIG_CMD_PSTORE=y
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CONFIG_CMD_PSTORE_MEM_ADDR=0x80000000
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CONFIG_CMD_PSTORE_RECORD_SIZE=0x400
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CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x8000
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CONFIG_CMD_REMOTEPROC=y
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CONFIG_CMD_UFS=y
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CONFIG_DM_DMA=y
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@@ -37,6 +42,7 @@ CONFIG_PHY_R8A78000_MP_PHY=y
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CONFIG_PHY_TI_DP83869=y
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CONFIG_POWER_DOMAIN=y
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CONFIG_RAM=y
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CONFIG_RAM_RENESAS_DBSC5=y
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CONFIG_REMOTEPROC_RENESAS_RSIP=y
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CONFIG_RENESAS_ETHER_SWITCH=y
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CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y
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@@ -1,7 +1,7 @@
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config RAM_RENESAS_DBSC5
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bool "Renesas R-Car V4H/V4M DBSC5 controller driver"
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depends on SPL && RAM && (R8A779G0 || R8A779H0)
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bool "Renesas R-Car V4H/V4M/X5H DBSC5 controller driver"
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depends on RAM && (R8A78000 || (SPL && (R8A779G0 || R8A779H0)))
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default n
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help
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Enable this to support the DBSC5 DRAM controller initialization
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on Renesas R8A779G0/R8A779H0 SoCs.
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on Renesas R8A779G0/R8A779H0/R8A78000 SoCs.
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@@ -1,6 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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ifdef CONFIG_XPL_BUILD
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obj-$(CONFIG_RAM_RENESAS_DBSC5) += dbsc5/
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endif
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obj-$(CONFIG_RZN1) += rzn1/
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@@ -1,3 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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obj-y += dbsc5.o dram.o qos.o rtvram.o
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obj-$(CONFIG_R8A779G0) += r8a779g0-dbsc5.o r8a779g0-dram.o qos.o
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obj-$(CONFIG_R8A78000) += r8a78000-dbsc5.o r8a78000-dram.o ecc.o
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obj-y += rtvram.o
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@@ -0,0 +1,168 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2026 Renesas Electronics Corp.
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*/
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#include <asm/io.h>
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#include <dm.h>
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#include <errno.h>
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#include <ram.h>
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#include <linux/sizes.h>
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#define DBSC5_DBSC_CNT 8
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#define DBSC_D_BASE(n) (0xe9900000 + ((n) * 0x4000))
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#define DBSC_A_BASE(n) (0xe9800000 + ((n) * 0x8000))
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#define DBSYSCNT 0x100
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#define DBACEN 0x200
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#define DBFSINTENB02A 0x7088
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#define DBFSINTENB04A 0x7090
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#define DBFSCONFAXI0 0x7400
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#define DBFSDRAMECCAREA00 0x7450
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#define DBFSCTRL01A 0x7604
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#define DBFSCONF00A 0x7640
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#define DBFSCONF01A 0x7644
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#define DBFSCONF02A 0x7648
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#define DBFSSTAT00A 0x7680
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#define DBFSSTAT01A 0x7684
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#define DBSYSCNT_ENABLE 0x1234
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#define DBSYSCNT_DISABLE 0x0
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#define DBACEN_ACCESS_DISABLE 0
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#define DBACEN_ACCESS_ENABLE 1
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#define ECM_BASE 0xb89a0000
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#define ECMERRCTLR0 (ECM_BASE + 0x0)
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#define ECMERRINCR0 (ECM_BASE + 0x200)
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#define ECMERROMKR0 (ECM_BASE + 0x600)
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#define ECMERRCTLR6 (ECM_BASE + (0x4 * 6))
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#define ECMERRINCR6 (ECM_BASE + 0x200U + (0x4 * 6))
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#define ECMERROMKR6 (ECM_BASE + 0x600U + (0x4 * 6))
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#define ECMWPCNTR (ECM_BASE + 0xa00)
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#define ECMWACNTR (ECM_BASE + 0xa04)
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struct renesas_dbsc5_ecc_priv {
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void __iomem *regs;
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};
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static void ecm_reg_unlock(void)
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{
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writel(0xacce0001, ECMWPCNTR);
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}
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static void ecm_reg_lock(void)
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{
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writel(0xacce0000, ECMWPCNTR);
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}
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static void ecm_reg_write(u32 adr, u32 val)
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{
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writel(0xacce0000 | (adr & 0xffff), ECMWACNTR);
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writel(val, adr);
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}
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static int renesas_dbsc5_ecc_probe(struct udevice *dev)
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{
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int i;
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ecm_reg_unlock();
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for (i = 0; i < DBSC5_DBSC_CNT; i++) {
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writel(DBSYSCNT_ENABLE, DBSC_D_BASE(i) + DBSYSCNT);
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writel(DBSYSCNT_ENABLE, DBSC_A_BASE(i) + DBSYSCNT);
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}
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ecm_reg_write(ECMERRINCR0, readl(ECMERRINCR0) | 0xAAA);
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ecm_reg_write(ECMERROMKR0, readl(ECMERROMKR0) | 0xAAA);
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ecm_reg_write(ECMERRCTLR0, readl(ECMERRCTLR0) | 0xAAA);
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ecm_reg_write(ECMERRINCR6, readl(ECMERRINCR6) | 0xA000);
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ecm_reg_write(ECMERROMKR6, readl(ECMERROMKR6) | 0xA000);
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ecm_reg_write(ECMERRCTLR6, readl(ECMERRCTLR6) | 0xA000);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0xcccc, DBSC_A_BASE(i) + DBFSDRAMECCAREA00);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(DBACEN_ACCESS_DISABLE, DBSC_A_BASE(i) + DBACEN);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0, DBSC_A_BASE(i) + DBFSCONF00A);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0, DBSC_A_BASE(i) + DBFSCONF01A);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0xcccb, DBSC_A_BASE(i) + DBFSCONF02A);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0x1, DBSC_A_BASE(i) + DBFSCTRL01A);
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u32 fsstat;
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do {
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fsstat = 0x1;
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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fsstat &= readl(DBSC_A_BASE(i) + DBFSSTAT01A);
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} while (!(fsstat & 0x1));
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(DBACEN_ACCESS_ENABLE, DBSC_A_BASE(i) + DBACEN);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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setbits_le32(DBSC_A_BASE(i) + DBFSCONFAXI0, 0x100);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0xff00ff00, DBSC_A_BASE(i) + DBFSINTENB02A);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0xffffffff, DBSC_A_BASE(i) + DBFSINTENB04A);
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ecm_reg_lock();
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for (i = 0; i < DBSC5_DBSC_CNT; i++) {
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writel(DBSYSCNT_DISABLE, DBSC_D_BASE(i) + DBSYSCNT);
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writel(DBSYSCNT_DISABLE, DBSC_A_BASE(i) + DBSYSCNT);
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}
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return 0;
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}
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static int renesas_dbsc5_ecc_of_to_plat(struct udevice *dev)
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{
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struct renesas_dbsc5_ecc_priv *priv = dev_get_priv(dev);
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priv->regs = dev_read_addr_ptr(dev);
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if (!priv->regs)
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return -EINVAL;
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return 0;
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}
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static int renesas_dbsc5_ecc_get_info(struct udevice *dev,
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struct ram_info *info)
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{
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struct renesas_dbsc5_ecc_priv *priv = dev_get_priv(dev);
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info->base = (phys_addr_t)priv->regs;
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info->size = 32 * SZ_1M;
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return 0;
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}
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|
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static const struct ram_ops renesas_dbsc5_ecc_ops = {
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.get_info = renesas_dbsc5_ecc_get_info,
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};
|
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|
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static const struct udevice_id renesas_dbsc5_ecc_ids[] = {
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{ .compatible = "renesas,r8a78000-ecc" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(renesas_dbsc5_ecc) = {
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.name = "dbsc5_ecc",
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.id = UCLASS_RAM,
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.of_match = renesas_dbsc5_ecc_ids,
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.of_to_plat = renesas_dbsc5_ecc_of_to_plat,
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.ops = &renesas_dbsc5_ecc_ops,
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.probe = renesas_dbsc5_ecc_probe,
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.priv_auto = sizeof(struct renesas_dbsc5_ecc_priv),
|
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};
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@@ -9,7 +9,7 @@
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||||
#include <hang.h>
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#include <linux/sizes.h>
|
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#include <ram.h>
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#include "dbsc5.h"
|
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#include "r8a779g0-dbsc5.h"
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|
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/* AXMM */
|
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#define AXMM_ADSPLCR0 0x4008
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@@ -10,7 +10,7 @@
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||||
#include <errno.h>
|
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#include <linux/sizes.h>
|
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#include <ram.h>
|
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#include "dbsc5.h"
|
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#include "r8a779g0-dbsc5.h"
|
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|
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static int renesas_dbsc5_probe(struct udevice *dev)
|
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{
|
||||
@@ -3,8 +3,8 @@
|
||||
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__
|
||||
#define __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__
|
||||
#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__
|
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#define __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__
|
||||
|
||||
/*
|
||||
* DBSC5 ... 0xe678_0000..0xe67fffff
|
||||
@@ -26,4 +26,4 @@ struct renesas_dbsc5_data {
|
||||
const char *otp_node;
|
||||
};
|
||||
|
||||
#endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */
|
||||
#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__ */
|
||||
@@ -4,14 +4,14 @@
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <dbsc5.h>
|
||||
#include <r8a779g0-dbsc5.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <hang.h>
|
||||
#include <ram.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/sizes.h>
|
||||
#include "dbsc5.h"
|
||||
#include "r8a779g0-dbsc5.h"
|
||||
|
||||
/* Number of array elements in Data Slice */
|
||||
#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100
|
||||
@@ -0,0 +1,76 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2026 Renesas Electronics Corp.
|
||||
*
|
||||
* Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/lists.h>
|
||||
#include <errno.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <ram.h>
|
||||
#include "r8a78000-dbsc5.h"
|
||||
|
||||
static int renesas_dbsc5_probe(struct udevice *dev)
|
||||
{
|
||||
struct udevice *ddev, *vdev, *edev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_dram", &ddev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = uclass_get_device_by_name(UCLASS_RAM, "ram@b8940000", &vdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_ecc", &edev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int renesas_dbsc5_bind(struct udevice *dev)
|
||||
{
|
||||
struct udevice *ramdev, *eccdev;
|
||||
struct driver *ramdrv, *eccdrv;
|
||||
int ret;
|
||||
|
||||
ramdrv = lists_driver_lookup_name("dbsc5_dram");
|
||||
if (!ramdrv)
|
||||
return -ENOENT;
|
||||
|
||||
eccdrv = lists_driver_lookup_name("dbsc5_ecc");
|
||||
if (!eccdrv)
|
||||
return -ENOENT;
|
||||
|
||||
ret = device_bind_with_driver_data(dev, ramdrv, "dbsc5_dram",
|
||||
dev_get_driver_data(dev),
|
||||
dev_ofnode(dev), &ramdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = device_bind_with_driver_data(dev, eccdrv, "dbsc5_ecc", 0,
|
||||
dev_ofnode(dev), &eccdev);
|
||||
if (ret)
|
||||
device_unbind(ramdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct udevice_id renesas_dbsc5_ids[] = {
|
||||
{ .compatible = "renesas,r8a78000-dbsc", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(renesas_dbsc5) = {
|
||||
.name = "dbsc5",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = renesas_dbsc5_ids,
|
||||
.bind = renesas_dbsc5_bind,
|
||||
.probe = renesas_dbsc5_probe,
|
||||
};
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2026 Renesas Electronics Corp.
|
||||
*
|
||||
* Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__
|
||||
#define __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__
|
||||
|
||||
struct renesas_dbsc5_data {
|
||||
const char *clock_node;
|
||||
const char *reset_node;
|
||||
const char *otp_node;
|
||||
};
|
||||
|
||||
#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -13,34 +13,41 @@
|
||||
#define RTVRAM_VBUF_CFG 0x6504
|
||||
#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1 << 8)
|
||||
#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6 << 0)
|
||||
#define RTVRAM_VBUF_CFG_VBUF_SIZE_32M (7 << 0)
|
||||
#define RTVRAM_EXT_MODE 0x8500
|
||||
#define RTVRAM_EXT_MODE_EXT BIT(0)
|
||||
#define RTVRAM_VBUF_BADDR 0xC580
|
||||
|
||||
#define RTVRAM_VBUF_NUM 7
|
||||
|
||||
#define SDRAM_40BIT_ADDR_TOP 0x0400000000ULL
|
||||
#define RTVRAM_VBUF_AREA_SIZE SZ_4M
|
||||
|
||||
struct renesas_dbsc5_rtvram_priv {
|
||||
void __iomem *regs;
|
||||
};
|
||||
|
||||
struct renesas_dbsc5_rtvram_data {
|
||||
u8 sdram_40bit_addr_top; /* Left-shift by 32 */
|
||||
u8 vbuf_num;
|
||||
u8 size;
|
||||
u8 size_bit;
|
||||
};
|
||||
|
||||
static int renesas_dbsc5_rtvram_probe(struct udevice *dev)
|
||||
{
|
||||
struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev);
|
||||
struct renesas_dbsc5_rtvram_data *data =
|
||||
(struct renesas_dbsc5_rtvram_data *)dev_get_driver_data(dev);
|
||||
u64 addr;
|
||||
int i;
|
||||
|
||||
/* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */
|
||||
for (i = 0; i < RTVRAM_VBUF_NUM; i++) {
|
||||
addr = (SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16;
|
||||
for (i = 0; i < data->vbuf_num + 1; i++) {
|
||||
addr = (((u64)(data->sdram_40bit_addr_top) << 32ULL) + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16;
|
||||
writel(lower_32_bits(addr), priv->regs + (RTVRAM_VBUF_BADDR + (4 * i)));
|
||||
}
|
||||
|
||||
/* Cache Mode: 8-way, VBF size: 28M */
|
||||
setbits_le32(priv->regs + RTVRAM_VBUF_CFG,
|
||||
RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M);
|
||||
RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | data->size_bit);
|
||||
|
||||
/* Change from Compatible Mode to Extended Mode */
|
||||
writel(RTVRAM_EXT_MODE_EXT, priv->regs + RTVRAM_EXT_MODE);
|
||||
@@ -65,9 +72,11 @@ static int renesas_dbsc5_rtvram_get_info(struct udevice *dev,
|
||||
struct ram_info *info)
|
||||
{
|
||||
struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev);
|
||||
struct renesas_dbsc5_rtvram_data *data =
|
||||
(struct renesas_dbsc5_rtvram_data *)dev_get_driver_data(dev);
|
||||
|
||||
info->base = (phys_addr_t)priv->regs;
|
||||
info->size = 28 * SZ_1M;
|
||||
info->size = data->size * SZ_1M;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -76,14 +85,29 @@ static const struct ram_ops renesas_dbsc5_rtvram_ops = {
|
||||
.get_info = renesas_dbsc5_rtvram_get_info,
|
||||
};
|
||||
|
||||
struct renesas_dbsc5_rtvram_data gen4_rtvram_data = {
|
||||
.sdram_40bit_addr_top = 0x4,
|
||||
.vbuf_num = 7,
|
||||
.size = 28,
|
||||
.size_bit = RTVRAM_VBUF_CFG_VBUF_SIZE_28M,
|
||||
};
|
||||
|
||||
struct renesas_dbsc5_rtvram_data gen5_rtvram_data = {
|
||||
.sdram_40bit_addr_top = 0x12,
|
||||
.vbuf_num = 8,
|
||||
.size = 32,
|
||||
.size_bit = RTVRAM_VBUF_CFG_VBUF_SIZE_32M,
|
||||
};
|
||||
|
||||
static const struct udevice_id renesas_dbsc5_rtvram_ids[] = {
|
||||
{ .compatible = "renesas,r8a779g0-rtvram" },
|
||||
{ .compatible = "renesas,r8a779h0-rtvram" },
|
||||
{ .compatible = "renesas,r8a779g0-rtvram", .data = (ulong)&gen4_rtvram_data },
|
||||
{ .compatible = "renesas,r8a779h0-rtvram", .data = (ulong)&gen4_rtvram_data },
|
||||
{ .compatible = "renesas,r8a78000-rtvram", .data = (ulong)&gen5_rtvram_data },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(renesas_dbsc5_rtvram) = {
|
||||
.name = "rtvram",
|
||||
.name = "dbsc5_rtvram",
|
||||
.id = UCLASS_RAM,
|
||||
.of_match = renesas_dbsc5_rtvram_ids,
|
||||
.of_to_plat = renesas_dbsc5_rtvram_of_to_plat,
|
||||
|
||||
@@ -26,10 +26,50 @@
|
||||
#if defined(CONFIG_RCAR_64_RSIP)
|
||||
#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
|
||||
#define CFG_SYS_TIMER_RATE (133333333 / 4)
|
||||
#endif
|
||||
|
||||
/* Environment setting */
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"rsip_ipl_params_base=0x8c100000\0" \
|
||||
"rsip_ipl_params_optee=0x8c100088\0" \
|
||||
"rsip_ipl_params_uboot=0x8c100030\0" \
|
||||
"rsip_ipl_optee_ep=0x8c400000\0" \
|
||||
"rsip_ipl_tfa_ep=0x8c200000\0" \
|
||||
"rsip_ipl_uboot_ep=0x8e300000\0" \
|
||||
"rsip_ipl_params_write=" \
|
||||
"base ${rsip_ipl_params_base} ; " \
|
||||
"mw 0x00 0 0x9e ; " /* Clear the area */ \
|
||||
"mw 0x00 0x00300103 ; " /* type, version, size */ \
|
||||
"mw 0x20 0x${rsip_ipl_params_uboot} ; " /* U-Boot descriptor */ \
|
||||
"" \
|
||||
"base ${rsip_ipl_params_uboot} ; " \
|
||||
"mw 0x00 0x00580101 ; " /* type, version, size */ \
|
||||
"mw 0x04 0x00000001 ; " /* attr */ \
|
||||
"mw 0x08 ${rsip_ipl_uboot_ep} ; " /* U-Boot entry point */ \
|
||||
"mw 0x10 0x000003c5 ; " /* SPSR */ \
|
||||
"" \
|
||||
"base ${rsip_ipl_params_optee} ; " \
|
||||
"mw 0x00 0x00580201 ; " /* type, version, size */ \
|
||||
"mw 0x04 0x00000008 ; " /* attr */ \
|
||||
"mw 0x08 ${rsip_ipl_optee_ep} ; " /* OPTEE-OS entry point */ \
|
||||
"mw 0x10 0x000003c5 ; " /* SPSR */ \
|
||||
"" \
|
||||
"base 0\0" \
|
||||
"rsip_ipl_boot_ca0=" /* Start TFA BL31, OPTEE-OS, U-Boot on Cortex-A720AE core 0 */ \
|
||||
"scsi scan && " /* Scan for UFS devices */ \
|
||||
"rproc init && " /* Start remoteproc */ \
|
||||
"rproc load 0 0x344c0000 0x60000 && " /* Load SCP from HF */ \
|
||||
"rproc start 0 && " /* Start SCP */ \
|
||||
"scsi read ${rsip_ipl_uboot_ep} 0x7200 0x100 && " /* Load U-Boot from UFS */ \
|
||||
"scsi read ${rsip_ipl_optee_ep} 0x5200 0x200 && " /* Load OPTEE-OS from UFS */ \
|
||||
"scsi read ${rsip_ipl_tfa_ep} 0x5000 0x40 && " /* Load TFA BL31 from UFS */ \
|
||||
"run rsip_ipl_params_write && " /* Write entry point descriptors */ \
|
||||
"rproc load 13 ${rsip_ipl_tfa_ep} 4 && " /* Set up Cortex-A720AE Core 0 */ \
|
||||
"rproc start 13\0" /* Start Cortex-A720AE Core 0 */
|
||||
|
||||
#else
|
||||
/* Environment setting */
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"bootm_size=0x10000000\0"
|
||||
#endif
|
||||
|
||||
#endif /* __RCAR_GEN5_COMMON_H */
|
||||
|
||||
@@ -0,0 +1,63 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2026 Renesas Electronics Corp.
|
||||
*
|
||||
* Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_DBSC5_H__
|
||||
#define __INCLUDE_DBSC5_H__
|
||||
|
||||
/* The number of channels X5H has */
|
||||
#define DRAM_CH_CNT 16
|
||||
/* The number of slices X5H has */
|
||||
#define SLICE_CNT 2
|
||||
/* The number of chip select X5H has */
|
||||
#define CS_CNT 2
|
||||
|
||||
struct renesas_dbsc5_board_config {
|
||||
u32 bdcfg_phyvalid;
|
||||
u32 bdcfg_tx_drv;
|
||||
u32 bdcfg_tx_ffc;
|
||||
u32 bdcfg_rx_odt;
|
||||
u8 bdcfg_rx_dfe;
|
||||
u8 bdcfg_tx_odt;
|
||||
u8 bdcfg_tx_ntodt;
|
||||
u8 bdcfg_tx_dfe;
|
||||
u8 bdcfg_rx_dca;
|
||||
u8 bdcfg_rx_drv;
|
||||
u32 bdcfg_rx_emphasis;
|
||||
u8 bdcfg_tx_dca;
|
||||
u8 bdcfg_ca_vref;
|
||||
u32 bdcfg_rx_vref;
|
||||
u32 bdcfg_rx_vref_step;
|
||||
u32 bdcfg_tx_vref;
|
||||
u8 bdcfg_rfm_chk;
|
||||
|
||||
/* Board parameter about channels */
|
||||
struct {
|
||||
/*
|
||||
* 0x00: 4Gb dual channel die / 2Gb single channel die
|
||||
* 0x01: 6Gb dual channel die / 3Gb single channel die
|
||||
* 0x02: 8Gb dual channel die / 4Gb single channel die
|
||||
* 0x03: 12Gb dual channel die / 6Gb single channel die
|
||||
* 0x04: 16Gb dual channel die / 8Gb single channel die
|
||||
* 0x05: 24Gb dual channel die / 12Gb single channel die
|
||||
* 0x06: 32Gb dual channel die / 16Gb single channel die
|
||||
* 0x07: 24Gb single channel die
|
||||
* 0x08: 32Gb single channel die
|
||||
* 0xFF: NO_MEMORY
|
||||
*/
|
||||
u8 bdcfg_ddr_density[CS_CNT];
|
||||
/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
|
||||
u32 bdcfg_ca_swap;
|
||||
/* SoC dqsX([1][0]) -> MEM dqsY: */
|
||||
u8 bdcfg_dqs_swap;
|
||||
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
|
||||
u32 bdcfg_dq_swap[SLICE_CNT];
|
||||
/* SoC dm -> MEM dqY/dm: (8 means DM) */
|
||||
u8 bdcfg_dm_swap[SLICE_CNT];
|
||||
} ch[DRAM_CH_CNT];
|
||||
};
|
||||
|
||||
#endif /* __INCLUDE_DBSC5_H__ */
|
||||
Reference in New Issue
Block a user