arm: dts: renesas: Enable DBSC5 on R-Car R8A78000 X5H Cortex-M33 RSIP port
Bind the DBSC5 DRAM controller driver on boot in board_early_init_r(), which brings up the DBSC5 DRAM controller and its PHY and which enables access to DRAM present on this system. Add default boot command which loads additional bootloader components from HF and UFS storage into SRAM and DRAM, and starts those components on SCP and AP core 0. The system is then capable of reaching U-Boot on the AP core 0. Specifically, the following components are loaded: - SCP firmware, 384 kiB from HF offset 0x4c0000 to SCP STCM - TFA BL31, 256 kiB from UFS0 offset 0x5000 * 4 kiB sectors to DRAM 0x8c200000 - TEE, 2 MiB from UFS0 offset 0x5200 * 4 kiB sectors to DRAM 0x8c400000 - U-Boot, 1 MiB from UFS0 offset 0x7200 * 4 kiB sectors to DRAM 0x8c300000 - IPL parameters table is generated at DRAM address 0x8c100000 Enable pstore command support to allow dumping kernel console from pstore/ramoops, which is convenient for debugging. Use as follows: => pstore set 0x80000000 0x10000 0x400 0x8000 0 0 0 => pstore display console Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
@@ -65,10 +65,20 @@
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syscon = <&ctl>;
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};
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ram@b8940000 { /* RT-VRAM */
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compatible = "renesas,r8a78000-rtvram";
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reg = <0 0xb8940000 0 0xf000>;
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};
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scp@c1340000 {
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compatible = "renesas,r8a78000-rproc";
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reg = <0 0xc1340000 0 0x80000>;
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};
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ram@e9800000 { /* DBSC5 */
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compatible = "renesas,r8a78000-dbsc";
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reg = <0 0xe9800000 0 0x1000000>;
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};
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};
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&cpg {
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@@ -2,6 +2,7 @@ if RCAR_GEN5
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config RCAR_64_RSIP
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bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)"
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select LMB_ARCH_MEM_MAP
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select SKIP_RELOCATE_CODE
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select TMU_TIMER
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help
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@@ -904,6 +904,24 @@ static void mfis_unprotect(void)
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writel(MFIS_CODEVALUE, MFIS_WPCNTR);
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}
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/**
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* rsip_write_reg() - Write RSIP control register
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* @reg: Register to write
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* @val: Value to set in the register
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*/
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static void rsip_write_reg(const u32 reg, const int val)
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{
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for (;;) {
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writel(RSIP_CTL_PROT0PCMD_WREN, RSIP_CTL_PROT0PCMD);
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writel(val, reg);
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writel(~val, reg);
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writel(val, reg);
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if (readl(RSIP_CTL_PROT0PS) != RSIP_CTL_PROT0PS_ERR)
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break;
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}
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}
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/**
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* rsip_irq_setup() - Configure RSIP interrupts
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*/
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@@ -1353,6 +1371,26 @@ int mach_cpu_init(void)
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return 0;
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}
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int board_early_init_r(void)
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{
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u32 remaptmp = readl(RSIP_CTL_ESICREMAP0);
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struct udevice *dev;
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int ret;
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/* Remap DDR PHY during DRAM init. */
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rsip_write_reg(RSIP_CTL_ESICREMAP0, 0xe0000000);
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/* Start DBSC5 */
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ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e9800000", &dev);
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if (ret)
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printf("DBSC5 init failed: %d\n", ret);
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/* Restore remapping. */
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rsip_write_reg(RSIP_CTL_ESICREMAP0, remaptmp);
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return 0;
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}
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/**
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* board_debug_uart_init() - Initialize all HSCIF
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*/
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@@ -1407,3 +1445,14 @@ void __weak reset_cpu(void)
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writel(RST_KCPROT_DIS, RST_RESKCPROT0);
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writel(0x1, RST_SWSRES1A);
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}
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/**
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* lmb_arch_add_memory() - Add memory to LMB
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*
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* Add the window to a subset of 32bit DRAM are into LMB,
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* to make it possible to TFTP into it.
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*/
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void lmb_arch_add_memory(void)
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{
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lmb_add(0x60000000, 0x40000000);
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}
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@@ -17,9 +17,14 @@ CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET=0xa0000000
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_BAUDRATE=1843200
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CONFIG_BOOTCOMMAND=""
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_BOOTCOMMAND="run rsip_ipl_boot_ca0"
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CONFIG_BOUNCE_BUFFER=y
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CONFIG_CMD_IMI=y
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CONFIG_CMD_PSTORE=y
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CONFIG_CMD_PSTORE_MEM_ADDR=0x80000000
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CONFIG_CMD_PSTORE_RECORD_SIZE=0x400
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CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x8000
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CONFIG_CMD_REMOTEPROC=y
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CONFIG_CMD_UFS=y
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CONFIG_DM_DMA=y
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@@ -37,6 +42,7 @@ CONFIG_PHY_R8A78000_MP_PHY=y
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CONFIG_PHY_TI_DP83869=y
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CONFIG_POWER_DOMAIN=y
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CONFIG_RAM=y
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CONFIG_RAM_RENESAS_DBSC5=y
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CONFIG_REMOTEPROC_RENESAS_RSIP=y
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CONFIG_RENESAS_ETHER_SWITCH=y
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CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y
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@@ -26,10 +26,50 @@
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#if defined(CONFIG_RCAR_64_RSIP)
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#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
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#define CFG_SYS_TIMER_RATE (133333333 / 4)
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#endif
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/* Environment setting */
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#define CFG_EXTRA_ENV_SETTINGS \
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"rsip_ipl_params_base=0x8c100000\0" \
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"rsip_ipl_params_optee=0x8c100088\0" \
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"rsip_ipl_params_uboot=0x8c100030\0" \
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"rsip_ipl_optee_ep=0x8c400000\0" \
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"rsip_ipl_tfa_ep=0x8c200000\0" \
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"rsip_ipl_uboot_ep=0x8e300000\0" \
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"rsip_ipl_params_write=" \
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"base ${rsip_ipl_params_base} ; " \
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"mw 0x00 0 0x9e ; " /* Clear the area */ \
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"mw 0x00 0x00300103 ; " /* type, version, size */ \
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"mw 0x20 0x${rsip_ipl_params_uboot} ; " /* U-Boot descriptor */ \
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"" \
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"base ${rsip_ipl_params_uboot} ; " \
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"mw 0x00 0x00580101 ; " /* type, version, size */ \
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"mw 0x04 0x00000001 ; " /* attr */ \
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"mw 0x08 ${rsip_ipl_uboot_ep} ; " /* U-Boot entry point */ \
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"mw 0x10 0x000003c5 ; " /* SPSR */ \
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"" \
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"base ${rsip_ipl_params_optee} ; " \
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"mw 0x00 0x00580201 ; " /* type, version, size */ \
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"mw 0x04 0x00000008 ; " /* attr */ \
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"mw 0x08 ${rsip_ipl_optee_ep} ; " /* OPTEE-OS entry point */ \
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"mw 0x10 0x000003c5 ; " /* SPSR */ \
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"" \
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"base 0\0" \
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"rsip_ipl_boot_ca0=" /* Start TFA BL31, OPTEE-OS, U-Boot on Cortex-A720AE core 0 */ \
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"scsi scan && " /* Scan for UFS devices */ \
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"rproc init && " /* Start remoteproc */ \
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"rproc load 0 0x344c0000 0x60000 && " /* Load SCP from HF */ \
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"rproc start 0 && " /* Start SCP */ \
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"scsi read ${rsip_ipl_uboot_ep} 0x7200 0x100 && " /* Load U-Boot from UFS */ \
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"scsi read ${rsip_ipl_optee_ep} 0x5200 0x200 && " /* Load OPTEE-OS from UFS */ \
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"scsi read ${rsip_ipl_tfa_ep} 0x5000 0x40 && " /* Load TFA BL31 from UFS */ \
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"run rsip_ipl_params_write && " /* Write entry point descriptors */ \
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"rproc load 13 ${rsip_ipl_tfa_ep} 4 && " /* Set up Cortex-A720AE Core 0 */ \
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"rproc start 13\0" /* Start Cortex-A720AE Core 0 */
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#else
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/* Environment setting */
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#define CFG_EXTRA_ENV_SETTINGS \
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"bootm_size=0x10000000\0"
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#endif
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#endif /* __RCAR_GEN5_COMMON_H */
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