ram: renesas: dbsc5: Add Renesas R-Car Gen5 DBSC5 driver
Add Renesas R-Car Gen5 DBSC5 DRAM controller driver. This driver is currently capable of bringing LPDDR5X DRAM on Renesas R-Car X5H Ironhide board. Further boards can be supported by supplying board specific DRAM configuration data via dbsc5_get_board_data(). The driver reuses parts of previous DBSC5 driver, but due to hardware changes, can not be fully integrated into existing DBSC and DRAM driver, therefore the currentl DBSC and DRAM drivers are moved into R8A779G0 V4H specific files, and the R8A78000 X5H files are added in parallel. The Gen5 DBSC driver is meant to be used in RSIP context, while the Gen4 DBSC driver is meant to be used in SPL, therefore the Kconfig conditionals have been adjusted to match. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
@@ -5,7 +5,7 @@
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#include <asm/io.h>
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#include <compiler.h>
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#include <dbsc5.h>
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#include <r8a779g0-dbsc5.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <spl.h>
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@@ -1,7 +1,7 @@
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config RAM_RENESAS_DBSC5
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bool "Renesas R-Car V4H/V4M DBSC5 controller driver"
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depends on SPL && RAM && (R8A779G0 || R8A779H0)
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bool "Renesas R-Car V4H/V4M/X5H DBSC5 controller driver"
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depends on RAM && (R8A78000 || (SPL && (R8A779G0 || R8A779H0)))
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default n
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help
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Enable this to support the DBSC5 DRAM controller initialization
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on Renesas R8A779G0/R8A779H0 SoCs.
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on Renesas R8A779G0/R8A779H0/R8A78000 SoCs.
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@@ -1,6 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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ifdef CONFIG_XPL_BUILD
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obj-$(CONFIG_RAM_RENESAS_DBSC5) += dbsc5/
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endif
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obj-$(CONFIG_RZN1) += rzn1/
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@@ -1,3 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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obj-y += dbsc5.o dram.o qos.o rtvram.o
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obj-$(CONFIG_R8A779G0) += r8a779g0-dbsc5.o r8a779g0-dram.o qos.o
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obj-$(CONFIG_R8A78000) += r8a78000-dbsc5.o r8a78000-dram.o ecc.o
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obj-y += rtvram.o
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@@ -0,0 +1,168 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2026 Renesas Electronics Corp.
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*/
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#include <asm/io.h>
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#include <dm.h>
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#include <errno.h>
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#include <ram.h>
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#include <linux/sizes.h>
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#define DBSC5_DBSC_CNT 8
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#define DBSC_D_BASE(n) (0xe9900000 + ((n) * 0x4000))
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#define DBSC_A_BASE(n) (0xe9800000 + ((n) * 0x8000))
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#define DBSYSCNT 0x100
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#define DBACEN 0x200
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#define DBFSINTENB02A 0x7088
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#define DBFSINTENB04A 0x7090
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#define DBFSCONFAXI0 0x7400
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#define DBFSDRAMECCAREA00 0x7450
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#define DBFSCTRL01A 0x7604
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#define DBFSCONF00A 0x7640
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#define DBFSCONF01A 0x7644
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#define DBFSCONF02A 0x7648
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#define DBFSSTAT00A 0x7680
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#define DBFSSTAT01A 0x7684
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#define DBSYSCNT_ENABLE 0x1234
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#define DBSYSCNT_DISABLE 0x0
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#define DBACEN_ACCESS_DISABLE 0
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#define DBACEN_ACCESS_ENABLE 1
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#define ECM_BASE 0xb89a0000
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#define ECMERRCTLR0 (ECM_BASE + 0x0)
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#define ECMERRINCR0 (ECM_BASE + 0x200)
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#define ECMERROMKR0 (ECM_BASE + 0x600)
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#define ECMERRCTLR6 (ECM_BASE + (0x4 * 6))
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#define ECMERRINCR6 (ECM_BASE + 0x200U + (0x4 * 6))
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#define ECMERROMKR6 (ECM_BASE + 0x600U + (0x4 * 6))
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#define ECMWPCNTR (ECM_BASE + 0xa00)
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#define ECMWACNTR (ECM_BASE + 0xa04)
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struct renesas_dbsc5_ecc_priv {
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void __iomem *regs;
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};
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static void ecm_reg_unlock(void)
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{
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writel(0xacce0001, ECMWPCNTR);
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}
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static void ecm_reg_lock(void)
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{
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writel(0xacce0000, ECMWPCNTR);
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}
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static void ecm_reg_write(u32 adr, u32 val)
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{
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writel(0xacce0000 | (adr & 0xffff), ECMWACNTR);
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writel(val, adr);
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}
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static int renesas_dbsc5_ecc_probe(struct udevice *dev)
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{
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int i;
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ecm_reg_unlock();
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for (i = 0; i < DBSC5_DBSC_CNT; i++) {
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writel(DBSYSCNT_ENABLE, DBSC_D_BASE(i) + DBSYSCNT);
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writel(DBSYSCNT_ENABLE, DBSC_A_BASE(i) + DBSYSCNT);
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}
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ecm_reg_write(ECMERRINCR0, readl(ECMERRINCR0) | 0xAAA);
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ecm_reg_write(ECMERROMKR0, readl(ECMERROMKR0) | 0xAAA);
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ecm_reg_write(ECMERRCTLR0, readl(ECMERRCTLR0) | 0xAAA);
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ecm_reg_write(ECMERRINCR6, readl(ECMERRINCR6) | 0xA000);
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ecm_reg_write(ECMERROMKR6, readl(ECMERROMKR6) | 0xA000);
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ecm_reg_write(ECMERRCTLR6, readl(ECMERRCTLR6) | 0xA000);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0xcccc, DBSC_A_BASE(i) + DBFSDRAMECCAREA00);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(DBACEN_ACCESS_DISABLE, DBSC_A_BASE(i) + DBACEN);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0, DBSC_A_BASE(i) + DBFSCONF00A);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0, DBSC_A_BASE(i) + DBFSCONF01A);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0xcccb, DBSC_A_BASE(i) + DBFSCONF02A);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0x1, DBSC_A_BASE(i) + DBFSCTRL01A);
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u32 fsstat;
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do {
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fsstat = 0x1;
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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fsstat &= readl(DBSC_A_BASE(i) + DBFSSTAT01A);
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} while (!(fsstat & 0x1));
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(DBACEN_ACCESS_ENABLE, DBSC_A_BASE(i) + DBACEN);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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setbits_le32(DBSC_A_BASE(i) + DBFSCONFAXI0, 0x100);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0xff00ff00, DBSC_A_BASE(i) + DBFSINTENB02A);
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for (i = 0; i < DBSC5_DBSC_CNT; i++)
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writel(0xffffffff, DBSC_A_BASE(i) + DBFSINTENB04A);
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ecm_reg_lock();
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for (i = 0; i < DBSC5_DBSC_CNT; i++) {
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writel(DBSYSCNT_DISABLE, DBSC_D_BASE(i) + DBSYSCNT);
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writel(DBSYSCNT_DISABLE, DBSC_A_BASE(i) + DBSYSCNT);
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}
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return 0;
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}
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static int renesas_dbsc5_ecc_of_to_plat(struct udevice *dev)
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{
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struct renesas_dbsc5_ecc_priv *priv = dev_get_priv(dev);
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priv->regs = dev_read_addr_ptr(dev);
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if (!priv->regs)
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return -EINVAL;
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return 0;
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}
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static int renesas_dbsc5_ecc_get_info(struct udevice *dev,
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struct ram_info *info)
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{
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struct renesas_dbsc5_ecc_priv *priv = dev_get_priv(dev);
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info->base = (phys_addr_t)priv->regs;
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info->size = 32 * SZ_1M;
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return 0;
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}
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static const struct ram_ops renesas_dbsc5_ecc_ops = {
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.get_info = renesas_dbsc5_ecc_get_info,
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};
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static const struct udevice_id renesas_dbsc5_ecc_ids[] = {
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{ .compatible = "renesas,r8a78000-ecc" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(renesas_dbsc5_ecc) = {
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.name = "dbsc5_ecc",
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.id = UCLASS_RAM,
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.of_match = renesas_dbsc5_ecc_ids,
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.of_to_plat = renesas_dbsc5_ecc_of_to_plat,
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.ops = &renesas_dbsc5_ecc_ops,
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.probe = renesas_dbsc5_ecc_probe,
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.priv_auto = sizeof(struct renesas_dbsc5_ecc_priv),
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};
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@@ -9,7 +9,7 @@
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#include <hang.h>
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#include <linux/sizes.h>
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#include <ram.h>
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#include "dbsc5.h"
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#include "r8a779g0-dbsc5.h"
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/* AXMM */
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#define AXMM_ADSPLCR0 0x4008
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@@ -10,7 +10,7 @@
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#include <errno.h>
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#include <linux/sizes.h>
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#include <ram.h>
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#include "dbsc5.h"
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#include "r8a779g0-dbsc5.h"
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static int renesas_dbsc5_probe(struct udevice *dev)
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{
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@@ -3,8 +3,8 @@
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#ifndef __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__
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#define __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__
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#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__
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#define __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__
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/*
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* DBSC5 ... 0xe678_0000..0xe67fffff
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@@ -26,4 +26,4 @@ struct renesas_dbsc5_data {
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const char *otp_node;
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};
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#endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */
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#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__ */
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@@ -4,14 +4,14 @@
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*/
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#include <asm/io.h>
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#include <dbsc5.h>
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#include <r8a779g0-dbsc5.h>
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#include <dm.h>
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#include <errno.h>
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#include <hang.h>
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#include <ram.h>
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#include <linux/iopoll.h>
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#include <linux/sizes.h>
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#include "dbsc5.h"
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#include "r8a779g0-dbsc5.h"
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/* Number of array elements in Data Slice */
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#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100
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@@ -0,0 +1,76 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2026 Renesas Electronics Corp.
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*
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* Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved.
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*/
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <errno.h>
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#include <linux/sizes.h>
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#include <ram.h>
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#include "r8a78000-dbsc5.h"
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static int renesas_dbsc5_probe(struct udevice *dev)
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{
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struct udevice *ddev, *vdev, *edev;
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int ret;
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ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_dram", &ddev);
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if (ret)
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return ret;
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ret = uclass_get_device_by_name(UCLASS_RAM, "ram@b8940000", &vdev);
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if (ret)
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return ret;
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ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_ecc", &edev);
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if (ret)
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return ret;
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return 0;
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}
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int renesas_dbsc5_bind(struct udevice *dev)
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{
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struct udevice *ramdev, *eccdev;
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struct driver *ramdrv, *eccdrv;
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int ret;
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ramdrv = lists_driver_lookup_name("dbsc5_dram");
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if (!ramdrv)
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return -ENOENT;
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eccdrv = lists_driver_lookup_name("dbsc5_ecc");
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if (!eccdrv)
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return -ENOENT;
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ret = device_bind_with_driver_data(dev, ramdrv, "dbsc5_dram",
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dev_get_driver_data(dev),
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dev_ofnode(dev), &ramdev);
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if (ret)
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return ret;
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ret = device_bind_with_driver_data(dev, eccdrv, "dbsc5_ecc", 0,
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dev_ofnode(dev), &eccdev);
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if (ret)
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device_unbind(ramdev);
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return ret;
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}
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static const struct udevice_id renesas_dbsc5_ids[] = {
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{ .compatible = "renesas,r8a78000-dbsc", },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(renesas_dbsc5) = {
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.name = "dbsc5",
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.id = UCLASS_NOP,
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.of_match = renesas_dbsc5_ids,
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.bind = renesas_dbsc5_bind,
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.probe = renesas_dbsc5_probe,
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};
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@@ -0,0 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2026 Renesas Electronics Corp.
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*
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* Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved.
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*/
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#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__
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#define __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__
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struct renesas_dbsc5_data {
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const char *clock_node;
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const char *reset_node;
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const char *otp_node;
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};
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#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__ */
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,63 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2026 Renesas Electronics Corp.
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*
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* Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved.
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*/
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#ifndef __INCLUDE_DBSC5_H__
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#define __INCLUDE_DBSC5_H__
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/* The number of channels X5H has */
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#define DRAM_CH_CNT 16
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/* The number of slices X5H has */
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#define SLICE_CNT 2
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/* The number of chip select X5H has */
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#define CS_CNT 2
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struct renesas_dbsc5_board_config {
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u32 bdcfg_phyvalid;
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u32 bdcfg_tx_drv;
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u32 bdcfg_tx_ffc;
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u32 bdcfg_rx_odt;
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u8 bdcfg_rx_dfe;
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u8 bdcfg_tx_odt;
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u8 bdcfg_tx_ntodt;
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u8 bdcfg_tx_dfe;
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u8 bdcfg_rx_dca;
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u8 bdcfg_rx_drv;
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u32 bdcfg_rx_emphasis;
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u8 bdcfg_tx_dca;
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u8 bdcfg_ca_vref;
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u32 bdcfg_rx_vref;
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u32 bdcfg_rx_vref_step;
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u32 bdcfg_tx_vref;
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u8 bdcfg_rfm_chk;
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/* Board parameter about channels */
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struct {
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/*
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* 0x00: 4Gb dual channel die / 2Gb single channel die
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* 0x01: 6Gb dual channel die / 3Gb single channel die
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* 0x02: 8Gb dual channel die / 4Gb single channel die
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* 0x03: 12Gb dual channel die / 6Gb single channel die
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* 0x04: 16Gb dual channel die / 8Gb single channel die
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* 0x05: 24Gb dual channel die / 12Gb single channel die
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* 0x06: 32Gb dual channel die / 16Gb single channel die
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* 0x07: 24Gb single channel die
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* 0x08: 32Gb single channel die
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* 0xFF: NO_MEMORY
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*/
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u8 bdcfg_ddr_density[CS_CNT];
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/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
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u32 bdcfg_ca_swap;
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/* SoC dqsX([1][0]) -> MEM dqsY: */
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u8 bdcfg_dqs_swap;
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/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
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u32 bdcfg_dq_swap[SLICE_CNT];
|
||||
/* SoC dm -> MEM dqY/dm: (8 means DM) */
|
||||
u8 bdcfg_dm_swap[SLICE_CNT];
|
||||
} ch[DRAM_CH_CNT];
|
||||
};
|
||||
|
||||
#endif /* __INCLUDE_DBSC5_H__ */
|
||||
Reference in New Issue
Block a user