Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv

CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/24428

- RISC-V: Add some fixes
- RISC-V: Integrate OP-TEE into the RISC-V boot flow
- RISC-V: Unify implementation of cleanup_before_linux() for RISC-V
  ports
- RISC-V: cmd: Add bhyve SBI implementation ID
- Board: K1: Probe dram size during boot phase

arch/riscv/Kconfig

@@ -459,6 +459,7 @@ config SPL_XIP
 
 config AVAILABLE_HARTS
 	bool "Send IPI by available harts"
+	depends on !XIP
 	default y
 	help
 	  By default, IPI sending mechanism will depend on available_harts.
@@ -587,4 +588,10 @@ config SPL_LOAD_FIT_OPENSBI_OS_BOOT
 	  This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper
 	  -> linux to u-boot SPL -> OpenSBI -> linux.
 
+config SPL_OPTEE_LOAD_ADDR
+	hex "OP-TEE Trusted OS image load address"
+	depends on OPTEE
+	help
+	  Load address of the OP-TEE binary.
+
 endmenu

arch/riscv/cpu/cpu.c

@@ -11,11 +11,13 @@
 #include <event.h>
 #include <hang.h>
 #include <init.h>
+#include <irq_func.h>
 #include <log.h>
 #include <asm/encoding.h>
 #include <asm/system.h>
 #include <asm/hwcap.h>
 #include <asm/cpufeature.h>
+#include <asm/cache.h>
 #include <dm/uclass-internal.h>
 #include <linux/bitops.h>
 #include <linux/log2.h>
@@ -729,3 +731,18 @@ void reset_cpu(void)
 	hang();
 }
 #endif
+
+/*
+ * cleanup_before_linux() is called just before we call linux, which prepares
+ * the processor for linux.
+ * this weak implementation is used by default. we disable interrupts and flush
+ * the cache.
+ */
+__weak int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+	cache_flush();
+
+	return 0;
+}

arch/riscv/cpu/generic/Makefile

@@ -3,4 +3,3 @@
 # Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
 
 obj-y += dram.o
-obj-y += cpu.o

arch/riscv/cpu/generic/cpu.c

@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <irq_func.h>
-#include <asm/cache.h>
-
-/*
- * cleanup_before_linux() is called just before we call linux
- * it prepares the processor for linux
- *
- * we disable interrupt and caches.
- */
-int cleanup_before_linux(void)
-{
-	disable_interrupts();
-
-	cache_flush();
-
-	return 0;
-}

arch/riscv/cpu/jh7110/Makefile

@@ -5,6 +5,5 @@
 ifeq ($(CONFIG_XPL_BUILD),y)
 obj-y += spl.o
 else
-obj-y += cpu.o
 obj-y += dram.o
 endif

arch/riscv/cpu/jh7110/cpu.c

@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
- */
-
-#include <asm/cache.h>
-#include <irq_func.h>
-
-/*
- * cleanup_before_linux() is called just before we call linux
- * it prepares the processor for linux
- *
- * we disable interrupt and caches.
- */
-int cleanup_before_linux(void)
-{
-	disable_interrupts();
-
-	cache_flush();
-
-	return 0;
-}

arch/riscv/cpu/k1/dram.c

@@ -4,17 +4,53 @@
  */
 
 #include <asm/global_data.h>
+#include <asm/io.h>
 #include <config.h>
+#include <bitfield.h>
 #include <fdt_support.h>
 #include <linux/sizes.h>
 
+#define DDR_BASE 0xC0000000
 DECLARE_GLOBAL_DATA_PTR;
 
+static phys_size_t ddr_map_size(u32 val)
+{
+	u32 tmp;
+
+	if (!(val & 0x1))
+		return 0;
+
+	tmp = bitfield_extract(val, 16, 5);
+	switch (tmp) {
+	case 0xd:
+		return 512;
+	case 0xe:
+		return 1024;
+	case 0xf:
+		return 2048;
+	case 0x10:
+		return 4096;
+	case 0x11:
+		return 8192;
+	default:
+		pr_info("Invalid DRAM density %x\n", val);
+		return 0;
+	}
+}
+
+phys_size_t ddr_get_density(void)
+{
+	phys_size_t cs0_size = ddr_map_size(readl((void *)DDR_BASE + 0x200));
+	phys_size_t cs1_size = ddr_map_size(readl((void *)DDR_BASE + 0x208));
+	phys_size_t ddr_size = cs0_size + cs1_size;
+
+	return ddr_size;
+}
+
 int dram_init(void)
 {
 	gd->ram_base = CFG_SYS_SDRAM_BASE;
-	/* TODO get ram size from ddr controller */
-	gd->ram_size = SZ_4G;
+	gd->ram_size = ddr_get_density() * SZ_1M;
 	return 0;
 }
 

arch/riscv/dts/binman.dtsi

@@ -53,6 +53,19 @@
 					};
 				};
 #endif
+#ifdef CONFIG_OPTEE
+				tee {
+					description = "OP-TEE";
+					type = "tee";
+					arch = "riscv";
+					compression = "none";
+					os = "tee";
+					load = /bits/ 64 <CONFIG_SPL_OPTEE_LOAD_ADDR>;
+					tee_blob: tee-os {
+						filename = "tee.bin";
+					};
+				};
+#endif
 
 				opensbi {
 					description = "OpenSBI fw_dynamic Firmware";
@@ -88,11 +101,20 @@
 #endif
 					description = "NAME";
 					firmware = "opensbi";
-#ifndef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
-					loadables = "uboot";
+#ifdef CONFIG_OPTEE
+#ifdef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
+					loadables = "linux", "tee";
 #else
-					loadables = "linux";
+					loadables = "uboot", "tee";
 #endif
+#else /* !CONFIG_OPTEEE */
+#ifdef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
+					loadables = "linux";
+#else
+					loadables = "uboot";
+#endif
+#endif /* CONFIG_OPTEE */
+
 #ifndef CONFIG_OF_BOARD
 					fdt = "fdt-SEQ";
 #endif

cmd/riscv/sbi.c

@@ -30,6 +30,7 @@ static struct sbi_imp implementations[] = {
 	{ 8, "PolarFire Hart Software Services" },
 	{ 9, "coreboot" },
 	{ 10, "oreboot" },
+	{ 11, "bhyve" },
 };
 
 static struct sbi_ext extensions[] = {

drivers/pinctrl/starfive/pinctrl-starfive.c

@@ -348,7 +348,7 @@ static const struct dm_gpio_ops starfive_gpio_ops = {
 	.set_value = starfive_gpio_set_value,
 };
 
-static struct driver starfive_gpio_driver = {
+U_BOOT_DRIVER(starfive_gpio) = {
 	.name = "starfive_gpio",
 	.id = UCLASS_GPIO,
 	.probe = starfive_gpio_probe,
@@ -367,7 +367,7 @@ static int starfive_gpiochip_register(struct udevice *parent)
 		return -ENOENT;
 
 	node = dev_ofnode(parent);
-	ret = device_bind_with_driver_data(parent, &starfive_gpio_driver,
+	ret = device_bind_with_driver_data(parent, DM_DRIVER_REF(starfive_gpio),
 					   "starfive_gpio", 0, node, &dev);
 
 	return (ret == 0) ? 0 : ret;