From b6d150b9496fc42a2c88515fa14426ac892c3500 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Thu, 16 Jan 2025 11:45:34 +0800 Subject: [PATCH 1/9] pinctrl: starfive: Correct driver declaration for starfive_gpio Use the driver macros so that the driver appears in the linker list. Reported-by: Simon Glass Fixes: 732f01aabf53 ("pinctrl: starfive: Add StarFive JH7110 driver") Signed-off-by: Hal Feng Reviewed-by: Anand Moon --- drivers/pinctrl/starfive/pinctrl-starfive.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c index 95b1a752de2..1b942e6f045 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive.c @@ -348,7 +348,7 @@ static const struct dm_gpio_ops starfive_gpio_ops = { .set_value = starfive_gpio_set_value, }; -static struct driver starfive_gpio_driver = { +U_BOOT_DRIVER(starfive_gpio) = { .name = "starfive_gpio", .id = UCLASS_GPIO, .probe = starfive_gpio_probe, @@ -367,7 +367,7 @@ static int starfive_gpiochip_register(struct udevice *parent) return -ENOENT; node = dev_ofnode(parent); - ret = device_bind_with_driver_data(parent, &starfive_gpio_driver, + ret = device_bind_with_driver_data(parent, DM_DRIVER_REF(starfive_gpio), "starfive_gpio", 0, node, &dev); return (ret == 0) ? 0 : ret; From 3691fbccfc89eda39faacb3fff3e6edbc9c62cd4 Mon Sep 17 00:00:00 2001 From: Huan Zhou Date: Mon, 20 Jan 2025 12:29:20 +0800 Subject: [PATCH 2/9] riscv: spacemit: k1: probe dram size during boot phase. Implement functionality to probe and calculate the DRAM size during the boot phase for the RISC-V spacemit K1 platform. Tested-by: Marcel Ziswiler # BPI-F3 16G Signed-off-by: Huan Zhou Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/k1/dram.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c index c477c15cbfb..cc1e903c9dd 100644 --- a/arch/riscv/cpu/k1/dram.c +++ b/arch/riscv/cpu/k1/dram.c @@ -4,17 +4,53 @@ */ #include +#include #include +#include #include #include +#define DDR_BASE 0xC0000000 DECLARE_GLOBAL_DATA_PTR; +static phys_size_t ddr_map_size(u32 val) +{ + u32 tmp; + + if (!(val & 0x1)) + return 0; + + tmp = bitfield_extract(val, 16, 5); + switch (tmp) { + case 0xd: + return 512; + case 0xe: + return 1024; + case 0xf: + return 2048; + case 0x10: + return 4096; + case 0x11: + return 8192; + default: + pr_info("Invalid DRAM density %x\n", val); + return 0; + } +} + +phys_size_t ddr_get_density(void) +{ + phys_size_t cs0_size = ddr_map_size(readl((void *)DDR_BASE + 0x200)); + phys_size_t cs1_size = ddr_map_size(readl((void *)DDR_BASE + 0x208)); + phys_size_t ddr_size = cs0_size + cs1_size; + + return ddr_size; +} + int dram_init(void) { gd->ram_base = CFG_SYS_SDRAM_BASE; - /* TODO get ram size from ddr controller */ - gd->ram_size = SZ_4G; + gd->ram_size = ddr_get_density() * SZ_1M; return 0; } From 490be9de22ac3dac18ebf33ebaefb5f93f29963e Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 23 Jan 2025 03:21:40 +0100 Subject: [PATCH 3/9] riscv: AVAILABLE_HARTS is not compatible with XIP If CONFIG_AVAILABLE_HARTS=y, variable available_harts_lock is created in the data section which will not be writable while executing from flash. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index faf70cb5d4c..f4e76db3df4 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -459,6 +459,7 @@ config SPL_XIP config AVAILABLE_HARTS bool "Send IPI by available harts" + depends on !XIP default y help By default, IPI sending mechanism will depend on available_harts. From ca3985ff86aee9afa110467bad027af8f288d17c Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 24 Jan 2025 17:00:14 +0100 Subject: [PATCH 4/9] cmd: sbi: add bhyve SBI implementation ID Bhyve is the hypervisor used by FreeBSD. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- cmd/riscv/sbi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 5ecf56781c1..b013c8c8d4e 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -30,6 +30,7 @@ static struct sbi_imp implementations[] = { { 8, "PolarFire Hart Software Services" }, { 9, "coreboot" }, { 10, "oreboot" }, + { 11, "bhyve" }, }; static struct sbi_ext extensions[] = { From 99654e1b9665de0245c0fd606760aa7d1e9b8810 Mon Sep 17 00:00:00 2001 From: Yu-Chien Peter Lin Date: Sat, 11 Jan 2025 09:55:26 +0800 Subject: [PATCH 5/9] riscv: Add CONFIG_SPL_OPTEE_LOAD_ADDR Allow specifying load address of OP-TEE binary. It is recommended that the specified address aligns with the base address of an PMP-protected NAPOT region and matches the CFG_TDDRAM_START configuration in OP-TEE. Signed-off-by: Yu-Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f4e76db3df4..b24623590f2 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -588,4 +588,10 @@ config SPL_LOAD_FIT_OPENSBI_OS_BOOT This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper -> linux to u-boot SPL -> OpenSBI -> linux. +config SPL_OPTEE_LOAD_ADDR + hex "OP-TEE Trusted OS image load address" + depends on OPTEE + help + Load address of the OP-TEE binary. + endmenu From 47d90f6bd30ad3c5cc909131dbf80081a8685e5d Mon Sep 17 00:00:00 2001 From: Yu-Chien Peter Lin Date: Sat, 11 Jan 2025 09:55:27 +0800 Subject: [PATCH 6/9] riscv: dts: binman.dtsi: Include OP-TEE OS image The following diagram illustrates the boot flow for OP-TEE OS initialization on RISC-V. (1)-----------+ | U-Boot SPL | +------------+ | v (2)-------------------------------------------------------------+ | OpenSBI (fw_dynamic.bin) | | (4)------------------------+ | | | optee dispatcher driver | | +-----------------+-------^---------|-------+------------------+ M-mode | | | ---------+--[trusted domain]---+----.----+--[untrusted domain]------- S-mode | (coldboot domain) | | | v | | v (3)---------------------------+ |(5)----------------------------+ | OP-TEE OS (tee.bin) | | | U-Boot (u-boot-nodtb.bin) | +----------------------------+ | +-----------------------------+ | | | v |(6)----------------------------+ | | Linux | | +-----------------------------+ This patch enables the inclusion of the OP-TEE binary within the U-Boot ITB, allowing it to be loaded to a platform defined address by U-Boot SPL. Signed-off-by: Yu-Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/binman.dtsi | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 9271de0ddfc..0405faca574 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -53,6 +53,19 @@ }; }; #endif +#ifdef CONFIG_OPTEE + tee { + description = "OP-TEE"; + type = "tee"; + arch = "riscv"; + compression = "none"; + os = "tee"; + load = /bits/ 64 ; + tee_blob: tee-os { + filename = "tee.bin"; + }; + }; +#endif opensbi { description = "OpenSBI fw_dynamic Firmware"; @@ -88,11 +101,20 @@ #endif description = "NAME"; firmware = "opensbi"; -#ifndef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT - loadables = "uboot"; +#ifdef CONFIG_OPTEE +#ifdef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT + loadables = "linux", "tee"; #else - loadables = "linux"; + loadables = "uboot", "tee"; #endif +#else /* !CONFIG_OPTEEE */ +#ifdef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT + loadables = "linux"; +#else + loadables = "uboot"; +#endif +#endif /* CONFIG_OPTEE */ + #ifndef CONFIG_OF_BOARD fdt = "fdt-SEQ"; #endif From f88e3b77395255ad001b9237a8e57b932330d673 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 23 Jan 2025 09:11:33 +0000 Subject: [PATCH 7/9] riscv: add a generic implementation for cleanup_before_linux() Most RISC-V SoCs have similar cleanup_before_linux() functions. Let's provide a weak symbol as fallback to reduce duplicated code. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/cpu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 06ecd92b9bc..5b31da64cbd 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -11,11 +11,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -729,3 +731,18 @@ void reset_cpu(void) hang(); } #endif + +/* + * cleanup_before_linux() is called just before we call linux, which prepares + * the processor for linux. + * this weak implementation is used by default. we disable interrupts and flush + * the cache. + */ +__weak int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} From 334980f4cf574a522e802b240f5ba05e8ab5e5f5 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 23 Jan 2025 09:11:34 +0000 Subject: [PATCH 8/9] riscv: cpu: generic: fallback to generic cleanup_before_linux() The current implementation is equivalent to the fallback one, so this shouldn't change any behaviour but cleans the code up only. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/generic/Makefile | 1 - arch/riscv/cpu/generic/cpu.c | 22 ---------------------- 2 files changed, 23 deletions(-) delete mode 100644 arch/riscv/cpu/generic/cpu.c diff --git a/arch/riscv/cpu/generic/Makefile b/arch/riscv/cpu/generic/Makefile index 258e4620dd4..a9be44ec387 100644 --- a/arch/riscv/cpu/generic/Makefile +++ b/arch/riscv/cpu/generic/Makefile @@ -3,4 +3,3 @@ # Copyright (C) 2018, Bin Meng obj-y += dram.o -obj-y += cpu.o diff --git a/arch/riscv/cpu/generic/cpu.c b/arch/riscv/cpu/generic/cpu.c deleted file mode 100644 index f13c18942f3..00000000000 --- a/arch/riscv/cpu/generic/cpu.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018, Bin Meng - */ - -#include -#include - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - - cache_flush(); - - return 0; -} From faf237d1b43c3221e78bfa0310833fc5bc71bc21 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 23 Jan 2025 09:11:35 +0000 Subject: [PATCH 9/9] riscv: cpu: jh7110: fallback to generic cleanup_before_linux() JH7110 SoC requires no specific handling before entering Linux kernel. Let's drop the specific implementation to avoid duplication. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/jh7110/Makefile | 1 - arch/riscv/cpu/jh7110/cpu.c | 23 ----------------------- 2 files changed, 24 deletions(-) delete mode 100644 arch/riscv/cpu/jh7110/cpu.c diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile index 0939c1061d0..4f91aafa9da 100644 --- a/arch/riscv/cpu/jh7110/Makefile +++ b/arch/riscv/cpu/jh7110/Makefile @@ -5,6 +5,5 @@ ifeq ($(CONFIG_XPL_BUILD),y) obj-y += spl.o else -obj-y += cpu.o obj-y += dram.o endif diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c deleted file mode 100644 index 1d7c026584a..00000000000 --- a/arch/riscv/cpu/jh7110/cpu.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * Author: Yanhong Wang - */ - -#include -#include - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - - cache_flush(); - - return 0; -}