a risc-v simulator

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vhaudiquet d6af840ed1 CSR: sie=mie, sip=mip		11 months ago
..
bootloader	ELF: added support for SHT_RISCV_ATTRIBUTES seg	11 months ago
cpu	CSR: sie=mie, sip=mip	11 months ago
devices	Added mock SBI_EXTENSION_TIMER	11 months ago
gdbstub	Refactor CPU mutex code	11 months ago
memory	Hardened MMU permission checks	11 months ago
main.c	Multiple cleanups and improvements	11 months ago
option.c	Added 'trace' option	12 months ago
vriscv.h	Added 'trace' option	12 months ago