a risc-v simulator
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vriscv/tests/blt.s

31 lines
540 B

.global _start
_start:
# Set base value of a0 to 'test failed'
addi a0, zero, 1
# Set A, B values of t0/t1, to test less than
addi t0, zero, 1
addi t1, zero, 2
blt t1, t0, lt0
# Inequality passed, now test with jump
blt t0, t1, lt1
# On failure, return
ebreak
ltNeg:
# All passed
addi a0, zero, 0
ebreak
lt0:
# Inequality failed
ebreak
lt1:
# Inequality passed ; now try with negative numbers
addi t0, zero, -1
addi t1, zero, -2
blt t1, t0, ltNeg
ebreak