a risc-v simulator
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vriscv/tests/beq.s

31 lines
551 B

.global _start
_start:
# Set base value of a0 to 'test failed'
addi a0, zero, 1
# Set A, B values of t0/t1, to test equality
addi t0, zero, 0xA
addi t1, zero, 0xB
beq t0, t1, eq0
# Inequality passed, now test equality
addi t0, zero, 0xA
addi t1, zero, 0xA
beq t0, t1, eq1
# On failure, return
ebreak
eqNeg:
# All passed
addi a0, zero, 0
ebreak
eq0:
# Inequality failed
ebreak
eq1:
# Equality passed ; now try to test a negative offset case
beq t0, t1, eqNeg
ebreak