gdbstub on bp, unreachable, previous privilege S
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@ -1,8 +1,9 @@
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#include "exception.h"
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#include "vriscv.h"
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#include <stdio.h>
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void exception_trigger(rv32_cpu_t* cpu, uint32_t scause, uint32_t tval)
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__attribute__((noreturn)) void exception_trigger(rv32_cpu_t* cpu, uint32_t scause, uint32_t tval)
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{
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// An exception can only be triggered by the CPU itself,
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// so we know we already own the mutex
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@ -14,21 +15,31 @@ void exception_trigger(rv32_cpu_t* cpu, uint32_t scause, uint32_t tval)
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// Exceptions cannot be disabled
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// Unset SIE (interrupt enable) bit
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cpu->csr[CSR_SSTATUS] &= ~0b10U;
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// Set xCAUSE : exception cause, with interrupt bit set to null
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cpu->csr[CSR_SCAUSE] = scause;
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if(gdbstub && scause == SCAUSE_BREAKPOINT)
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{
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cpu->sim_ticks_left = 0;
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// No simulation ticks left : wakeup people waiting on sim end
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pthread_cond_signal(&cpu->sim_condition);
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// Then, wait for simulation state to change until we get more ticks to simulate
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while(!cpu->sim_ticks_left)
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pthread_cond_wait(&cpu->sim_condition, &cpu->mutex);
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}
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// Save previous interrupt enable in xSTATUS.xPIE
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if(cpu->csr[CSR_SSTATUS] & 0b10U)
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cpu->csr[CSR_SSTATUS] |= 0x80;
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// Set previous privilege mode in xSTATUS.xPP
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// TODO
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// Unset SIE (interrupt enable) bit
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cpu->csr[CSR_SSTATUS] &= ~0b10U;
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// TODO : Allow user mode exceptions (by not setting this)
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cpu->csr[CSR_SSTATUS] |= 0x100;
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// Set privilege mode for exception handling, checking for delegation
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// TODO
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// TODO
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// Set xTVAL, exception-specific information related to xCAUSE
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cpu->csr[CSR_STVAL] = tval;
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@ -41,9 +52,12 @@ void exception_trigger(rv32_cpu_t* cpu, uint32_t scause, uint32_t tval)
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// Exceptions are not vectored (we can safely ignore mode)
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cpu->pc = cpu->csr[CSR_STVEC] & 0xFFFFFFFC;
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// Unlock cpu mutex, cpu_loop will lock it just after
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// Unlock cpu mutex, cpu_loop will lock it just after
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pthread_mutex_unlock(&cpu->mutex);
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// cpu loop (attribute noreturn should erase previous stack)
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// TODO : Hard reset the stack pointer
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// cpu loop
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cpu_loop(cpu);
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__builtin_unreachable();
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}
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@ -3,7 +3,7 @@
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#include "rv32cpu.h"
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void exception_trigger(rv32_cpu_t* cpu, uint32_t scause, uint32_t tval);
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__attribute__((noreturn)) void exception_trigger(rv32_cpu_t* cpu, uint32_t scause, uint32_t tval);
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#define SCAUSE_INSTRUCTION_MISSALIGNED 0x0
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#define SCAUSE_INSTRUCTION_ACCESS_FAULT 0x1
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@ -42,6 +42,8 @@ void interrupt_trigger(rv32_cpu_t* cpu, uint32_t scause)
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cpu->csr[CSR_SSTATUS] |= 0x80;
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// Set xSTATUS.xPP (Previous Privilege) bit
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// TODO : Allow user mode interrupts (by not setting this)
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cpu->csr[CSR_SSTATUS] |= 0x100;
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// Unset xSTATUS.xIE (interrupt enable) bit
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cpu->csr[CSR_SSTATUS] &= ~0b10U;
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@ -759,6 +759,8 @@ __attribute__((noreturn)) void cpu_loop(rv32_cpu_t* cpu)
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// Let go of cpu mutex
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pthread_mutex_unlock(&cpu->mutex);
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}
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__builtin_unreachable();
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}
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static void cpu_print_instruction(instruction_t* instruction)
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