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Added resource, fixed memaccess

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Valentin Haudiquet 2023-10-17 13:25:31 +02:00
parent 43d22052e5
commit c404defb42
2 changed files with 4 additions and 1 deletions
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3
README.md
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@ -13,6 +13,9 @@ RISC-V Specifications:
- https://five-embeddev.com/riscv-isa-manual/latest/instr-table.html (instruction table) - https://five-embeddev.com/riscv-isa-manual/latest/instr-table.html (instruction table)
- https://five-embeddev.com/riscv-isa-manual/latest/priv-instr-table.html (privileged instructions) - https://five-embeddev.com/riscv-isa-manual/latest/priv-instr-table.html (privileged instructions)
Device Tree Source :
- https://elinux.org/Device_Tree_Usage
Juraj's Blog, mostly: Juraj's Blog, mostly:
- https://jborza.com/post/2021-04-04-riscv-supervisor-mode/ - https://jborza.com/post/2021-04-04-riscv-supervisor-mode/
- https://jborza.com/emulation/2021/04/22/ecalls-and-syscalls.html - https://jborza.com/emulation/2021/04/22/ecalls-and-syscalls.html

2
src/cpu/rv32cpu.c
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@ -698,7 +698,7 @@ void cpu_loop(rv32_cpu_t* cpu)
fprintf(stderr, "Error: instruction fetch: pc is out of addressable memory\n"); fprintf(stderr, "Error: instruction fetch: pc is out of addressable memory\n");
exit(EXIT_FAILURE); exit(EXIT_FAILURE);
} }
raw_instruction.data = *((uint32_t*) (&memory[cpu->pc])); raw_instruction.data = mem_read32(cpu->pc);
// Decode // Decode
instruction_t instruction; instruction_t instruction;