Added resource, fixed memaccess

README.md

@@ -13,6 +13,9 @@ RISC-V Specifications:
 - https://five-embeddev.com/riscv-isa-manual/latest/instr-table.html (instruction table)
 - https://five-embeddev.com/riscv-isa-manual/latest/priv-instr-table.html (privileged instructions)
 
+Device Tree Source :
+- https://elinux.org/Device_Tree_Usage
+
 Juraj's Blog, mostly:
 - https://jborza.com/post/2021-04-04-riscv-supervisor-mode/
 - https://jborza.com/emulation/2021/04/22/ecalls-and-syscalls.html

src/cpu/rv32cpu.c

@@ -698,7 +698,7 @@ void cpu_loop(rv32_cpu_t* cpu)
 			fprintf(stderr, "Error: instruction fetch: pc is out of addressable memory\n");
 			exit(EXIT_FAILURE);
 		}
-		raw_instruction.data = *((uint32_t*) (&memory[cpu->pc]));
+		raw_instruction.data = mem_read32(cpu->pc);
 
 		// Decode
 		instruction_t instruction;